drivers/staging/media/allegro-dvt/allegro-core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2019 Pengutronix, Michael Tretter <kernel@pengutronix.de>
   4  *
   5  * Allegro DVT video encoder driver
   6  */
   7
   8 #include <linux/bits.h>
   9 #include <linux/firmware.h>
  10 #include <linux/gcd.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/io.h>
  13 #include <linux/kernel.h>
  14 #include <linux/log2.h>
  15 #include <linux/module.h>
  16 #include <linux/of.h>
  17 #include <linux/of_device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/regmap.h>
  20 #include <linux/sizes.h>
  21 #include <linux/slab.h>
  22 #include <linux/videodev2.h>
  23 #include <media/v4l2-ctrls.h>
  24 #include <media/v4l2-device.h>
  25 #include <media/v4l2-event.h>
  26 #include <media/v4l2-ioctl.h>
  27 #include <media/v4l2-mem2mem.h>
  28 #include <media/videobuf2-dma-contig.h>
  29 #include <media/videobuf2-v4l2.h>
  30
  31 #include "allegro-mail.h"
  32 #include "nal-h264.h"
  33
  34 /*
  35  * Support up to 4k video streams. The hardware actually supports higher
  36  * resolutions, which are specified in PG252 June 6, 2018 (H.264/H.265 Video
  37  * Codec Unit v1.1) Chapter 3.
  38  */
  39 #define ALLEGRO_WIDTH_MIN 128
  40 #define ALLEGRO_WIDTH_DEFAULT 1920
  41 #define ALLEGRO_WIDTH_MAX 3840
  42 #define ALLEGRO_HEIGHT_MIN 64
  43 #define ALLEGRO_HEIGHT_DEFAULT 1080
  44 #define ALLEGRO_HEIGHT_MAX 2160
  45
  46 #define ALLEGRO_FRAMERATE_DEFAULT ((struct v4l2_fract) { 30, 1 })
  47
  48 #define ALLEGRO_GOP_SIZE_DEFAULT 25
  49 #define ALLEGRO_GOP_SIZE_MAX 1000
  50
  51 /*
  52  * MCU Control Registers
  53  *
  54  * The Zynq UltraScale+ Devices Register Reference documents the registers
  55  * with an offset of 0x9000, which equals the size of the SRAM and one page
  56  * gap. The driver handles SRAM and registers separately and, therefore, is
  57  * oblivious of the offset.
  58  */
  59 #define AL5_MCU_RESET                   0x0000
  60 #define AL5_MCU_RESET_SOFT              BIT(0)
  61 #define AL5_MCU_RESET_REGS              BIT(1)
  62 #define AL5_MCU_RESET_MODE              0x0004
  63 #define AL5_MCU_RESET_MODE_SLEEP        BIT(0)
  64 #define AL5_MCU_RESET_MODE_HALT         BIT(1)
  65 #define AL5_MCU_STA                     0x0008
  66 #define AL5_MCU_STA_SLEEP               BIT(0)
  67 #define AL5_MCU_WAKEUP                  0x000c
  68
  69 #define AL5_ICACHE_ADDR_OFFSET_MSB      0x0010
  70 #define AL5_ICACHE_ADDR_OFFSET_LSB      0x0014
  71 #define AL5_DCACHE_ADDR_OFFSET_MSB      0x0018
  72 #define AL5_DCACHE_ADDR_OFFSET_LSB      0x001c
  73
  74 #define AL5_MCU_INTERRUPT               0x0100
  75 #define AL5_ITC_CPU_IRQ_MSK             0x0104
  76 #define AL5_ITC_CPU_IRQ_CLR             0x0108
  77 #define AL5_ITC_CPU_IRQ_STA             0x010C
  78 #define AL5_ITC_CPU_IRQ_STA_TRIGGERED   BIT(0)
  79
  80 #define AXI_ADDR_OFFSET_IP              0x0208
  81
  82 /*
  83  * The MCU accesses the system memory with a 2G offset compared to CPU
  84  * physical addresses.
  85  */
  86 #define MCU_CACHE_OFFSET SZ_2G
  87
  88 /*
  89  * The driver needs to reserve some space at the beginning of capture buffers,
  90  * because it needs to write SPS/PPS NAL units. The encoder writes the actual
  91  * frame data after the offset.
  92  */
  93 #define ENCODER_STREAM_OFFSET SZ_64
  94
  95 #define SIZE_MACROBLOCK 16
  96
  97 static int debug;
  98 module_param(debug, int, 0644);
  99 MODULE_PARM_DESC(debug, "Debug level (0-2)");
 100
 101 struct allegro_buffer {
 102         void *vaddr;
 103         dma_addr_t paddr;
 104         size_t size;
 105         struct list_head head;
 106 };
 107
 108 struct allegro_dev;
 109 struct allegro_channel;
 110
 111 struct allegro_mbox {
 112         struct allegro_dev *dev;
 113         unsigned int head;
 114         unsigned int tail;
 115         unsigned int data;
 116         size_t size;
 117         /* protect mailbox from simultaneous accesses */
 118         struct mutex lock;
 119 };
 120
 121 struct allegro_dev {
 122         struct v4l2_device v4l2_dev;
 123         struct video_device video_dev;
 124         struct v4l2_m2m_dev *m2m_dev;
 125         struct platform_device *plat_dev;
 126
 127         /* mutex protecting vb2_queue structure */
 128         struct mutex lock;
 129
 130         struct regmap *regmap;
 131         struct regmap *sram;
 132
 133         const struct fw_info *fw_info;
 134         struct allegro_buffer firmware;
 135         struct allegro_buffer suballocator;
 136
 137         struct completion init_complete;
 138
 139         /* The mailbox interface */
 140         struct allegro_mbox *mbox_command;
 141         struct allegro_mbox *mbox_status;
 142
 143         /*
 144          * The downstream driver limits the users to 64 users, thus I can use
 145          * a bitfield for the user_ids that are in use. See also user_id in
 146          * struct allegro_channel.
 147          */
 148         unsigned long channel_user_ids;
 149         struct list_head channels;
 150 };
 151
 152 static struct regmap_config allegro_regmap_config = {
 153         .name = "regmap",
 154         .reg_bits = 32,
 155         .val_bits = 32,
 156         .reg_stride = 4,
 157         .max_register = 0xfff,
 158         .cache_type = REGCACHE_NONE,
 159 };
 160
 161 static struct regmap_config allegro_sram_config = {
 162         .name = "sram",
 163         .reg_bits = 32,
 164         .val_bits = 32,
 165         .reg_stride = 4,
 166         .max_register = 0x7fff,
 167         .cache_type = REGCACHE_NONE,
 168 };
 169
 170 enum allegro_state {
 171         ALLEGRO_STATE_ENCODING,
 172         ALLEGRO_STATE_DRAIN,
 173         ALLEGRO_STATE_WAIT_FOR_BUFFER,
 174         ALLEGRO_STATE_STOPPED,
 175 };
 176
 177 #define fh_to_channel(__fh) container_of(__fh, struct allegro_channel, fh)
 178
 179 struct allegro_channel {
 180         struct allegro_dev *dev;
 181         struct v4l2_fh fh;
 182         struct v4l2_ctrl_handler ctrl_handler;
 183
 184         unsigned int width;
 185         unsigned int height;
 186         unsigned int stride;
 187         struct v4l2_fract framerate;
 188
 189         enum v4l2_colorspace colorspace;
 190         enum v4l2_ycbcr_encoding ycbcr_enc;
 191         enum v4l2_quantization quantization;
 192         enum v4l2_xfer_func xfer_func;
 193
 194         u32 pixelformat;
 195         unsigned int sizeimage_raw;
 196         unsigned int osequence;
 197
 198         u32 codec;
 199         enum v4l2_mpeg_video_h264_profile profile;
 200         enum v4l2_mpeg_video_h264_level level;
 201         unsigned int sizeimage_encoded;
 202         unsigned int csequence;
 203
 204         bool frame_rc_enable;
 205         unsigned int bitrate;
 206         unsigned int bitrate_peak;
 207         unsigned int cpb_size;
 208         unsigned int gop_size;
 209
 210         struct allegro_buffer config_blob;
 211
 212         unsigned int num_ref_idx_l0;
 213         unsigned int num_ref_idx_l1;
 214
 215         struct v4l2_ctrl *mpeg_video_h264_profile;
 216         struct v4l2_ctrl *mpeg_video_h264_level;
 217         struct v4l2_ctrl *mpeg_video_h264_i_frame_qp;
 218         struct v4l2_ctrl *mpeg_video_h264_max_qp;
 219         struct v4l2_ctrl *mpeg_video_h264_min_qp;
 220         struct v4l2_ctrl *mpeg_video_h264_p_frame_qp;
 221         struct v4l2_ctrl *mpeg_video_h264_b_frame_qp;
 222         struct v4l2_ctrl *mpeg_video_frame_rc_enable;
 223         struct { /* video bitrate mode control cluster */
 224                 struct v4l2_ctrl *mpeg_video_bitrate_mode;
 225                 struct v4l2_ctrl *mpeg_video_bitrate;
 226                 struct v4l2_ctrl *mpeg_video_bitrate_peak;
 227         };
 228         struct v4l2_ctrl *mpeg_video_cpb_size;
 229         struct v4l2_ctrl *mpeg_video_gop_size;
 230
 231         /* user_id is used to identify the channel during CREATE_CHANNEL */
 232         /* not sure, what to set here and if this is actually required */
 233         int user_id;
 234         /* channel_id is set by the mcu and used by all later commands */
 235         int mcu_channel_id;
 236
 237         struct list_head buffers_reference;
 238         struct list_head buffers_intermediate;
 239
 240         struct list_head source_shadow_list;
 241         struct list_head stream_shadow_list;
 242         /* protect shadow lists of buffers passed to firmware */
 243         struct mutex shadow_list_lock;
 244
 245         struct list_head list;
 246         struct completion completion;
 247
 248         unsigned int error;
 249         enum allegro_state state;
 250 };
 251
 252 static inline int
 253 allegro_set_state(struct allegro_channel *channel, enum allegro_state state)
 254 {
 255         channel->state = state;
 256
 257         return 0;
 258 }
 259
 260 static inline enum allegro_state
 261 allegro_get_state(struct allegro_channel *channel)
 262 {
 263         return channel->state;
 264 }
 265
 266 struct allegro_m2m_buffer {
 267         struct v4l2_m2m_buffer buf;
 268         struct list_head head;
 269 };
 270
 271 #define to_allegro_m2m_buffer(__buf) \
 272         container_of(__buf, struct allegro_m2m_buffer, buf)
 273
 274 struct fw_info {
 275         unsigned int id;
 276         unsigned int id_codec;
 277         char *version;
 278         unsigned int mailbox_cmd;
 279         unsigned int mailbox_status;
 280         size_t mailbox_size;
 281         enum mcu_msg_version mailbox_version;
 282         size_t suballocator_size;
 283 };
 284
 285 static const struct fw_info supported_firmware[] = {
 286         {
 287                 .id = 18296,
 288                 .id_codec = 96272,
 289                 .version = "v2018.2",
 290                 .mailbox_cmd = 0x7800,
 291                 .mailbox_status = 0x7c00,
 292                 .mailbox_size = 0x400 - 0x8,
 293                 .mailbox_version = MCU_MSG_VERSION_2018_2,
 294                 .suballocator_size = SZ_16M,
 295         }, {
 296                 .id = 14680,
 297                 .id_codec = 126572,
 298                 .version = "v2019.2",
 299                 .mailbox_cmd = 0x7000,
 300                 .mailbox_status = 0x7800,
 301                 .mailbox_size = 0x800 - 0x8,
 302                 .mailbox_version = MCU_MSG_VERSION_2019_2,
 303                 .suballocator_size = SZ_32M,
 304         },
 305 };
 306
 307 static inline u32 to_mcu_addr(struct allegro_dev *dev, dma_addr_t phys)
 308 {
 309         if (upper_32_bits(phys) || (lower_32_bits(phys) & MCU_CACHE_OFFSET))
 310                 v4l2_warn(&dev->v4l2_dev,
 311                           "address %pad is outside mcu window\n", &phys);
 312
 313         return lower_32_bits(phys) | MCU_CACHE_OFFSET;
 314 }
 315
 316 static inline u32 to_mcu_size(struct allegro_dev *dev, size_t size)
 317 {
 318         return lower_32_bits(size);
 319 }
 320
 321 static inline u32 to_codec_addr(struct allegro_dev *dev, dma_addr_t phys)
 322 {
 323         if (upper_32_bits(phys))
 324                 v4l2_warn(&dev->v4l2_dev,
 325                           "address %pad cannot be used by codec\n", &phys);
 326
 327         return lower_32_bits(phys);
 328 }
 329
 330 static inline u64 ptr_to_u64(const void *ptr)
 331 {
 332         return (uintptr_t)ptr;
 333 }
 334
 335 /* Helper functions for channel and user operations */
 336
 337 static unsigned long allegro_next_user_id(struct allegro_dev *dev)
 338 {
 339         if (dev->channel_user_ids == ~0UL)
 340                 return -EBUSY;
 341
 342         return ffz(dev->channel_user_ids);
 343 }
 344
 345 static struct allegro_channel *
 346 allegro_find_channel_by_user_id(struct allegro_dev *dev,
 347                                 unsigned int user_id)
 348 {
 349         struct allegro_channel *channel;
 350
 351         list_for_each_entry(channel, &dev->channels, list) {
 352                 if (channel->user_id == user_id)
 353                         return channel;
 354         }
 355
 356         return ERR_PTR(-EINVAL);
 357 }
 358
 359 static struct allegro_channel *
 360 allegro_find_channel_by_channel_id(struct allegro_dev *dev,
 361                                    unsigned int channel_id)
 362 {
 363         struct allegro_channel *channel;
 364
 365         list_for_each_entry(channel, &dev->channels, list) {
 366                 if (channel->mcu_channel_id == channel_id)
 367                         return channel;
 368         }
 369
 370         return ERR_PTR(-EINVAL);
 371 }
 372
 373 static inline bool channel_exists(struct allegro_channel *channel)
 374 {
 375         return channel->mcu_channel_id != -1;
 376 }
 377
 378 #define AL_ERROR                        0x80
 379 #define AL_ERR_INIT_FAILED              0x81
 380 #define AL_ERR_NO_FRAME_DECODED         0x82
 381 #define AL_ERR_RESOLUTION_CHANGE        0x85
 382 #define AL_ERR_NO_MEMORY                0x87
 383 #define AL_ERR_STREAM_OVERFLOW          0x88
 384 #define AL_ERR_TOO_MANY_SLICES          0x89
 385 #define AL_ERR_BUF_NOT_READY            0x8c
 386 #define AL_ERR_NO_CHANNEL_AVAILABLE     0x8d
 387 #define AL_ERR_RESOURCE_UNAVAILABLE     0x8e
 388 #define AL_ERR_NOT_ENOUGH_CORES         0x8f
 389 #define AL_ERR_REQUEST_MALFORMED        0x90
 390 #define AL_ERR_CMD_NOT_ALLOWED          0x91
 391 #define AL_ERR_INVALID_CMD_VALUE        0x92
 392
 393 static inline const char *allegro_err_to_string(unsigned int err)
 394 {
 395         switch (err) {
 396         case AL_ERR_INIT_FAILED:
 397                 return "initialization failed";
 398         case AL_ERR_NO_FRAME_DECODED:
 399                 return "no frame decoded";
 400         case AL_ERR_RESOLUTION_CHANGE:
 401                 return "resolution change";
 402         case AL_ERR_NO_MEMORY:
 403                 return "out of memory";
 404         case AL_ERR_STREAM_OVERFLOW:
 405                 return "stream buffer overflow";
 406         case AL_ERR_TOO_MANY_SLICES:
 407                 return "too many slices";
 408         case AL_ERR_BUF_NOT_READY:
 409                 return "buffer not ready";
 410         case AL_ERR_NO_CHANNEL_AVAILABLE:
 411                 return "no channel available";
 412         case AL_ERR_RESOURCE_UNAVAILABLE:
 413                 return "resource unavailable";
 414         case AL_ERR_NOT_ENOUGH_CORES:
 415                 return "not enough cores";
 416         case AL_ERR_REQUEST_MALFORMED:
 417                 return "request malformed";
 418         case AL_ERR_CMD_NOT_ALLOWED:
 419                 return "command not allowed";
 420         case AL_ERR_INVALID_CMD_VALUE:
 421                 return "invalid command value";
 422         case AL_ERROR:
 423         default:
 424                 return "unknown error";
 425         }
 426 }
 427
 428 static unsigned int estimate_stream_size(unsigned int width,
 429                                          unsigned int height)
 430 {
 431         unsigned int offset = ENCODER_STREAM_OFFSET;
 432         unsigned int num_blocks = DIV_ROUND_UP(width, SIZE_MACROBLOCK) *
 433                                         DIV_ROUND_UP(height, SIZE_MACROBLOCK);
 434         unsigned int pcm_size = SZ_256;
 435         unsigned int partition_table = SZ_256;
 436
 437         return round_up(offset + num_blocks * pcm_size + partition_table, 32);
 438 }
 439
 440 static enum v4l2_mpeg_video_h264_level
 441 select_minimum_h264_level(unsigned int width, unsigned int height)
 442 {
 443         unsigned int pic_width_in_mb = DIV_ROUND_UP(width, SIZE_MACROBLOCK);
 444         unsigned int frame_height_in_mb = DIV_ROUND_UP(height, SIZE_MACROBLOCK);
 445         unsigned int frame_size_in_mb = pic_width_in_mb * frame_height_in_mb;
 446         enum v4l2_mpeg_video_h264_level level = V4L2_MPEG_VIDEO_H264_LEVEL_4_0;
 447
 448         /*
 449          * The level limits are specified in Rec. ITU-T H.264 Annex A.3.1 and
 450          * also specify limits regarding bit rate and CBP size. Only approximate
 451          * the levels using the frame size.
 452          *
 453          * Level 5.1 allows up to 4k video resolution.
 454          */
 455         if (frame_size_in_mb <= 99)
 456                 level = V4L2_MPEG_VIDEO_H264_LEVEL_1_0;
 457         else if (frame_size_in_mb <= 396)
 458                 level = V4L2_MPEG_VIDEO_H264_LEVEL_1_1;
 459         else if (frame_size_in_mb <= 792)
 460                 level = V4L2_MPEG_VIDEO_H264_LEVEL_2_1;
 461         else if (frame_size_in_mb <= 1620)
 462                 level = V4L2_MPEG_VIDEO_H264_LEVEL_2_2;
 463         else if (frame_size_in_mb <= 3600)
 464                 level = V4L2_MPEG_VIDEO_H264_LEVEL_3_1;
 465         else if (frame_size_in_mb <= 5120)
 466                 level = V4L2_MPEG_VIDEO_H264_LEVEL_3_2;
 467         else if (frame_size_in_mb <= 8192)
 468                 level = V4L2_MPEG_VIDEO_H264_LEVEL_4_0;
 469         else if (frame_size_in_mb <= 8704)
 470                 level = V4L2_MPEG_VIDEO_H264_LEVEL_4_2;
 471         else if (frame_size_in_mb <= 22080)
 472                 level = V4L2_MPEG_VIDEO_H264_LEVEL_5_0;
 473         else
 474                 level = V4L2_MPEG_VIDEO_H264_LEVEL_5_1;
 475
 476         return level;
 477 }
 478
 479 static unsigned int maximum_bitrate(enum v4l2_mpeg_video_h264_level level)
 480 {
 481         switch (level) {
 482         case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
 483                 return 64000;
 484         case V4L2_MPEG_VIDEO_H264_LEVEL_1B:
 485                 return 128000;
 486         case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
 487                 return 192000;
 488         case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
 489                 return 384000;
 490         case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
 491                 return 768000;
 492         case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
 493                 return 2000000;
 494         case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
 495                 return 4000000;
 496         case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
 497                 return 4000000;
 498         case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
 499                 return 10000000;
 500         case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
 501                 return 14000000;
 502         case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
 503                 return 20000000;
 504         case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
 505                 return 20000000;
 506         case V4L2_MPEG_VIDEO_H264_LEVEL_4_1:
 507                 return 50000000;
 508         case V4L2_MPEG_VIDEO_H264_LEVEL_4_2:
 509                 return 50000000;
 510         case V4L2_MPEG_VIDEO_H264_LEVEL_5_0:
 511                 return 135000000;
 512         case V4L2_MPEG_VIDEO_H264_LEVEL_5_1:
 513         default:
 514                 return 240000000;
 515         }
 516 }
 517
 518 static unsigned int maximum_cpb_size(enum v4l2_mpeg_video_h264_level level)
 519 {
 520         switch (level) {
 521         case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
 522                 return 175;
 523         case V4L2_MPEG_VIDEO_H264_LEVEL_1B:
 524                 return 350;
 525         case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
 526                 return 500;
 527         case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
 528                 return 1000;
 529         case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
 530                 return 2000;
 531         case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
 532                 return 2000;
 533         case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
 534                 return 4000;
 535         case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
 536                 return 4000;
 537         case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
 538                 return 10000;
 539         case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
 540                 return 14000;
 541         case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
 542                 return 20000;
 543         case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
 544                 return 25000;
 545         case V4L2_MPEG_VIDEO_H264_LEVEL_4_1:
 546                 return 62500;
 547         case V4L2_MPEG_VIDEO_H264_LEVEL_4_2:
 548                 return 62500;
 549         case V4L2_MPEG_VIDEO_H264_LEVEL_5_0:
 550                 return 135000;
 551         case V4L2_MPEG_VIDEO_H264_LEVEL_5_1:
 552         default:
 553                 return 240000;
 554         }
 555 }
 556
 557 static const struct fw_info *
 558 allegro_get_firmware_info(struct allegro_dev *dev,
 559                           const struct firmware *fw,
 560                           const struct firmware *fw_codec)
 561 {
 562         int i;
 563         unsigned int id = fw->size;
 564         unsigned int id_codec = fw_codec->size;
 565
 566         for (i = 0; i < ARRAY_SIZE(supported_firmware); i++)
 567                 if (supported_firmware[i].id == id &&
 568                     supported_firmware[i].id_codec == id_codec)
 569                         return &supported_firmware[i];
 570
 571         return NULL;
 572 }
 573
 574 /*
 575  * Buffers that are used internally by the MCU.
 576  */
 577
 578 static int allegro_alloc_buffer(struct allegro_dev *dev,
 579                                 struct allegro_buffer *buffer, size_t size)
 580 {
 581         buffer->vaddr = dma_alloc_coherent(&dev->plat_dev->dev, size,
 582                                            &buffer->paddr, GFP_KERNEL);
 583         if (!buffer->vaddr)
 584                 return -ENOMEM;
 585         buffer->size = size;
 586
 587         return 0;
 588 }
 589
 590 static void allegro_free_buffer(struct allegro_dev *dev,
 591                                 struct allegro_buffer *buffer)
 592 {
 593         if (buffer->vaddr) {
 594                 dma_free_coherent(&dev->plat_dev->dev, buffer->size,
 595                                   buffer->vaddr, buffer->paddr);
 596                 buffer->vaddr = NULL;
 597                 buffer->size = 0;
 598         }
 599 }
 600
 601 /*
 602  * Mailbox interface to send messages to the MCU.
 603  */
 604
 605 static void allegro_mcu_interrupt(struct allegro_dev *dev);
 606 static void allegro_handle_message(struct allegro_dev *dev,
 607                                    union mcu_msg_response *msg);
 608
 609 static struct allegro_mbox *allegro_mbox_init(struct allegro_dev *dev,
 610                                               unsigned int base, size_t size)
 611 {
 612         struct allegro_mbox *mbox;
 613
 614         mbox = devm_kmalloc(&dev->plat_dev->dev, sizeof(*mbox), GFP_KERNEL);
 615         if (!mbox)
 616                 return ERR_PTR(-ENOMEM);
 617
 618         mbox->dev = dev;
 619
 620         mbox->head = base;
 621         mbox->tail = base + 0x4;
 622         mbox->data = base + 0x8;
 623         mbox->size = size;
 624         mutex_init(&mbox->lock);
 625
 626         regmap_write(dev->sram, mbox->head, 0);
 627         regmap_write(dev->sram, mbox->tail, 0);
 628
 629         return mbox;
 630 }
 631
 632 static int allegro_mbox_write(struct allegro_mbox *mbox,
 633                               const u32 *src, size_t size)
 634 {
 635         struct regmap *sram = mbox->dev->sram;
 636         unsigned int tail;
 637         size_t size_no_wrap;
 638         int err = 0;
 639         int stride = regmap_get_reg_stride(sram);
 640
 641         if (!src)
 642                 return -EINVAL;
 643
 644         if (size > mbox->size)
 645                 return -EINVAL;
 646
 647         mutex_lock(&mbox->lock);
 648         regmap_read(sram, mbox->tail, &tail);
 649         if (tail > mbox->size) {
 650                 err = -EIO;
 651                 goto out;
 652         }
 653         size_no_wrap = min(size, mbox->size - (size_t)tail);
 654         regmap_bulk_write(sram, mbox->data + tail,
 655                           src, size_no_wrap / stride);
 656         regmap_bulk_write(sram, mbox->data,
 657                           src + (size_no_wrap / sizeof(*src)),
 658                           (size - size_no_wrap) / stride);
 659         regmap_write(sram, mbox->tail, (tail + size) % mbox->size);
 660
 661 out:
 662         mutex_unlock(&mbox->lock);
 663
 664         return err;
 665 }
 666
 667 static ssize_t allegro_mbox_read(struct allegro_mbox *mbox,
 668                                  u32 *dst, size_t nbyte)
 669 {
 670         struct {
 671                 u16 length;
 672                 u16 type;
 673         } __attribute__ ((__packed__)) *header;
 674         struct regmap *sram = mbox->dev->sram;
 675         unsigned int head;
 676         ssize_t size;
 677         size_t body_no_wrap;
 678         int stride = regmap_get_reg_stride(sram);
 679
 680         regmap_read(sram, mbox->head, &head);
 681         if (head > mbox->size)
 682                 return -EIO;
 683
 684         /* Assume that the header does not wrap. */
 685         regmap_bulk_read(sram, mbox->data + head,
 686                          dst, sizeof(*header) / stride);
 687         header = (void *)dst;
 688         size = header->length + sizeof(*header);
 689         if (size > mbox->size || size & 0x3)
 690                 return -EIO;
 691         if (size > nbyte)
 692                 return -EINVAL;
 693
 694         /*
 695          * The message might wrap within the mailbox. If the message does not
 696          * wrap, the first read will read the entire message, otherwise the
 697          * first read will read message until the end of the mailbox and the
 698          * second read will read the remaining bytes from the beginning of the
 699          * mailbox.
 700          *
 701          * Skip the header, as was already read to get the size of the body.
 702          */
 703         body_no_wrap = min((size_t)header->length,
 704                            (size_t)(mbox->size - (head + sizeof(*header))));
 705         regmap_bulk_read(sram, mbox->data + head + sizeof(*header),
 706                          dst + (sizeof(*header) / sizeof(*dst)),
 707                          body_no_wrap / stride);
 708         regmap_bulk_read(sram, mbox->data,
 709                          dst + (sizeof(*header) + body_no_wrap) / sizeof(*dst),
 710                          (header->length - body_no_wrap) / stride);
 711
 712         regmap_write(sram, mbox->head, (head + size) % mbox->size);
 713
 714         return size;
 715 }
 716
 717 /**
 718  * allegro_mbox_send() - Send a message via the mailbox
 719  * @mbox: the mailbox which is used to send the message
 720  * @msg: the message to send
 721  */
 722 static int allegro_mbox_send(struct allegro_mbox *mbox, void *msg)
 723 {
 724         struct allegro_dev *dev = mbox->dev;
 725         ssize_t size;
 726         int err;
 727         u32 *tmp;
 728
 729         tmp = kzalloc(mbox->size, GFP_KERNEL);
 730         if (!tmp) {
 731                 err = -ENOMEM;
 732                 goto out;
 733         }
 734
 735         size = allegro_encode_mail(tmp, msg);
 736
 737         err = allegro_mbox_write(mbox, tmp, size);
 738         kfree(tmp);
 739         if (err)
 740                 goto out;
 741
 742         allegro_mcu_interrupt(dev);
 743
 744 out:
 745         return err;
 746 }
 747
 748 /**
 749  * allegro_mbox_notify() - Notify the mailbox about a new message
 750  * @mbox: The allegro_mbox to notify
 751  */
 752 static void allegro_mbox_notify(struct allegro_mbox *mbox)
 753 {
 754         struct allegro_dev *dev = mbox->dev;
 755         union mcu_msg_response *msg;
 756         ssize_t size;
 757         u32 *tmp;
 758         int err;
 759
 760         msg = kmalloc(sizeof(*msg), GFP_KERNEL);
 761         if (!msg)
 762                 return;
 763
 764         msg->header.version = dev->fw_info->mailbox_version;
 765
 766         tmp = kmalloc(mbox->size, GFP_KERNEL);
 767         if (!tmp)
 768                 goto out;
 769
 770         size = allegro_mbox_read(mbox, tmp, mbox->size);
 771         if (size < 0)
 772                 goto out;
 773
 774         err = allegro_decode_mail(msg, tmp);
 775         if (err)
 776                 goto out;
 777
 778         allegro_handle_message(dev, msg);
 779
 780 out:
 781         kfree(tmp);
 782         kfree(msg);
 783 }
 784
 785 static void allegro_mcu_send_init(struct allegro_dev *dev,
 786                                   dma_addr_t suballoc_dma, size_t suballoc_size)
 787 {
 788         struct mcu_msg_init_request msg;
 789
 790         memset(&msg, 0, sizeof(msg));
 791
 792         msg.header.type = MCU_MSG_TYPE_INIT;
 793         msg.header.version = dev->fw_info->mailbox_version;
 794
 795         msg.suballoc_dma = to_mcu_addr(dev, suballoc_dma);
 796         msg.suballoc_size = to_mcu_size(dev, suballoc_size);
 797
 798         /* disable L2 cache */
 799         msg.l2_cache[0] = -1;
 800         msg.l2_cache[1] = -1;
 801         msg.l2_cache[2] = -1;
 802
 803         allegro_mbox_send(dev->mbox_command, &msg);
 804 }
 805
 806 static u32 v4l2_pixelformat_to_mcu_format(u32 pixelformat)
 807 {
 808         switch (pixelformat) {
 809         case V4L2_PIX_FMT_NV12:
 810                 /* AL_420_8BITS: 0x100 -> NV12, 0x88 -> 8 bit */
 811                 return 0x100 | 0x88;
 812         default:
 813                 return -EINVAL;
 814         }
 815 }
 816
 817 static u32 v4l2_colorspace_to_mcu_colorspace(enum v4l2_colorspace colorspace)
 818 {
 819         switch (colorspace) {
 820         case V4L2_COLORSPACE_REC709:
 821                 return 2;
 822         case V4L2_COLORSPACE_SMPTE170M:
 823                 return 3;
 824         case V4L2_COLORSPACE_SMPTE240M:
 825                 return 4;
 826         case V4L2_COLORSPACE_SRGB:
 827                 return 7;
 828         default:
 829                 /* UNKNOWN */
 830                 return 0;
 831         }
 832 }
 833
 834 static u8 v4l2_profile_to_mcu_profile(enum v4l2_mpeg_video_h264_profile profile)
 835 {
 836         switch (profile) {
 837         case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE:
 838         default:
 839                 return 66;
 840         }
 841 }
 842
 843 static u16 v4l2_level_to_mcu_level(enum v4l2_mpeg_video_h264_level level)
 844 {
 845         switch (level) {
 846         case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
 847                 return 10;
 848         case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
 849                 return 11;
 850         case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
 851                 return 12;
 852         case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
 853                 return 13;
 854         case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
 855                 return 20;
 856         case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
 857                 return 21;
 858         case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
 859                 return 22;
 860         case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
 861                 return 30;
 862         case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
 863                 return 31;
 864         case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
 865                 return 32;
 866         case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
 867                 return 40;
 868         case V4L2_MPEG_VIDEO_H264_LEVEL_4_1:
 869                 return 41;
 870         case V4L2_MPEG_VIDEO_H264_LEVEL_4_2:
 871                 return 42;
 872         case V4L2_MPEG_VIDEO_H264_LEVEL_5_0:
 873                 return 50;
 874         case V4L2_MPEG_VIDEO_H264_LEVEL_5_1:
 875         default:
 876                 return 51;
 877         }
 878 }
 879
 880 static u32
 881 v4l2_bitrate_mode_to_mcu_mode(enum v4l2_mpeg_video_bitrate_mode mode)
 882 {
 883         switch (mode) {
 884         case V4L2_MPEG_VIDEO_BITRATE_MODE_VBR:
 885                 return 2;
 886         case V4L2_MPEG_VIDEO_BITRATE_MODE_CBR:
 887         default:
 888                 return 1;
 889         }
 890 }
 891
 892 static u32 v4l2_cpb_size_to_mcu(unsigned int cpb_size, unsigned int bitrate)
 893 {
 894         unsigned int cpb_size_kbit;
 895         unsigned int bitrate_kbps;
 896
 897         /*
 898          * The mcu expects the CPB size in units of a 90 kHz clock, but the
 899          * channel follows the V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE and stores
 900          * the CPB size in kilobytes.
 901          */
 902         cpb_size_kbit = cpb_size * BITS_PER_BYTE;
 903         bitrate_kbps = bitrate / 1000;
 904
 905         return (cpb_size_kbit * 90000) / bitrate_kbps;
 906 }
 907
 908 static s16 get_qp_delta(int minuend, int subtrahend)
 909 {
 910         if (minuend == subtrahend)
 911                 return -1;
 912         else
 913                 return minuend - subtrahend;
 914 }
 915
 916 static int fill_create_channel_param(struct allegro_channel *channel,
 917                                      struct create_channel_param *param)
 918 {
 919         int i_frame_qp = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_i_frame_qp);
 920         int p_frame_qp = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_p_frame_qp);
 921         int b_frame_qp = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_b_frame_qp);
 922         int bitrate_mode = v4l2_ctrl_g_ctrl(channel->mpeg_video_bitrate_mode);
 923
 924         param->width = channel->width;
 925         param->height = channel->height;
 926         param->format = v4l2_pixelformat_to_mcu_format(channel->pixelformat);
 927         param->colorspace =
 928                 v4l2_colorspace_to_mcu_colorspace(channel->colorspace);
 929         param->src_mode = 0x0;
 930         param->profile = v4l2_profile_to_mcu_profile(channel->profile);
 931         param->constraint_set_flags = BIT(1);
 932         param->codec = channel->codec;
 933         param->level = v4l2_level_to_mcu_level(channel->level);
 934         param->tier = 0;
 935
 936         param->log2_max_poc = 10;
 937         param->log2_max_frame_num = 4;
 938         param->temporal_mvp_enable = 1;
 939
 940         param->dbf_ovr_en = 1;
 941         param->rdo_cost_mode = 1;
 942         param->custom_lda = 1;
 943         param->lf = 1;
 944         param->lf_x_tile = 1;
 945         param->lf_x_slice = 1;
 946
 947         param->src_bit_depth = 8;
 948
 949         param->beta_offset = -1;
 950         param->tc_offset = -1;
 951         param->num_slices = 1;
 952         param->me_range[0] = 8;
 953         param->me_range[1] = 8;
 954         param->me_range[2] = 16;
 955         param->me_range[3] = 16;
 956         param->max_cu_size = ilog2(SIZE_MACROBLOCK);
 957         param->min_cu_size = ilog2(8);
 958         param->max_tu_size = 2;
 959         param->min_tu_size = 2;
 960         param->max_transfo_depth_intra = 1;
 961         param->max_transfo_depth_inter = 1;
 962
 963         param->prefetch_auto = 0;
 964         param->prefetch_mem_offset = 0;
 965         param->prefetch_mem_size = 0;
 966
 967         param->rate_control_mode = channel->frame_rc_enable ?
 968                 v4l2_bitrate_mode_to_mcu_mode(bitrate_mode) : 0;
 969
 970         param->cpb_size = v4l2_cpb_size_to_mcu(channel->cpb_size,
 971                                                channel->bitrate_peak);
 972         /* Shall be ]0;cpb_size in 90 kHz units]. Use maximum value. */
 973         param->initial_rem_delay = param->cpb_size;
 974         param->framerate = DIV_ROUND_UP(channel->framerate.numerator,
 975                                         channel->framerate.denominator);
 976         param->clk_ratio = channel->framerate.denominator == 1001 ? 1001 : 1000;
 977         param->target_bitrate = channel->bitrate;
 978         param->max_bitrate = channel->bitrate_peak;
 979         param->initial_qp = i_frame_qp;
 980         param->min_qp = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_min_qp);
 981         param->max_qp = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_max_qp);
 982         param->ip_delta = get_qp_delta(i_frame_qp, p_frame_qp);
 983         param->pb_delta = get_qp_delta(p_frame_qp, b_frame_qp);
 984         param->golden_ref = 0;
 985         param->golden_delta = 2;
 986         param->golden_ref_frequency = 10;
 987         param->rate_control_option = 0x00000000;
 988
 989         param->num_pixel = channel->width + channel->height;
 990         param->max_psnr = 4200;
 991         param->max_pixel_value = 255;
 992
 993         param->gop_ctrl_mode = 0x00000002;
 994         param->freq_idr = channel->gop_size;
 995         param->freq_lt = 0;
 996         param->gdr_mode = 0x00000000;
 997         param->gop_length = channel->gop_size;
 998         param->subframe_latency = 0x00000000;
 999
1000         param->lda_factors[0] = 51;
1001         param->lda_factors[1] = 90;
1002         param->lda_factors[2] = 151;
1003         param->lda_factors[3] = 151;
1004         param->lda_factors[4] = 151;
1005         param->lda_factors[5] = 151;
1006
1007         param->max_num_merge_cand = 5;
1008
1009         return 0;
1010 }
1011
1012 static int allegro_mcu_send_create_channel(struct allegro_dev *dev,
1013                                            struct allegro_channel *channel)
1014 {
1015         struct mcu_msg_create_channel msg;
1016         struct allegro_buffer *blob = &channel->config_blob;
1017         struct create_channel_param param;
1018         size_t size;
1019
1020         memset(&param, 0, sizeof(param));
1021         fill_create_channel_param(channel, &param);
1022         allegro_alloc_buffer(dev, blob, sizeof(struct create_channel_param));
1023         param.version = dev->fw_info->mailbox_version;
1024         size = allegro_encode_config_blob(blob->vaddr, &param);
1025
1026         memset(&msg, 0, sizeof(msg));
1027
1028         msg.header.type = MCU_MSG_TYPE_CREATE_CHANNEL;
1029         msg.header.version = dev->fw_info->mailbox_version;
1030
1031         msg.user_id = channel->user_id;
1032
1033         msg.blob = blob->vaddr;
1034         msg.blob_size = size;
1035         msg.blob_mcu_addr = to_mcu_addr(dev, blob->paddr);
1036
1037         allegro_mbox_send(dev->mbox_command, &msg);
1038
1039         return 0;
1040 }
1041
1042 static int allegro_mcu_send_destroy_channel(struct allegro_dev *dev,
1043                                             struct allegro_channel *channel)
1044 {
1045         struct mcu_msg_destroy_channel msg;
1046
1047         memset(&msg, 0, sizeof(msg));
1048
1049         msg.header.type = MCU_MSG_TYPE_DESTROY_CHANNEL;
1050         msg.header.version = dev->fw_info->mailbox_version;
1051
1052         msg.channel_id = channel->mcu_channel_id;
1053
1054         allegro_mbox_send(dev->mbox_command, &msg);
1055
1056         return 0;
1057 }
1058
1059 static int allegro_mcu_send_put_stream_buffer(struct allegro_dev *dev,
1060                                               struct allegro_channel *channel,
1061                                               dma_addr_t paddr,
1062                                               unsigned long size,
1063                                               u64 stream_id)
1064 {
1065         struct mcu_msg_put_stream_buffer msg;
1066
1067         memset(&msg, 0, sizeof(msg));
1068
1069         msg.header.type = MCU_MSG_TYPE_PUT_STREAM_BUFFER;
1070         msg.header.version = dev->fw_info->mailbox_version;
1071
1072         msg.channel_id = channel->mcu_channel_id;
1073         msg.dma_addr = to_codec_addr(dev, paddr);
1074         msg.mcu_addr = to_mcu_addr(dev, paddr);
1075         msg.size = size;
1076         msg.offset = ENCODER_STREAM_OFFSET;
1077         /* copied to mcu_msg_encode_frame_response */
1078         msg.stream_id = stream_id;
1079
1080         allegro_mbox_send(dev->mbox_command, &msg);
1081
1082         return 0;
1083 }
1084
1085 static int allegro_mcu_send_encode_frame(struct allegro_dev *dev,
1086                                          struct allegro_channel *channel,
1087                                          dma_addr_t src_y, dma_addr_t src_uv,
1088                                          u64 src_handle)
1089 {
1090         struct mcu_msg_encode_frame msg;
1091
1092         memset(&msg, 0, sizeof(msg));
1093
1094         msg.header.type = MCU_MSG_TYPE_ENCODE_FRAME;
1095         msg.header.version = dev->fw_info->mailbox_version;
1096
1097         msg.channel_id = channel->mcu_channel_id;
1098         msg.encoding_options = AL_OPT_FORCE_LOAD;
1099         msg.pps_qp = 26; /* qp are relative to 26 */
1100         msg.user_param = 0; /* copied to mcu_msg_encode_frame_response */
1101         /* src_handle is copied to mcu_msg_encode_frame_response */
1102         msg.src_handle = src_handle;
1103         msg.src_y = to_codec_addr(dev, src_y);
1104         msg.src_uv = to_codec_addr(dev, src_uv);
1105         msg.stride = channel->stride;
1106         msg.ep2 = 0x0;
1107         msg.ep2_v = to_mcu_addr(dev, msg.ep2);
1108
1109         allegro_mbox_send(dev->mbox_command, &msg);
1110
1111         return 0;
1112 }
1113
1114 static int allegro_mcu_wait_for_init_timeout(struct allegro_dev *dev,
1115                                              unsigned long timeout_ms)
1116 {
1117         unsigned long tmo;
1118
1119         tmo = wait_for_completion_timeout(&dev->init_complete,
1120                                           msecs_to_jiffies(timeout_ms));
1121         if (tmo == 0)
1122                 return -ETIMEDOUT;
1123
1124         reinit_completion(&dev->init_complete);
1125         return 0;
1126 }
1127
1128 static int allegro_mcu_push_buffer_internal(struct allegro_channel *channel,
1129                                             enum mcu_msg_type type)
1130 {
1131         struct allegro_dev *dev = channel->dev;
1132         struct mcu_msg_push_buffers_internal *msg;
1133         struct mcu_msg_push_buffers_internal_buffer *buffer;
1134         unsigned int num_buffers = 0;
1135         size_t size;
1136         struct allegro_buffer *al_buffer;
1137         struct list_head *list;
1138         int err;
1139
1140         switch (type) {
1141         case MCU_MSG_TYPE_PUSH_BUFFER_REFERENCE:
1142                 list = &channel->buffers_reference;
1143                 break;
1144         case MCU_MSG_TYPE_PUSH_BUFFER_INTERMEDIATE:
1145                 list = &channel->buffers_intermediate;
1146                 break;
1147         default:
1148                 return -EINVAL;
1149         }
1150
1151         list_for_each_entry(al_buffer, list, head)
1152                 num_buffers++;
1153         size = struct_size(msg, buffer, num_buffers);
1154
1155         msg = kmalloc(size, GFP_KERNEL);
1156         if (!msg)
1157                 return -ENOMEM;
1158
1159         msg->header.type = type;
1160         msg->header.version = dev->fw_info->mailbox_version;
1161
1162         msg->channel_id = channel->mcu_channel_id;
1163         msg->num_buffers = num_buffers;
1164
1165         buffer = msg->buffer;
1166         list_for_each_entry(al_buffer, list, head) {
1167                 buffer->dma_addr = to_codec_addr(dev, al_buffer->paddr);
1168                 buffer->mcu_addr = to_mcu_addr(dev, al_buffer->paddr);
1169                 buffer->size = to_mcu_size(dev, al_buffer->size);
1170                 buffer++;
1171         }
1172
1173         err = allegro_mbox_send(dev->mbox_command, msg);
1174
1175         kfree(msg);
1176         return err;
1177 }
1178
1179 static int allegro_mcu_push_buffer_intermediate(struct allegro_channel *channel)
1180 {
1181         enum mcu_msg_type type = MCU_MSG_TYPE_PUSH_BUFFER_INTERMEDIATE;
1182
1183         return allegro_mcu_push_buffer_internal(channel, type);
1184 }
1185
1186 static int allegro_mcu_push_buffer_reference(struct allegro_channel *channel)
1187 {
1188         enum mcu_msg_type type = MCU_MSG_TYPE_PUSH_BUFFER_REFERENCE;
1189
1190         return allegro_mcu_push_buffer_internal(channel, type);
1191 }
1192
1193 static int allocate_buffers_internal(struct allegro_channel *channel,
1194                                      struct list_head *list,
1195                                      size_t n, size_t size)
1196 {
1197         struct allegro_dev *dev = channel->dev;
1198         unsigned int i;
1199         int err;
1200         struct allegro_buffer *buffer, *tmp;
1201
1202         for (i = 0; i < n; i++) {
1203                 buffer = kmalloc(sizeof(*buffer), GFP_KERNEL);
1204                 if (!buffer) {
1205                         err = -ENOMEM;
1206                         goto err;
1207                 }
1208                 INIT_LIST_HEAD(&buffer->head);
1209
1210                 err = allegro_alloc_buffer(dev, buffer, size);
1211                 if (err)
1212                         goto err;
1213                 list_add(&buffer->head, list);
1214         }
1215
1216         return 0;
1217
1218 err:
1219         list_for_each_entry_safe(buffer, tmp, list, head) {
1220                 list_del(&buffer->head);
1221                 allegro_free_buffer(dev, buffer);
1222                 kfree(buffer);
1223         }
1224         return err;
1225 }
1226
1227 static void destroy_buffers_internal(struct allegro_channel *channel,
1228                                      struct list_head *list)
1229 {
1230         struct allegro_dev *dev = channel->dev;
1231         struct allegro_buffer *buffer, *tmp;
1232
1233         list_for_each_entry_safe(buffer, tmp, list, head) {
1234                 list_del(&buffer->head);
1235                 allegro_free_buffer(dev, buffer);
1236                 kfree(buffer);
1237         }
1238 }
1239
1240 static void destroy_reference_buffers(struct allegro_channel *channel)
1241 {
1242         return destroy_buffers_internal(channel, &channel->buffers_reference);
1243 }
1244
1245 static void destroy_intermediate_buffers(struct allegro_channel *channel)
1246 {
1247         return destroy_buffers_internal(channel,
1248                                         &channel->buffers_intermediate);
1249 }
1250
1251 static int allocate_intermediate_buffers(struct allegro_channel *channel,
1252                                          size_t n, size_t size)
1253 {
1254         return allocate_buffers_internal(channel,
1255                                          &channel->buffers_intermediate,
1256                                          n, size);
1257 }
1258
1259 static int allocate_reference_buffers(struct allegro_channel *channel,
1260                                       size_t n, size_t size)
1261 {
1262         return allocate_buffers_internal(channel,
1263                                          &channel->buffers_reference,
1264                                          n, PAGE_ALIGN(size));
1265 }
1266
1267 static ssize_t allegro_h264_write_sps(struct allegro_channel *channel,
1268                                       void *dest, size_t n)
1269 {
1270         struct allegro_dev *dev = channel->dev;
1271         struct nal_h264_sps *sps;
1272         ssize_t size;
1273         unsigned int size_mb = SIZE_MACROBLOCK;
1274         /* Calculation of crop units in Rec. ITU-T H.264 (04/2017) p. 76 */
1275         unsigned int crop_unit_x = 2;
1276         unsigned int crop_unit_y = 2;
1277
1278         sps = kzalloc(sizeof(*sps), GFP_KERNEL);
1279         if (!sps)
1280                 return -ENOMEM;
1281
1282         sps->profile_idc = nal_h264_profile_from_v4l2(channel->profile);
1283         sps->constraint_set0_flag = 0;
1284         sps->constraint_set1_flag = 1;
1285         sps->constraint_set2_flag = 0;
1286         sps->constraint_set3_flag = 0;
1287         sps->constraint_set4_flag = 0;
1288         sps->constraint_set5_flag = 0;
1289         sps->level_idc = nal_h264_level_from_v4l2(channel->level);
1290         sps->seq_parameter_set_id = 0;
1291         sps->log2_max_frame_num_minus4 = 0;
1292         sps->pic_order_cnt_type = 0;
1293         sps->log2_max_pic_order_cnt_lsb_minus4 = 6;
1294         sps->max_num_ref_frames = 3;
1295         sps->gaps_in_frame_num_value_allowed_flag = 0;
1296         sps->pic_width_in_mbs_minus1 =
1297                 DIV_ROUND_UP(channel->width, size_mb) - 1;
1298         sps->pic_height_in_map_units_minus1 =
1299                 DIV_ROUND_UP(channel->height, size_mb) - 1;
1300         sps->frame_mbs_only_flag = 1;
1301         sps->mb_adaptive_frame_field_flag = 0;
1302         sps->direct_8x8_inference_flag = 1;
1303         sps->frame_cropping_flag =
1304                 (channel->width % size_mb) || (channel->height % size_mb);
1305         if (sps->frame_cropping_flag) {
1306                 sps->crop_left = 0;
1307                 sps->crop_right = (round_up(channel->width, size_mb) - channel->width) / crop_unit_x;
1308                 sps->crop_top = 0;
1309                 sps->crop_bottom = (round_up(channel->height, size_mb) - channel->height) / crop_unit_y;
1310         }
1311         sps->vui_parameters_present_flag = 1;
1312         sps->vui.aspect_ratio_info_present_flag = 0;
1313         sps->vui.overscan_info_present_flag = 0;
1314         sps->vui.video_signal_type_present_flag = 1;
1315         sps->vui.video_format = 1;
1316         sps->vui.video_full_range_flag = 0;
1317         sps->vui.colour_description_present_flag = 1;
1318         sps->vui.colour_primaries = 5;
1319         sps->vui.transfer_characteristics = 5;
1320         sps->vui.matrix_coefficients = 5;
1321         sps->vui.chroma_loc_info_present_flag = 1;
1322         sps->vui.chroma_sample_loc_type_top_field = 0;
1323         sps->vui.chroma_sample_loc_type_bottom_field = 0;
1324
1325         sps->vui.timing_info_present_flag = 1;
1326         sps->vui.num_units_in_tick = channel->framerate.denominator;
1327         sps->vui.time_scale = 2 * channel->framerate.numerator;
1328
1329         sps->vui.fixed_frame_rate_flag = 1;
1330         sps->vui.nal_hrd_parameters_present_flag = 0;
1331         sps->vui.vcl_hrd_parameters_present_flag = 1;
1332         sps->vui.vcl_hrd_parameters.cpb_cnt_minus1 = 0;
1333         sps->vui.vcl_hrd_parameters.bit_rate_scale = 0;
1334         sps->vui.vcl_hrd_parameters.cpb_size_scale = 1;
1335         /* See Rec. ITU-T H.264 (04/2017) p. 410 E-53 */
1336         sps->vui.vcl_hrd_parameters.bit_rate_value_minus1[0] =
1337                 channel->bitrate_peak / (1 << (6 + sps->vui.vcl_hrd_parameters.bit_rate_scale)) - 1;
1338         /* See Rec. ITU-T H.264 (04/2017) p. 410 E-54 */
1339         sps->vui.vcl_hrd_parameters.cpb_size_value_minus1[0] =
1340                 (channel->cpb_size * 1000) / (1 << (4 + sps->vui.vcl_hrd_parameters.cpb_size_scale)) - 1;
1341         sps->vui.vcl_hrd_parameters.cbr_flag[0] =
1342                 !v4l2_ctrl_g_ctrl(channel->mpeg_video_frame_rc_enable);
1343         sps->vui.vcl_hrd_parameters.initial_cpb_removal_delay_length_minus1 = 31;
1344         sps->vui.vcl_hrd_parameters.cpb_removal_delay_length_minus1 = 31;
1345         sps->vui.vcl_hrd_parameters.dpb_output_delay_length_minus1 = 31;
1346         sps->vui.vcl_hrd_parameters.time_offset_length = 0;
1347         sps->vui.low_delay_hrd_flag = 0;
1348         sps->vui.pic_struct_present_flag = 1;
1349         sps->vui.bitstream_restriction_flag = 0;
1350
1351         size = nal_h264_write_sps(&dev->plat_dev->dev, dest, n, sps);
1352
1353         kfree(sps);
1354
1355         return size;
1356 }
1357
1358 static ssize_t allegro_h264_write_pps(struct allegro_channel *channel,
1359                                       void *dest, size_t n)
1360 {
1361         struct allegro_dev *dev = channel->dev;
1362         struct nal_h264_pps *pps;
1363         ssize_t size;
1364
1365         pps = kzalloc(sizeof(*pps), GFP_KERNEL);
1366         if (!pps)
1367                 return -ENOMEM;
1368
1369         pps->pic_parameter_set_id = 0;
1370         pps->seq_parameter_set_id = 0;
1371         pps->entropy_coding_mode_flag = 0;
1372         pps->bottom_field_pic_order_in_frame_present_flag = 0;
1373         pps->num_slice_groups_minus1 = 0;
1374         pps->num_ref_idx_l0_default_active_minus1 = channel->num_ref_idx_l0 - 1;
1375         pps->num_ref_idx_l1_default_active_minus1 = channel->num_ref_idx_l1 - 1;
1376         pps->weighted_pred_flag = 0;
1377         pps->weighted_bipred_idc = 0;
1378         pps->pic_init_qp_minus26 = 0;
1379         pps->pic_init_qs_minus26 = 0;
1380         pps->chroma_qp_index_offset = 0;
1381         pps->deblocking_filter_control_present_flag = 1;
1382         pps->constrained_intra_pred_flag = 0;
1383         pps->redundant_pic_cnt_present_flag = 0;
1384         pps->transform_8x8_mode_flag = 0;
1385         pps->pic_scaling_matrix_present_flag = 0;
1386         pps->second_chroma_qp_index_offset = 0;
1387
1388         size = nal_h264_write_pps(&dev->plat_dev->dev, dest, n, pps);
1389
1390         kfree(pps);
1391
1392         return size;
1393 }
1394
1395 static bool allegro_channel_is_at_eos(struct allegro_channel *channel)
1396 {
1397         bool is_at_eos = false;
1398
1399         switch (allegro_get_state(channel)) {
1400         case ALLEGRO_STATE_STOPPED:
1401                 is_at_eos = true;
1402                 break;
1403         case ALLEGRO_STATE_DRAIN:
1404         case ALLEGRO_STATE_WAIT_FOR_BUFFER:
1405                 mutex_lock(&channel->shadow_list_lock);
1406                 if (v4l2_m2m_num_src_bufs_ready(channel->fh.m2m_ctx) == 0 &&
1407                     list_empty(&channel->source_shadow_list))
1408                         is_at_eos = true;
1409                 mutex_unlock(&channel->shadow_list_lock);
1410                 break;
1411         default:
1412                 break;
1413         }
1414
1415         return is_at_eos;
1416 }
1417
1418 static void allegro_channel_buf_done(struct allegro_channel *channel,
1419                                      struct vb2_v4l2_buffer *buf,
1420                                      enum vb2_buffer_state state)
1421 {
1422         const struct v4l2_event eos_event = {
1423                 .type = V4L2_EVENT_EOS
1424         };
1425
1426         if (allegro_channel_is_at_eos(channel)) {
1427                 buf->flags |= V4L2_BUF_FLAG_LAST;
1428                 v4l2_event_queue_fh(&channel->fh, &eos_event);
1429
1430                 allegro_set_state(channel, ALLEGRO_STATE_STOPPED);
1431         }
1432
1433         v4l2_m2m_buf_done(buf, state);
1434 }
1435
1436 static u64 allegro_put_buffer(struct allegro_channel *channel,
1437                               struct list_head *list,
1438                               struct vb2_v4l2_buffer *buffer)
1439 {
1440         struct v4l2_m2m_buffer *b = container_of(buffer,
1441                                                  struct v4l2_m2m_buffer, vb);
1442         struct allegro_m2m_buffer *shadow = to_allegro_m2m_buffer(b);
1443
1444         mutex_lock(&channel->shadow_list_lock);
1445         list_add_tail(&shadow->head, list);
1446         mutex_unlock(&channel->shadow_list_lock);
1447
1448         return ptr_to_u64(buffer);
1449 }
1450
1451 static struct vb2_v4l2_buffer *
1452 allegro_get_buffer(struct allegro_channel *channel,
1453                    struct list_head *list, u64 handle)
1454 {
1455         struct allegro_m2m_buffer *shadow, *tmp;
1456         struct vb2_v4l2_buffer *buffer = NULL;
1457
1458         mutex_lock(&channel->shadow_list_lock);
1459         list_for_each_entry_safe(shadow, tmp, list, head) {
1460                 if (handle == ptr_to_u64(&shadow->buf.vb)) {
1461                         buffer = &shadow->buf.vb;
1462                         list_del_init(&shadow->head);
1463                         break;
1464                 }
1465         }
1466         mutex_unlock(&channel->shadow_list_lock);
1467
1468         return buffer;
1469 }
1470
1471 static void allegro_channel_finish_frame(struct allegro_channel *channel,
1472                 struct mcu_msg_encode_frame_response *msg)
1473 {
1474         struct allegro_dev *dev = channel->dev;
1475         struct vb2_v4l2_buffer *src_buf;
1476         struct vb2_v4l2_buffer *dst_buf;
1477         struct {
1478                 u32 offset;
1479                 u32 size;
1480         } *partition;
1481         enum vb2_buffer_state state = VB2_BUF_STATE_ERROR;
1482         char *curr;
1483         ssize_t len;
1484         ssize_t free;
1485
1486         src_buf = allegro_get_buffer(channel, &channel->source_shadow_list,
1487                                      msg->src_handle);
1488         if (!src_buf)
1489                 v4l2_warn(&dev->v4l2_dev,
1490                           "channel %d: invalid source buffer\n",
1491                           channel->mcu_channel_id);
1492
1493         dst_buf = allegro_get_buffer(channel, &channel->stream_shadow_list,
1494                                      msg->stream_id);
1495         if (!dst_buf)
1496                 v4l2_warn(&dev->v4l2_dev,
1497                           "channel %d: invalid stream buffer\n",
1498                           channel->mcu_channel_id);
1499
1500         if (!src_buf || !dst_buf)
1501                 goto err;
1502
1503         dst_buf->sequence = channel->csequence++;
1504
1505         if (msg->error_code & AL_ERROR) {
1506                 v4l2_err(&dev->v4l2_dev,
1507                          "channel %d: failed to encode frame: %s (%x)\n",
1508                          channel->mcu_channel_id,
1509                          allegro_err_to_string(msg->error_code),
1510                          msg->error_code);
1511                 goto err;
1512         }
1513
1514         if (msg->partition_table_size != 1) {
1515                 v4l2_warn(&dev->v4l2_dev,
1516                           "channel %d: only handling first partition table entry (%d entries)\n",
1517                           channel->mcu_channel_id, msg->partition_table_size);
1518         }
1519
1520         if (msg->partition_table_offset +
1521             msg->partition_table_size * sizeof(*partition) >
1522             vb2_plane_size(&dst_buf->vb2_buf, 0)) {
1523                 v4l2_err(&dev->v4l2_dev,
1524                          "channel %d: partition table outside of dst_buf\n",
1525                          channel->mcu_channel_id);
1526                 goto err;
1527         }
1528
1529         partition =
1530             vb2_plane_vaddr(&dst_buf->vb2_buf, 0) + msg->partition_table_offset;
1531         if (partition->offset + partition->size >
1532             vb2_plane_size(&dst_buf->vb2_buf, 0)) {
1533                 v4l2_err(&dev->v4l2_dev,
1534                          "channel %d: encoded frame is outside of dst_buf (offset 0x%x, size 0x%x)\n",
1535                          channel->mcu_channel_id, partition->offset,
1536                          partition->size);
1537                 goto err;
1538         }
1539
1540         v4l2_dbg(2, debug, &dev->v4l2_dev,
1541                  "channel %d: encoded frame of size %d is at offset 0x%x\n",
1542                  channel->mcu_channel_id, partition->size, partition->offset);
1543
1544         /*
1545          * The payload must include the data before the partition offset,
1546          * because we will put the sps and pps data there.
1547          */
1548         vb2_set_plane_payload(&dst_buf->vb2_buf, 0,
1549                               partition->offset + partition->size);
1550
1551         curr = vb2_plane_vaddr(&dst_buf->vb2_buf, 0);
1552         free = partition->offset;
1553         if (msg->is_idr) {
1554                 len = allegro_h264_write_sps(channel, curr, free);
1555                 if (len < 0) {
1556                         v4l2_err(&dev->v4l2_dev,
1557                                  "not enough space for sequence parameter set: %zd left\n",
1558                                  free);
1559                         goto err;
1560                 }
1561                 curr += len;
1562                 free -= len;
1563                 v4l2_dbg(1, debug, &dev->v4l2_dev,
1564                          "channel %d: wrote %zd byte SPS nal unit\n",
1565                          channel->mcu_channel_id, len);
1566         }
1567
1568         if (msg->slice_type == AL_ENC_SLICE_TYPE_I) {
1569                 len = allegro_h264_write_pps(channel, curr, free);
1570                 if (len < 0) {
1571                         v4l2_err(&dev->v4l2_dev,
1572                                  "not enough space for picture parameter set: %zd left\n",
1573                                  free);
1574                         goto err;
1575                 }
1576                 curr += len;
1577                 free -= len;
1578                 v4l2_dbg(1, debug, &dev->v4l2_dev,
1579                          "channel %d: wrote %zd byte PPS nal unit\n",
1580                          channel->mcu_channel_id, len);
1581         }
1582
1583         if (msg->slice_type != AL_ENC_SLICE_TYPE_I && !msg->is_idr) {
1584                 dst_buf->vb2_buf.planes[0].data_offset = free;
1585                 free = 0;
1586         } else {
1587                 len = nal_h264_write_filler(&dev->plat_dev->dev, curr, free);
1588                 if (len < 0) {
1589                         v4l2_err(&dev->v4l2_dev,
1590                                  "failed to write %zd filler data\n", free);
1591                         goto err;
1592                 }
1593                 curr += len;
1594                 free -= len;
1595                 v4l2_dbg(2, debug, &dev->v4l2_dev,
1596                          "channel %d: wrote %zd bytes filler nal unit\n",
1597                          channel->mcu_channel_id, len);
1598         }
1599
1600         if (free != 0) {
1601                 v4l2_err(&dev->v4l2_dev,
1602                          "non-VCL NAL units do not fill space until VCL NAL unit: %zd bytes left\n",
1603                          free);
1604                 goto err;
1605         }
1606
1607         state = VB2_BUF_STATE_DONE;
1608
1609         v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, false);
1610         if (msg->is_idr)
1611                 dst_buf->flags |= V4L2_BUF_FLAG_KEYFRAME;
1612         else
1613                 dst_buf->flags |= V4L2_BUF_FLAG_PFRAME;
1614
1615         v4l2_dbg(1, debug, &dev->v4l2_dev,
1616                  "channel %d: encoded frame #%03d (%s%s, QP %d, %d bytes)\n",
1617                  channel->mcu_channel_id,
1618                  dst_buf->sequence,
1619                  msg->is_idr ? "IDR, " : "",
1620                  msg->slice_type == AL_ENC_SLICE_TYPE_I ? "I slice" :
1621                  msg->slice_type == AL_ENC_SLICE_TYPE_P ? "P slice" : "unknown",
1622                  msg->qp, partition->size);
1623
1624 err:
1625         if (src_buf)
1626                 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
1627
1628         if (dst_buf)
1629                 allegro_channel_buf_done(channel, dst_buf, state);
1630 }
1631
1632 static int allegro_handle_init(struct allegro_dev *dev,
1633                                struct mcu_msg_init_response *msg)
1634 {
1635         complete(&dev->init_complete);
1636
1637         return 0;
1638 }
1639
1640 static int
1641 allegro_handle_create_channel(struct allegro_dev *dev,
1642                               struct mcu_msg_create_channel_response *msg)
1643 {
1644         struct allegro_channel *channel;
1645         int err = 0;
1646         struct create_channel_param param;
1647
1648         channel = allegro_find_channel_by_user_id(dev, msg->user_id);
1649         if (IS_ERR(channel)) {
1650                 v4l2_warn(&dev->v4l2_dev,
1651                           "received %s for unknown user %d\n",
1652                           msg_type_name(msg->header.type),
1653                           msg->user_id);
1654                 return -EINVAL;
1655         }
1656
1657         if (msg->error_code) {
1658                 v4l2_err(&dev->v4l2_dev,
1659                          "user %d: mcu failed to create channel: %s (%x)\n",
1660                          channel->user_id,
1661                          allegro_err_to_string(msg->error_code),
1662                          msg->error_code);
1663                 err = -EIO;
1664                 goto out;
1665         }
1666
1667         channel->mcu_channel_id = msg->channel_id;
1668         v4l2_dbg(1, debug, &dev->v4l2_dev,
1669                  "user %d: channel has channel id %d\n",
1670                  channel->user_id, channel->mcu_channel_id);
1671
1672         err = allegro_decode_config_blob(&param, msg, channel->config_blob.vaddr);
1673         allegro_free_buffer(channel->dev, &channel->config_blob);
1674         if (err)
1675                 goto out;
1676
1677         channel->num_ref_idx_l0 = param.num_ref_idx_l0;
1678         channel->num_ref_idx_l1 = param.num_ref_idx_l1;
1679
1680         v4l2_dbg(1, debug, &dev->v4l2_dev,
1681                  "channel %d: intermediate buffers: %d x %d bytes\n",
1682                  channel->mcu_channel_id,
1683                  msg->int_buffers_count, msg->int_buffers_size);
1684         err = allocate_intermediate_buffers(channel, msg->int_buffers_count,
1685                                             msg->int_buffers_size);
1686         if (err) {
1687                 v4l2_err(&dev->v4l2_dev,
1688                          "channel %d: failed to allocate intermediate buffers\n",
1689                          channel->mcu_channel_id);
1690                 goto out;
1691         }
1692         err = allegro_mcu_push_buffer_intermediate(channel);
1693         if (err)
1694                 goto out;
1695
1696         v4l2_dbg(1, debug, &dev->v4l2_dev,
1697                  "channel %d: reference buffers: %d x %d bytes\n",
1698                  channel->mcu_channel_id,
1699                  msg->rec_buffers_count, msg->rec_buffers_size);
1700         err = allocate_reference_buffers(channel, msg->rec_buffers_count,
1701                                          msg->rec_buffers_size);
1702         if (err) {
1703                 v4l2_err(&dev->v4l2_dev,
1704                          "channel %d: failed to allocate reference buffers\n",
1705                          channel->mcu_channel_id);
1706                 goto out;
1707         }
1708         err = allegro_mcu_push_buffer_reference(channel);
1709         if (err)
1710                 goto out;
1711
1712 out:
1713         channel->error = err;
1714         complete(&channel->completion);
1715
1716         /* Handled successfully, error is passed via channel->error */
1717         return 0;
1718 }
1719
1720 static int
1721 allegro_handle_destroy_channel(struct allegro_dev *dev,
1722                                struct mcu_msg_destroy_channel_response *msg)
1723 {
1724         struct allegro_channel *channel;
1725
1726         channel = allegro_find_channel_by_channel_id(dev, msg->channel_id);
1727         if (IS_ERR(channel)) {
1728                 v4l2_err(&dev->v4l2_dev,
1729                          "received %s for unknown channel %d\n",
1730                          msg_type_name(msg->header.type),
1731                          msg->channel_id);
1732                 return -EINVAL;
1733         }
1734
1735         v4l2_dbg(2, debug, &dev->v4l2_dev,
1736                  "user %d: vcu destroyed channel %d\n",
1737                  channel->user_id, channel->mcu_channel_id);
1738         complete(&channel->completion);
1739
1740         return 0;
1741 }
1742
1743 static int
1744 allegro_handle_encode_frame(struct allegro_dev *dev,
1745                             struct mcu_msg_encode_frame_response *msg)
1746 {
1747         struct allegro_channel *channel;
1748
1749         channel = allegro_find_channel_by_channel_id(dev, msg->channel_id);
1750         if (IS_ERR(channel)) {
1751                 v4l2_err(&dev->v4l2_dev,
1752                          "received %s for unknown channel %d\n",
1753                          msg_type_name(msg->header.type),
1754                          msg->channel_id);
1755                 return -EINVAL;
1756         }
1757
1758         allegro_channel_finish_frame(channel, msg);
1759
1760         return 0;
1761 }
1762
1763 static void allegro_handle_message(struct allegro_dev *dev,
1764                                    union mcu_msg_response *msg)
1765 {
1766         switch (msg->header.type) {
1767         case MCU_MSG_TYPE_INIT:
1768                 allegro_handle_init(dev, &msg->init);
1769                 break;
1770         case MCU_MSG_TYPE_CREATE_CHANNEL:
1771                 allegro_handle_create_channel(dev, &msg->create_channel);
1772                 break;
1773         case MCU_MSG_TYPE_DESTROY_CHANNEL:
1774                 allegro_handle_destroy_channel(dev, &msg->destroy_channel);
1775                 break;
1776         case MCU_MSG_TYPE_ENCODE_FRAME:
1777                 allegro_handle_encode_frame(dev, &msg->encode_frame);
1778                 break;
1779         default:
1780                 v4l2_warn(&dev->v4l2_dev,
1781                           "%s: unknown message %s\n",
1782                           __func__, msg_type_name(msg->header.type));
1783                 break;
1784         }
1785 }
1786
1787 static irqreturn_t allegro_hardirq(int irq, void *data)
1788 {
1789         struct allegro_dev *dev = data;
1790         unsigned int status;
1791
1792         regmap_read(dev->regmap, AL5_ITC_CPU_IRQ_STA, &status);
1793         if (!(status & AL5_ITC_CPU_IRQ_STA_TRIGGERED))
1794                 return IRQ_NONE;
1795
1796         regmap_write(dev->regmap, AL5_ITC_CPU_IRQ_CLR, status);
1797
1798         return IRQ_WAKE_THREAD;
1799 }
1800
1801 static irqreturn_t allegro_irq_thread(int irq, void *data)
1802 {
1803         struct allegro_dev *dev = data;
1804
1805         /*
1806          * The firmware is initialized after the mailbox is setup. We further
1807          * check the AL5_ITC_CPU_IRQ_STA register, if the firmware actually
1808          * triggered the interrupt. Although this should not happen, make sure
1809          * that we ignore interrupts, if the mailbox is not initialized.
1810          */
1811         if (!dev->mbox_status)
1812                 return IRQ_NONE;
1813
1814         allegro_mbox_notify(dev->mbox_status);
1815
1816         return IRQ_HANDLED;
1817 }
1818
1819 static void allegro_copy_firmware(struct allegro_dev *dev,
1820                                   const u8 * const buf, size_t size)
1821 {
1822         int err = 0;
1823
1824         v4l2_dbg(1, debug, &dev->v4l2_dev,
1825                  "copy mcu firmware (%zu B) to SRAM\n", size);
1826         err = regmap_bulk_write(dev->sram, 0x0, buf, size / 4);
1827         if (err)
1828                 v4l2_err(&dev->v4l2_dev,
1829                          "failed to copy firmware: %d\n", err);
1830 }
1831
1832 static void allegro_copy_fw_codec(struct allegro_dev *dev,
1833                                   const u8 * const buf, size_t size)
1834 {
1835         int err;
1836         dma_addr_t icache_offset, dcache_offset;
1837
1838         /*
1839          * The downstream allocates 600 KB for the codec firmware to have some
1840          * extra space for "possible extensions." My tests were fine with
1841          * allocating just enough memory for the actual firmware, but I am not
1842          * sure that the firmware really does not use the remaining space.
1843          */
1844         err = allegro_alloc_buffer(dev, &dev->firmware, size);
1845         if (err) {
1846                 v4l2_err(&dev->v4l2_dev,
1847                          "failed to allocate %zu bytes for firmware\n", size);
1848                 return;
1849         }
1850
1851         v4l2_dbg(1, debug, &dev->v4l2_dev,
1852                  "copy codec firmware (%zd B) to phys %pad\n",
1853                  size, &dev->firmware.paddr);
1854         memcpy(dev->firmware.vaddr, buf, size);
1855
1856         regmap_write(dev->regmap, AXI_ADDR_OFFSET_IP,
1857                      upper_32_bits(dev->firmware.paddr));
1858
1859         icache_offset = dev->firmware.paddr - MCU_CACHE_OFFSET;
1860         v4l2_dbg(2, debug, &dev->v4l2_dev,
1861                  "icache_offset: msb = 0x%x, lsb = 0x%x\n",
1862                  upper_32_bits(icache_offset), lower_32_bits(icache_offset));
1863         regmap_write(dev->regmap, AL5_ICACHE_ADDR_OFFSET_MSB,
1864                      upper_32_bits(icache_offset));
1865         regmap_write(dev->regmap, AL5_ICACHE_ADDR_OFFSET_LSB,
1866                      lower_32_bits(icache_offset));
1867
1868         dcache_offset =
1869             (dev->firmware.paddr & 0xffffffff00000000ULL) - MCU_CACHE_OFFSET;
1870         v4l2_dbg(2, debug, &dev->v4l2_dev,
1871                  "dcache_offset: msb = 0x%x, lsb = 0x%x\n",
1872                  upper_32_bits(dcache_offset), lower_32_bits(dcache_offset));
1873         regmap_write(dev->regmap, AL5_DCACHE_ADDR_OFFSET_MSB,
1874                      upper_32_bits(dcache_offset));
1875         regmap_write(dev->regmap, AL5_DCACHE_ADDR_OFFSET_LSB,
1876                      lower_32_bits(dcache_offset));
1877 }
1878
1879 static void allegro_free_fw_codec(struct allegro_dev *dev)
1880 {
1881         allegro_free_buffer(dev, &dev->firmware);
1882 }
1883
1884 /*
1885  * Control functions for the MCU
1886  */
1887
1888 static int allegro_mcu_enable_interrupts(struct allegro_dev *dev)
1889 {
1890         return regmap_write(dev->regmap, AL5_ITC_CPU_IRQ_MSK, BIT(0));
1891 }
1892
1893 static int allegro_mcu_disable_interrupts(struct allegro_dev *dev)
1894 {
1895         return regmap_write(dev->regmap, AL5_ITC_CPU_IRQ_MSK, 0);
1896 }
1897
1898 static int allegro_mcu_wait_for_sleep(struct allegro_dev *dev)
1899 {
1900         unsigned long timeout;
1901         unsigned int status;
1902
1903         timeout = jiffies + msecs_to_jiffies(100);
1904         while (regmap_read(dev->regmap, AL5_MCU_STA, &status) == 0 &&
1905                status != AL5_MCU_STA_SLEEP) {
1906                 if (time_after(jiffies, timeout))
1907                         return -ETIMEDOUT;
1908                 cpu_relax();
1909         }
1910
1911         return 0;
1912 }
1913
1914 static int allegro_mcu_start(struct allegro_dev *dev)
1915 {
1916         unsigned long timeout;
1917         unsigned int status;
1918         int err;
1919
1920         err = regmap_write(dev->regmap, AL5_MCU_WAKEUP, BIT(0));
1921         if (err)
1922                 return err;
1923
1924         timeout = jiffies + msecs_to_jiffies(100);
1925         while (regmap_read(dev->regmap, AL5_MCU_STA, &status) == 0 &&
1926                status == AL5_MCU_STA_SLEEP) {
1927                 if (time_after(jiffies, timeout))
1928                         return -ETIMEDOUT;
1929                 cpu_relax();
1930         }
1931
1932         err = regmap_write(dev->regmap, AL5_MCU_WAKEUP, 0);
1933         if (err)
1934                 return err;
1935
1936         return 0;
1937 }
1938
1939 static int allegro_mcu_reset(struct allegro_dev *dev)
1940 {
1941         int err;
1942
1943         /*
1944          * Ensure that the AL5_MCU_WAKEUP bit is set to 0 otherwise the mcu
1945          * does not go to sleep after the reset.
1946          */
1947         err = regmap_write(dev->regmap, AL5_MCU_WAKEUP, 0);
1948         if (err)
1949                 return err;
1950
1951         err = regmap_write(dev->regmap,
1952                            AL5_MCU_RESET_MODE, AL5_MCU_RESET_MODE_SLEEP);
1953         if (err < 0)
1954                 return err;
1955
1956         err = regmap_write(dev->regmap, AL5_MCU_RESET, AL5_MCU_RESET_SOFT);
1957         if (err < 0)
1958                 return err;
1959
1960         return allegro_mcu_wait_for_sleep(dev);
1961 }
1962
1963 static void allegro_mcu_interrupt(struct allegro_dev *dev)
1964 {
1965         regmap_write(dev->regmap, AL5_MCU_INTERRUPT, BIT(0));
1966 }
1967
1968 static void allegro_destroy_channel(struct allegro_channel *channel)
1969 {
1970         struct allegro_dev *dev = channel->dev;
1971         unsigned long timeout;
1972
1973         if (channel_exists(channel)) {
1974                 reinit_completion(&channel->completion);
1975                 allegro_mcu_send_destroy_channel(dev, channel);
1976                 timeout = wait_for_completion_timeout(&channel->completion,
1977                                                       msecs_to_jiffies(5000));
1978                 if (timeout == 0)
1979                         v4l2_warn(&dev->v4l2_dev,
1980                                   "channel %d: timeout while destroying\n",
1981                                   channel->mcu_channel_id);
1982
1983                 channel->mcu_channel_id = -1;
1984         }
1985
1986         destroy_intermediate_buffers(channel);
1987         destroy_reference_buffers(channel);
1988
1989         v4l2_ctrl_grab(channel->mpeg_video_h264_profile, false);
1990         v4l2_ctrl_grab(channel->mpeg_video_h264_level, false);
1991         v4l2_ctrl_grab(channel->mpeg_video_h264_i_frame_qp, false);
1992         v4l2_ctrl_grab(channel->mpeg_video_h264_max_qp, false);
1993         v4l2_ctrl_grab(channel->mpeg_video_h264_min_qp, false);
1994         v4l2_ctrl_grab(channel->mpeg_video_h264_p_frame_qp, false);
1995         v4l2_ctrl_grab(channel->mpeg_video_h264_b_frame_qp, false);
1996         v4l2_ctrl_grab(channel->mpeg_video_frame_rc_enable, false);
1997         v4l2_ctrl_grab(channel->mpeg_video_bitrate_mode, false);
1998         v4l2_ctrl_grab(channel->mpeg_video_bitrate, false);
1999         v4l2_ctrl_grab(channel->mpeg_video_bitrate_peak, false);
2000         v4l2_ctrl_grab(channel->mpeg_video_cpb_size, false);
2001         v4l2_ctrl_grab(channel->mpeg_video_gop_size, false);
2002
2003         if (channel->user_id != -1) {
2004                 clear_bit(channel->user_id, &dev->channel_user_ids);
2005                 channel->user_id = -1;
2006         }
2007 }
2008
2009 /*
2010  * Create the MCU channel
2011  *
2012  * After the channel has been created, the picture size, format, colorspace
2013  * and framerate are fixed. Also the codec, profile, bitrate, etc. cannot be
2014  * changed anymore.
2015  *
2016  * The channel can be created only once. The MCU will accept source buffers
2017  * and stream buffers only after a channel has been created.
2018  */
2019 static int allegro_create_channel(struct allegro_channel *channel)
2020 {
2021         struct allegro_dev *dev = channel->dev;
2022         unsigned long timeout;
2023         enum v4l2_mpeg_video_h264_level min_level;
2024
2025         if (channel_exists(channel)) {
2026                 v4l2_warn(&dev->v4l2_dev,
2027                           "channel already exists\n");
2028                 return 0;
2029         }
2030
2031         channel->user_id = allegro_next_user_id(dev);
2032         if (channel->user_id < 0) {
2033                 v4l2_err(&dev->v4l2_dev,
2034                          "no free channels available\n");
2035                 return -EBUSY;
2036         }
2037         set_bit(channel->user_id, &dev->channel_user_ids);
2038
2039         v4l2_dbg(1, debug, &dev->v4l2_dev,
2040                  "user %d: creating channel (%4.4s, %dx%d@%d)\n",
2041                  channel->user_id,
2042                  (char *)&channel->codec, channel->width, channel->height,
2043                  DIV_ROUND_UP(channel->framerate.numerator,
2044                               channel->framerate.denominator));
2045
2046         min_level = select_minimum_h264_level(channel->width, channel->height);
2047         if (channel->level < min_level) {
2048                 v4l2_warn(&dev->v4l2_dev,
2049                           "user %d: selected Level %s too low: increasing to Level %s\n",
2050                           channel->user_id,
2051                           v4l2_ctrl_get_menu(V4L2_CID_MPEG_VIDEO_H264_LEVEL)[channel->level],
2052                           v4l2_ctrl_get_menu(V4L2_CID_MPEG_VIDEO_H264_LEVEL)[min_level]);
2053                 channel->level = min_level;
2054         }
2055
2056         v4l2_ctrl_grab(channel->mpeg_video_h264_profile, true);
2057         v4l2_ctrl_grab(channel->mpeg_video_h264_level, true);
2058         v4l2_ctrl_grab(channel->mpeg_video_h264_i_frame_qp, true);
2059         v4l2_ctrl_grab(channel->mpeg_video_h264_max_qp, true);
2060         v4l2_ctrl_grab(channel->mpeg_video_h264_min_qp, true);
2061         v4l2_ctrl_grab(channel->mpeg_video_h264_p_frame_qp, true);
2062         v4l2_ctrl_grab(channel->mpeg_video_h264_b_frame_qp, true);
2063         v4l2_ctrl_grab(channel->mpeg_video_frame_rc_enable, true);
2064         v4l2_ctrl_grab(channel->mpeg_video_bitrate_mode, true);
2065         v4l2_ctrl_grab(channel->mpeg_video_bitrate, true);
2066         v4l2_ctrl_grab(channel->mpeg_video_bitrate_peak, true);
2067         v4l2_ctrl_grab(channel->mpeg_video_cpb_size, true);
2068         v4l2_ctrl_grab(channel->mpeg_video_gop_size, true);
2069
2070         reinit_completion(&channel->completion);
2071         allegro_mcu_send_create_channel(dev, channel);
2072         timeout = wait_for_completion_timeout(&channel->completion,
2073                                               msecs_to_jiffies(5000));
2074         if (timeout == 0)
2075                 channel->error = -ETIMEDOUT;
2076         if (channel->error)
2077                 goto err;
2078
2079         v4l2_dbg(1, debug, &dev->v4l2_dev,
2080                  "channel %d: accepting buffers\n",
2081                  channel->mcu_channel_id);
2082
2083         return 0;
2084
2085 err:
2086         allegro_destroy_channel(channel);
2087
2088         return channel->error;
2089 }
2090
2091 static void allegro_set_default_params(struct allegro_channel *channel)
2092 {
2093         channel->width = ALLEGRO_WIDTH_DEFAULT;
2094         channel->height = ALLEGRO_HEIGHT_DEFAULT;
2095         channel->stride = round_up(channel->width, 32);
2096         channel->framerate = ALLEGRO_FRAMERATE_DEFAULT;
2097
2098         channel->colorspace = V4L2_COLORSPACE_REC709;
2099         channel->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
2100         channel->quantization = V4L2_QUANTIZATION_DEFAULT;
2101         channel->xfer_func = V4L2_XFER_FUNC_DEFAULT;
2102
2103         channel->pixelformat = V4L2_PIX_FMT_NV12;
2104         channel->sizeimage_raw = channel->stride * channel->height * 3 / 2;
2105
2106         channel->codec = V4L2_PIX_FMT_H264;
2107         channel->profile = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE;
2108         channel->level =
2109                 select_minimum_h264_level(channel->width, channel->height);
2110         channel->sizeimage_encoded =
2111                 estimate_stream_size(channel->width, channel->height);
2112
2113         channel->bitrate = maximum_bitrate(channel->level);
2114         channel->bitrate_peak = maximum_bitrate(channel->level);
2115         channel->cpb_size = maximum_cpb_size(channel->level);
2116         channel->gop_size = ALLEGRO_GOP_SIZE_DEFAULT;
2117 }
2118
2119 static int allegro_queue_setup(struct vb2_queue *vq,
2120                                unsigned int *nbuffers, unsigned int *nplanes,
2121                                unsigned int sizes[],
2122                                struct device *alloc_devs[])
2123 {
2124         struct allegro_channel *channel = vb2_get_drv_priv(vq);
2125         struct allegro_dev *dev = channel->dev;
2126
2127         v4l2_dbg(2, debug, &dev->v4l2_dev,
2128                  "%s: queue setup[%s]: nplanes = %d\n",
2129                  V4L2_TYPE_IS_OUTPUT(vq->type) ? "output" : "capture",
2130                  *nplanes == 0 ? "REQBUFS" : "CREATE_BUFS", *nplanes);
2131
2132         if (*nplanes != 0) {
2133                 if (V4L2_TYPE_IS_OUTPUT(vq->type)) {
2134                         if (sizes[0] < channel->sizeimage_raw)
2135                                 return -EINVAL;
2136                 } else {
2137                         if (sizes[0] < channel->sizeimage_encoded)
2138                                 return -EINVAL;
2139                 }
2140         } else {
2141                 *nplanes = 1;
2142                 if (V4L2_TYPE_IS_OUTPUT(vq->type))
2143                         sizes[0] = channel->sizeimage_raw;
2144                 else
2145                         sizes[0] = channel->sizeimage_encoded;
2146         }
2147
2148         return 0;
2149 }
2150
2151 static int allegro_buf_prepare(struct vb2_buffer *vb)
2152 {
2153         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2154         struct allegro_channel *channel = vb2_get_drv_priv(vb->vb2_queue);
2155         struct allegro_dev *dev = channel->dev;
2156
2157         if (allegro_get_state(channel) == ALLEGRO_STATE_DRAIN &&
2158             V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type))
2159                 return -EBUSY;
2160
2161         if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {
2162                 if (vbuf->field == V4L2_FIELD_ANY)
2163                         vbuf->field = V4L2_FIELD_NONE;
2164                 if (vbuf->field != V4L2_FIELD_NONE) {
2165                         v4l2_err(&dev->v4l2_dev,
2166                                  "channel %d: unsupported field\n",
2167                                  channel->mcu_channel_id);
2168                         return -EINVAL;
2169                 }
2170         }
2171
2172         return 0;
2173 }
2174
2175 static void allegro_buf_queue(struct vb2_buffer *vb)
2176 {
2177         struct allegro_channel *channel = vb2_get_drv_priv(vb->vb2_queue);
2178         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2179
2180         if (allegro_get_state(channel) == ALLEGRO_STATE_WAIT_FOR_BUFFER &&
2181             vb->vb2_queue->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
2182                 allegro_channel_buf_done(channel, vbuf, VB2_BUF_STATE_DONE);
2183                 return;
2184         }
2185
2186         v4l2_m2m_buf_queue(channel->fh.m2m_ctx, vbuf);
2187 }
2188
2189 static int allegro_start_streaming(struct vb2_queue *q, unsigned int count)
2190 {
2191         struct allegro_channel *channel = vb2_get_drv_priv(q);
2192         struct allegro_dev *dev = channel->dev;
2193
2194         v4l2_dbg(2, debug, &dev->v4l2_dev,
2195                  "%s: start streaming\n",
2196                  V4L2_TYPE_IS_OUTPUT(q->type) ? "output" : "capture");
2197
2198         if (V4L2_TYPE_IS_OUTPUT(q->type)) {
2199                 channel->osequence = 0;
2200                 allegro_set_state(channel, ALLEGRO_STATE_ENCODING);
2201         } else if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
2202                 channel->csequence = 0;
2203         }
2204
2205         return 0;
2206 }
2207
2208 static void allegro_stop_streaming(struct vb2_queue *q)
2209 {
2210         struct allegro_channel *channel = vb2_get_drv_priv(q);
2211         struct allegro_dev *dev = channel->dev;
2212         struct vb2_v4l2_buffer *buffer;
2213         struct allegro_m2m_buffer *shadow, *tmp;
2214
2215         v4l2_dbg(2, debug, &dev->v4l2_dev,
2216                  "%s: stop streaming\n",
2217                  V4L2_TYPE_IS_OUTPUT(q->type) ? "output" : "capture");
2218
2219         if (V4L2_TYPE_IS_OUTPUT(q->type)) {
2220                 mutex_lock(&channel->shadow_list_lock);
2221                 list_for_each_entry_safe(shadow, tmp,
2222                                          &channel->source_shadow_list, head) {
2223                         list_del(&shadow->head);
2224                         v4l2_m2m_buf_done(&shadow->buf.vb, VB2_BUF_STATE_ERROR);
2225                 }
2226                 mutex_unlock(&channel->shadow_list_lock);
2227
2228                 allegro_set_state(channel, ALLEGRO_STATE_STOPPED);
2229                 while ((buffer = v4l2_m2m_src_buf_remove(channel->fh.m2m_ctx)))
2230                         v4l2_m2m_buf_done(buffer, VB2_BUF_STATE_ERROR);
2231         } else if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
2232                 mutex_lock(&channel->shadow_list_lock);
2233                 list_for_each_entry_safe(shadow, tmp,
2234                                          &channel->stream_shadow_list, head) {
2235                         list_del(&shadow->head);
2236                         v4l2_m2m_buf_done(&shadow->buf.vb, VB2_BUF_STATE_ERROR);
2237                 }
2238                 mutex_unlock(&channel->shadow_list_lock);
2239
2240                 allegro_destroy_channel(channel);
2241                 while ((buffer = v4l2_m2m_dst_buf_remove(channel->fh.m2m_ctx)))
2242                         v4l2_m2m_buf_done(buffer, VB2_BUF_STATE_ERROR);
2243         }
2244 }
2245
2246 static const struct vb2_ops allegro_queue_ops = {
2247         .queue_setup = allegro_queue_setup,
2248         .buf_prepare = allegro_buf_prepare,
2249         .buf_queue = allegro_buf_queue,
2250         .start_streaming = allegro_start_streaming,
2251         .stop_streaming = allegro_stop_streaming,
2252         .wait_prepare = vb2_ops_wait_prepare,
2253         .wait_finish = vb2_ops_wait_finish,
2254 };
2255
2256 static int allegro_queue_init(void *priv,
2257                               struct vb2_queue *src_vq,
2258                               struct vb2_queue *dst_vq)
2259 {
2260         int err;
2261         struct allegro_channel *channel = priv;
2262
2263         src_vq->dev = &channel->dev->plat_dev->dev;
2264         src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
2265         src_vq->io_modes = VB2_DMABUF | VB2_MMAP;
2266         src_vq->mem_ops = &vb2_dma_contig_memops;
2267         src_vq->drv_priv = channel;
2268         src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2269         src_vq->ops = &allegro_queue_ops;
2270         src_vq->buf_struct_size = sizeof(struct allegro_m2m_buffer);
2271         src_vq->lock = &channel->dev->lock;
2272         err = vb2_queue_init(src_vq);
2273         if (err)
2274                 return err;
2275
2276         dst_vq->dev = &channel->dev->plat_dev->dev;
2277         dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2278         dst_vq->io_modes = VB2_DMABUF | VB2_MMAP;
2279         dst_vq->mem_ops = &vb2_dma_contig_memops;
2280         dst_vq->drv_priv = channel;
2281         dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2282         dst_vq->ops = &allegro_queue_ops;
2283         dst_vq->buf_struct_size = sizeof(struct allegro_m2m_buffer);
2284         dst_vq->lock = &channel->dev->lock;
2285         err = vb2_queue_init(dst_vq);
2286         if (err)
2287                 return err;
2288
2289         return 0;
2290 }
2291
2292 static int allegro_clamp_qp(struct allegro_channel *channel,
2293                             struct v4l2_ctrl *ctrl)
2294 {
2295         struct v4l2_ctrl *next_ctrl;
2296
2297         if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP)
2298                 next_ctrl = channel->mpeg_video_h264_p_frame_qp;
2299         else if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP)
2300                 next_ctrl = channel->mpeg_video_h264_b_frame_qp;
2301         else
2302                 return 0;
2303
2304         /* Modify range automatically updates the value */
2305         __v4l2_ctrl_modify_range(next_ctrl, ctrl->val, 51, 1, ctrl->val);
2306
2307         return allegro_clamp_qp(channel, next_ctrl);
2308 }
2309
2310 static int allegro_clamp_bitrate(struct allegro_channel *channel,
2311                                  struct v4l2_ctrl *ctrl)
2312 {
2313         struct v4l2_ctrl *ctrl_bitrate = channel->mpeg_video_bitrate;
2314         struct v4l2_ctrl *ctrl_bitrate_peak = channel->mpeg_video_bitrate_peak;
2315
2316         if (ctrl->val == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR &&
2317             ctrl_bitrate_peak->val < ctrl_bitrate->val)
2318                 ctrl_bitrate_peak->val = ctrl_bitrate->val;
2319
2320         return 0;
2321 }
2322
2323 static int allegro_try_ctrl(struct v4l2_ctrl *ctrl)
2324 {
2325         struct allegro_channel *channel = container_of(ctrl->handler,
2326                                                        struct allegro_channel,
2327                                                        ctrl_handler);
2328
2329         switch (ctrl->id) {
2330         case V4L2_CID_MPEG_VIDEO_BITRATE_MODE:
2331                 allegro_clamp_bitrate(channel, ctrl);
2332                 break;
2333         }
2334
2335         return 0;
2336 }
2337
2338 static int allegro_s_ctrl(struct v4l2_ctrl *ctrl)
2339 {
2340         struct allegro_channel *channel = container_of(ctrl->handler,
2341                                                        struct allegro_channel,
2342                                                        ctrl_handler);
2343         struct allegro_dev *dev = channel->dev;
2344
2345         v4l2_dbg(1, debug, &dev->v4l2_dev,
2346                  "s_ctrl: %s = %d\n", v4l2_ctrl_get_name(ctrl->id), ctrl->val);
2347
2348         switch (ctrl->id) {
2349         case V4L2_CID_MPEG_VIDEO_H264_LEVEL:
2350                 channel->level = ctrl->val;
2351                 break;
2352         case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE:
2353                 channel->frame_rc_enable = ctrl->val;
2354                 break;
2355         case V4L2_CID_MPEG_VIDEO_BITRATE_MODE:
2356                 channel->bitrate = channel->mpeg_video_bitrate->val;
2357                 channel->bitrate_peak = channel->mpeg_video_bitrate_peak->val;
2358                 v4l2_ctrl_activate(channel->mpeg_video_bitrate_peak,
2359                                    ctrl->val == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR);
2360                 break;
2361         case V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE:
2362                 channel->cpb_size = ctrl->val;
2363                 break;
2364         case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
2365                 channel->gop_size = ctrl->val;
2366                 break;
2367         case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP:
2368         case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP:
2369         case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP:
2370                 allegro_clamp_qp(channel, ctrl);
2371                 break;
2372         }
2373
2374         return 0;
2375 }
2376
2377 static const struct v4l2_ctrl_ops allegro_ctrl_ops = {
2378         .try_ctrl = allegro_try_ctrl,
2379         .s_ctrl = allegro_s_ctrl,
2380 };
2381
2382 static int allegro_open(struct file *file)
2383 {
2384         struct video_device *vdev = video_devdata(file);
2385         struct allegro_dev *dev = video_get_drvdata(vdev);
2386         struct allegro_channel *channel = NULL;
2387         struct v4l2_ctrl_handler *handler;
2388         u64 mask;
2389         int ret;
2390
2391         channel = kzalloc(sizeof(*channel), GFP_KERNEL);
2392         if (!channel)
2393                 return -ENOMEM;
2394
2395         v4l2_fh_init(&channel->fh, vdev);
2396
2397         init_completion(&channel->completion);
2398         INIT_LIST_HEAD(&channel->source_shadow_list);
2399         INIT_LIST_HEAD(&channel->stream_shadow_list);
2400         mutex_init(&channel->shadow_list_lock);
2401
2402         channel->dev = dev;
2403
2404         allegro_set_default_params(channel);
2405
2406         handler = &channel->ctrl_handler;
2407         v4l2_ctrl_handler_init(handler, 0);
2408         channel->mpeg_video_h264_profile = v4l2_ctrl_new_std_menu(handler,
2409                         &allegro_ctrl_ops,
2410                         V4L2_CID_MPEG_VIDEO_H264_PROFILE,
2411                         V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, 0x0,
2412                         V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE);
2413         mask = 1 << V4L2_MPEG_VIDEO_H264_LEVEL_1B;
2414         channel->mpeg_video_h264_level = v4l2_ctrl_new_std_menu(handler,
2415                         &allegro_ctrl_ops,
2416                         V4L2_CID_MPEG_VIDEO_H264_LEVEL,
2417                         V4L2_MPEG_VIDEO_H264_LEVEL_5_1, mask,
2418                         V4L2_MPEG_VIDEO_H264_LEVEL_5_1);
2419         channel->mpeg_video_h264_i_frame_qp =
2420                 v4l2_ctrl_new_std(handler,
2421                                   &allegro_ctrl_ops,
2422                                   V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP,
2423                                   0, 51, 1, 30);
2424         channel->mpeg_video_h264_max_qp =
2425                 v4l2_ctrl_new_std(handler,
2426                                   &allegro_ctrl_ops,
2427                                   V4L2_CID_MPEG_VIDEO_H264_MAX_QP,
2428                                   0, 51, 1, 51);
2429         channel->mpeg_video_h264_min_qp =
2430                 v4l2_ctrl_new_std(handler,
2431                                   &allegro_ctrl_ops,
2432                                   V4L2_CID_MPEG_VIDEO_H264_MIN_QP,
2433                                   0, 51, 1, 0);
2434         channel->mpeg_video_h264_p_frame_qp =
2435                 v4l2_ctrl_new_std(handler,
2436                                   &allegro_ctrl_ops,
2437                                   V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP,
2438                                   0, 51, 1, 30);
2439         channel->mpeg_video_h264_b_frame_qp =
2440                 v4l2_ctrl_new_std(handler,
2441                                   &allegro_ctrl_ops,
2442                                   V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP,
2443                                   0, 51, 1, 30);
2444         channel->mpeg_video_frame_rc_enable =
2445                 v4l2_ctrl_new_std(handler,
2446                                   &allegro_ctrl_ops,
2447                                   V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE,
2448                                   false, 0x1,
2449                                   true, false);
2450         channel->mpeg_video_bitrate_mode = v4l2_ctrl_new_std_menu(handler,
2451                         &allegro_ctrl_ops,
2452                         V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
2453                         V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, 0,
2454                         V4L2_MPEG_VIDEO_BITRATE_MODE_CBR);
2455         channel->mpeg_video_bitrate = v4l2_ctrl_new_std(handler,
2456                         &allegro_ctrl_ops,
2457                         V4L2_CID_MPEG_VIDEO_BITRATE,
2458                         0, maximum_bitrate(V4L2_MPEG_VIDEO_H264_LEVEL_5_1),
2459                         1, channel->bitrate);
2460         channel->mpeg_video_bitrate_peak = v4l2_ctrl_new_std(handler,
2461                         &allegro_ctrl_ops,
2462                         V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
2463                         0, maximum_bitrate(V4L2_MPEG_VIDEO_H264_LEVEL_5_1),
2464                         1, channel->bitrate_peak);
2465         channel->mpeg_video_cpb_size = v4l2_ctrl_new_std(handler,
2466                         &allegro_ctrl_ops,
2467                         V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE,
2468                         0, maximum_cpb_size(V4L2_MPEG_VIDEO_H264_LEVEL_5_1),
2469                         1, channel->cpb_size);
2470         channel->mpeg_video_gop_size = v4l2_ctrl_new_std(handler,
2471                         &allegro_ctrl_ops,
2472                         V4L2_CID_MPEG_VIDEO_GOP_SIZE,
2473                         0, ALLEGRO_GOP_SIZE_MAX,
2474                         1, channel->gop_size);
2475         v4l2_ctrl_new_std(handler,
2476                           &allegro_ctrl_ops,
2477                           V4L2_CID_MIN_BUFFERS_FOR_OUTPUT,
2478                           1, 32,
2479                           1, 1);
2480         if (handler->error != 0) {
2481                 ret = handler->error;
2482                 goto error;
2483         }
2484
2485         channel->fh.ctrl_handler = handler;
2486
2487         v4l2_ctrl_cluster(3, &channel->mpeg_video_bitrate_mode);
2488
2489         channel->mcu_channel_id = -1;
2490         channel->user_id = -1;
2491
2492         INIT_LIST_HEAD(&channel->buffers_reference);
2493         INIT_LIST_HEAD(&channel->buffers_intermediate);
2494
2495         channel->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, channel,
2496                                                 allegro_queue_init);
2497
2498         if (IS_ERR(channel->fh.m2m_ctx)) {
2499                 ret = PTR_ERR(channel->fh.m2m_ctx);
2500                 goto error;
2501         }
2502
2503         list_add(&channel->list, &dev->channels);
2504         file->private_data = &channel->fh;
2505         v4l2_fh_add(&channel->fh);
2506
2507         return 0;
2508
2509 error:
2510         v4l2_ctrl_handler_free(handler);
2511         kfree(channel);
2512         return ret;
2513 }
2514
2515 static int allegro_release(struct file *file)
2516 {
2517         struct allegro_channel *channel = fh_to_channel(file->private_data);
2518
2519         v4l2_m2m_ctx_release(channel->fh.m2m_ctx);
2520
2521         list_del(&channel->list);
2522
2523         v4l2_ctrl_handler_free(&channel->ctrl_handler);
2524
2525         v4l2_fh_del(&channel->fh);
2526         v4l2_fh_exit(&channel->fh);
2527
2528         kfree(channel);
2529
2530         return 0;
2531 }
2532
2533 static int allegro_querycap(struct file *file, void *fh,
2534                             struct v4l2_capability *cap)
2535 {
2536         struct video_device *vdev = video_devdata(file);
2537         struct allegro_dev *dev = video_get_drvdata(vdev);
2538
2539         strscpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver));
2540         strscpy(cap->card, "Allegro DVT Video Encoder", sizeof(cap->card));
2541         snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
2542                  dev_name(&dev->plat_dev->dev));
2543
2544         return 0;
2545 }
2546
2547 static int allegro_enum_fmt_vid(struct file *file, void *fh,
2548                                 struct v4l2_fmtdesc *f)
2549 {
2550         if (f->index)
2551                 return -EINVAL;
2552         switch (f->type) {
2553         case V4L2_BUF_TYPE_VIDEO_OUTPUT:
2554                 f->pixelformat = V4L2_PIX_FMT_NV12;
2555                 break;
2556         case V4L2_BUF_TYPE_VIDEO_CAPTURE:
2557                 f->pixelformat = V4L2_PIX_FMT_H264;
2558                 break;
2559         default:
2560                 return -EINVAL;
2561         }
2562         return 0;
2563 }
2564
2565 static int allegro_g_fmt_vid_cap(struct file *file, void *fh,
2566                                  struct v4l2_format *f)
2567 {
2568         struct allegro_channel *channel = fh_to_channel(fh);
2569
2570         f->fmt.pix.field = V4L2_FIELD_NONE;
2571         f->fmt.pix.width = channel->width;
2572         f->fmt.pix.height = channel->height;
2573
2574         f->fmt.pix.colorspace = channel->colorspace;
2575         f->fmt.pix.ycbcr_enc = channel->ycbcr_enc;
2576         f->fmt.pix.quantization = channel->quantization;
2577         f->fmt.pix.xfer_func = channel->xfer_func;
2578
2579         f->fmt.pix.pixelformat = channel->codec;
2580         f->fmt.pix.bytesperline = 0;
2581         f->fmt.pix.sizeimage = channel->sizeimage_encoded;
2582
2583         return 0;
2584 }
2585
2586 static int allegro_try_fmt_vid_cap(struct file *file, void *fh,
2587                                    struct v4l2_format *f)
2588 {
2589         f->fmt.pix.field = V4L2_FIELD_NONE;
2590
2591         f->fmt.pix.width = clamp_t(__u32, f->fmt.pix.width,
2592                                    ALLEGRO_WIDTH_MIN, ALLEGRO_WIDTH_MAX);
2593         f->fmt.pix.height = clamp_t(__u32, f->fmt.pix.height,
2594                                     ALLEGRO_HEIGHT_MIN, ALLEGRO_HEIGHT_MAX);
2595
2596         f->fmt.pix.pixelformat = V4L2_PIX_FMT_H264;
2597         f->fmt.pix.bytesperline = 0;
2598         f->fmt.pix.sizeimage =
2599                 estimate_stream_size(f->fmt.pix.width, f->fmt.pix.height);
2600
2601         return 0;
2602 }
2603
2604 static int allegro_g_fmt_vid_out(struct file *file, void *fh,
2605                                  struct v4l2_format *f)
2606 {
2607         struct allegro_channel *channel = fh_to_channel(fh);
2608
2609         f->fmt.pix.field = V4L2_FIELD_NONE;
2610
2611         f->fmt.pix.width = channel->width;
2612         f->fmt.pix.height = channel->height;
2613
2614         f->fmt.pix.colorspace = channel->colorspace;
2615         f->fmt.pix.ycbcr_enc = channel->ycbcr_enc;
2616         f->fmt.pix.quantization = channel->quantization;
2617         f->fmt.pix.xfer_func = channel->xfer_func;
2618
2619         f->fmt.pix.pixelformat = channel->pixelformat;
2620         f->fmt.pix.bytesperline = channel->stride;
2621         f->fmt.pix.sizeimage = channel->sizeimage_raw;
2622
2623         return 0;
2624 }
2625
2626 static int allegro_try_fmt_vid_out(struct file *file, void *fh,
2627                                    struct v4l2_format *f)
2628 {
2629         f->fmt.pix.field = V4L2_FIELD_NONE;
2630
2631         /*
2632          * The firmware of the Allegro codec handles the padding internally
2633          * and expects the visual frame size when configuring a channel.
2634          * Therefore, unlike other encoder drivers, this driver does not round
2635          * up the width and height to macroblock alignment and does not
2636          * implement the selection api.
2637          */
2638         f->fmt.pix.width = clamp_t(__u32, f->fmt.pix.width,
2639                                    ALLEGRO_WIDTH_MIN, ALLEGRO_WIDTH_MAX);
2640         f->fmt.pix.height = clamp_t(__u32, f->fmt.pix.height,
2641                                     ALLEGRO_HEIGHT_MIN, ALLEGRO_HEIGHT_MAX);
2642
2643         f->fmt.pix.pixelformat = V4L2_PIX_FMT_NV12;
2644         f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 32);
2645         f->fmt.pix.sizeimage =
2646                 f->fmt.pix.bytesperline * f->fmt.pix.height * 3 / 2;
2647
2648         return 0;
2649 }
2650
2651 static int allegro_s_fmt_vid_out(struct file *file, void *fh,
2652                                  struct v4l2_format *f)
2653 {
2654         struct allegro_channel *channel = fh_to_channel(fh);
2655         int err;
2656
2657         err = allegro_try_fmt_vid_out(file, fh, f);
2658         if (err)
2659                 return err;
2660
2661         channel->width = f->fmt.pix.width;
2662         channel->height = f->fmt.pix.height;
2663         channel->stride = f->fmt.pix.bytesperline;
2664         channel->sizeimage_raw = f->fmt.pix.sizeimage;
2665
2666         channel->colorspace = f->fmt.pix.colorspace;
2667         channel->ycbcr_enc = f->fmt.pix.ycbcr_enc;
2668         channel->quantization = f->fmt.pix.quantization;
2669         channel->xfer_func = f->fmt.pix.xfer_func;
2670
2671         channel->level =
2672                 select_minimum_h264_level(channel->width, channel->height);
2673         channel->sizeimage_encoded =
2674                 estimate_stream_size(channel->width, channel->height);
2675
2676         return 0;
2677 }
2678
2679 static int allegro_channel_cmd_stop(struct allegro_channel *channel)
2680 {
2681         struct allegro_dev *dev = channel->dev;
2682         struct vb2_v4l2_buffer *dst_buf;
2683
2684         switch (allegro_get_state(channel)) {
2685         case ALLEGRO_STATE_DRAIN:
2686         case ALLEGRO_STATE_WAIT_FOR_BUFFER:
2687                 return -EBUSY;
2688         case ALLEGRO_STATE_ENCODING:
2689                 allegro_set_state(channel, ALLEGRO_STATE_DRAIN);
2690                 break;
2691         default:
2692                 return 0;
2693         }
2694
2695         /* If there are output buffers, they must be encoded */
2696         if (v4l2_m2m_num_src_bufs_ready(channel->fh.m2m_ctx) != 0) {
2697                 v4l2_dbg(1, debug,  &dev->v4l2_dev,
2698                          "channel %d: CMD_STOP: continue encoding src buffers\n",
2699                          channel->mcu_channel_id);
2700                 return 0;
2701         }
2702
2703         /* If there are capture buffers, use it to signal EOS */
2704         dst_buf = v4l2_m2m_dst_buf_remove(channel->fh.m2m_ctx);
2705         if (dst_buf) {
2706                 v4l2_dbg(1, debug,  &dev->v4l2_dev,
2707                          "channel %d: CMD_STOP: signaling EOS\n",
2708                          channel->mcu_channel_id);
2709                 allegro_channel_buf_done(channel, dst_buf, VB2_BUF_STATE_DONE);
2710                 return 0;
2711         }
2712
2713         /*
2714          * If there are no capture buffers, we need to wait for the next
2715          * buffer to signal EOS.
2716          */
2717         v4l2_dbg(1, debug,  &dev->v4l2_dev,
2718                  "channel %d: CMD_STOP: wait for CAPTURE buffer to signal EOS\n",
2719                  channel->mcu_channel_id);
2720         allegro_set_state(channel, ALLEGRO_STATE_WAIT_FOR_BUFFER);
2721
2722         return 0;
2723 }
2724
2725 static int allegro_channel_cmd_start(struct allegro_channel *channel)
2726 {
2727         switch (allegro_get_state(channel)) {
2728         case ALLEGRO_STATE_DRAIN:
2729         case ALLEGRO_STATE_WAIT_FOR_BUFFER:
2730                 return -EBUSY;
2731         case ALLEGRO_STATE_STOPPED:
2732                 allegro_set_state(channel, ALLEGRO_STATE_ENCODING);
2733                 break;
2734         default:
2735                 return 0;
2736         }
2737
2738         return 0;
2739 }
2740
2741 static int allegro_encoder_cmd(struct file *file, void *fh,
2742                                struct v4l2_encoder_cmd *cmd)
2743 {
2744         struct allegro_channel *channel = fh_to_channel(fh);
2745         int err;
2746
2747         err = v4l2_m2m_ioctl_try_encoder_cmd(file, fh, cmd);
2748         if (err)
2749                 return err;
2750
2751         switch (cmd->cmd) {
2752         case V4L2_ENC_CMD_STOP:
2753                 err = allegro_channel_cmd_stop(channel);
2754                 break;
2755         case V4L2_ENC_CMD_START:
2756                 err = allegro_channel_cmd_start(channel);
2757                 break;
2758         default:
2759                 err = -EINVAL;
2760                 break;
2761         }
2762
2763         return err;
2764 }
2765
2766 static int allegro_enum_framesizes(struct file *file, void *fh,
2767                                    struct v4l2_frmsizeenum *fsize)
2768 {
2769         switch (fsize->pixel_format) {
2770         case V4L2_PIX_FMT_H264:
2771         case V4L2_PIX_FMT_NV12:
2772                 break;
2773         default:
2774                 return -EINVAL;
2775         }
2776
2777         if (fsize->index)
2778                 return -EINVAL;
2779
2780         fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
2781         fsize->stepwise.min_width = ALLEGRO_WIDTH_MIN;
2782         fsize->stepwise.max_width = ALLEGRO_WIDTH_MAX;
2783         fsize->stepwise.step_width = 1;
2784         fsize->stepwise.min_height = ALLEGRO_HEIGHT_MIN;
2785         fsize->stepwise.max_height = ALLEGRO_HEIGHT_MAX;
2786         fsize->stepwise.step_height = 1;
2787
2788         return 0;
2789 }
2790
2791 static int allegro_ioctl_streamon(struct file *file, void *priv,
2792                                   enum v4l2_buf_type type)
2793 {
2794         struct v4l2_fh *fh = file->private_data;
2795         struct allegro_channel *channel = fh_to_channel(fh);
2796         int err;
2797
2798         if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
2799                 err = allegro_create_channel(channel);
2800                 if (err)
2801                         return err;
2802         }
2803
2804         return v4l2_m2m_streamon(file, fh->m2m_ctx, type);
2805 }
2806
2807 static int allegro_g_parm(struct file *file, void *fh,
2808                           struct v4l2_streamparm *a)
2809 {
2810         struct allegro_channel *channel = fh_to_channel(fh);
2811         struct v4l2_fract *timeperframe;
2812
2813         if (a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
2814                 return -EINVAL;
2815
2816         a->parm.output.capability = V4L2_CAP_TIMEPERFRAME;
2817         timeperframe = &a->parm.output.timeperframe;
2818         timeperframe->numerator = channel->framerate.denominator;
2819         timeperframe->denominator = channel->framerate.numerator;
2820
2821         return 0;
2822 }
2823
2824 static int allegro_s_parm(struct file *file, void *fh,
2825                           struct v4l2_streamparm *a)
2826 {
2827         struct allegro_channel *channel = fh_to_channel(fh);
2828         struct v4l2_fract *timeperframe;
2829         int div;
2830
2831         if (a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
2832                 return -EINVAL;
2833
2834         a->parm.output.capability = V4L2_CAP_TIMEPERFRAME;
2835         timeperframe = &a->parm.output.timeperframe;
2836
2837         if (timeperframe->numerator == 0 || timeperframe->denominator == 0)
2838                 return allegro_g_parm(file, fh, a);
2839
2840         div = gcd(timeperframe->denominator, timeperframe->numerator);
2841         channel->framerate.numerator = timeperframe->denominator / div;
2842         channel->framerate.denominator = timeperframe->numerator / div;
2843
2844         return 0;
2845 }
2846
2847 static int allegro_subscribe_event(struct v4l2_fh *fh,
2848                                    const struct v4l2_event_subscription *sub)
2849 {
2850         switch (sub->type) {
2851         case V4L2_EVENT_EOS:
2852                 return v4l2_event_subscribe(fh, sub, 0, NULL);
2853         default:
2854                 return v4l2_ctrl_subscribe_event(fh, sub);
2855         }
2856 }
2857
2858 static const struct v4l2_ioctl_ops allegro_ioctl_ops = {
2859         .vidioc_querycap = allegro_querycap,
2860         .vidioc_enum_fmt_vid_cap = allegro_enum_fmt_vid,
2861         .vidioc_enum_fmt_vid_out = allegro_enum_fmt_vid,
2862         .vidioc_g_fmt_vid_cap = allegro_g_fmt_vid_cap,
2863         .vidioc_try_fmt_vid_cap = allegro_try_fmt_vid_cap,
2864         .vidioc_s_fmt_vid_cap = allegro_try_fmt_vid_cap,
2865         .vidioc_g_fmt_vid_out = allegro_g_fmt_vid_out,
2866         .vidioc_try_fmt_vid_out = allegro_try_fmt_vid_out,
2867         .vidioc_s_fmt_vid_out = allegro_s_fmt_vid_out,
2868
2869         .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
2870         .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
2871
2872         .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
2873         .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
2874         .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
2875         .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
2876         .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
2877
2878         .vidioc_streamon = allegro_ioctl_streamon,
2879         .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
2880
2881         .vidioc_try_encoder_cmd = v4l2_m2m_ioctl_try_encoder_cmd,
2882         .vidioc_encoder_cmd = allegro_encoder_cmd,
2883         .vidioc_enum_framesizes = allegro_enum_framesizes,
2884
2885         .vidioc_g_parm          = allegro_g_parm,
2886         .vidioc_s_parm          = allegro_s_parm,
2887
2888         .vidioc_subscribe_event = allegro_subscribe_event,
2889         .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
2890 };
2891
2892 static const struct v4l2_file_operations allegro_fops = {
2893         .owner = THIS_MODULE,
2894         .open = allegro_open,
2895         .release = allegro_release,
2896         .poll = v4l2_m2m_fop_poll,
2897         .unlocked_ioctl = video_ioctl2,
2898         .mmap = v4l2_m2m_fop_mmap,
2899 };
2900
2901 static int allegro_register_device(struct allegro_dev *dev)
2902 {
2903         struct video_device *video_dev = &dev->video_dev;
2904
2905         strscpy(video_dev->name, "allegro", sizeof(video_dev->name));
2906         video_dev->fops = &allegro_fops;
2907         video_dev->ioctl_ops = &allegro_ioctl_ops;
2908         video_dev->release = video_device_release_empty;
2909         video_dev->lock = &dev->lock;
2910         video_dev->v4l2_dev = &dev->v4l2_dev;
2911         video_dev->vfl_dir = VFL_DIR_M2M;
2912         video_dev->device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING;
2913         video_set_drvdata(video_dev, dev);
2914
2915         return video_register_device(video_dev, VFL_TYPE_VIDEO, 0);
2916 }
2917
2918 static void allegro_device_run(void *priv)
2919 {
2920         struct allegro_channel *channel = priv;
2921         struct allegro_dev *dev = channel->dev;
2922         struct vb2_v4l2_buffer *src_buf;
2923         struct vb2_v4l2_buffer *dst_buf;
2924         dma_addr_t src_y;
2925         dma_addr_t src_uv;
2926         dma_addr_t dst_addr;
2927         unsigned long dst_size;
2928         u64 src_handle;
2929         u64 dst_handle;
2930
2931         dst_buf = v4l2_m2m_dst_buf_remove(channel->fh.m2m_ctx);
2932         dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
2933         dst_size = vb2_plane_size(&dst_buf->vb2_buf, 0);
2934         dst_handle = allegro_put_buffer(channel, &channel->stream_shadow_list,
2935                                         dst_buf);
2936         allegro_mcu_send_put_stream_buffer(dev, channel, dst_addr, dst_size,
2937                                            dst_handle);
2938
2939         src_buf = v4l2_m2m_src_buf_remove(channel->fh.m2m_ctx);
2940         src_buf->sequence = channel->osequence++;
2941         src_y = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
2942         src_uv = src_y + (channel->stride * channel->height);
2943         src_handle = allegro_put_buffer(channel, &channel->source_shadow_list,
2944                                         src_buf);
2945         allegro_mcu_send_encode_frame(dev, channel, src_y, src_uv, src_handle);
2946
2947         v4l2_m2m_job_finish(dev->m2m_dev, channel->fh.m2m_ctx);
2948 }
2949
2950 static const struct v4l2_m2m_ops allegro_m2m_ops = {
2951         .device_run = allegro_device_run,
2952 };
2953
2954 static int allegro_mcu_hw_init(struct allegro_dev *dev,
2955                                const struct fw_info *info)
2956 {
2957         int err;
2958
2959         dev->mbox_command = allegro_mbox_init(dev, info->mailbox_cmd,
2960                                               info->mailbox_size);
2961         dev->mbox_status = allegro_mbox_init(dev, info->mailbox_status,
2962                                              info->mailbox_size);
2963         if (IS_ERR(dev->mbox_command) || IS_ERR(dev->mbox_status)) {
2964                 v4l2_err(&dev->v4l2_dev,
2965                          "failed to initialize mailboxes\n");
2966                 return -EIO;
2967         }
2968
2969         allegro_mcu_enable_interrupts(dev);
2970
2971         /* The mcu sends INIT after reset. */
2972         allegro_mcu_start(dev);
2973         err = allegro_mcu_wait_for_init_timeout(dev, 5000);
2974         if (err < 0) {
2975                 v4l2_err(&dev->v4l2_dev,
2976                          "mcu did not send INIT after reset\n");
2977                 err = -EIO;
2978                 goto err_disable_interrupts;
2979         }
2980
2981         err = allegro_alloc_buffer(dev, &dev->suballocator,
2982                                    info->suballocator_size);
2983         if (err) {
2984                 v4l2_err(&dev->v4l2_dev,
2985                          "failed to allocate %zu bytes for suballocator\n",
2986                          info->suballocator_size);
2987                 goto err_reset_mcu;
2988         }
2989
2990         allegro_mcu_send_init(dev, dev->suballocator.paddr,
2991                               dev->suballocator.size);
2992         err = allegro_mcu_wait_for_init_timeout(dev, 5000);
2993         if (err < 0) {
2994                 v4l2_err(&dev->v4l2_dev,
2995                          "mcu failed to configure sub-allocator\n");
2996                 err = -EIO;
2997                 goto err_free_suballocator;
2998         }
2999
3000         return 0;
3001
3002 err_free_suballocator:
3003         allegro_free_buffer(dev, &dev->suballocator);
3004 err_reset_mcu:
3005         allegro_mcu_reset(dev);
3006 err_disable_interrupts:
3007         allegro_mcu_disable_interrupts(dev);
3008
3009         return err;
3010 }
3011
3012 static int allegro_mcu_hw_deinit(struct allegro_dev *dev)
3013 {
3014         int err;
3015
3016         err = allegro_mcu_reset(dev);
3017         if (err)
3018                 v4l2_warn(&dev->v4l2_dev,
3019                           "mcu failed to enter sleep state\n");
3020
3021         err = allegro_mcu_disable_interrupts(dev);
3022         if (err)
3023                 v4l2_warn(&dev->v4l2_dev,
3024                           "failed to disable interrupts\n");
3025
3026         allegro_free_buffer(dev, &dev->suballocator);
3027
3028         return 0;
3029 }
3030
3031 static void allegro_fw_callback(const struct firmware *fw, void *context)
3032 {
3033         struct allegro_dev *dev = context;
3034         const char *fw_codec_name = "/*(DEBLOBBED)*/";
3035         const struct firmware *fw_codec;
3036         int err;
3037
3038         if (!fw)
3039                 return;
3040
3041         v4l2_dbg(1, debug, &dev->v4l2_dev,
3042                  "requesting codec firmware '%s'\n", fw_codec_name);
3043         err = reject_firmware(&fw_codec, fw_codec_name, &dev->plat_dev->dev);
3044         if (err)
3045                 goto err_release_firmware;
3046
3047         dev->fw_info = allegro_get_firmware_info(dev, fw, fw_codec);
3048         if (!dev->fw_info) {
3049                 v4l2_err(&dev->v4l2_dev, "firmware is not supported\n");
3050                 goto err_release_firmware_codec;
3051         }
3052
3053         v4l2_info(&dev->v4l2_dev,
3054                   "using mcu firmware version '%s'\n", dev->fw_info->version);
3055
3056         /* Ensure that the mcu is sleeping at the reset vector */
3057         err = allegro_mcu_reset(dev);
3058         if (err) {
3059                 v4l2_err(&dev->v4l2_dev, "failed to reset mcu\n");
3060                 goto err_release_firmware_codec;
3061         }
3062
3063         allegro_copy_firmware(dev, fw->data, fw->size);
3064         allegro_copy_fw_codec(dev, fw_codec->data, fw_codec->size);
3065
3066         err = allegro_mcu_hw_init(dev, dev->fw_info);
3067         if (err) {
3068                 v4l2_err(&dev->v4l2_dev, "failed to initialize mcu\n");
3069                 goto err_free_fw_codec;
3070         }
3071
3072         dev->m2m_dev = v4l2_m2m_init(&allegro_m2m_ops);
3073         if (IS_ERR(dev->m2m_dev)) {
3074                 v4l2_err(&dev->v4l2_dev, "failed to init mem2mem device\n");
3075                 goto err_mcu_hw_deinit;
3076         }
3077
3078         err = allegro_register_device(dev);
3079         if (err) {
3080                 v4l2_err(&dev->v4l2_dev, "failed to register video device\n");
3081                 goto err_m2m_release;
3082         }
3083
3084         v4l2_dbg(1, debug, &dev->v4l2_dev,
3085                  "allegro codec registered as /dev/video%d\n",
3086                  dev->video_dev.num);
3087
3088         release_firmware(fw_codec);
3089         release_firmware(fw);
3090
3091         return;
3092
3093 err_m2m_release:
3094         v4l2_m2m_release(dev->m2m_dev);
3095         dev->m2m_dev = NULL;
3096 err_mcu_hw_deinit:
3097         allegro_mcu_hw_deinit(dev);
3098 err_free_fw_codec:
3099         allegro_free_fw_codec(dev);
3100 err_release_firmware_codec:
3101         release_firmware(fw_codec);
3102 err_release_firmware:
3103         release_firmware(fw);
3104 }
3105
3106 static int allegro_firmware_request_nowait(struct allegro_dev *dev)
3107 {
3108         const char *fw = "/*(DEBLOBBED)*/";
3109
3110         v4l2_dbg(1, debug, &dev->v4l2_dev,
3111                  "requesting firmware '%s'\n", fw);
3112         return reject_firmware_nowait(THIS_MODULE, true, fw,
3113                                        &dev->plat_dev->dev, GFP_KERNEL, dev,
3114                                        allegro_fw_callback);
3115 }
3116
3117 static int allegro_probe(struct platform_device *pdev)
3118 {
3119         struct allegro_dev *dev;
3120         struct resource *res, *sram_res;
3121         int ret;
3122         int irq;
3123         void __iomem *regs, *sram_regs;
3124
3125         dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
3126         if (!dev)
3127                 return -ENOMEM;
3128         dev->plat_dev = pdev;
3129         init_completion(&dev->init_complete);
3130         INIT_LIST_HEAD(&dev->channels);
3131
3132         mutex_init(&dev->lock);
3133
3134         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
3135         if (!res) {
3136                 dev_err(&pdev->dev,
3137                         "regs resource missing from device tree\n");
3138                 return -EINVAL;
3139         }
3140         regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
3141         if (!regs) {
3142                 dev_err(&pdev->dev, "failed to map registers\n");
3143                 return -ENOMEM;
3144         }
3145         dev->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
3146                                             &allegro_regmap_config);
3147         if (IS_ERR(dev->regmap)) {
3148                 dev_err(&pdev->dev, "failed to init regmap\n");
3149                 return PTR_ERR(dev->regmap);
3150         }
3151
3152         sram_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
3153         if (!sram_res) {
3154                 dev_err(&pdev->dev,
3155                         "sram resource missing from device tree\n");
3156                 return -EINVAL;
3157         }
3158         sram_regs = devm_ioremap(&pdev->dev,
3159                                  sram_res->start,
3160                                  resource_size(sram_res));
3161         if (!sram_regs) {
3162                 dev_err(&pdev->dev, "failed to map sram\n");
3163                 return -ENOMEM;
3164         }
3165         dev->sram = devm_regmap_init_mmio(&pdev->dev, sram_regs,
3166                                           &allegro_sram_config);
3167         if (IS_ERR(dev->sram)) {
3168                 dev_err(&pdev->dev, "failed to init sram\n");
3169                 return PTR_ERR(dev->sram);
3170         }
3171
3172         irq = platform_get_irq(pdev, 0);
3173         if (irq < 0)
3174                 return irq;
3175         ret = devm_request_threaded_irq(&pdev->dev, irq,
3176                                         allegro_hardirq,
3177                                         allegro_irq_thread,
3178                                         IRQF_SHARED, dev_name(&pdev->dev), dev);
3179         if (ret < 0) {
3180                 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
3181                 return ret;
3182         }
3183
3184         ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
3185         if (ret)
3186                 return ret;
3187
3188         platform_set_drvdata(pdev, dev);
3189
3190         ret = allegro_firmware_request_nowait(dev);
3191         if (ret < 0) {
3192                 v4l2_err(&dev->v4l2_dev,
3193                          "failed to request firmware: %d\n", ret);
3194                 return ret;
3195         }
3196
3197         return 0;
3198 }
3199
3200 static int allegro_remove(struct platform_device *pdev)
3201 {
3202         struct allegro_dev *dev = platform_get_drvdata(pdev);
3203
3204         video_unregister_device(&dev->video_dev);
3205         if (dev->m2m_dev)
3206                 v4l2_m2m_release(dev->m2m_dev);
3207         allegro_mcu_hw_deinit(dev);
3208         allegro_free_fw_codec(dev);
3209
3210         v4l2_device_unregister(&dev->v4l2_dev);
3211
3212         return 0;
3213 }
3214
3215 static const struct of_device_id allegro_dt_ids[] = {
3216         { .compatible = "allegro,al5e-1.1" },
3217         { /* sentinel */ }
3218 };
3219
3220 MODULE_DEVICE_TABLE(of, allegro_dt_ids);
3221
3222 static struct platform_driver allegro_driver = {
3223         .probe = allegro_probe,
3224         .remove = allegro_remove,
3225         .driver = {
3226                 .name = "allegro",
3227                 .of_match_table = of_match_ptr(allegro_dt_ids),
3228         },
3229 };
3230
3231 module_platform_driver(allegro_driver);
3232
3233 MODULE_LICENSE("GPL");
3234 MODULE_AUTHOR("Michael Tretter <kernel@pengutronix.de>");
3235 MODULE_DESCRIPTION("Allegro DVT encoder driver");