drivers/staging/irda/drivers/sh_sir.c

   1 /*
   2  * SuperH IrDA Driver
   3  *
   4  * Copyright (C) 2009 Renesas Solutions Corp.
   5  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
   6  *
   7  * Based on bfin_sir.c
   8  * Copyright 2006-2009 Analog Devices Inc.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/io.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/module.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/slab.h>
  20 #include <net/irda/wrapper.h>
  21 #include <net/irda/irda_device.h>
  22 #include <asm/clock.h>
  23
  24 #define DRIVER_NAME "sh_sir"
  25
  26 #define RX_PHASE        (1 << 0)
  27 #define TX_PHASE        (1 << 1)
  28 #define TX_COMP_PHASE   (1 << 2) /* tx complete */
  29 #define NONE_PHASE      (1 << 31)
  30
  31 #define IRIF_RINTCLR    0x0016 /* DMA rx interrupt source clear */
  32 #define IRIF_TINTCLR    0x0018 /* DMA tx interrupt source clear */
  33 #define IRIF_SIR0       0x0020 /* IrDA-SIR10 control */
  34 #define IRIF_SIR1       0x0022 /* IrDA-SIR10 baudrate error correction */
  35 #define IRIF_SIR2       0x0024 /* IrDA-SIR10 baudrate count */
  36 #define IRIF_SIR3       0x0026 /* IrDA-SIR10 status */
  37 #define IRIF_SIR_FRM    0x0028 /* Hardware frame processing set */
  38 #define IRIF_SIR_EOF    0x002A /* EOF value */
  39 #define IRIF_SIR_FLG    0x002C /* Flag clear */
  40 #define IRIF_UART_STS2  0x002E /* UART status 2 */
  41 #define IRIF_UART0      0x0030 /* UART control */
  42 #define IRIF_UART1      0x0032 /* UART status */
  43 #define IRIF_UART2      0x0034 /* UART mode */
  44 #define IRIF_UART3      0x0036 /* UART transmit data */
  45 #define IRIF_UART4      0x0038 /* UART receive data */
  46 #define IRIF_UART5      0x003A /* UART interrupt mask */
  47 #define IRIF_UART6      0x003C /* UART baud rate error correction */
  48 #define IRIF_UART7      0x003E /* UART baud rate count set */
  49 #define IRIF_CRC0       0x0040 /* CRC engine control */
  50 #define IRIF_CRC1       0x0042 /* CRC engine input data */
  51 #define IRIF_CRC2       0x0044 /* CRC engine calculation */
  52 #define IRIF_CRC3       0x0046 /* CRC engine output data 1 */
  53 #define IRIF_CRC4       0x0048 /* CRC engine output data 2 */
  54
  55 /* IRIF_SIR0 */
  56 #define IRTPW           (1 << 1) /* transmit pulse width select */
  57 #define IRERRC          (1 << 0) /* Clear receive pulse width error */
  58
  59 /* IRIF_SIR3 */
  60 #define IRERR           (1 << 0) /* received pulse width Error */
  61
  62 /* IRIF_SIR_FRM */
  63 #define EOFD            (1 << 9) /* EOF detection flag */
  64 #define FRER            (1 << 8) /* Frame Error bit */
  65 #define FRP             (1 << 0) /* Frame processing set */
  66
  67 /* IRIF_UART_STS2 */
  68 #define IRSME           (1 << 6) /* Receive Sum     Error flag */
  69 #define IROVE           (1 << 5) /* Receive Overrun Error flag */
  70 #define IRFRE           (1 << 4) /* Receive Framing Error flag */
  71 #define IRPRE           (1 << 3) /* Receive Parity  Error flag */
  72
  73 /* IRIF_UART0_*/
  74 #define TBEC            (1 << 2) /* Transmit Data Clear */
  75 #define RIE             (1 << 1) /* Receive Enable */
  76 #define TIE             (1 << 0) /* Transmit Enable */
  77
  78 /* IRIF_UART1 */
  79 #define URSME           (1 << 6) /* Receive Sum Error Flag */
  80 #define UROVE           (1 << 5) /* Receive Overrun Error Flag */
  81 #define URFRE           (1 << 4) /* Receive Framing Error Flag */
  82 #define URPRE           (1 << 3) /* Receive Parity Error Flag */
  83 #define RBF             (1 << 2) /* Receive Buffer Full Flag */
  84 #define TSBE            (1 << 1) /* Transmit Shift Buffer Empty Flag */
  85 #define TBE             (1 << 0) /* Transmit Buffer Empty flag */
  86 #define TBCOMP          (TSBE | TBE)
  87
  88 /* IRIF_UART5 */
  89 #define RSEIM           (1 << 6) /* Receive Sum Error Flag IRQ Mask */
  90 #define RBFIM           (1 << 2) /* Receive Buffer Full Flag IRQ Mask */
  91 #define TSBEIM          (1 << 1) /* Transmit Shift Buffer Empty Flag IRQ Mask */
  92 #define TBEIM           (1 << 0) /* Transmit Buffer Empty Flag IRQ Mask */
  93 #define RX_MASK         (RSEIM  | RBFIM)
  94
  95 /* IRIF_CRC0 */
  96 #define CRC_RST         (1 << 15) /* CRC Engine Reset */
  97 #define CRC_CT_MASK     0x0FFF
  98
  99 /************************************************************************
 100
 101
 102                         structure
 103
 104
 105 ************************************************************************/
 106 struct sh_sir_self {
 107         void __iomem            *membase;
 108         unsigned int             irq;
 109         struct clk              *clk;
 110
 111         struct net_device       *ndev;
 112
 113         struct irlap_cb         *irlap;
 114         struct qos_info         qos;
 115
 116         iobuff_t                tx_buff;
 117         iobuff_t                rx_buff;
 118 };
 119
 120 /************************************************************************
 121
 122
 123                         common function
 124
 125
 126 ************************************************************************/
 127 static void sh_sir_write(struct sh_sir_self *self, u32 offset, u16 data)
 128 {
 129         iowrite16(data, self->membase + offset);
 130 }
 131
 132 static u16 sh_sir_read(struct sh_sir_self *self, u32 offset)
 133 {
 134         return ioread16(self->membase + offset);
 135 }
 136
 137 static void sh_sir_update_bits(struct sh_sir_self *self, u32 offset,
 138                                u16 mask, u16 data)
 139 {
 140         u16 old, new;
 141
 142         old = sh_sir_read(self, offset);
 143         new = (old & ~mask) | data;
 144         if (old != new)
 145                 sh_sir_write(self, offset, new);
 146 }
 147
 148 /************************************************************************
 149
 150
 151                         CRC function
 152
 153
 154 ************************************************************************/
 155 static void sh_sir_crc_reset(struct sh_sir_self *self)
 156 {
 157         sh_sir_write(self, IRIF_CRC0, CRC_RST);
 158 }
 159
 160 static void sh_sir_crc_add(struct sh_sir_self *self, u8 data)
 161 {
 162         sh_sir_write(self, IRIF_CRC1, (u16)data);
 163 }
 164
 165 static u16 sh_sir_crc_cnt(struct sh_sir_self *self)
 166 {
 167         return CRC_CT_MASK & sh_sir_read(self, IRIF_CRC0);
 168 }
 169
 170 static u16 sh_sir_crc_out(struct sh_sir_self *self)
 171 {
 172         return sh_sir_read(self, IRIF_CRC4);
 173 }
 174
 175 static int sh_sir_crc_init(struct sh_sir_self *self)
 176 {
 177         struct device *dev = &self->ndev->dev;
 178         int ret = -EIO;
 179         u16 val;
 180
 181         sh_sir_crc_reset(self);
 182
 183         sh_sir_crc_add(self, 0xCC);
 184         sh_sir_crc_add(self, 0xF5);
 185         sh_sir_crc_add(self, 0xF1);
 186         sh_sir_crc_add(self, 0xA7);
 187
 188         val = sh_sir_crc_cnt(self);
 189         if (4 != val) {
 190                 dev_err(dev, "CRC count error %x\n", val);
 191                 goto crc_init_out;
 192         }
 193
 194         val = sh_sir_crc_out(self);
 195         if (0x51DF != val) {
 196                 dev_err(dev, "CRC result error%x\n", val);
 197                 goto crc_init_out;
 198         }
 199
 200         ret = 0;
 201
 202 crc_init_out:
 203
 204         sh_sir_crc_reset(self);
 205         return ret;
 206 }
 207
 208 /************************************************************************
 209
 210
 211                         baud rate functions
 212
 213
 214 ************************************************************************/
 215 #define SCLK_BASE 1843200 /* 1.8432MHz */
 216
 217 static u32 sh_sir_find_sclk(struct clk *irda_clk)
 218 {
 219         struct cpufreq_frequency_table *freq_table = irda_clk->freq_table;
 220         struct cpufreq_frequency_table *pos;
 221         struct clk *pclk = clk_get(NULL, "peripheral_clk");
 222         u32 limit, min = 0xffffffff, tmp;
 223         int index = 0;
 224
 225         limit = clk_get_rate(pclk);
 226         clk_put(pclk);
 227
 228         /* IrDA can not set over peripheral_clk */
 229         cpufreq_for_each_valid_entry(pos, freq_table) {
 230                 u32 freq = pos->frequency;
 231
 232                 /* IrDA should not over peripheral_clk */
 233                 if (freq > limit)
 234                         continue;
 235
 236                 tmp = freq % SCLK_BASE;
 237                 if (tmp < min) {
 238                         min = tmp;
 239                         index = pos - freq_table;
 240                 }
 241         }
 242
 243         return freq_table[index].frequency;
 244 }
 245
 246 #define ERR_ROUNDING(a) ((a + 5000) / 10000)
 247 static int sh_sir_set_baudrate(struct sh_sir_self *self, u32 baudrate)
 248 {
 249         struct clk *clk;
 250         struct device *dev = &self->ndev->dev;
 251         u32 rate;
 252         u16 uabca, uabc;
 253         u16 irbca, irbc;
 254         u32 min, rerr, tmp;
 255         int i;
 256
 257         /* Baud Rate Error Correction x 10000 */
 258         u32 rate_err_array[] = {
 259                    0,  625, 1250, 1875,
 260                 2500, 3125, 3750, 4375,
 261                 5000, 5625, 6250, 6875,
 262                 7500, 8125, 8750, 9375,
 263         };
 264
 265         /*
 266          * FIXME
 267          *
 268          * it support 9600 only now
 269          */
 270         switch (baudrate) {
 271         case 9600:
 272                 break;
 273         default:
 274                 dev_err(dev, "un-supported baudrate %d\n", baudrate);
 275                 return -EIO;
 276         }
 277
 278         clk = clk_get(NULL, "irda_clk");
 279         if (IS_ERR(clk)) {
 280                 dev_err(dev, "can not get irda_clk\n");
 281                 return -EIO;
 282         }
 283
 284         clk_set_rate(clk, sh_sir_find_sclk(clk));
 285         rate = clk_get_rate(clk);
 286         clk_put(clk);
 287
 288         dev_dbg(dev, "selected sclk = %d\n", rate);
 289
 290         /*
 291          * CALCULATION
 292          *
 293          * 1843200 = system rate / (irbca + (irbc + 1))
 294          */
 295
 296         irbc = rate / SCLK_BASE;
 297
 298         tmp = rate - (SCLK_BASE * irbc);
 299         tmp *= 10000;
 300
 301         rerr = tmp / SCLK_BASE;
 302
 303         min = 0xffffffff;
 304         irbca = 0;
 305         for (i = 0; i < ARRAY_SIZE(rate_err_array); i++) {
 306                 tmp = abs(rate_err_array[i] - rerr);
 307                 if (min > tmp) {
 308                         min = tmp;
 309                         irbca = i;
 310                 }
 311         }
 312
 313         tmp = rate / (irbc + ERR_ROUNDING(rate_err_array[irbca]));
 314         if ((SCLK_BASE / 100) < abs(tmp - SCLK_BASE))
 315                 dev_warn(dev, "IrDA freq error margin over %d\n", tmp);
 316
 317         dev_dbg(dev, "target = %d, result = %d, infrared = %d.%d\n",
 318                SCLK_BASE, tmp, irbc, rate_err_array[irbca]);
 319
 320         irbca = (irbca & 0xF) << 4;
 321         irbc  = (irbc - 1) & 0xF;
 322
 323         if (!irbc) {
 324                 dev_err(dev, "sh_sir can not set 0 in IRIF_SIR2\n");
 325                 return -EIO;
 326         }
 327
 328         sh_sir_write(self, IRIF_SIR0, IRTPW | IRERRC);
 329         sh_sir_write(self, IRIF_SIR1, irbca);
 330         sh_sir_write(self, IRIF_SIR2, irbc);
 331
 332         /*
 333          * CALCULATION
 334          *
 335          * BaudRate[bps] = system rate / (uabca + (uabc + 1) x 16)
 336          */
 337
 338         uabc = rate / baudrate;
 339         uabc = (uabc / 16) - 1;
 340         uabc = (uabc + 1) * 16;
 341
 342         tmp = rate - (uabc * baudrate);
 343         tmp *= 10000;
 344
 345         rerr = tmp / baudrate;
 346
 347         min = 0xffffffff;
 348         uabca = 0;
 349         for (i = 0; i < ARRAY_SIZE(rate_err_array); i++) {
 350                 tmp = abs(rate_err_array[i] - rerr);
 351                 if (min > tmp) {
 352                         min = tmp;
 353                         uabca = i;
 354                 }
 355         }
 356
 357         tmp = rate / (uabc + ERR_ROUNDING(rate_err_array[uabca]));
 358         if ((baudrate / 100) < abs(tmp - baudrate))
 359                 dev_warn(dev, "UART freq error margin over %d\n", tmp);
 360
 361         dev_dbg(dev, "target = %d, result = %d, uart = %d.%d\n",
 362                baudrate, tmp,
 363                uabc, rate_err_array[uabca]);
 364
 365         uabca = (uabca & 0xF) << 4;
 366         uabc  = (uabc / 16) - 1;
 367
 368         sh_sir_write(self, IRIF_UART6, uabca);
 369         sh_sir_write(self, IRIF_UART7, uabc);
 370
 371         return 0;
 372 }
 373
 374 /************************************************************************
 375
 376
 377                         iobuf function
 378
 379
 380 ************************************************************************/
 381 static int __sh_sir_init_iobuf(iobuff_t *io, int size)
 382 {
 383         io->head = kmalloc(size, GFP_KERNEL);
 384         if (!io->head)
 385                 return -ENOMEM;
 386
 387         io->truesize    = size;
 388         io->in_frame    = FALSE;
 389         io->state       = OUTSIDE_FRAME;
 390         io->data        = io->head;
 391
 392         return 0;
 393 }
 394
 395 static void sh_sir_remove_iobuf(struct sh_sir_self *self)
 396 {
 397         kfree(self->rx_buff.head);
 398         kfree(self->tx_buff.head);
 399
 400         self->rx_buff.head = NULL;
 401         self->tx_buff.head = NULL;
 402 }
 403
 404 static int sh_sir_init_iobuf(struct sh_sir_self *self, int rxsize, int txsize)
 405 {
 406         int err = -ENOMEM;
 407
 408         if (self->rx_buff.head ||
 409             self->tx_buff.head) {
 410                 dev_err(&self->ndev->dev, "iobuff has already existed.");
 411                 return err;
 412         }
 413
 414         err = __sh_sir_init_iobuf(&self->rx_buff, rxsize);
 415         if (err)
 416                 goto iobuf_err;
 417
 418         err = __sh_sir_init_iobuf(&self->tx_buff, txsize);
 419
 420 iobuf_err:
 421         if (err)
 422                 sh_sir_remove_iobuf(self);
 423
 424         return err;
 425 }
 426
 427 /************************************************************************
 428
 429
 430                         status function
 431
 432
 433 ************************************************************************/
 434 static void sh_sir_clear_all_err(struct sh_sir_self *self)
 435 {
 436         /* Clear error flag for receive pulse width */
 437         sh_sir_update_bits(self, IRIF_SIR0, IRERRC, IRERRC);
 438
 439         /* Clear frame / EOF error flag */
 440         sh_sir_write(self, IRIF_SIR_FLG, 0xffff);
 441
 442         /* Clear all status error */
 443         sh_sir_write(self, IRIF_UART_STS2, 0);
 444 }
 445
 446 static void sh_sir_set_phase(struct sh_sir_self *self, int phase)
 447 {
 448         u16 uart5 = 0;
 449         u16 uart0 = 0;
 450
 451         switch (phase) {
 452         case TX_PHASE:
 453                 uart5 = TBEIM;
 454                 uart0 = TBEC | TIE;
 455                 break;
 456         case TX_COMP_PHASE:
 457                 uart5 = TSBEIM;
 458                 uart0 = TIE;
 459                 break;
 460         case RX_PHASE:
 461                 uart5 = RX_MASK;
 462                 uart0 = RIE;
 463                 break;
 464         default:
 465                 break;
 466         }
 467
 468         sh_sir_write(self, IRIF_UART5, uart5);
 469         sh_sir_write(self, IRIF_UART0, uart0);
 470 }
 471
 472 static int sh_sir_is_which_phase(struct sh_sir_self *self)
 473 {
 474         u16 val = sh_sir_read(self, IRIF_UART5);
 475
 476         if (val & TBEIM)
 477                 return TX_PHASE;
 478
 479         if (val & TSBEIM)
 480                 return TX_COMP_PHASE;
 481
 482         if (val & RX_MASK)
 483                 return RX_PHASE;
 484
 485         return NONE_PHASE;
 486 }
 487
 488 static void sh_sir_tx(struct sh_sir_self *self, int phase)
 489 {
 490         switch (phase) {
 491         case TX_PHASE:
 492                 if (0 >= self->tx_buff.len) {
 493                         sh_sir_set_phase(self, TX_COMP_PHASE);
 494                 } else {
 495                         sh_sir_write(self, IRIF_UART3, self->tx_buff.data[0]);
 496                         self->tx_buff.len--;
 497                         self->tx_buff.data++;
 498                 }
 499                 break;
 500         case TX_COMP_PHASE:
 501                 sh_sir_set_phase(self, RX_PHASE);
 502                 netif_wake_queue(self->ndev);
 503                 break;
 504         default:
 505                 dev_err(&self->ndev->dev, "should not happen\n");
 506                 break;
 507         }
 508 }
 509
 510 static int sh_sir_read_data(struct sh_sir_self *self)
 511 {
 512         u16 val = 0;
 513         int timeout = 1024;
 514
 515         while (timeout--) {
 516                 val = sh_sir_read(self, IRIF_UART1);
 517
 518                 /* data get */
 519                 if (val & RBF) {
 520                         if (val & (URSME | UROVE | URFRE | URPRE))
 521                                 break;
 522
 523                         return (int)sh_sir_read(self, IRIF_UART4);
 524                 }
 525
 526                 udelay(1);
 527         }
 528
 529         dev_err(&self->ndev->dev, "UART1 %04x : STATUS %04x\n",
 530                 val, sh_sir_read(self, IRIF_UART_STS2));
 531
 532         /* read data register for clear error */
 533         sh_sir_read(self, IRIF_UART4);
 534
 535         return -1;
 536 }
 537
 538 static void sh_sir_rx(struct sh_sir_self *self)
 539 {
 540         int timeout = 1024;
 541         int data;
 542
 543         while (timeout--) {
 544                 data = sh_sir_read_data(self);
 545                 if (data < 0)
 546                         break;
 547
 548                 async_unwrap_char(self->ndev, &self->ndev->stats,
 549                                   &self->rx_buff, (u8)data);
 550
 551                 if (EOFD & sh_sir_read(self, IRIF_SIR_FRM))
 552                         continue;
 553
 554                 break;
 555         }
 556 }
 557
 558 static irqreturn_t sh_sir_irq(int irq, void *dev_id)
 559 {
 560         struct sh_sir_self *self = dev_id;
 561         struct device *dev = &self->ndev->dev;
 562         int phase = sh_sir_is_which_phase(self);
 563
 564         switch (phase) {
 565         case TX_COMP_PHASE:
 566         case TX_PHASE:
 567                 sh_sir_tx(self, phase);
 568                 break;
 569         case RX_PHASE:
 570                 if (sh_sir_read(self, IRIF_SIR3))
 571                         dev_err(dev, "rcv pulse width error occurred\n");
 572
 573                 sh_sir_rx(self);
 574                 sh_sir_clear_all_err(self);
 575                 break;
 576         default:
 577                 dev_err(dev, "unknown interrupt\n");
 578         }
 579
 580          return IRQ_HANDLED;
 581 }
 582
 583 /************************************************************************
 584
 585
 586                         net_device_ops function
 587
 588
 589 ************************************************************************/
 590 static int sh_sir_hard_xmit(struct sk_buff *skb, struct net_device *ndev)
 591 {
 592         struct sh_sir_self *self = netdev_priv(ndev);
 593         int speed = irda_get_next_speed(skb);
 594
 595         if ((0 < speed) &&
 596             (9600 != speed)) {
 597                 dev_err(&ndev->dev, "support 9600 only (%d)\n", speed);
 598                 return -EIO;
 599         }
 600
 601         netif_stop_queue(ndev);
 602
 603         self->tx_buff.data = self->tx_buff.head;
 604         self->tx_buff.len = 0;
 605         if (skb->len)
 606                 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
 607                                                    self->tx_buff.truesize);
 608
 609         sh_sir_set_phase(self, TX_PHASE);
 610         dev_kfree_skb(skb);
 611
 612         return 0;
 613 }
 614
 615 static int sh_sir_ioctl(struct net_device *ndev, struct ifreq *ifreq, int cmd)
 616 {
 617         /*
 618          * FIXME
 619          *
 620          * This function is needed for irda framework.
 621          * But nothing to do now
 622          */
 623         return 0;
 624 }
 625
 626 static struct net_device_stats *sh_sir_stats(struct net_device *ndev)
 627 {
 628         struct sh_sir_self *self = netdev_priv(ndev);
 629
 630         return &self->ndev->stats;
 631 }
 632
 633 static int sh_sir_open(struct net_device *ndev)
 634 {
 635         struct sh_sir_self *self = netdev_priv(ndev);
 636         int err;
 637
 638         clk_enable(self->clk);
 639         err = sh_sir_crc_init(self);
 640         if (err)
 641                 goto open_err;
 642
 643         sh_sir_set_baudrate(self, 9600);
 644
 645         self->irlap = irlap_open(ndev, &self->qos, DRIVER_NAME);
 646         if (!self->irlap) {
 647                 err = -ENODEV;
 648                 goto open_err;
 649         }
 650
 651         /*
 652          * Now enable the interrupt then start the queue
 653          */
 654         sh_sir_update_bits(self, IRIF_SIR_FRM, FRP, FRP);
 655         sh_sir_read(self, IRIF_UART1); /* flag clear */
 656         sh_sir_read(self, IRIF_UART4); /* flag clear */
 657         sh_sir_set_phase(self, RX_PHASE);
 658
 659         netif_start_queue(ndev);
 660
 661         dev_info(&self->ndev->dev, "opened\n");
 662
 663         return 0;
 664
 665 open_err:
 666         clk_disable(self->clk);
 667
 668         return err;
 669 }
 670
 671 static int sh_sir_stop(struct net_device *ndev)
 672 {
 673         struct sh_sir_self *self = netdev_priv(ndev);
 674
 675         /* Stop IrLAP */
 676         if (self->irlap) {
 677                 irlap_close(self->irlap);
 678                 self->irlap = NULL;
 679         }
 680
 681         netif_stop_queue(ndev);
 682
 683         dev_info(&ndev->dev, "stopped\n");
 684
 685         return 0;
 686 }
 687
 688 static const struct net_device_ops sh_sir_ndo = {
 689         .ndo_open               = sh_sir_open,
 690         .ndo_stop               = sh_sir_stop,
 691         .ndo_start_xmit         = sh_sir_hard_xmit,
 692         .ndo_do_ioctl           = sh_sir_ioctl,
 693         .ndo_get_stats          = sh_sir_stats,
 694 };
 695
 696 /************************************************************************
 697
 698
 699                         platform_driver function
 700
 701
 702 ************************************************************************/
 703 static int sh_sir_probe(struct platform_device *pdev)
 704 {
 705         struct net_device *ndev;
 706         struct sh_sir_self *self;
 707         struct resource *res;
 708         char clk_name[8];
 709         int irq;
 710         int err = -ENOMEM;
 711
 712         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 713         irq = platform_get_irq(pdev, 0);
 714         if (!res || irq < 0) {
 715                 dev_err(&pdev->dev, "Not enough platform resources.\n");
 716                 goto exit;
 717         }
 718
 719         ndev = alloc_irdadev(sizeof(*self));
 720         if (!ndev)
 721                 goto exit;
 722
 723         self = netdev_priv(ndev);
 724         self->membase = ioremap_nocache(res->start, resource_size(res));
 725         if (!self->membase) {
 726                 err = -ENXIO;
 727                 dev_err(&pdev->dev, "Unable to ioremap.\n");
 728                 goto err_mem_1;
 729         }
 730
 731         err = sh_sir_init_iobuf(self, IRDA_SKB_MAX_MTU, IRDA_SIR_MAX_FRAME);
 732         if (err)
 733                 goto err_mem_2;
 734
 735         snprintf(clk_name, sizeof(clk_name), "irda%d", pdev->id);
 736         self->clk = clk_get(&pdev->dev, clk_name);
 737         if (IS_ERR(self->clk)) {
 738                 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
 739                 err = -ENODEV;
 740                 goto err_mem_3;
 741         }
 742
 743         irda_init_max_qos_capabilies(&self->qos);
 744
 745         ndev->netdev_ops        = &sh_sir_ndo;
 746         ndev->irq               = irq;
 747
 748         self->ndev                      = ndev;
 749         self->qos.baud_rate.bits        &= IR_9600; /* FIXME */
 750         self->qos.min_turn_time.bits    = 1; /* 10 ms or more */
 751
 752         irda_qos_bits_to_value(&self->qos);
 753
 754         err = register_netdev(ndev);
 755         if (err)
 756                 goto err_mem_4;
 757
 758         platform_set_drvdata(pdev, ndev);
 759         err = devm_request_irq(&pdev->dev, irq, sh_sir_irq, 0, "sh_sir", self);
 760         if (err) {
 761                 dev_warn(&pdev->dev, "Unable to attach sh_sir interrupt\n");
 762                 goto err_mem_4;
 763         }
 764
 765         dev_info(&pdev->dev, "SuperH IrDA probed\n");
 766
 767         goto exit;
 768
 769 err_mem_4:
 770         clk_put(self->clk);
 771 err_mem_3:
 772         sh_sir_remove_iobuf(self);
 773 err_mem_2:
 774         iounmap(self->membase);
 775 err_mem_1:
 776         free_netdev(ndev);
 777 exit:
 778         return err;
 779 }
 780
 781 static int sh_sir_remove(struct platform_device *pdev)
 782 {
 783         struct net_device *ndev = platform_get_drvdata(pdev);
 784         struct sh_sir_self *self = netdev_priv(ndev);
 785
 786         if (!self)
 787                 return 0;
 788
 789         unregister_netdev(ndev);
 790         clk_put(self->clk);
 791         sh_sir_remove_iobuf(self);
 792         iounmap(self->membase);
 793         free_netdev(ndev);
 794
 795         return 0;
 796 }
 797
 798 static struct platform_driver sh_sir_driver = {
 799         .probe   = sh_sir_probe,
 800         .remove  = sh_sir_remove,
 801         .driver  = {
 802                 .name = DRIVER_NAME,
 803         },
 804 };
 805
 806 module_platform_driver(sh_sir_driver);
 807
 808 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
 809 MODULE_DESCRIPTION("SuperH IrDA driver");
 810 MODULE_LICENSE("GPL");