drivers/staging/iio/meter/ade7758_core.c

   1 /*
   2  * ADE7758 Poly Phase Multifunction Energy Metering IC driver
   3  *
   4  * Copyright 2010-2011 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2.
   7  */
   8
   9 #include <linux/interrupt.h>
  10 #include <linux/irq.h>
  11 #include <linux/delay.h>
  12 #include <linux/mutex.h>
  13 #include <linux/device.h>
  14 #include <linux/kernel.h>
  15 #include <linux/spi/spi.h>
  16 #include <linux/slab.h>
  17 #include <linux/sysfs.h>
  18 #include <linux/list.h>
  19 #include <linux/module.h>
  20
  21 #include <linux/iio/iio.h>
  22 #include <linux/iio/sysfs.h>
  23 #include <linux/iio/buffer.h>
  24 #include "meter.h"
  25 #include "ade7758.h"
  26
  27 int ade7758_spi_write_reg_8(struct device *dev, u8 reg_address, u8 val)
  28 {
  29         int ret;
  30         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
  31         struct ade7758_state *st = iio_priv(indio_dev);
  32
  33         mutex_lock(&st->buf_lock);
  34         st->tx[0] = ADE7758_WRITE_REG(reg_address);
  35         st->tx[1] = val;
  36
  37         ret = spi_write(st->us, st->tx, 2);
  38         mutex_unlock(&st->buf_lock);
  39
  40         return ret;
  41 }
  42
  43 static int ade7758_spi_write_reg_16(struct device *dev, u8 reg_address,
  44                                     u16 value)
  45 {
  46         int ret;
  47         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
  48         struct ade7758_state *st = iio_priv(indio_dev);
  49         struct spi_transfer xfers[] = {
  50                 {
  51                         .tx_buf = st->tx,
  52                         .bits_per_word = 8,
  53                         .len = 3,
  54                 }
  55         };
  56
  57         mutex_lock(&st->buf_lock);
  58         st->tx[0] = ADE7758_WRITE_REG(reg_address);
  59         st->tx[1] = (value >> 8) & 0xFF;
  60         st->tx[2] = value & 0xFF;
  61
  62         ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
  63         mutex_unlock(&st->buf_lock);
  64
  65         return ret;
  66 }
  67
  68 static int ade7758_spi_write_reg_24(struct device *dev, u8 reg_address,
  69                                     u32 value)
  70 {
  71         int ret;
  72         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
  73         struct ade7758_state *st = iio_priv(indio_dev);
  74         struct spi_transfer xfers[] = {
  75                 {
  76                         .tx_buf = st->tx,
  77                         .bits_per_word = 8,
  78                         .len = 4,
  79                 }
  80         };
  81
  82         mutex_lock(&st->buf_lock);
  83         st->tx[0] = ADE7758_WRITE_REG(reg_address);
  84         st->tx[1] = (value >> 16) & 0xFF;
  85         st->tx[2] = (value >> 8) & 0xFF;
  86         st->tx[3] = value & 0xFF;
  87
  88         ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
  89         mutex_unlock(&st->buf_lock);
  90
  91         return ret;
  92 }
  93
  94 int ade7758_spi_read_reg_8(struct device *dev, u8 reg_address, u8 *val)
  95 {
  96         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
  97         struct ade7758_state *st = iio_priv(indio_dev);
  98         int ret;
  99         struct spi_transfer xfers[] = {
 100                 {
 101                         .tx_buf = st->tx,
 102                         .bits_per_word = 8,
 103                         .len = 1,
 104                         .delay_usecs = 4,
 105                 },
 106                 {
 107                         .tx_buf = &st->tx[1],
 108                         .rx_buf = st->rx,
 109                         .bits_per_word = 8,
 110                         .len = 1,
 111                 },
 112         };
 113
 114         mutex_lock(&st->buf_lock);
 115         st->tx[0] = ADE7758_READ_REG(reg_address);
 116         st->tx[1] = 0;
 117
 118         ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
 119         if (ret) {
 120                 dev_err(&st->us->dev, "problem when reading 8 bit register 0x%02X",
 121                         reg_address);
 122                 goto error_ret;
 123         }
 124         *val = st->rx[0];
 125
 126 error_ret:
 127         mutex_unlock(&st->buf_lock);
 128         return ret;
 129 }
 130
 131 static int ade7758_spi_read_reg_16(struct device *dev, u8 reg_address,
 132                                    u16 *val)
 133 {
 134         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 135         struct ade7758_state *st = iio_priv(indio_dev);
 136         int ret;
 137         struct spi_transfer xfers[] = {
 138                 {
 139                         .tx_buf = st->tx,
 140                         .bits_per_word = 8,
 141                         .len = 1,
 142                         .delay_usecs = 4,
 143                 },
 144                 {
 145                         .tx_buf = &st->tx[1],
 146                         .rx_buf = st->rx,
 147                         .bits_per_word = 8,
 148                         .len = 2,
 149                 },
 150         };
 151
 152         mutex_lock(&st->buf_lock);
 153         st->tx[0] = ADE7758_READ_REG(reg_address);
 154         st->tx[1] = 0;
 155         st->tx[2] = 0;
 156
 157         ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
 158         if (ret) {
 159                 dev_err(&st->us->dev, "problem when reading 16 bit register 0x%02X",
 160                         reg_address);
 161                 goto error_ret;
 162         }
 163
 164         *val = (st->rx[0] << 8) | st->rx[1];
 165
 166 error_ret:
 167         mutex_unlock(&st->buf_lock);
 168         return ret;
 169 }
 170
 171 static int ade7758_spi_read_reg_24(struct device *dev, u8 reg_address,
 172                                    u32 *val)
 173 {
 174         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 175         struct ade7758_state *st = iio_priv(indio_dev);
 176         int ret;
 177         struct spi_transfer xfers[] = {
 178                 {
 179                         .tx_buf = st->tx,
 180                         .bits_per_word = 8,
 181                         .len = 1,
 182                         .delay_usecs = 4,
 183                 },
 184                 {
 185                         .tx_buf = &st->tx[1],
 186                         .rx_buf = st->rx,
 187                         .bits_per_word = 8,
 188                         .len = 3,
 189                 },
 190         };
 191
 192         mutex_lock(&st->buf_lock);
 193         st->tx[0] = ADE7758_READ_REG(reg_address);
 194         st->tx[1] = 0;
 195         st->tx[2] = 0;
 196         st->tx[3] = 0;
 197
 198         ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
 199         if (ret) {
 200                 dev_err(&st->us->dev, "problem when reading 24 bit register 0x%02X",
 201                         reg_address);
 202                 goto error_ret;
 203         }
 204         *val = (st->rx[0] << 16) | (st->rx[1] << 8) | st->rx[2];
 205
 206 error_ret:
 207         mutex_unlock(&st->buf_lock);
 208         return ret;
 209 }
 210
 211 static ssize_t ade7758_read_8bit(struct device *dev,
 212                                  struct device_attribute *attr, char *buf)
 213 {
 214         int ret;
 215         u8 val = 0;
 216         struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
 217
 218         ret = ade7758_spi_read_reg_8(dev, this_attr->address, &val);
 219         if (ret)
 220                 return ret;
 221
 222         return sprintf(buf, "%u\n", val);
 223 }
 224
 225 static ssize_t ade7758_read_16bit(struct device *dev,
 226                                   struct device_attribute *attr, char *buf)
 227 {
 228         int ret;
 229         u16 val = 0;
 230         struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
 231
 232         ret = ade7758_spi_read_reg_16(dev, this_attr->address, &val);
 233         if (ret)
 234                 return ret;
 235
 236         return sprintf(buf, "%u\n", val);
 237 }
 238
 239 static ssize_t ade7758_read_24bit(struct device *dev,
 240                                   struct device_attribute *attr, char *buf)
 241 {
 242         int ret;
 243         u32 val = 0;
 244         struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
 245
 246         ret = ade7758_spi_read_reg_24(dev, this_attr->address, &val);
 247         if (ret)
 248                 return ret;
 249
 250         return sprintf(buf, "%u\n", val & 0xFFFFFF);
 251 }
 252
 253 static ssize_t ade7758_write_8bit(struct device *dev,
 254                                   struct device_attribute *attr,
 255                                   const char *buf, size_t len)
 256 {
 257         struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
 258         int ret;
 259         u8 val;
 260
 261         ret = kstrtou8(buf, 10, &val);
 262         if (ret)
 263                 goto error_ret;
 264         ret = ade7758_spi_write_reg_8(dev, this_attr->address, val);
 265
 266 error_ret:
 267         return ret ? ret : len;
 268 }
 269
 270 static ssize_t ade7758_write_16bit(struct device *dev,
 271                                    struct device_attribute *attr,
 272                                    const char *buf, size_t len)
 273 {
 274         struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
 275         int ret;
 276         u16 val;
 277
 278         ret = kstrtou16(buf, 10, &val);
 279         if (ret)
 280                 goto error_ret;
 281         ret = ade7758_spi_write_reg_16(dev, this_attr->address, val);
 282
 283 error_ret:
 284         return ret ? ret : len;
 285 }
 286
 287 static int ade7758_reset(struct device *dev)
 288 {
 289         int ret;
 290         u8 val;
 291
 292         ret = ade7758_spi_read_reg_8(dev, ADE7758_OPMODE, &val);
 293         if (ret < 0) {
 294                 dev_err(dev, "Failed to read opmode reg\n");
 295                 return ret;
 296         }
 297         val |= BIT(6); /* Software Chip Reset */
 298         ret = ade7758_spi_write_reg_8(dev, ADE7758_OPMODE, val);
 299         if (ret < 0)
 300                 dev_err(dev, "Failed to write opmode reg\n");
 301         return ret;
 302 }
 303
 304 static IIO_DEV_ATTR_VPEAK(0644,
 305                 ade7758_read_8bit,
 306                 ade7758_write_8bit,
 307                 ADE7758_VPEAK);
 308 static IIO_DEV_ATTR_IPEAK(0644,
 309                 ade7758_read_8bit,
 310                 ade7758_write_8bit,
 311                 ADE7758_VPEAK);
 312 static IIO_DEV_ATTR_APHCAL(0644,
 313                 ade7758_read_8bit,
 314                 ade7758_write_8bit,
 315                 ADE7758_APHCAL);
 316 static IIO_DEV_ATTR_BPHCAL(0644,
 317                 ade7758_read_8bit,
 318                 ade7758_write_8bit,
 319                 ADE7758_BPHCAL);
 320 static IIO_DEV_ATTR_CPHCAL(0644,
 321                 ade7758_read_8bit,
 322                 ade7758_write_8bit,
 323                 ADE7758_CPHCAL);
 324 static IIO_DEV_ATTR_WDIV(0644,
 325                 ade7758_read_8bit,
 326                 ade7758_write_8bit,
 327                 ADE7758_WDIV);
 328 static IIO_DEV_ATTR_VADIV(0644,
 329                 ade7758_read_8bit,
 330                 ade7758_write_8bit,
 331                 ADE7758_VADIV);
 332 static IIO_DEV_ATTR_AIRMS(0444,
 333                 ade7758_read_24bit,
 334                 NULL,
 335                 ADE7758_AIRMS);
 336 static IIO_DEV_ATTR_BIRMS(0444,
 337                 ade7758_read_24bit,
 338                 NULL,
 339                 ADE7758_BIRMS);
 340 static IIO_DEV_ATTR_CIRMS(0444,
 341                 ade7758_read_24bit,
 342                 NULL,
 343                 ADE7758_CIRMS);
 344 static IIO_DEV_ATTR_AVRMS(0444,
 345                 ade7758_read_24bit,
 346                 NULL,
 347                 ADE7758_AVRMS);
 348 static IIO_DEV_ATTR_BVRMS(0444,
 349                 ade7758_read_24bit,
 350                 NULL,
 351                 ADE7758_BVRMS);
 352 static IIO_DEV_ATTR_CVRMS(0444,
 353                 ade7758_read_24bit,
 354                 NULL,
 355                 ADE7758_CVRMS);
 356 static IIO_DEV_ATTR_AIRMSOS(0644,
 357                 ade7758_read_16bit,
 358                 ade7758_write_16bit,
 359                 ADE7758_AIRMSOS);
 360 static IIO_DEV_ATTR_BIRMSOS(0644,
 361                 ade7758_read_16bit,
 362                 ade7758_write_16bit,
 363                 ADE7758_BIRMSOS);
 364 static IIO_DEV_ATTR_CIRMSOS(0644,
 365                 ade7758_read_16bit,
 366                 ade7758_write_16bit,
 367                 ADE7758_CIRMSOS);
 368 static IIO_DEV_ATTR_AVRMSOS(0644,
 369                 ade7758_read_16bit,
 370                 ade7758_write_16bit,
 371                 ADE7758_AVRMSOS);
 372 static IIO_DEV_ATTR_BVRMSOS(0644,
 373                 ade7758_read_16bit,
 374                 ade7758_write_16bit,
 375                 ADE7758_BVRMSOS);
 376 static IIO_DEV_ATTR_CVRMSOS(0644,
 377                 ade7758_read_16bit,
 378                 ade7758_write_16bit,
 379                 ADE7758_CVRMSOS);
 380 static IIO_DEV_ATTR_AIGAIN(0644,
 381                 ade7758_read_16bit,
 382                 ade7758_write_16bit,
 383                 ADE7758_AIGAIN);
 384 static IIO_DEV_ATTR_BIGAIN(0644,
 385                 ade7758_read_16bit,
 386                 ade7758_write_16bit,
 387                 ADE7758_BIGAIN);
 388 static IIO_DEV_ATTR_CIGAIN(0644,
 389                 ade7758_read_16bit,
 390                 ade7758_write_16bit,
 391                 ADE7758_CIGAIN);
 392 static IIO_DEV_ATTR_AVRMSGAIN(0644,
 393                 ade7758_read_16bit,
 394                 ade7758_write_16bit,
 395                 ADE7758_AVRMSGAIN);
 396 static IIO_DEV_ATTR_BVRMSGAIN(0644,
 397                 ade7758_read_16bit,
 398                 ade7758_write_16bit,
 399                 ADE7758_BVRMSGAIN);
 400 static IIO_DEV_ATTR_CVRMSGAIN(0644,
 401                 ade7758_read_16bit,
 402                 ade7758_write_16bit,
 403                 ADE7758_CVRMSGAIN);
 404
 405 int ade7758_set_irq(struct device *dev, bool enable)
 406 {
 407         int ret;
 408         u32 irqen;
 409
 410         ret = ade7758_spi_read_reg_24(dev, ADE7758_MASK, &irqen);
 411         if (ret)
 412                 return ret;
 413
 414         if (enable)
 415                 irqen |= BIT(16); /* Enables an interrupt when a data is
 416                                    * present in the waveform register
 417                                    */
 418         else
 419                 irqen &= ~BIT(16);
 420
 421         ret = ade7758_spi_write_reg_24(dev, ADE7758_MASK, irqen);
 422
 423         return ret;
 424 }
 425
 426 /* Power down the device */
 427 static int ade7758_stop_device(struct device *dev)
 428 {
 429         int ret;
 430         u8 val;
 431
 432         ret = ade7758_spi_read_reg_8(dev, ADE7758_OPMODE, &val);
 433         if (ret < 0) {
 434                 dev_err(dev, "Failed to read opmode reg\n");
 435                 return ret;
 436         }
 437         val |= 7 << 3;  /* ADE7758 powered down */
 438         ret = ade7758_spi_write_reg_8(dev, ADE7758_OPMODE, val);
 439         if (ret < 0)
 440                 dev_err(dev, "Failed to write opmode reg\n");
 441         return ret;
 442 }
 443
 444 static int ade7758_initial_setup(struct iio_dev *indio_dev)
 445 {
 446         struct ade7758_state *st = iio_priv(indio_dev);
 447         struct device *dev = &indio_dev->dev;
 448         int ret;
 449
 450         /* use low spi speed for init */
 451         st->us->mode = SPI_MODE_1;
 452         spi_setup(st->us);
 453
 454         /* Disable IRQ */
 455         ret = ade7758_set_irq(dev, false);
 456         if (ret) {
 457                 dev_err(dev, "disable irq failed");
 458                 goto err_ret;
 459         }
 460
 461         ade7758_reset(dev);
 462         usleep_range(ADE7758_STARTUP_DELAY, ADE7758_STARTUP_DELAY + 100);
 463
 464 err_ret:
 465         return ret;
 466 }
 467
 468 static int ade7758_read_samp_freq(struct device *dev, int *val)
 469 {
 470         int ret;
 471         u8 t;
 472
 473         ret = ade7758_spi_read_reg_8(dev, ADE7758_WAVMODE, &t);
 474         if (ret)
 475                 return ret;
 476
 477         t = (t >> 5) & 0x3;
 478         *val = 26040 / (1 << t);
 479
 480         return 0;
 481 }
 482
 483 static int ade7758_write_samp_freq(struct device *dev, int val)
 484 {
 485         int ret;
 486         u8 reg, t;
 487
 488         switch (val) {
 489         case 26040:
 490                 t = 0;
 491                 break;
 492         case 13020:
 493                 t = 1;
 494                 break;
 495         case 6510:
 496                 t = 2;
 497                 break;
 498         case 3255:
 499                 t = 3;
 500                 break;
 501         default:
 502                 ret = -EINVAL;
 503                 goto out;
 504         }
 505
 506         ret = ade7758_spi_read_reg_8(dev, ADE7758_WAVMODE, &reg);
 507         if (ret)
 508                 goto out;
 509
 510         reg &= ~(5 << 3);
 511         reg |= t << 5;
 512
 513         ret = ade7758_spi_write_reg_8(dev, ADE7758_WAVMODE, reg);
 514
 515 out:
 516         return ret;
 517 }
 518
 519 static int ade7758_read_raw(struct iio_dev *indio_dev,
 520                             struct iio_chan_spec const *chan,
 521                             int *val,
 522                             int *val2,
 523                             long mask)
 524 {
 525         int ret;
 526
 527         switch (mask) {
 528         case IIO_CHAN_INFO_SAMP_FREQ:
 529                 mutex_lock(&indio_dev->mlock);
 530                 ret = ade7758_read_samp_freq(&indio_dev->dev, val);
 531                 mutex_unlock(&indio_dev->mlock);
 532                 return ret;
 533         default:
 534                 return -EINVAL;
 535         }
 536
 537         return ret;
 538 }
 539
 540 static int ade7758_write_raw(struct iio_dev *indio_dev,
 541                              struct iio_chan_spec const *chan,
 542                              int val, int val2, long mask)
 543 {
 544         int ret;
 545
 546         switch (mask) {
 547         case IIO_CHAN_INFO_SAMP_FREQ:
 548                 if (val2)
 549                         return -EINVAL;
 550                 mutex_lock(&indio_dev->mlock);
 551                 ret = ade7758_write_samp_freq(&indio_dev->dev, val);
 552                 mutex_unlock(&indio_dev->mlock);
 553                 return ret;
 554         default:
 555                 return -EINVAL;
 556         }
 557
 558         return ret;
 559 }
 560
 561 static IIO_DEV_ATTR_TEMP_RAW(ade7758_read_8bit);
 562 static IIO_CONST_ATTR(in_temp_offset, "129 C");
 563 static IIO_CONST_ATTR(in_temp_scale, "4 C");
 564
 565 static IIO_DEV_ATTR_AWATTHR(ade7758_read_16bit,
 566                 ADE7758_AWATTHR);
 567 static IIO_DEV_ATTR_BWATTHR(ade7758_read_16bit,
 568                 ADE7758_BWATTHR);
 569 static IIO_DEV_ATTR_CWATTHR(ade7758_read_16bit,
 570                 ADE7758_CWATTHR);
 571 static IIO_DEV_ATTR_AVARHR(ade7758_read_16bit,
 572                 ADE7758_AVARHR);
 573 static IIO_DEV_ATTR_BVARHR(ade7758_read_16bit,
 574                 ADE7758_BVARHR);
 575 static IIO_DEV_ATTR_CVARHR(ade7758_read_16bit,
 576                 ADE7758_CVARHR);
 577 static IIO_DEV_ATTR_AVAHR(ade7758_read_16bit,
 578                 ADE7758_AVAHR);
 579 static IIO_DEV_ATTR_BVAHR(ade7758_read_16bit,
 580                 ADE7758_BVAHR);
 581 static IIO_DEV_ATTR_CVAHR(ade7758_read_16bit,
 582                 ADE7758_CVAHR);
 583
 584 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("26040 13020 6510 3255");
 585
 586 static struct attribute *ade7758_attributes[] = {
 587         &iio_dev_attr_in_temp_raw.dev_attr.attr,
 588         &iio_const_attr_in_temp_offset.dev_attr.attr,
 589         &iio_const_attr_in_temp_scale.dev_attr.attr,
 590         &iio_const_attr_sampling_frequency_available.dev_attr.attr,
 591         &iio_dev_attr_awatthr.dev_attr.attr,
 592         &iio_dev_attr_bwatthr.dev_attr.attr,
 593         &iio_dev_attr_cwatthr.dev_attr.attr,
 594         &iio_dev_attr_avarhr.dev_attr.attr,
 595         &iio_dev_attr_bvarhr.dev_attr.attr,
 596         &iio_dev_attr_cvarhr.dev_attr.attr,
 597         &iio_dev_attr_avahr.dev_attr.attr,
 598         &iio_dev_attr_bvahr.dev_attr.attr,
 599         &iio_dev_attr_cvahr.dev_attr.attr,
 600         &iio_dev_attr_vpeak.dev_attr.attr,
 601         &iio_dev_attr_ipeak.dev_attr.attr,
 602         &iio_dev_attr_aphcal.dev_attr.attr,
 603         &iio_dev_attr_bphcal.dev_attr.attr,
 604         &iio_dev_attr_cphcal.dev_attr.attr,
 605         &iio_dev_attr_wdiv.dev_attr.attr,
 606         &iio_dev_attr_vadiv.dev_attr.attr,
 607         &iio_dev_attr_airms.dev_attr.attr,
 608         &iio_dev_attr_birms.dev_attr.attr,
 609         &iio_dev_attr_cirms.dev_attr.attr,
 610         &iio_dev_attr_avrms.dev_attr.attr,
 611         &iio_dev_attr_bvrms.dev_attr.attr,
 612         &iio_dev_attr_cvrms.dev_attr.attr,
 613         &iio_dev_attr_aigain.dev_attr.attr,
 614         &iio_dev_attr_bigain.dev_attr.attr,
 615         &iio_dev_attr_cigain.dev_attr.attr,
 616         &iio_dev_attr_avrmsgain.dev_attr.attr,
 617         &iio_dev_attr_bvrmsgain.dev_attr.attr,
 618         &iio_dev_attr_cvrmsgain.dev_attr.attr,
 619         &iio_dev_attr_airmsos.dev_attr.attr,
 620         &iio_dev_attr_birmsos.dev_attr.attr,
 621         &iio_dev_attr_cirmsos.dev_attr.attr,
 622         &iio_dev_attr_avrmsos.dev_attr.attr,
 623         &iio_dev_attr_bvrmsos.dev_attr.attr,
 624         &iio_dev_attr_cvrmsos.dev_attr.attr,
 625         NULL,
 626 };
 627
 628 static const struct attribute_group ade7758_attribute_group = {
 629         .attrs = ade7758_attributes,
 630 };
 631
 632 static const struct iio_chan_spec ade7758_channels[] = {
 633         {
 634                 .type = IIO_VOLTAGE,
 635                 .indexed = 1,
 636                 .channel = 0,
 637                 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
 638                 .address = AD7758_WT(AD7758_PHASE_A, AD7758_VOLTAGE),
 639                 .scan_index = 0,
 640                 .scan_type = {
 641                         .sign = 's',
 642                         .realbits = 24,
 643                         .storagebits = 32,
 644                 },
 645         }, {
 646                 .type = IIO_CURRENT,
 647                 .indexed = 1,
 648                 .channel = 0,
 649                 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
 650                 .address = AD7758_WT(AD7758_PHASE_A, AD7758_CURRENT),
 651                 .scan_index = 1,
 652                 .scan_type = {
 653                         .sign = 's',
 654                         .realbits = 24,
 655                         .storagebits = 32,
 656                 },
 657         }, {
 658                 .type = IIO_POWER,
 659                 .indexed = 1,
 660                 .channel = 0,
 661                 .extend_name = "apparent",
 662                 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
 663                 .address = AD7758_WT(AD7758_PHASE_A, AD7758_APP_PWR),
 664                 .scan_index = 2,
 665                 .scan_type = {
 666                         .sign = 's',
 667                         .realbits = 24,
 668                         .storagebits = 32,
 669                 },
 670         }, {
 671                 .type = IIO_POWER,
 672                 .indexed = 1,
 673                 .channel = 0,
 674                 .extend_name = "active",
 675                 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
 676                 .address = AD7758_WT(AD7758_PHASE_A, AD7758_ACT_PWR),
 677                 .scan_index = 3,
 678                 .scan_type = {
 679                         .sign = 's',
 680                         .realbits = 24,
 681                         .storagebits = 32,
 682                 },
 683         }, {
 684                 .type = IIO_POWER,
 685                 .indexed = 1,
 686                 .channel = 0,
 687                 .extend_name = "reactive",
 688                 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
 689                 .address = AD7758_WT(AD7758_PHASE_A, AD7758_REACT_PWR),
 690                 .scan_index = 4,
 691                 .scan_type = {
 692                         .sign = 's',
 693                         .realbits = 24,
 694                         .storagebits = 32,
 695                 },
 696         }, {
 697                 .type = IIO_VOLTAGE,
 698                 .indexed = 1,
 699                 .channel = 1,
 700                 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
 701                 .address = AD7758_WT(AD7758_PHASE_B, AD7758_VOLTAGE),
 702                 .scan_index = 5,
 703                 .scan_type = {
 704                         .sign = 's',
 705                         .realbits = 24,
 706                         .storagebits = 32,
 707                 },
 708         }, {
 709                 .type = IIO_CURRENT,
 710                 .indexed = 1,
 711                 .channel = 1,
 712                 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
 713                 .address = AD7758_WT(AD7758_PHASE_B, AD7758_CURRENT),
 714                 .scan_index = 6,
 715                 .scan_type = {
 716                         .sign = 's',
 717                         .realbits = 24,
 718                         .storagebits = 32,
 719                 },
 720         }, {
 721                 .type = IIO_POWER,
 722                 .indexed = 1,
 723                 .channel = 1,
 724                 .extend_name = "apparent",
 725                 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
 726                 .address = AD7758_WT(AD7758_PHASE_B, AD7758_APP_PWR),
 727                 .scan_index = 7,
 728                 .scan_type = {
 729                         .sign = 's',
 730                         .realbits = 24,
 731                         .storagebits = 32,
 732                 },
 733         }, {
 734                 .type = IIO_POWER,
 735                 .indexed = 1,
 736                 .channel = 1,
 737                 .extend_name = "active",
 738                 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
 739                 .address = AD7758_WT(AD7758_PHASE_B, AD7758_ACT_PWR),
 740                 .scan_index = 8,
 741                 .scan_type = {
 742                         .sign = 's',
 743                         .realbits = 24,
 744                         .storagebits = 32,
 745                 },
 746         }, {
 747                 .type = IIO_POWER,
 748                 .indexed = 1,
 749                 .channel = 1,
 750                 .extend_name = "reactive",
 751                 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
 752                 .address = AD7758_WT(AD7758_PHASE_B, AD7758_REACT_PWR),
 753                 .scan_index = 9,
 754                 .scan_type = {
 755                         .sign = 's',
 756                         .realbits = 24,
 757                         .storagebits = 32,
 758                 },
 759         }, {
 760                 .type = IIO_VOLTAGE,
 761                 .indexed = 1,
 762                 .channel = 2,
 763                 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
 764                 .address = AD7758_WT(AD7758_PHASE_C, AD7758_VOLTAGE),
 765                 .scan_index = 10,
 766                 .scan_type = {
 767                         .sign = 's',
 768                         .realbits = 24,
 769                         .storagebits = 32,
 770                 },
 771         }, {
 772                 .type = IIO_CURRENT,
 773                 .indexed = 1,
 774                 .channel = 2,
 775                 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
 776                 .address = AD7758_WT(AD7758_PHASE_C, AD7758_CURRENT),
 777                 .scan_index = 11,
 778                 .scan_type = {
 779                         .sign = 's',
 780                         .realbits = 24,
 781                         .storagebits = 32,
 782                 },
 783         }, {
 784                 .type = IIO_POWER,
 785                 .indexed = 1,
 786                 .channel = 2,
 787                 .extend_name = "apparent",
 788                 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
 789                 .address = AD7758_WT(AD7758_PHASE_C, AD7758_APP_PWR),
 790                 .scan_index = 12,
 791                 .scan_type = {
 792                         .sign = 's',
 793                         .realbits = 24,
 794                         .storagebits = 32,
 795                 },
 796         }, {
 797                 .type = IIO_POWER,
 798                 .indexed = 1,
 799                 .channel = 2,
 800                 .extend_name = "active",
 801                 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
 802                 .address = AD7758_WT(AD7758_PHASE_C, AD7758_ACT_PWR),
 803                 .scan_index = 13,
 804                 .scan_type = {
 805                         .sign = 's',
 806                         .realbits = 24,
 807                         .storagebits = 32,
 808                 },
 809         }, {
 810                 .type = IIO_POWER,
 811                 .indexed = 1,
 812                 .channel = 2,
 813                 .extend_name = "reactive",
 814                 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
 815                 .address = AD7758_WT(AD7758_PHASE_C, AD7758_REACT_PWR),
 816                 .scan_index = 14,
 817                 .scan_type = {
 818                         .sign = 's',
 819                         .realbits = 24,
 820                         .storagebits = 32,
 821                 },
 822         },
 823         IIO_CHAN_SOFT_TIMESTAMP(15),
 824 };
 825
 826 static const struct iio_info ade7758_info = {
 827         .attrs = &ade7758_attribute_group,
 828         .read_raw = &ade7758_read_raw,
 829         .write_raw = &ade7758_write_raw,
 830         .driver_module = THIS_MODULE,
 831 };
 832
 833 static int ade7758_probe(struct spi_device *spi)
 834 {
 835         int ret;
 836         struct ade7758_state *st;
 837         struct iio_dev *indio_dev;
 838
 839         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
 840         if (!indio_dev)
 841                 return -ENOMEM;
 842
 843         st = iio_priv(indio_dev);
 844         /* this is only used for removal purposes */
 845         spi_set_drvdata(spi, indio_dev);
 846
 847         /* Allocate the comms buffers */
 848         st->rx = kcalloc(ADE7758_MAX_RX, sizeof(*st->rx), GFP_KERNEL);
 849         if (!st->rx)
 850                 return -ENOMEM;
 851         st->tx = kcalloc(ADE7758_MAX_TX, sizeof(*st->tx), GFP_KERNEL);
 852         if (!st->tx) {
 853                 ret = -ENOMEM;
 854                 goto error_free_rx;
 855         }
 856         st->us = spi;
 857         mutex_init(&st->buf_lock);
 858
 859         indio_dev->name = spi->dev.driver->name;
 860         indio_dev->dev.parent = &spi->dev;
 861         indio_dev->info = &ade7758_info;
 862         indio_dev->modes = INDIO_DIRECT_MODE;
 863         indio_dev->channels = ade7758_channels;
 864         indio_dev->num_channels = ARRAY_SIZE(ade7758_channels);
 865
 866         ret = ade7758_configure_ring(indio_dev);
 867         if (ret)
 868                 goto error_free_tx;
 869
 870         /* Get the device into a sane initial state */
 871         ret = ade7758_initial_setup(indio_dev);
 872         if (ret)
 873                 goto error_unreg_ring_funcs;
 874
 875         if (spi->irq) {
 876                 ret = ade7758_probe_trigger(indio_dev);
 877                 if (ret)
 878                         goto error_unreg_ring_funcs;
 879         }
 880
 881         ret = iio_device_register(indio_dev);
 882         if (ret)
 883                 goto error_remove_trigger;
 884
 885         return 0;
 886
 887 error_remove_trigger:
 888         if (spi->irq)
 889                 ade7758_remove_trigger(indio_dev);
 890 error_unreg_ring_funcs:
 891         ade7758_unconfigure_ring(indio_dev);
 892 error_free_tx:
 893         kfree(st->tx);
 894 error_free_rx:
 895         kfree(st->rx);
 896         return ret;
 897 }
 898
 899 static int ade7758_remove(struct spi_device *spi)
 900 {
 901         struct iio_dev *indio_dev = spi_get_drvdata(spi);
 902         struct ade7758_state *st = iio_priv(indio_dev);
 903
 904         iio_device_unregister(indio_dev);
 905         ade7758_stop_device(&indio_dev->dev);
 906         ade7758_remove_trigger(indio_dev);
 907         ade7758_unconfigure_ring(indio_dev);
 908         kfree(st->tx);
 909         kfree(st->rx);
 910
 911         return 0;
 912 }
 913
 914 static const struct spi_device_id ade7758_id[] = {
 915         {"ade7758", 0},
 916         {}
 917 };
 918 MODULE_DEVICE_TABLE(spi, ade7758_id);
 919
 920 static struct spi_driver ade7758_driver = {
 921         .driver = {
 922                 .name = "ade7758",
 923         },
 924         .probe = ade7758_probe,
 925         .remove = ade7758_remove,
 926         .id_table = ade7758_id,
 927 };
 928 module_spi_driver(ade7758_driver);
 929
 930 MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
 931 MODULE_DESCRIPTION("Analog Devices ADE7758 Polyphase Multifunction Energy Metering IC Driver");
 932 MODULE_LICENSE("GPL v2");