GNU Linux-libre 4.14.262-gnu1
[releases.git] / drivers / staging / iio / frequency / ad9834.c
1 /*
2  * AD9833/AD9834/AD9837/AD9838 SPI DDS driver
3  *
4  * Copyright 2010-2011 Analog Devices Inc.
5  *
6  * Licensed under the GPL-2.
7  */
8
9 #include <linux/interrupt.h>
10 #include <linux/workqueue.h>
11 #include <linux/device.h>
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
14 #include <linux/sysfs.h>
15 #include <linux/list.h>
16 #include <linux/spi/spi.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/err.h>
19 #include <linux/module.h>
20 #include <asm/div64.h>
21
22 #include <linux/iio/iio.h>
23 #include <linux/iio/sysfs.h>
24 #include "dds.h"
25
26 #include "ad9834.h"
27
28 /* Registers */
29
30 #define AD9834_REG_CMD          0
31 #define AD9834_REG_FREQ0        BIT(14)
32 #define AD9834_REG_FREQ1        BIT(15)
33 #define AD9834_REG_PHASE0       (BIT(15) | BIT(14))
34 #define AD9834_REG_PHASE1       (BIT(15) | BIT(14) | BIT(13))
35
36 /* Command Control Bits */
37
38 #define AD9834_B28              BIT(13)
39 #define AD9834_HLB              BIT(12)
40 #define AD9834_FSEL             BIT(11)
41 #define AD9834_PSEL             BIT(10)
42 #define AD9834_PIN_SW           BIT(9)
43 #define AD9834_RESET            BIT(8)
44 #define AD9834_SLEEP1           BIT(7)
45 #define AD9834_SLEEP12          BIT(6)
46 #define AD9834_OPBITEN          BIT(5)
47 #define AD9834_SIGN_PIB         BIT(4)
48 #define AD9834_DIV2             BIT(3)
49 #define AD9834_MODE             BIT(1)
50
51 #define AD9834_FREQ_BITS        28
52 #define AD9834_PHASE_BITS       12
53
54 #define RES_MASK(bits)  (BIT(bits) - 1)
55
56 /**
57  * struct ad9834_state - driver instance specific data
58  * @spi:                spi_device
59  * @reg:                supply regulator
60  * @mclk:               external master clock
61  * @control:            cached control word
62  * @xfer:               default spi transfer
63  * @msg:                default spi message
64  * @freq_xfer:          tuning word spi transfer
65  * @freq_msg:           tuning word spi message
66  * @lock:               protect sensor state
67  * @data:               spi transmit buffer
68  * @freq_data:          tuning word spi transmit buffer
69  */
70
71 struct ad9834_state {
72         struct spi_device               *spi;
73         struct regulator                *reg;
74         unsigned int                    mclk;
75         unsigned short                  control;
76         unsigned short                  devid;
77         struct spi_transfer             xfer;
78         struct spi_message              msg;
79         struct spi_transfer             freq_xfer[2];
80         struct spi_message              freq_msg;
81         struct mutex                    lock;   /* protect sensor state */
82
83         /*
84          * DMA (thus cache coherency maintenance) requires the
85          * transfer buffers to live in their own cache lines.
86          */
87         __be16                          data ____cacheline_aligned;
88         __be16                          freq_data[2];
89 };
90
91 /**
92  * ad9834_supported_device_ids:
93  */
94
95 enum ad9834_supported_device_ids {
96         ID_AD9833,
97         ID_AD9834,
98         ID_AD9837,
99         ID_AD9838,
100 };
101
102 static unsigned int ad9834_calc_freqreg(unsigned long mclk, unsigned long fout)
103 {
104         unsigned long long freqreg = (u64)fout * (u64)BIT(AD9834_FREQ_BITS);
105
106         do_div(freqreg, mclk);
107         return freqreg;
108 }
109
110 static int ad9834_write_frequency(struct ad9834_state *st,
111                                   unsigned long addr, unsigned long fout)
112 {
113         unsigned long regval;
114
115         if (fout > (st->mclk / 2))
116                 return -EINVAL;
117
118         regval = ad9834_calc_freqreg(st->mclk, fout);
119
120         st->freq_data[0] = cpu_to_be16(addr | (regval &
121                                        RES_MASK(AD9834_FREQ_BITS / 2)));
122         st->freq_data[1] = cpu_to_be16(addr | ((regval >>
123                                        (AD9834_FREQ_BITS / 2)) &
124                                        RES_MASK(AD9834_FREQ_BITS / 2)));
125
126         return spi_sync(st->spi, &st->freq_msg);
127 }
128
129 static int ad9834_write_phase(struct ad9834_state *st,
130                               unsigned long addr, unsigned long phase)
131 {
132         if (phase > BIT(AD9834_PHASE_BITS))
133                 return -EINVAL;
134         st->data = cpu_to_be16(addr | phase);
135
136         return spi_sync(st->spi, &st->msg);
137 }
138
139 static ssize_t ad9834_write(struct device *dev,
140                             struct device_attribute *attr,
141                             const char *buf,
142                             size_t len)
143 {
144         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
145         struct ad9834_state *st = iio_priv(indio_dev);
146         struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
147         int ret;
148         unsigned long val;
149
150         ret = kstrtoul(buf, 10, &val);
151         if (ret)
152                 return ret;
153
154         mutex_lock(&st->lock);
155         switch ((u32)this_attr->address) {
156         case AD9834_REG_FREQ0:
157         case AD9834_REG_FREQ1:
158                 ret = ad9834_write_frequency(st, this_attr->address, val);
159                 break;
160         case AD9834_REG_PHASE0:
161         case AD9834_REG_PHASE1:
162                 ret = ad9834_write_phase(st, this_attr->address, val);
163                 break;
164         case AD9834_OPBITEN:
165                 if (st->control & AD9834_MODE) {
166                         ret = -EINVAL;  /* AD9843 reserved mode */
167                         break;
168                 }
169
170                 if (val)
171                         st->control |= AD9834_OPBITEN;
172                 else
173                         st->control &= ~AD9834_OPBITEN;
174
175                 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
176                 ret = spi_sync(st->spi, &st->msg);
177                 break;
178         case AD9834_PIN_SW:
179                 if (val)
180                         st->control |= AD9834_PIN_SW;
181                 else
182                         st->control &= ~AD9834_PIN_SW;
183                 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
184                 ret = spi_sync(st->spi, &st->msg);
185                 break;
186         case AD9834_FSEL:
187         case AD9834_PSEL:
188                 if (!val) {
189                         st->control &= ~(this_attr->address | AD9834_PIN_SW);
190                 } else if (val == 1) {
191                         st->control |= this_attr->address;
192                         st->control &= ~AD9834_PIN_SW;
193                 } else {
194                         ret = -EINVAL;
195                         break;
196                 }
197                 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
198                 ret = spi_sync(st->spi, &st->msg);
199                 break;
200         case AD9834_RESET:
201                 if (val)
202                         st->control &= ~AD9834_RESET;
203                 else
204                         st->control |= AD9834_RESET;
205
206                 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
207                 ret = spi_sync(st->spi, &st->msg);
208                 break;
209         default:
210                 ret = -ENODEV;
211         }
212         mutex_unlock(&st->lock);
213
214         return ret ? ret : len;
215 }
216
217 static ssize_t ad9834_store_wavetype(struct device *dev,
218                                      struct device_attribute *attr,
219                                      const char *buf,
220                                      size_t len)
221 {
222         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
223         struct ad9834_state *st = iio_priv(indio_dev);
224         struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
225         int ret = 0;
226         bool is_ad9833_7 = (st->devid == ID_AD9833) || (st->devid == ID_AD9837);
227
228         mutex_lock(&st->lock);
229
230         switch ((u32)this_attr->address) {
231         case 0:
232                 if (sysfs_streq(buf, "sine")) {
233                         st->control &= ~AD9834_MODE;
234                         if (is_ad9833_7)
235                                 st->control &= ~AD9834_OPBITEN;
236                 } else if (sysfs_streq(buf, "triangle")) {
237                         if (is_ad9833_7) {
238                                 st->control &= ~AD9834_OPBITEN;
239                                 st->control |= AD9834_MODE;
240                         } else if (st->control & AD9834_OPBITEN) {
241                                 ret = -EINVAL;  /* AD9843 reserved mode */
242                         } else {
243                                 st->control |= AD9834_MODE;
244                         }
245                 } else if (is_ad9833_7 && sysfs_streq(buf, "square")) {
246                         st->control &= ~AD9834_MODE;
247                         st->control |= AD9834_OPBITEN;
248                 } else {
249                         ret = -EINVAL;
250                 }
251
252                 break;
253         case 1:
254                 if (sysfs_streq(buf, "square") &&
255                     !(st->control & AD9834_MODE)) {
256                         st->control &= ~AD9834_MODE;
257                         st->control |= AD9834_OPBITEN;
258                 } else {
259                         ret = -EINVAL;
260                 }
261                 break;
262         default:
263                 ret = -EINVAL;
264                 break;
265         }
266
267         if (!ret) {
268                 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
269                 ret = spi_sync(st->spi, &st->msg);
270         }
271         mutex_unlock(&st->lock);
272
273         return ret ? ret : len;
274 }
275
276 static
277 ssize_t ad9834_show_out0_wavetype_available(struct device *dev,
278                                             struct device_attribute *attr,
279                                             char *buf)
280 {
281         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
282         struct ad9834_state *st = iio_priv(indio_dev);
283         char *str;
284
285         if ((st->devid == ID_AD9833) || (st->devid == ID_AD9837))
286                 str = "sine triangle square";
287         else if (st->control & AD9834_OPBITEN)
288                 str = "sine";
289         else
290                 str = "sine triangle";
291
292         return sprintf(buf, "%s\n", str);
293 }
294
295 static IIO_DEVICE_ATTR(out_altvoltage0_out0_wavetype_available, 0444,
296                        ad9834_show_out0_wavetype_available, NULL, 0);
297
298 static
299 ssize_t ad9834_show_out1_wavetype_available(struct device *dev,
300                                             struct device_attribute *attr,
301                                             char *buf)
302 {
303         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
304         struct ad9834_state *st = iio_priv(indio_dev);
305         char *str;
306
307         if (st->control & AD9834_MODE)
308                 str = "";
309         else
310                 str = "square";
311
312         return sprintf(buf, "%s\n", str);
313 }
314
315 static IIO_DEVICE_ATTR(out_altvoltage0_out1_wavetype_available, 0444,
316                        ad9834_show_out1_wavetype_available, NULL, 0);
317
318 /**
319  * see dds.h for further information
320  */
321
322 static IIO_DEV_ATTR_FREQ(0, 0, 0200, NULL, ad9834_write, AD9834_REG_FREQ0);
323 static IIO_DEV_ATTR_FREQ(0, 1, 0200, NULL, ad9834_write, AD9834_REG_FREQ1);
324 static IIO_DEV_ATTR_FREQSYMBOL(0, 0200, NULL, ad9834_write, AD9834_FSEL);
325 static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */
326
327 static IIO_DEV_ATTR_PHASE(0, 0, 0200, NULL, ad9834_write, AD9834_REG_PHASE0);
328 static IIO_DEV_ATTR_PHASE(0, 1, 0200, NULL, ad9834_write, AD9834_REG_PHASE1);
329 static IIO_DEV_ATTR_PHASESYMBOL(0, 0200, NULL, ad9834_write, AD9834_PSEL);
330 static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/
331
332 static IIO_DEV_ATTR_PINCONTROL_EN(0, 0200, NULL,
333         ad9834_write, AD9834_PIN_SW);
334 static IIO_DEV_ATTR_OUT_ENABLE(0, 0200, NULL, ad9834_write, AD9834_RESET);
335 static IIO_DEV_ATTR_OUTY_ENABLE(0, 1, 0200, NULL,
336         ad9834_write, AD9834_OPBITEN);
337 static IIO_DEV_ATTR_OUT_WAVETYPE(0, 0, ad9834_store_wavetype, 0);
338 static IIO_DEV_ATTR_OUT_WAVETYPE(0, 1, ad9834_store_wavetype, 1);
339
340 static struct attribute *ad9834_attributes[] = {
341         &iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr,
342         &iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr,
343         &iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr,
344         &iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr,
345         &iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr,
346         &iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr,
347         &iio_dev_attr_out_altvoltage0_pincontrol_en.dev_attr.attr,
348         &iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr,
349         &iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr,
350         &iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr,
351         &iio_dev_attr_out_altvoltage0_out1_enable.dev_attr.attr,
352         &iio_dev_attr_out_altvoltage0_out0_wavetype.dev_attr.attr,
353         &iio_dev_attr_out_altvoltage0_out1_wavetype.dev_attr.attr,
354         &iio_dev_attr_out_altvoltage0_out0_wavetype_available.dev_attr.attr,
355         &iio_dev_attr_out_altvoltage0_out1_wavetype_available.dev_attr.attr,
356         NULL,
357 };
358
359 static struct attribute *ad9833_attributes[] = {
360         &iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr,
361         &iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr,
362         &iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr,
363         &iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr,
364         &iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr,
365         &iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr,
366         &iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr,
367         &iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr,
368         &iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr,
369         &iio_dev_attr_out_altvoltage0_out0_wavetype.dev_attr.attr,
370         &iio_dev_attr_out_altvoltage0_out0_wavetype_available.dev_attr.attr,
371         NULL,
372 };
373
374 static const struct attribute_group ad9834_attribute_group = {
375         .attrs = ad9834_attributes,
376 };
377
378 static const struct attribute_group ad9833_attribute_group = {
379         .attrs = ad9833_attributes,
380 };
381
382 static const struct iio_info ad9834_info = {
383         .attrs = &ad9834_attribute_group,
384         .driver_module = THIS_MODULE,
385 };
386
387 static const struct iio_info ad9833_info = {
388         .attrs = &ad9833_attribute_group,
389         .driver_module = THIS_MODULE,
390 };
391
392 static int ad9834_probe(struct spi_device *spi)
393 {
394         struct ad9834_platform_data *pdata = dev_get_platdata(&spi->dev);
395         struct ad9834_state *st;
396         struct iio_dev *indio_dev;
397         struct regulator *reg;
398         int ret;
399
400         if (!pdata) {
401                 dev_dbg(&spi->dev, "no platform data?\n");
402                 return -ENODEV;
403         }
404
405         reg = devm_regulator_get(&spi->dev, "avdd");
406         if (IS_ERR(reg))
407                 return PTR_ERR(reg);
408
409         ret = regulator_enable(reg);
410         if (ret) {
411                 dev_err(&spi->dev, "Failed to enable specified AVDD supply\n");
412                 return ret;
413         }
414
415         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
416         if (!indio_dev) {
417                 ret = -ENOMEM;
418                 goto error_disable_reg;
419         }
420         spi_set_drvdata(spi, indio_dev);
421         st = iio_priv(indio_dev);
422         mutex_init(&st->lock);
423         st->mclk = pdata->mclk;
424         st->spi = spi;
425         st->devid = spi_get_device_id(spi)->driver_data;
426         st->reg = reg;
427         indio_dev->dev.parent = &spi->dev;
428         indio_dev->name = spi_get_device_id(spi)->name;
429         switch (st->devid) {
430         case ID_AD9833:
431         case ID_AD9837:
432                 indio_dev->info = &ad9833_info;
433                 break;
434         default:
435                 indio_dev->info = &ad9834_info;
436                 break;
437         }
438         indio_dev->modes = INDIO_DIRECT_MODE;
439
440         /* Setup default messages */
441
442         st->xfer.tx_buf = &st->data;
443         st->xfer.len = 2;
444
445         spi_message_init(&st->msg);
446         spi_message_add_tail(&st->xfer, &st->msg);
447
448         st->freq_xfer[0].tx_buf = &st->freq_data[0];
449         st->freq_xfer[0].len = 2;
450         st->freq_xfer[0].cs_change = 1;
451         st->freq_xfer[1].tx_buf = &st->freq_data[1];
452         st->freq_xfer[1].len = 2;
453
454         spi_message_init(&st->freq_msg);
455         spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
456         spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
457
458         st->control = AD9834_B28 | AD9834_RESET;
459
460         if (!pdata->en_div2)
461                 st->control |= AD9834_DIV2;
462
463         if (!pdata->en_signbit_msb_out && (st->devid == ID_AD9834))
464                 st->control |= AD9834_SIGN_PIB;
465
466         st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
467         ret = spi_sync(st->spi, &st->msg);
468         if (ret) {
469                 dev_err(&spi->dev, "device init failed\n");
470                 goto error_disable_reg;
471         }
472
473         ret = ad9834_write_frequency(st, AD9834_REG_FREQ0, pdata->freq0);
474         if (ret)
475                 goto error_disable_reg;
476
477         ret = ad9834_write_frequency(st, AD9834_REG_FREQ1, pdata->freq1);
478         if (ret)
479                 goto error_disable_reg;
480
481         ret = ad9834_write_phase(st, AD9834_REG_PHASE0, pdata->phase0);
482         if (ret)
483                 goto error_disable_reg;
484
485         ret = ad9834_write_phase(st, AD9834_REG_PHASE1, pdata->phase1);
486         if (ret)
487                 goto error_disable_reg;
488
489         ret = iio_device_register(indio_dev);
490         if (ret)
491                 goto error_disable_reg;
492
493         return 0;
494
495 error_disable_reg:
496         regulator_disable(reg);
497
498         return ret;
499 }
500
501 static int ad9834_remove(struct spi_device *spi)
502 {
503         struct iio_dev *indio_dev = spi_get_drvdata(spi);
504         struct ad9834_state *st = iio_priv(indio_dev);
505
506         iio_device_unregister(indio_dev);
507         regulator_disable(st->reg);
508
509         return 0;
510 }
511
512 static const struct spi_device_id ad9834_id[] = {
513         {"ad9833", ID_AD9833},
514         {"ad9834", ID_AD9834},
515         {"ad9837", ID_AD9837},
516         {"ad9838", ID_AD9838},
517         {}
518 };
519 MODULE_DEVICE_TABLE(spi, ad9834_id);
520
521 static struct spi_driver ad9834_driver = {
522         .driver = {
523                 .name   = "ad9834",
524         },
525         .probe          = ad9834_probe,
526         .remove         = ad9834_remove,
527         .id_table       = ad9834_id,
528 };
529 module_spi_driver(ad9834_driver);
530
531 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
532 MODULE_DESCRIPTION("Analog Devices AD9833/AD9834/AD9837/AD9838 DDS");
533 MODULE_LICENSE("GPL v2");