2 * Copyright 2003 Digi International (www.digi.com)
3 * Scott H Kilau <Scott_Kilau at digi dot com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more details.
19 #include "dgnc_driver.h"
22 * struct neo_uart_struct - Per channel/port NEO UART structure
24 * key - W = read write
28 * @txrx: (RW) Holding Register.
29 * @ier: (RW) Interrupt Enable Register.
30 * @isr_fcr: (RW) Interrupt Status Reg/Fifo Control Register.
31 * @lcr: (RW) Line Control Register.
32 * @mcr: (RW) Modem Control Register.
33 * @lsr: (RW) Line Status Register.
34 * @msr: (RW) Modem Status Register.
35 * @spr: (RW) Scratch Pad Register.
36 * @fctr: (RW) Feature Control Register.
37 * @efr: (RW) Enhanced Function Register.
38 * @tfifo: (RW) Transmit FIFO Register.
39 * @rfifo: (RW) Receive FIFO Register.
40 * @xoffchar1: (RW) XOff Character 1 Register.
41 * @xoffchar2: (RW) XOff Character 2 Register.
42 * @xonchar1: (RW) Xon Character 1 Register.
43 * @xonchar2: (RW) XOn Character 2 Register.
44 * @reserved1: (U) Reserved by Exar.
45 * @txrxburst: (RW) 64 bytes of RX/TX FIFO Data.
46 * @reserved2: (U) Reserved by Exar.
47 * @rxburst_with_errors: (R) bytes of RX FIFO Data + LSR.
49 struct neo_uart_struct {
68 u8 reserved1[0x2ff - 0x200];
70 u8 reserved2[0x37f - 0x340];
71 u8 rxburst_with_errors[64];
74 /* Where to read the extended interrupt register (32bits instead of 8bits) */
75 #define UART_17158_POLL_ADDR_OFFSET 0x80
77 /* These are the current dvid's of the Neo boards */
78 #define UART_XR17C158_DVID 0x20
79 #define UART_XR17D158_DVID 0x20
80 #define UART_XR17E158_DVID 0x40
82 #define NEO_EECK 0x10 /* Clock */
83 #define NEO_EECS 0x20 /* Chip Select */
84 #define NEO_EEDI 0x40 /* Data In is an Output Pin */
85 #define NEO_EEDO 0x80 /* Data Out is an Input Pin */
86 #define NEO_EEREG 0x8E /* offset to EEPROM control reg */
88 #define NEO_VPD_IMAGESIZE 0x40 /* size of image to read from EEPROM in words */
89 #define NEO_VPD_IMAGEBYTES (NEO_VPD_IMAGESIZE * 2)
92 * These are the redefinitions for the FCTR on the XR17C158, since
93 * Exar made them different than their earlier design. (XR16C854)
96 /* These are only applicable when table D is selected */
97 #define UART_17158_FCTR_RTS_NODELAY 0x00
98 #define UART_17158_FCTR_RTS_4DELAY 0x01
99 #define UART_17158_FCTR_RTS_6DELAY 0x02
100 #define UART_17158_FCTR_RTS_8DELAY 0x03
101 #define UART_17158_FCTR_RTS_12DELAY 0x12
102 #define UART_17158_FCTR_RTS_16DELAY 0x05
103 #define UART_17158_FCTR_RTS_20DELAY 0x13
104 #define UART_17158_FCTR_RTS_24DELAY 0x06
105 #define UART_17158_FCTR_RTS_28DELAY 0x14
106 #define UART_17158_FCTR_RTS_32DELAY 0x07
107 #define UART_17158_FCTR_RTS_36DELAY 0x16
108 #define UART_17158_FCTR_RTS_40DELAY 0x08
109 #define UART_17158_FCTR_RTS_44DELAY 0x09
110 #define UART_17158_FCTR_RTS_48DELAY 0x10
111 #define UART_17158_FCTR_RTS_52DELAY 0x11
113 #define UART_17158_FCTR_RTS_IRDA 0x10
114 #define UART_17158_FCTR_RS485 0x20
115 #define UART_17158_FCTR_TRGA 0x00
116 #define UART_17158_FCTR_TRGB 0x40
117 #define UART_17158_FCTR_TRGC 0x80
118 #define UART_17158_FCTR_TRGD 0xC0
120 /* 17158 trigger table selects.. */
121 #define UART_17158_FCTR_BIT6 0x40
122 #define UART_17158_FCTR_BIT7 0x80
124 /* 17158 TX/RX memmapped buffer offsets */
125 #define UART_17158_RX_FIFOSIZE 64
126 #define UART_17158_TX_FIFOSIZE 64
128 /* 17158 Extended IIR's */
129 #define UART_17158_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */
130 #define UART_17158_IIR_XONXOFF 0x10 /* Received an XON/XOFF char */
131 #define UART_17158_IIR_HWFLOW_STATE_CHANGE 0x20 /* CTS/DSR or RTS/DTR
134 #define UART_17158_IIR_FIFO_ENABLED 0xC0 /* 16550 FIFOs are Enabled */
137 * These are the extended interrupts that get sent
138 * back to us from the UART's 32bit interrupt register
140 #define UART_17158_RX_LINE_STATUS 0x1 /* RX Ready */
141 #define UART_17158_RXRDY_TIMEOUT 0x2 /* RX Ready Timeout */
142 #define UART_17158_TXRDY 0x3 /* TX Ready */
143 #define UART_17158_MSR 0x4 /* Modem State Change */
144 #define UART_17158_TX_AND_FIFO_CLR 0x40 /* Transmitter Holding
147 #define UART_17158_RX_FIFO_DATA_ERROR 0x80 /* UART detected an RX FIFO
152 * These are the EXTENDED definitions for the 17C158's Interrupt
155 #define UART_17158_EFR_ECB 0x10 /* Enhanced control bit */
156 #define UART_17158_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */
157 #define UART_17158_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */
158 #define UART_17158_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */
159 #define UART_17158_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow Control Enable */
161 #define UART_17158_XOFF_DETECT 0x1 /* Indicates whether chip saw an
164 #define UART_17158_XON_DETECT 0x2 /* Indicates whether chip saw an
168 #define UART_17158_IER_RSVD1 0x10 /* Reserved by Exar */
169 #define UART_17158_IER_XOFF 0x20 /* Xoff Interrupt Enable */
170 #define UART_17158_IER_RTSDTR 0x40 /* Output Interrupt Enable */
171 #define UART_17158_IER_CTSDSR 0x80 /* Input Interrupt Enable */
173 extern struct board_ops dgnc_neo_ops;
175 #endif /* _DGNC_NEO_H */