2 * Copyright 2003 Digi International (www.digi.com)
3 * Scott H Kilau <Scott_Kilau at digi dot com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more details.
16 #include <linux/kernel.h>
17 #include <linux/sched.h> /* For jiffies, task states */
18 #include <linux/interrupt.h> /* For tasklet and interrupt structs/defines */
19 #include <linux/delay.h> /* For udelay */
20 #include <linux/io.h> /* For read[bwl]/write[bwl] */
21 #include <linux/serial.h> /* For struct async_serial */
22 #include <linux/serial_reg.h> /* For the various UART offsets */
24 #include "dgnc_driver.h" /* Driver main header file */
25 #include "dgnc_neo.h" /* Our header file */
28 static inline void neo_parse_lsr(struct dgnc_board *brd, uint port);
29 static inline void neo_parse_isr(struct dgnc_board *brd, uint port);
30 static void neo_copy_data_from_uart_to_queue(struct channel_t *ch);
31 static inline void neo_clear_break(struct channel_t *ch, int force);
32 static inline void neo_set_cts_flow_control(struct channel_t *ch);
33 static inline void neo_set_rts_flow_control(struct channel_t *ch);
34 static inline void neo_set_ixon_flow_control(struct channel_t *ch);
35 static inline void neo_set_ixoff_flow_control(struct channel_t *ch);
36 static inline void neo_set_no_output_flow_control(struct channel_t *ch);
37 static inline void neo_set_no_input_flow_control(struct channel_t *ch);
38 static inline void neo_set_new_start_stop_chars(struct channel_t *ch);
39 static void neo_parse_modem(struct channel_t *ch, unsigned char signals);
40 static void neo_tasklet(unsigned long data);
41 static void neo_vpd(struct dgnc_board *brd);
42 static void neo_uart_init(struct channel_t *ch);
43 static void neo_uart_off(struct channel_t *ch);
44 static int neo_drain(struct tty_struct *tty, uint seconds);
45 static void neo_param(struct tty_struct *tty);
46 static void neo_assert_modem_signals(struct channel_t *ch);
47 static void neo_flush_uart_write(struct channel_t *ch);
48 static void neo_flush_uart_read(struct channel_t *ch);
49 static void neo_disable_receiver(struct channel_t *ch);
50 static void neo_enable_receiver(struct channel_t *ch);
51 static void neo_send_break(struct channel_t *ch, int msecs);
52 static void neo_send_start_character(struct channel_t *ch);
53 static void neo_send_stop_character(struct channel_t *ch);
54 static void neo_copy_data_from_queue_to_uart(struct channel_t *ch);
55 static uint neo_get_uart_bytes_left(struct channel_t *ch);
56 static void neo_send_immediate_char(struct channel_t *ch, unsigned char c);
57 static irqreturn_t neo_intr(int irq, void *voidbrd);
59 struct board_ops dgnc_neo_ops = {
60 .tasklet = neo_tasklet,
62 .uart_init = neo_uart_init,
63 .uart_off = neo_uart_off,
67 .assert_modem_signals = neo_assert_modem_signals,
68 .flush_uart_write = neo_flush_uart_write,
69 .flush_uart_read = neo_flush_uart_read,
70 .disable_receiver = neo_disable_receiver,
71 .enable_receiver = neo_enable_receiver,
72 .send_break = neo_send_break,
73 .send_start_character = neo_send_start_character,
74 .send_stop_character = neo_send_stop_character,
75 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart,
76 .get_uart_bytes_left = neo_get_uart_bytes_left,
77 .send_immediate_char = neo_send_immediate_char
81 * This function allows calls to ensure that all outstanding
82 * PCI writes have been completed, by doing a PCI read against
83 * a non-destructive, read-only location on the Neo card.
85 * In this case, we are reading the DVID (Read-only Device Identification)
86 * value of the Neo card.
88 static inline void neo_pci_posting_flush(struct dgnc_board *bd)
90 readb(bd->re_map_membase + 0x8D);
93 static inline void neo_set_cts_flow_control(struct channel_t *ch)
95 unsigned char ier = readb(&ch->ch_neo_uart->ier);
96 unsigned char efr = readb(&ch->ch_neo_uart->efr);
98 /* Turn on auto CTS flow control */
100 ier |= UART_17158_IER_CTSDSR;
102 ier &= ~(UART_17158_IER_CTSDSR);
105 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
107 /* Turn off auto Xon flow control */
108 efr &= ~UART_17158_EFR_IXON;
110 /* Why? Because Exar's spec says we have to zero it
111 * out before setting it
113 writeb(0, &ch->ch_neo_uart->efr);
115 /* Turn on UART enhanced bits */
116 writeb(efr, &ch->ch_neo_uart->efr);
118 /* Turn on table D, with 8 char hi/low watermarks */
119 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY,
120 &ch->ch_neo_uart->fctr);
122 /* Feed the UART our trigger levels */
123 writeb(8, &ch->ch_neo_uart->tfifo);
126 writeb(ier, &ch->ch_neo_uart->ier);
128 neo_pci_posting_flush(ch->ch_bd);
131 static inline void neo_set_rts_flow_control(struct channel_t *ch)
133 unsigned char ier = readb(&ch->ch_neo_uart->ier);
134 unsigned char efr = readb(&ch->ch_neo_uart->efr);
136 /* Turn on auto RTS flow control */
138 ier |= UART_17158_IER_RTSDTR;
140 ier &= ~(UART_17158_IER_RTSDTR);
142 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
144 /* Turn off auto Xoff flow control */
145 ier &= ~UART_17158_IER_XOFF;
146 efr &= ~UART_17158_EFR_IXOFF;
148 /* Why? Because Exar's spec says we have to zero it
149 * out before setting it
151 writeb(0, &ch->ch_neo_uart->efr);
153 /* Turn on UART enhanced bits */
154 writeb(efr, &ch->ch_neo_uart->efr);
156 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY,
157 &ch->ch_neo_uart->fctr);
158 ch->ch_r_watermark = 4;
160 writeb(32, &ch->ch_neo_uart->rfifo);
161 ch->ch_r_tlevel = 32;
163 writeb(ier, &ch->ch_neo_uart->ier);
166 * From the Neo UART spec sheet:
167 * The auto RTS/DTR function must be started by asserting
168 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after
171 ch->ch_mostat |= UART_MCR_RTS;
173 neo_pci_posting_flush(ch->ch_bd);
176 static inline void neo_set_ixon_flow_control(struct channel_t *ch)
178 unsigned char ier = readb(&ch->ch_neo_uart->ier);
179 unsigned char efr = readb(&ch->ch_neo_uart->efr);
181 /* Turn off auto CTS flow control */
182 ier &= ~UART_17158_IER_CTSDSR;
183 efr &= ~UART_17158_EFR_CTSDSR;
185 /* Turn on auto Xon flow control */
186 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
188 /* Why? Because Exar's spec says we have to zero it
189 * out before setting it
191 writeb(0, &ch->ch_neo_uart->efr);
193 /* Turn on UART enhanced bits */
194 writeb(efr, &ch->ch_neo_uart->efr);
196 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
197 &ch->ch_neo_uart->fctr);
198 ch->ch_r_watermark = 4;
200 writeb(32, &ch->ch_neo_uart->rfifo);
201 ch->ch_r_tlevel = 32;
203 /* Tell UART what start/stop chars it should be looking for */
204 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
205 writeb(0, &ch->ch_neo_uart->xonchar2);
207 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
208 writeb(0, &ch->ch_neo_uart->xoffchar2);
210 writeb(ier, &ch->ch_neo_uart->ier);
212 neo_pci_posting_flush(ch->ch_bd);
215 static inline void neo_set_ixoff_flow_control(struct channel_t *ch)
217 unsigned char ier = readb(&ch->ch_neo_uart->ier);
218 unsigned char efr = readb(&ch->ch_neo_uart->efr);
220 /* Turn off auto RTS flow control */
221 ier &= ~UART_17158_IER_RTSDTR;
222 efr &= ~UART_17158_EFR_RTSDTR;
224 /* Turn on auto Xoff flow control */
225 ier |= UART_17158_IER_XOFF;
226 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
228 /* Why? Because Exar's spec says we have to zero it
229 * out before setting it
231 writeb(0, &ch->ch_neo_uart->efr);
233 /* Turn on UART enhanced bits */
234 writeb(efr, &ch->ch_neo_uart->efr);
236 /* Turn on table D, with 8 char hi/low watermarks */
237 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
238 &ch->ch_neo_uart->fctr);
240 writeb(8, &ch->ch_neo_uart->tfifo);
243 /* Tell UART what start/stop chars it should be looking for */
244 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
245 writeb(0, &ch->ch_neo_uart->xonchar2);
247 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
248 writeb(0, &ch->ch_neo_uart->xoffchar2);
250 writeb(ier, &ch->ch_neo_uart->ier);
252 neo_pci_posting_flush(ch->ch_bd);
255 static inline void neo_set_no_input_flow_control(struct channel_t *ch)
257 unsigned char ier = readb(&ch->ch_neo_uart->ier);
258 unsigned char efr = readb(&ch->ch_neo_uart->efr);
260 /* Turn off auto RTS flow control */
261 ier &= ~UART_17158_IER_RTSDTR;
262 efr &= ~UART_17158_EFR_RTSDTR;
264 /* Turn off auto Xoff flow control */
265 ier &= ~UART_17158_IER_XOFF;
266 if (ch->ch_c_iflag & IXON)
267 efr &= ~(UART_17158_EFR_IXOFF);
269 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
271 /* Why? Because Exar's spec says we have to zero
272 * it out before setting it
274 writeb(0, &ch->ch_neo_uart->efr);
276 /* Turn on UART enhanced bits */
277 writeb(efr, &ch->ch_neo_uart->efr);
279 /* Turn on table D, with 8 char hi/low watermarks */
280 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
281 &ch->ch_neo_uart->fctr);
283 ch->ch_r_watermark = 0;
285 writeb(16, &ch->ch_neo_uart->tfifo);
286 ch->ch_t_tlevel = 16;
288 writeb(16, &ch->ch_neo_uart->rfifo);
289 ch->ch_r_tlevel = 16;
291 writeb(ier, &ch->ch_neo_uart->ier);
293 neo_pci_posting_flush(ch->ch_bd);
296 static inline void neo_set_no_output_flow_control(struct channel_t *ch)
298 unsigned char ier = readb(&ch->ch_neo_uart->ier);
299 unsigned char efr = readb(&ch->ch_neo_uart->efr);
301 /* Turn off auto CTS flow control */
302 ier &= ~UART_17158_IER_CTSDSR;
303 efr &= ~UART_17158_EFR_CTSDSR;
305 /* Turn off auto Xon flow control */
306 if (ch->ch_c_iflag & IXOFF)
307 efr &= ~UART_17158_EFR_IXON;
309 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
311 /* Why? Because Exar's spec says we have to zero it
312 * out before setting it
314 writeb(0, &ch->ch_neo_uart->efr);
316 /* Turn on UART enhanced bits */
317 writeb(efr, &ch->ch_neo_uart->efr);
319 /* Turn on table D, with 8 char hi/low watermarks */
320 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
321 &ch->ch_neo_uart->fctr);
323 ch->ch_r_watermark = 0;
325 writeb(16, &ch->ch_neo_uart->tfifo);
326 ch->ch_t_tlevel = 16;
328 writeb(16, &ch->ch_neo_uart->rfifo);
329 ch->ch_r_tlevel = 16;
331 writeb(ier, &ch->ch_neo_uart->ier);
333 neo_pci_posting_flush(ch->ch_bd);
336 /* change UARTs start/stop chars */
337 static inline void neo_set_new_start_stop_chars(struct channel_t *ch)
339 /* if hardware flow control is set, then skip this whole thing */
340 if (ch->ch_digi.digi_flags & (CTSPACE | RTSPACE) ||
341 ch->ch_c_cflag & CRTSCTS)
344 /* Tell UART what start/stop chars it should be looking for */
345 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
346 writeb(0, &ch->ch_neo_uart->xonchar2);
348 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
349 writeb(0, &ch->ch_neo_uart->xoffchar2);
351 neo_pci_posting_flush(ch->ch_bd);
355 * No locks are assumed to be held when calling this function.
357 static inline void neo_clear_break(struct channel_t *ch, int force)
361 spin_lock_irqsave(&ch->ch_lock, flags);
363 /* Bail if we aren't currently sending a break. */
364 if (!ch->ch_stop_sending_break) {
365 spin_unlock_irqrestore(&ch->ch_lock, flags);
369 /* Turn break off, and unset some variables */
370 if (ch->ch_flags & CH_BREAK_SENDING) {
372 time_after_eq(jiffies, ch->ch_stop_sending_break)) {
373 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
375 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
376 neo_pci_posting_flush(ch->ch_bd);
377 ch->ch_flags &= ~(CH_BREAK_SENDING);
378 ch->ch_stop_sending_break = 0;
381 spin_unlock_irqrestore(&ch->ch_lock, flags);
385 * Parse the ISR register.
387 static inline void neo_parse_isr(struct dgnc_board *brd, uint port)
389 struct channel_t *ch;
394 ch = brd->channels[port];
395 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
398 /* Here we try to figure out what caused the interrupt to happen */
400 isr = readb(&ch->ch_neo_uart->isr_fcr);
402 /* Bail if no pending interrupt */
403 if (isr & UART_IIR_NO_INT)
407 * Yank off the upper 2 bits,
408 * which just show that the FIFO's are enabled.
410 isr &= ~(UART_17158_IIR_FIFO_ENABLED);
412 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
413 /* Read data from uart -> queue */
414 neo_copy_data_from_uart_to_queue(ch);
416 /* Call our tty layer to enforce queue
417 * flow control if needed.
419 spin_lock_irqsave(&ch->ch_lock, flags);
420 dgnc_check_queue_flow_control(ch);
421 spin_unlock_irqrestore(&ch->ch_lock, flags);
424 if (isr & UART_IIR_THRI) {
425 /* Transfer data (if any) from Write Queue -> UART. */
426 spin_lock_irqsave(&ch->ch_lock, flags);
427 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
428 spin_unlock_irqrestore(&ch->ch_lock, flags);
429 neo_copy_data_from_queue_to_uart(ch);
432 if (isr & UART_17158_IIR_XONXOFF) {
433 cause = readb(&ch->ch_neo_uart->xoffchar1);
436 * Since the UART detected either an XON or
437 * XOFF match, we need to figure out which
438 * one it was, so we can suspend or resume data flow.
440 if (cause == UART_17158_XON_DETECT) {
441 /* Is output stopped right now, if so,
444 if (brd->channels[port]->ch_flags & CH_STOP) {
445 spin_lock_irqsave(&ch->ch_lock,
447 ch->ch_flags &= ~(CH_STOP);
448 spin_unlock_irqrestore(&ch->ch_lock,
451 } else if (cause == UART_17158_XOFF_DETECT) {
452 if (!(brd->channels[port]->ch_flags &
454 spin_lock_irqsave(&ch->ch_lock,
456 ch->ch_flags |= CH_STOP;
457 spin_unlock_irqrestore(&ch->ch_lock,
463 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
465 * If we get here, this means the hardware is
466 * doing auto flow control. Check to see whether
467 * RTS/DTR or CTS/DSR caused this interrupt.
469 cause = readb(&ch->ch_neo_uart->mcr);
470 /* Which pin is doing auto flow? RTS or DTR? */
471 if ((cause & 0x4) == 0) {
472 if (cause & UART_MCR_RTS) {
473 spin_lock_irqsave(&ch->ch_lock,
475 ch->ch_mostat |= UART_MCR_RTS;
476 spin_unlock_irqrestore(&ch->ch_lock,
479 spin_lock_irqsave(&ch->ch_lock,
481 ch->ch_mostat &= ~(UART_MCR_RTS);
482 spin_unlock_irqrestore(&ch->ch_lock,
486 if (cause & UART_MCR_DTR) {
487 spin_lock_irqsave(&ch->ch_lock,
489 ch->ch_mostat |= UART_MCR_DTR;
490 spin_unlock_irqrestore(&ch->ch_lock,
493 spin_lock_irqsave(&ch->ch_lock,
495 ch->ch_mostat &= ~(UART_MCR_DTR);
496 spin_unlock_irqrestore(&ch->ch_lock,
502 /* Parse any modem signal changes */
503 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
507 static inline void neo_parse_lsr(struct dgnc_board *brd, uint port)
509 struct channel_t *ch;
514 * Check to make sure it didn't receive interrupt with a null board
515 * associated or a board pointer that wasn't ours.
517 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
520 if (port >= brd->maxports)
523 ch = brd->channels[port];
524 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
527 linestatus = readb(&ch->ch_neo_uart->lsr);
529 ch->ch_cached_lsr |= linestatus;
531 if (ch->ch_cached_lsr & UART_LSR_DR) {
532 /* Read data from uart -> queue */
533 neo_copy_data_from_uart_to_queue(ch);
534 spin_lock_irqsave(&ch->ch_lock, flags);
535 dgnc_check_queue_flow_control(ch);
536 spin_unlock_irqrestore(&ch->ch_lock, flags);
540 * The next 3 tests should *NOT* happen, as the above test
541 * should encapsulate all 3... At least, thats what Exar says.
544 if (linestatus & UART_LSR_PE)
547 if (linestatus & UART_LSR_FE)
550 if (linestatus & UART_LSR_BI)
553 if (linestatus & UART_LSR_OE) {
555 * Rx Oruns. Exar says that an orun will NOT corrupt
556 * the FIFO. It will just replace the holding register
557 * with this new data byte. So basically just ignore this.
558 * Probably we should eventually have an orun stat in our
561 ch->ch_err_overrun++;
564 if (linestatus & UART_LSR_THRE) {
565 spin_lock_irqsave(&ch->ch_lock, flags);
566 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
567 spin_unlock_irqrestore(&ch->ch_lock, flags);
569 /* Transfer data (if any) from Write Queue -> UART. */
570 neo_copy_data_from_queue_to_uart(ch);
571 } else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
572 spin_lock_irqsave(&ch->ch_lock, flags);
573 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
574 spin_unlock_irqrestore(&ch->ch_lock, flags);
576 /* Transfer data (if any) from Write Queue -> UART. */
577 neo_copy_data_from_queue_to_uart(ch);
583 * Send any/all changes to the line to the UART.
585 static void neo_param(struct tty_struct *tty)
587 unsigned char lcr = 0;
588 unsigned char uart_lcr = 0;
589 unsigned char ier = 0;
590 unsigned char uart_ier = 0;
593 struct dgnc_board *bd;
594 struct channel_t *ch;
597 if (!tty || tty->magic != TTY_MAGIC)
600 un = (struct un_t *)tty->driver_data;
601 if (!un || un->magic != DGNC_UNIT_MAGIC)
605 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
609 if (!bd || bd->magic != DGNC_BOARD_MAGIC)
613 * If baud rate is zero, flush queues, and set mval to drop DTR.
615 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
623 neo_flush_uart_write(ch);
624 neo_flush_uart_read(ch);
626 /* The baudrate is B0 so all modem lines are to be dropped. */
627 ch->ch_flags |= (CH_BAUD0);
628 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
629 neo_assert_modem_signals(ch);
633 } else if (ch->ch_custom_speed) {
634 baud = ch->ch_custom_speed;
635 /* Handle transition from B0 */
636 if (ch->ch_flags & CH_BAUD0) {
637 ch->ch_flags &= ~(CH_BAUD0);
640 * Bring back up RTS and DTR...
641 * Also handle RTS or DTR toggle if set.
643 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
644 ch->ch_mostat |= (UART_MCR_RTS);
645 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
646 ch->ch_mostat |= (UART_MCR_DTR);
652 ulong bauds[4][16] = {
656 600, 1200, 1800, 2400,
657 4800, 9600, 19200, 38400 },
658 { /* slowbaud & CBAUDEX */
659 0, 57600, 115200, 230400,
660 460800, 150, 200, 921600,
661 600, 1200, 1800, 2400,
662 4800, 9600, 19200, 38400 },
664 0, 57600, 76800, 115200,
665 131657, 153600, 230400, 460800,
666 921600, 1200, 1800, 2400,
667 4800, 9600, 19200, 38400 },
668 { /* fastbaud & CBAUDEX */
669 0, 57600, 115200, 230400,
670 460800, 150, 200, 921600,
671 600, 1200, 1800, 2400,
672 4800, 9600, 19200, 38400 }
675 /* Only use the TXPrint baud rate if the terminal unit
678 if (!(ch->ch_tun.un_flags & UN_ISOPEN) &&
679 (un->un_type == DGNC_PRINT))
680 baud = C_BAUD(ch->ch_pun.un_tty) & 0xff;
682 baud = C_BAUD(ch->ch_tun.un_tty) & 0xff;
684 if (ch->ch_c_cflag & CBAUDEX)
687 if (ch->ch_digi.digi_flags & DIGI_FAST)
692 if ((iindex >= 0) && (iindex < 4) &&
693 (jindex >= 0) && (jindex < 16))
694 baud = bauds[iindex][jindex];
701 /* Handle transition from B0 */
702 if (ch->ch_flags & CH_BAUD0) {
703 ch->ch_flags &= ~(CH_BAUD0);
706 * Bring back up RTS and DTR...
707 * Also handle RTS or DTR toggle if set.
709 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
710 ch->ch_mostat |= (UART_MCR_RTS);
711 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
712 ch->ch_mostat |= (UART_MCR_DTR);
716 if (ch->ch_c_cflag & PARENB)
717 lcr |= UART_LCR_PARITY;
719 if (!(ch->ch_c_cflag & PARODD))
720 lcr |= UART_LCR_EPAR;
723 * Not all platforms support mark/space parity,
724 * so this will hide behind an ifdef.
727 if (ch->ch_c_cflag & CMSPAR)
728 lcr |= UART_LCR_SPAR;
731 if (ch->ch_c_cflag & CSTOPB)
732 lcr |= UART_LCR_STOP;
734 switch (ch->ch_c_cflag & CSIZE) {
736 lcr |= UART_LCR_WLEN5;
739 lcr |= UART_LCR_WLEN6;
742 lcr |= UART_LCR_WLEN7;
746 lcr |= UART_LCR_WLEN8;
750 uart_ier = readb(&ch->ch_neo_uart->ier);
753 uart_lcr = readb(&ch->ch_neo_uart->lcr);
758 quot = ch->ch_bd->bd_dividend / baud;
760 if (quot != 0 && ch->ch_old_baud != baud) {
761 ch->ch_old_baud = baud;
762 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
763 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
764 writeb((quot >> 8), &ch->ch_neo_uart->ier);
765 writeb(lcr, &ch->ch_neo_uart->lcr);
769 writeb(lcr, &ch->ch_neo_uart->lcr);
771 if (ch->ch_c_cflag & CREAD)
772 ier |= (UART_IER_RDI | UART_IER_RLSI);
774 ier &= ~(UART_IER_RDI | UART_IER_RLSI);
777 * Have the UART interrupt on modem signal changes ONLY when
778 * we are in hardware flow control mode, or CLOCAL/FORCEDCD is not set.
780 if ((ch->ch_digi.digi_flags & CTSPACE) ||
781 (ch->ch_digi.digi_flags & RTSPACE) ||
782 (ch->ch_c_cflag & CRTSCTS) ||
783 !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) ||
784 !(ch->ch_c_cflag & CLOCAL))
787 ier &= ~UART_IER_MSI;
789 ier |= UART_IER_THRI;
792 writeb(ier, &ch->ch_neo_uart->ier);
794 /* Set new start/stop chars */
795 neo_set_new_start_stop_chars(ch);
797 if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) {
798 neo_set_cts_flow_control(ch);
799 } else if (ch->ch_c_iflag & IXON) {
800 /* If start/stop is set to disable, then we should
801 * disable flow control
803 if ((ch->ch_startc == _POSIX_VDISABLE) ||
804 (ch->ch_stopc == _POSIX_VDISABLE))
805 neo_set_no_output_flow_control(ch);
807 neo_set_ixon_flow_control(ch);
809 neo_set_no_output_flow_control(ch);
812 if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) {
813 neo_set_rts_flow_control(ch);
814 } else if (ch->ch_c_iflag & IXOFF) {
815 /* If start/stop is set to disable, then we should
816 * disable flow control
818 if ((ch->ch_startc == _POSIX_VDISABLE) ||
819 (ch->ch_stopc == _POSIX_VDISABLE))
820 neo_set_no_input_flow_control(ch);
822 neo_set_ixoff_flow_control(ch);
824 neo_set_no_input_flow_control(ch);
828 * Adjust the RX FIFO Trigger level if baud is less than 9600.
829 * Not exactly elegant, but this is needed because of the Exar chip's
830 * delay on firing off the RX FIFO interrupt on slower baud rates.
833 writeb(1, &ch->ch_neo_uart->rfifo);
837 neo_assert_modem_signals(ch);
839 /* Get current status of the modem signals now */
840 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
844 * Our board poller function.
846 static void neo_tasklet(unsigned long data)
848 struct dgnc_board *bd = (struct dgnc_board *)data;
849 struct channel_t *ch;
855 if (!bd || bd->magic != DGNC_BOARD_MAGIC)
858 /* Cache a couple board values */
859 spin_lock_irqsave(&bd->bd_lock, flags);
862 spin_unlock_irqrestore(&bd->bd_lock, flags);
865 * Do NOT allow the interrupt routine to read the intr registers
866 * Until we release this lock.
868 spin_lock_irqsave(&bd->bd_intr_lock, flags);
871 * If board is ready, parse deeper to see if there is anything to do.
873 if ((state == BOARD_READY) && (ports > 0)) {
874 /* Loop on each port */
875 for (i = 0; i < ports; i++) {
876 ch = bd->channels[i];
878 /* Just being careful... */
879 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
883 * NOTE: Remember you CANNOT hold any channel
884 * locks when calling the input routine.
886 * During input processing, its possible we
887 * will call the Linux ld, which might in turn,
888 * do a callback right back into us, resulting
889 * in us trying to grab the channel lock twice!
894 * Channel lock is grabbed and then released
895 * inside both of these routines, but neither
896 * call anything else that could call back into us.
898 neo_copy_data_from_queue_to_uart(ch);
899 dgnc_wakeup_writes(ch);
902 * Call carrier carrier function, in case something
908 * Check to see if we need to turn off a sending break.
909 * The timing check is done inside clear_break()
911 if (ch->ch_stop_sending_break)
912 neo_clear_break(ch, 0);
916 /* Allow interrupt routine to access the interrupt register again */
917 spin_unlock_irqrestore(&bd->bd_intr_lock, flags);
923 * Neo specific interrupt handler.
925 static irqreturn_t neo_intr(int irq, void *voidbrd)
927 struct dgnc_board *brd = voidbrd;
928 struct channel_t *ch;
933 unsigned long flags2;
936 * Check to make sure it didn't receive interrupt with a null board
937 * associated or a board pointer that wasn't ours.
939 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
942 /* Lock out the slow poller from running on this board. */
943 spin_lock_irqsave(&brd->bd_intr_lock, flags);
946 * Read in "extended" IRQ information from the 32bit Neo register.
947 * Bits 0-7: What port triggered the interrupt.
948 * Bits 8-31: Each 3bits indicate what type of interrupt occurred.
950 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
953 * If 0, no interrupts pending.
954 * This can happen if the IRQ is shared among a couple Neo/Classic
958 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
963 * At this point, we have at least SOMETHING to service, dig
967 /* Loop on each port */
968 while ((uart_poll & 0xff) != 0) {
969 type = uart_poll >> (8 + (port * 3));
972 uart_poll &= ~(0x01 << port);
974 /* Switch on type of interrupt we have */
976 case UART_17158_RXRDY_TIMEOUT:
978 * RXRDY Time-out is cleared by reading data in the
979 * RX FIFO until it falls below the trigger level.
982 /* Verify the port is in range. */
983 if (port >= brd->nasync)
986 ch = brd->channels[port];
987 neo_copy_data_from_uart_to_queue(ch);
990 * Call our tty layer to enforce queue flow control if
993 spin_lock_irqsave(&ch->ch_lock, flags2);
994 dgnc_check_queue_flow_control(ch);
995 spin_unlock_irqrestore(&ch->ch_lock, flags2);
999 case UART_17158_RX_LINE_STATUS:
1001 * RXRDY and RX LINE Status (logic OR of LSR[4:1])
1003 neo_parse_lsr(brd, port);
1006 case UART_17158_TXRDY:
1008 * TXRDY interrupt clears after reading ISR register
1009 * for the UART channel.
1013 * Yes, this is odd...
1014 * Why would I check EVERY possibility of type of
1015 * interrupt, when we know its TXRDY???
1016 * Becuz for some reason, even tho we got triggered for
1017 * TXRDY, it seems to be occasionally wrong. Instead of
1018 * TX, which it should be, I was getting things like
1021 neo_parse_isr(brd, port);
1024 case UART_17158_MSR:
1026 * MSR or flow control was seen.
1028 neo_parse_isr(brd, port);
1033 * The UART triggered us with a bogus interrupt type.
1034 * It appears the Exar chip, when REALLY bogged down,
1035 * will throw these once and awhile.
1036 * Its harmless, just ignore it and move on.
1045 * Schedule tasklet to more in-depth servicing at a better time.
1047 tasklet_schedule(&brd->helper_tasklet);
1049 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
1055 * Neo specific way of turning off the receiver.
1056 * Used as a way to enforce queue flow control when in
1057 * hardware flow control mode.
1059 static void neo_disable_receiver(struct channel_t *ch)
1061 unsigned char tmp = readb(&ch->ch_neo_uart->ier);
1063 tmp &= ~(UART_IER_RDI);
1064 writeb(tmp, &ch->ch_neo_uart->ier);
1065 neo_pci_posting_flush(ch->ch_bd);
1069 * Neo specific way of turning on the receiver.
1070 * Used as a way to un-enforce queue flow control when in
1071 * hardware flow control mode.
1073 static void neo_enable_receiver(struct channel_t *ch)
1075 unsigned char tmp = readb(&ch->ch_neo_uart->ier);
1077 tmp |= (UART_IER_RDI);
1078 writeb(tmp, &ch->ch_neo_uart->ier);
1079 neo_pci_posting_flush(ch->ch_bd);
1082 static void neo_copy_data_from_uart_to_queue(struct channel_t *ch)
1085 unsigned char linestatus = 0;
1086 unsigned char error_mask = 0;
1091 unsigned long flags;
1093 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1096 spin_lock_irqsave(&ch->ch_lock, flags);
1098 /* cache head and tail of queue */
1099 head = ch->ch_r_head & RQUEUEMASK;
1100 tail = ch->ch_r_tail & RQUEUEMASK;
1102 /* Get our cached LSR */
1103 linestatus = ch->ch_cached_lsr;
1104 ch->ch_cached_lsr = 0;
1106 /* Store how much space we have left in the queue */
1107 qleft = tail - head - 1;
1109 qleft += RQUEUEMASK + 1;
1112 * If the UART is not in FIFO mode, force the FIFO copy to
1113 * NOT be run, by setting total to 0.
1115 * On the other hand, if the UART IS in FIFO mode, then ask
1116 * the UART to give us an approximation of data it has RX'ed.
1118 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
1121 total = readb(&ch->ch_neo_uart->rfifo);
1124 * EXAR chip bug - RX FIFO COUNT - Fudge factor.
1126 * This resolves a problem/bug with the Exar chip that sometimes
1127 * returns a bogus value in the rfifo register.
1128 * The count can be any where from 0-3 bytes "off".
1129 * Bizarre, but true.
1131 if ((ch->ch_bd->dvid & 0xf0) >= UART_XR17E158_DVID)
1138 * Finally, bound the copy to make sure we don't overflow
1140 * The byte by byte copy loop below this loop this will
1141 * deal with the queue overflow possibility.
1143 total = min(total, qleft);
1147 * Grab the linestatus register, we need to check
1148 * to see if there are any errors in the FIFO.
1150 linestatus = readb(&ch->ch_neo_uart->lsr);
1153 * Break out if there is a FIFO error somewhere.
1154 * This will allow us to go byte by byte down below,
1155 * finding the exact location of the error.
1157 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
1160 /* Make sure we don't go over the end of our queue */
1161 n = min(((uint)total), (RQUEUESIZE - (uint)head));
1164 * Cut down n even further if needed, this is to fix
1165 * a problem with memcpy_fromio() with the Neo on the
1166 * IBM pSeries platform.
1167 * 15 bytes max appears to be the magic number.
1169 n = min_t(uint, n, 12);
1172 * Since we are grabbing the linestatus register, which
1173 * will reset some bits after our read, we need to ensure
1174 * we don't miss our TX FIFO emptys.
1176 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
1177 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1181 /* Copy data from uart to the queue */
1182 memcpy_fromio(ch->ch_rqueue + head,
1183 &ch->ch_neo_uart->txrxburst, n);
1186 * Since RX_FIFO_DATA_ERROR was 0, we are guaranteed
1187 * that all the data currently in the FIFO is free of
1188 * breaks and parity/frame/orun errors.
1190 memset(ch->ch_equeue + head, 0, n);
1192 /* Add to and flip head if needed */
1193 head = (head + n) & RQUEUEMASK;
1196 ch->ch_rxcount += n;
1200 * Create a mask to determine whether we should
1201 * insert the character (if any) into our queue.
1203 if (ch->ch_c_iflag & IGNBRK)
1204 error_mask |= UART_LSR_BI;
1207 * Now cleanup any leftover bytes still in the UART.
1208 * Also deal with any possible queue overflow here as well.
1212 * Its possible we have a linestatus from the loop above
1213 * this, so we "OR" on any extra bits.
1215 linestatus |= readb(&ch->ch_neo_uart->lsr);
1218 * If the chip tells us there is no more data pending to
1219 * be read, we can then leave.
1220 * But before we do, cache the linestatus, just in case.
1222 if (!(linestatus & UART_LSR_DR)) {
1223 ch->ch_cached_lsr = linestatus;
1227 /* No need to store this bit */
1228 linestatus &= ~UART_LSR_DR;
1231 * Since we are grabbing the linestatus register, which
1232 * will reset some bits after our read, we need to ensure
1233 * we don't miss our TX FIFO emptys.
1235 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
1236 linestatus &= ~(UART_LSR_THRE |
1237 UART_17158_TX_AND_FIFO_CLR);
1238 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1242 * Discard character if we are ignoring the error mask.
1244 if (linestatus & error_mask) {
1245 unsigned char discard;
1248 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
1253 * If our queue is full, we have no choice but to drop some
1255 * The assumption is that HWFLOW or SWFLOW should have stopped
1256 * things way way before we got to this point.
1258 * I decided that I wanted to ditch the oldest data first,
1259 * I hope thats okay with everyone? Yes? Good.
1262 tail = (tail + 1) & RQUEUEMASK;
1263 ch->ch_r_tail = tail;
1264 ch->ch_err_overrun++;
1268 memcpy_fromio(ch->ch_rqueue + head,
1269 &ch->ch_neo_uart->txrxburst, 1);
1270 ch->ch_equeue[head] = (unsigned char)linestatus;
1272 /* Ditch any remaining linestatus value. */
1275 /* Add to and flip head if needed */
1276 head = (head + 1) & RQUEUEMASK;
1283 * Write new final heads to channel structure.
1285 ch->ch_r_head = head & RQUEUEMASK;
1286 ch->ch_e_head = head & EQUEUEMASK;
1288 spin_unlock_irqrestore(&ch->ch_lock, flags);
1292 * This function basically goes to sleep for secs, or until
1293 * it gets signalled that the port has fully drained.
1295 static int neo_drain(struct tty_struct *tty, uint seconds)
1297 unsigned long flags;
1298 struct channel_t *ch;
1302 if (!tty || tty->magic != TTY_MAGIC)
1305 un = (struct un_t *)tty->driver_data;
1306 if (!un || un->magic != DGNC_UNIT_MAGIC)
1310 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1313 spin_lock_irqsave(&ch->ch_lock, flags);
1314 un->un_flags |= UN_EMPTY;
1315 spin_unlock_irqrestore(&ch->ch_lock, flags);
1318 * Go to sleep waiting for the tty layer to wake me back up when
1319 * the empty flag goes away.
1321 rc = wait_event_interruptible_timeout(un->un_flags_wait,
1322 ((un->un_flags & UN_EMPTY) == 0),
1323 msecs_to_jiffies(seconds * 1000));
1325 /* If ret is non-zero, user ctrl-c'ed us */
1330 * Flush the WRITE FIFO on the Neo.
1332 * NOTE: Channel lock MUST be held before calling this function!
1334 static void neo_flush_uart_write(struct channel_t *ch)
1336 unsigned char tmp = 0;
1339 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1342 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT),
1343 &ch->ch_neo_uart->isr_fcr);
1344 neo_pci_posting_flush(ch->ch_bd);
1346 for (i = 0; i < 10; i++) {
1348 * Check to see if the UART feels it completely flushed the
1351 tmp = readb(&ch->ch_neo_uart->isr_fcr);
1358 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1362 * Flush the READ FIFO on the Neo.
1364 * NOTE: Channel lock MUST be held before calling this function!
1366 static void neo_flush_uart_read(struct channel_t *ch)
1368 unsigned char tmp = 0;
1371 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1374 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR,
1375 &ch->ch_neo_uart->isr_fcr);
1376 neo_pci_posting_flush(ch->ch_bd);
1378 for (i = 0; i < 10; i++) {
1380 * Check to see if the UART feels it completely flushed the
1383 tmp = readb(&ch->ch_neo_uart->isr_fcr);
1391 static void neo_copy_data_from_queue_to_uart(struct channel_t *ch)
1398 uint len_written = 0;
1399 unsigned long flags;
1401 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1404 spin_lock_irqsave(&ch->ch_lock, flags);
1406 /* No data to write to the UART */
1407 if (ch->ch_w_tail == ch->ch_w_head)
1410 /* If port is "stopped", don't send any data to the UART */
1411 if ((ch->ch_flags & CH_FORCED_STOP) ||
1412 (ch->ch_flags & CH_BREAK_SENDING))
1416 * If FIFOs are disabled. Send data directly to txrx register
1418 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
1419 unsigned char lsrbits = readb(&ch->ch_neo_uart->lsr);
1421 /* Cache the LSR bits for later parsing */
1422 ch->ch_cached_lsr |= lsrbits;
1423 if (ch->ch_cached_lsr & UART_LSR_THRE) {
1424 ch->ch_cached_lsr &= ~(UART_LSR_THRE);
1427 * If RTS Toggle mode is on, turn on RTS now if not
1428 * already set, and make sure we get an event when the
1429 * data transfer has completed.
1431 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1432 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1433 ch->ch_mostat |= (UART_MCR_RTS);
1434 neo_assert_modem_signals(ch);
1436 ch->ch_tun.un_flags |= (UN_EMPTY);
1439 * If DTR Toggle mode is on, turn on DTR now if not
1440 * already set, and make sure we get an event when the
1441 * data transfer has completed.
1443 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1444 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1445 ch->ch_mostat |= (UART_MCR_DTR);
1446 neo_assert_modem_signals(ch);
1448 ch->ch_tun.un_flags |= (UN_EMPTY);
1451 writeb(ch->ch_wqueue[ch->ch_w_tail],
1452 &ch->ch_neo_uart->txrx);
1454 ch->ch_w_tail &= WQUEUEMASK;
1462 * We have to do it this way, because of the EXAR TXFIFO count bug.
1464 if ((ch->ch_bd->dvid & 0xf0) < UART_XR17E158_DVID) {
1465 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
1470 n = readb(&ch->ch_neo_uart->tfifo);
1472 if ((unsigned int)n > ch->ch_t_tlevel)
1475 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
1477 n = UART_17158_TX_FIFOSIZE - readb(&ch->ch_neo_uart->tfifo);
1480 /* cache head and tail of queue */
1481 head = ch->ch_w_head & WQUEUEMASK;
1482 tail = ch->ch_w_tail & WQUEUEMASK;
1483 qlen = (head - tail) & WQUEUEMASK;
1485 /* Find minimum of the FIFO space, versus queue length */
1489 s = ((head >= tail) ? head : WQUEUESIZE) - tail;
1496 * If RTS Toggle mode is on, turn on RTS now if not already set,
1497 * and make sure we get an event when the data transfer has
1500 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1501 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1502 ch->ch_mostat |= (UART_MCR_RTS);
1503 neo_assert_modem_signals(ch);
1505 ch->ch_tun.un_flags |= (UN_EMPTY);
1509 * If DTR Toggle mode is on, turn on DTR now if not already set,
1510 * and make sure we get an event when the data transfer has
1513 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1514 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1515 ch->ch_mostat |= (UART_MCR_DTR);
1516 neo_assert_modem_signals(ch);
1518 ch->ch_tun.un_flags |= (UN_EMPTY);
1521 memcpy_toio(&ch->ch_neo_uart->txrxburst,
1522 ch->ch_wqueue + tail, s);
1524 /* Add and flip queue if needed */
1525 tail = (tail + s) & WQUEUEMASK;
1527 ch->ch_txcount += s;
1531 /* Update the final tail */
1532 ch->ch_w_tail = tail & WQUEUEMASK;
1534 if (len_written > 0) {
1535 neo_pci_posting_flush(ch->ch_bd);
1536 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1540 spin_unlock_irqrestore(&ch->ch_lock, flags);
1543 static void neo_parse_modem(struct channel_t *ch, unsigned char signals)
1545 unsigned char msignals = signals;
1547 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1551 * Do altpin switching. Altpin switches DCD and DSR.
1552 * This prolly breaks DSRPACE, so we should be more clever here.
1554 if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
1555 unsigned char mswap = msignals;
1557 if (mswap & UART_MSR_DDCD) {
1558 msignals &= ~UART_MSR_DDCD;
1559 msignals |= UART_MSR_DDSR;
1561 if (mswap & UART_MSR_DDSR) {
1562 msignals &= ~UART_MSR_DDSR;
1563 msignals |= UART_MSR_DDCD;
1565 if (mswap & UART_MSR_DCD) {
1566 msignals &= ~UART_MSR_DCD;
1567 msignals |= UART_MSR_DSR;
1569 if (mswap & UART_MSR_DSR) {
1570 msignals &= ~UART_MSR_DSR;
1571 msignals |= UART_MSR_DCD;
1576 * Scrub off lower bits. They signify delta's, which I don't care
1581 if (msignals & UART_MSR_DCD)
1582 ch->ch_mistat |= UART_MSR_DCD;
1584 ch->ch_mistat &= ~UART_MSR_DCD;
1586 if (msignals & UART_MSR_DSR)
1587 ch->ch_mistat |= UART_MSR_DSR;
1589 ch->ch_mistat &= ~UART_MSR_DSR;
1591 if (msignals & UART_MSR_RI)
1592 ch->ch_mistat |= UART_MSR_RI;
1594 ch->ch_mistat &= ~UART_MSR_RI;
1596 if (msignals & UART_MSR_CTS)
1597 ch->ch_mistat |= UART_MSR_CTS;
1599 ch->ch_mistat &= ~UART_MSR_CTS;
1602 /* Make the UART raise any of the output signals we want up */
1603 static void neo_assert_modem_signals(struct channel_t *ch)
1607 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1610 out = ch->ch_mostat;
1612 if (ch->ch_flags & CH_LOOPBACK)
1613 out |= UART_MCR_LOOP;
1615 writeb(out, &ch->ch_neo_uart->mcr);
1616 neo_pci_posting_flush(ch->ch_bd);
1618 /* Give time for the UART to actually raise/drop the signals */
1622 static void neo_send_start_character(struct channel_t *ch)
1624 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1627 if (ch->ch_startc != _POSIX_VDISABLE) {
1629 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1630 neo_pci_posting_flush(ch->ch_bd);
1635 static void neo_send_stop_character(struct channel_t *ch)
1637 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1640 if (ch->ch_stopc != _POSIX_VDISABLE) {
1641 ch->ch_xoff_sends++;
1642 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1643 neo_pci_posting_flush(ch->ch_bd);
1651 static void neo_uart_init(struct channel_t *ch)
1653 writeb(0, &ch->ch_neo_uart->ier);
1654 writeb(0, &ch->ch_neo_uart->efr);
1655 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1657 /* Clear out UART and FIFO */
1658 readb(&ch->ch_neo_uart->txrx);
1659 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
1660 &ch->ch_neo_uart->isr_fcr);
1661 readb(&ch->ch_neo_uart->lsr);
1662 readb(&ch->ch_neo_uart->msr);
1664 ch->ch_flags |= CH_FIFO_ENABLED;
1666 /* Assert any signals we want up */
1667 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1668 neo_pci_posting_flush(ch->ch_bd);
1672 * Make the UART completely turn off.
1674 static void neo_uart_off(struct channel_t *ch)
1676 /* Turn off UART enhanced bits */
1677 writeb(0, &ch->ch_neo_uart->efr);
1679 /* Stop all interrupts from occurring. */
1680 writeb(0, &ch->ch_neo_uart->ier);
1681 neo_pci_posting_flush(ch->ch_bd);
1684 static uint neo_get_uart_bytes_left(struct channel_t *ch)
1686 unsigned char left = 0;
1687 unsigned char lsr = readb(&ch->ch_neo_uart->lsr);
1689 /* We must cache the LSR as some of the bits get reset once read... */
1690 ch->ch_cached_lsr |= lsr;
1692 /* Determine whether the Transmitter is empty or not */
1693 if (!(lsr & UART_LSR_TEMT)) {
1694 if (ch->ch_flags & CH_TX_FIFO_EMPTY)
1695 tasklet_schedule(&ch->ch_bd->helper_tasklet);
1698 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1705 /* Channel lock MUST be held by the calling function! */
1706 static void neo_send_break(struct channel_t *ch, int msecs)
1709 * If we receive a time of 0, this means turn off the break.
1712 if (ch->ch_flags & CH_BREAK_SENDING) {
1713 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
1715 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1716 neo_pci_posting_flush(ch->ch_bd);
1717 ch->ch_flags &= ~(CH_BREAK_SENDING);
1718 ch->ch_stop_sending_break = 0;
1724 * Set the time we should stop sending the break.
1725 * If we are already sending a break, toss away the existing
1726 * time to stop, and use this new value instead.
1728 ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs);
1730 /* Tell the UART to start sending the break */
1731 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1732 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
1734 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1735 neo_pci_posting_flush(ch->ch_bd);
1736 ch->ch_flags |= (CH_BREAK_SENDING);
1741 * neo_send_immediate_char.
1743 * Sends a specific character as soon as possible to the UART,
1744 * jumping over any bytes that might be in the write queue.
1746 * The channel lock MUST be held by the calling function.
1748 static void neo_send_immediate_char(struct channel_t *ch, unsigned char c)
1750 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1753 writeb(c, &ch->ch_neo_uart->txrx);
1754 neo_pci_posting_flush(ch->ch_bd);
1757 static unsigned int neo_read_eeprom(unsigned char __iomem *base,
1758 unsigned int address)
1760 unsigned int enable;
1762 unsigned int databit;
1765 /* enable chip select */
1766 writeb(NEO_EECS, base + NEO_EEREG);
1768 enable = address | 0x180;
1770 for (bits = 9; bits--; ) {
1771 databit = (enable & (1 << bits)) ? NEO_EEDI : 0;
1772 /* Set read address */
1773 writeb(databit | NEO_EECS, base + NEO_EEREG);
1774 writeb(databit | NEO_EECS | NEO_EECK, base + NEO_EEREG);
1779 for (bits = 17; bits--; ) {
1780 /* clock to EEPROM */
1781 writeb(NEO_EECS, base + NEO_EEREG);
1782 writeb(NEO_EECS | NEO_EECK, base + NEO_EEREG);
1785 if (readb(base + NEO_EEREG) & NEO_EEDO)
1789 /* clock falling edge */
1790 writeb(NEO_EECS, base + NEO_EEREG);
1792 /* drop chip select */
1793 writeb(0x00, base + NEO_EEREG);
1798 static void neo_vpd(struct dgnc_board *brd)
1803 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
1806 if (!brd->re_map_membase)
1809 /* Store the VPD into our buffer */
1810 for (i = 0; i < NEO_VPD_IMAGESIZE; i++) {
1811 a = neo_read_eeprom(brd->re_map_membase, i);
1812 brd->vpd[i * 2] = a & 0xff;
1813 brd->vpd[(i * 2) + 1] = (a >> 8) & 0xff;
1817 * brd->vpd has different name tags by below index.
1818 * 0x08 : long resource name tag
1819 * 0x10 : long resource name tage (PCI-66 files)
1820 * 0x7F : small resource end tag
1822 if (((brd->vpd[0x08] != 0x82) &&
1823 (brd->vpd[0x10] != 0x82)) ||
1824 (brd->vpd[0x7F] != 0x78)) {
1825 memset(brd->vpd, '\0', NEO_VPD_IMAGESIZE);
1827 /* Search for the serial number */
1828 for (i = 0; i < NEO_VPD_IMAGEBYTES - 3; i++)
1829 if (brd->vpd[i] == 'S' && brd->vpd[i + 1] == 'N')
1830 strncpy(brd->serial_num, &brd->vpd[i + 3], 9);