2 * Copyright 2003 Digi International (www.digi.com)
3 * Scott H Kilau <Scott_Kilau at digi dot com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more details.
20 * struct cls_uart_struct - Per channel/port Classic UART.
22 * key - W = read write
26 * @txrx: (WR) Holding Register.
27 * @ier: (WR) Interrupt Enable Register.
28 * @isr_fcr: (WR) Interrupt Status Register/Fifo Control Register.
29 * @lcr: (WR) Line Control Register.
30 * @mcr: (WR) Modem Control Register.
31 * @lsr: (WR) Line Status Register.
32 * @msr: (WR) Modem Status Register.
33 * @spr: (WR) Scratch Pad Register.
35 struct cls_uart_struct {
46 /* Where to read the interrupt register (8bits) */
47 #define UART_CLASSIC_POLL_ADDR_OFFSET 0x40
49 #define UART_EXAR654_ENHANCED_REGISTER_SET 0xBF
51 #define UART_16654_FCR_TXTRIGGER_16 0x10
52 #define UART_16654_FCR_RXTRIGGER_16 0x40
53 #define UART_16654_FCR_RXTRIGGER_56 0x80
55 /* Received CTS/RTS change of state */
56 #define UART_IIR_CTSRTS 0x20
58 /* Receiver data TIMEOUT */
59 #define UART_IIR_RDI_TIMEOUT 0x0C
62 * These are the EXTENDED definitions for the Exar 654's Interrupt
65 #define UART_EXAR654_EFR_ECB 0x10 /* Enhanced control bit */
66 #define UART_EXAR654_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */
67 #define UART_EXAR654_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */
68 #define UART_EXAR654_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */
69 #define UART_EXAR654_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow Control Enable */
70 #define UART_EXAR654_IER_XOFF 0x20 /* Xoff Interrupt Enable */
71 #define UART_EXAR654_IER_RTSDTR 0x40 /* Output Interrupt Enable */
72 #define UART_EXAR654_IER_CTSDSR 0x80 /* Input Interrupt Enable */
74 extern struct board_ops dgnc_cls_ops;
76 #endif /* _DGNC_CLS_H */