2 comedi/drivers/ni_tiocmd.c
3 Command support for NI general purpose counters
5 Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
20 * Description: National Instruments general purpose counters command support
21 * Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
22 * Herman.Bruyninckx@mech.kuleuven.ac.be,
23 * Wim.Meeussen@mech.kuleuven.ac.be,
24 * Klaas.Gadeyne@mech.kuleuven.ac.be,
25 * Frank Mori Hess <fmhess@users.sourceforge.net>
26 * Updated: Fri, 11 Apr 2008 12:32:35 +0100
29 * This module is not used directly by end-users. Rather, it
30 * is used by other drivers (for example ni_660x and ni_pcimio)
31 * to provide command support for NI's general purpose counters.
32 * It was originally split out of ni_tio.c to stop the 'ni_tio'
33 * module depending on the 'mite' module.
36 * DAQ 660x Register-Level Programmer Manual (NI 370505A-01)
37 * DAQ 6601/6602 User Manual (NI 322137B-01)
38 * 340934b.pdf DAQ-STC reference manual
43 Support use of both banks X and Y
46 #include <linux/module.h>
47 #include "ni_tio_internal.h"
50 static void ni_tio_configure_dma(struct ni_gpct *counter,
51 bool enable, bool read)
53 struct ni_gpct_device *counter_dev = counter->counter_dev;
54 unsigned cidx = counter->counter_index;
58 mask = GI_READ_ACKS_IRQ | GI_WRITE_ACKS_IRQ;
63 bits |= GI_READ_ACKS_IRQ;
65 bits |= GI_WRITE_ACKS_IRQ;
67 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), mask, bits);
69 switch (counter_dev->variant) {
70 case ni_gpct_variant_e_series:
72 case ni_gpct_variant_m_series:
73 case ni_gpct_variant_660x:
74 mask = GI_DMA_ENABLE | GI_DMA_INT_ENA | GI_DMA_WRITE;
78 bits |= GI_DMA_ENABLE | GI_DMA_INT_ENA;
81 ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx), mask, bits);
86 static int ni_tio_input_inttrig(struct comedi_device *dev,
87 struct comedi_subdevice *s,
88 unsigned int trig_num)
90 struct ni_gpct *counter = s->private;
91 struct comedi_cmd *cmd = &s->async->cmd;
95 if (trig_num != cmd->start_arg)
98 spin_lock_irqsave(&counter->lock, flags);
99 if (counter->mite_chan)
100 mite_dma_arm(counter->mite_chan);
103 spin_unlock_irqrestore(&counter->lock, flags);
106 ret = ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE);
107 s->async->inttrig = NULL;
112 static int ni_tio_input_cmd(struct comedi_subdevice *s)
114 struct ni_gpct *counter = s->private;
115 struct ni_gpct_device *counter_dev = counter->counter_dev;
116 unsigned cidx = counter->counter_index;
117 struct comedi_async *async = s->async;
118 struct comedi_cmd *cmd = &async->cmd;
121 /* write alloc the entire buffer */
122 comedi_buf_write_alloc(s, async->prealloc_bufsz);
123 counter->mite_chan->dir = COMEDI_INPUT;
124 switch (counter_dev->variant) {
125 case ni_gpct_variant_m_series:
126 case ni_gpct_variant_660x:
127 mite_prep_dma(counter->mite_chan, 32, 32);
129 case ni_gpct_variant_e_series:
130 mite_prep_dma(counter->mite_chan, 16, 32);
136 ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_SAVE_TRACE, 0);
137 ni_tio_configure_dma(counter, true, true);
139 if (cmd->start_src == TRIG_INT) {
140 async->inttrig = &ni_tio_input_inttrig;
141 } else { /* TRIG_NOW || TRIG_EXT || TRIG_OTHER */
142 async->inttrig = NULL;
143 mite_dma_arm(counter->mite_chan);
145 if (cmd->start_src == TRIG_NOW)
146 ret = ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE);
147 else if (cmd->start_src == TRIG_EXT)
148 ret = ni_tio_arm(counter, 1, cmd->start_arg);
153 static int ni_tio_output_cmd(struct comedi_subdevice *s)
155 struct ni_gpct *counter = s->private;
157 dev_err(counter->counter_dev->dev->class_dev,
158 "output commands not yet implemented.\n");
162 static int ni_tio_cmd_setup(struct comedi_subdevice *s)
164 struct comedi_cmd *cmd = &s->async->cmd;
165 struct ni_gpct *counter = s->private;
166 unsigned cidx = counter->counter_index;
167 int set_gate_source = 0;
168 unsigned gate_source;
171 if (cmd->scan_begin_src == TRIG_EXT) {
173 gate_source = cmd->scan_begin_arg;
174 } else if (cmd->convert_src == TRIG_EXT) {
176 gate_source = cmd->convert_arg;
179 retval = ni_tio_set_gate_src(counter, 0, gate_source);
180 if (cmd->flags & CMDF_WAKE_EOS) {
181 ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx),
182 GI_GATE_INTERRUPT_ENABLE(cidx),
183 GI_GATE_INTERRUPT_ENABLE(cidx));
188 int ni_tio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
190 struct ni_gpct *counter = s->private;
191 struct comedi_async *async = s->async;
192 struct comedi_cmd *cmd = &async->cmd;
196 spin_lock_irqsave(&counter->lock, flags);
197 if (!counter->mite_chan) {
198 dev_err(counter->counter_dev->dev->class_dev,
199 "commands only supported with DMA. ");
200 dev_err(counter->counter_dev->dev->class_dev,
201 "Interrupt-driven commands not yet implemented.\n");
204 retval = ni_tio_cmd_setup(s);
206 if (cmd->flags & CMDF_WRITE)
207 retval = ni_tio_output_cmd(s);
209 retval = ni_tio_input_cmd(s);
212 spin_unlock_irqrestore(&counter->lock, flags);
215 EXPORT_SYMBOL_GPL(ni_tio_cmd);
217 int ni_tio_cmdtest(struct comedi_device *dev,
218 struct comedi_subdevice *s,
219 struct comedi_cmd *cmd)
221 struct ni_gpct *counter = s->private;
223 unsigned int sources;
225 /* Step 1 : check if triggers are trivially valid */
227 sources = TRIG_NOW | TRIG_INT | TRIG_OTHER;
228 if (ni_tio_counting_mode_registers_present(counter->counter_dev))
230 err |= comedi_check_trigger_src(&cmd->start_src, sources);
232 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
233 TRIG_FOLLOW | TRIG_EXT | TRIG_OTHER);
234 err |= comedi_check_trigger_src(&cmd->convert_src,
235 TRIG_NOW | TRIG_EXT | TRIG_OTHER);
236 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
237 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
242 /* Step 2a : make sure trigger sources are unique */
244 err |= comedi_check_trigger_is_unique(cmd->start_src);
245 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
246 err |= comedi_check_trigger_is_unique(cmd->convert_src);
248 /* Step 2b : and mutually compatible */
250 if (cmd->convert_src != TRIG_NOW && cmd->scan_begin_src != TRIG_FOLLOW)
256 /* Step 3: check if arguments are trivially valid */
258 switch (cmd->start_src) {
262 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
265 /* start_arg is the start_trigger passed to ni_tio_arm() */
269 if (cmd->scan_begin_src != TRIG_EXT)
270 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
272 if (cmd->convert_src != TRIG_EXT)
273 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
275 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
277 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
282 /* Step 4: fix up any arguments */
284 /* Step 5: check channel list if it exists */
288 EXPORT_SYMBOL_GPL(ni_tio_cmdtest);
290 int ni_tio_cancel(struct ni_gpct *counter)
292 unsigned cidx = counter->counter_index;
295 ni_tio_arm(counter, 0, 0);
296 spin_lock_irqsave(&counter->lock, flags);
297 if (counter->mite_chan)
298 mite_dma_disarm(counter->mite_chan);
299 spin_unlock_irqrestore(&counter->lock, flags);
300 ni_tio_configure_dma(counter, false, false);
302 ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx),
303 GI_GATE_INTERRUPT_ENABLE(cidx), 0x0);
306 EXPORT_SYMBOL_GPL(ni_tio_cancel);
308 /* During buffered input counter operation for e-series, the gate
309 interrupt is acked automatically by the dma controller, due to the
310 Gi_Read/Write_Acknowledges_IRQ bits in the input select register. */
311 static int should_ack_gate(struct ni_gpct *counter)
316 switch (counter->counter_dev->variant) {
317 case ni_gpct_variant_m_series:
318 /* not sure if 660x really supports gate
319 interrupts (the bits are not listed
320 in register-level manual) */
321 case ni_gpct_variant_660x:
323 case ni_gpct_variant_e_series:
324 spin_lock_irqsave(&counter->lock, flags);
326 if (!counter->mite_chan ||
327 counter->mite_chan->dir != COMEDI_INPUT ||
328 (mite_done(counter->mite_chan))) {
332 spin_unlock_irqrestore(&counter->lock, flags);
338 static void ni_tio_acknowledge_and_confirm(struct ni_gpct *counter,
341 int *perm_stale_data,
344 unsigned cidx = counter->counter_index;
345 const unsigned short gxx_status = read_register(counter,
346 NITIO_SHARED_STATUS_REG(cidx));
347 const unsigned short gi_status = read_register(counter,
348 NITIO_STATUS_REG(cidx));
356 *perm_stale_data = 0;
360 if (gxx_status & GI_GATE_ERROR(cidx)) {
361 ack |= GI_GATE_ERROR_CONFIRM(cidx);
363 /*660x don't support automatic acknowledgment
364 of gate interrupt via dma read/write
365 and report bogus gate errors */
366 if (counter->counter_dev->variant !=
367 ni_gpct_variant_660x)
371 if (gxx_status & GI_TC_ERROR(cidx)) {
372 ack |= GI_TC_ERROR_CONFIRM(cidx);
376 if (gi_status & GI_TC)
377 ack |= GI_TC_INTERRUPT_ACK;
378 if (gi_status & GI_GATE_INTERRUPT) {
379 if (should_ack_gate(counter))
380 ack |= GI_GATE_INTERRUPT_ACK;
383 write_register(counter, ack, NITIO_INT_ACK_REG(cidx));
384 if (ni_tio_get_soft_copy(counter, NITIO_MODE_REG(cidx)) &
385 GI_LOADING_ON_GATE) {
386 if (gxx_status & GI_STALE_DATA(cidx)) {
390 if (read_register(counter, NITIO_STATUS2_REG(cidx)) &
391 GI_PERMANENT_STALE(cidx)) {
392 dev_info(counter->counter_dev->dev->class_dev,
393 "%s: Gi_Permanent_Stale_Data detected.\n",
396 *perm_stale_data = 1;
401 void ni_tio_acknowledge(struct ni_gpct *counter)
403 ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
405 EXPORT_SYMBOL_GPL(ni_tio_acknowledge);
407 void ni_tio_handle_interrupt(struct ni_gpct *counter,
408 struct comedi_subdevice *s)
410 unsigned cidx = counter->counter_index;
411 unsigned gpct_mite_status;
417 ni_tio_acknowledge_and_confirm(counter, &gate_error, &tc_error,
418 &perm_stale_data, NULL);
420 dev_notice(counter->counter_dev->dev->class_dev,
421 "%s: Gi_Gate_Error detected.\n", __func__);
422 s->async->events |= COMEDI_CB_OVERFLOW;
425 s->async->events |= COMEDI_CB_ERROR;
426 switch (counter->counter_dev->variant) {
427 case ni_gpct_variant_m_series:
428 case ni_gpct_variant_660x:
429 if (read_register(counter, NITIO_DMA_STATUS_REG(cidx)) &
431 dev_notice(counter->counter_dev->dev->class_dev,
432 "%s: Gi_DRQ_Error detected.\n", __func__);
433 s->async->events |= COMEDI_CB_OVERFLOW;
436 case ni_gpct_variant_e_series:
439 spin_lock_irqsave(&counter->lock, flags);
440 if (!counter->mite_chan) {
441 spin_unlock_irqrestore(&counter->lock, flags);
444 gpct_mite_status = mite_get_status(counter->mite_chan);
445 if (gpct_mite_status & CHSR_LINKC)
447 counter->mite_chan->mite->mite_io_addr +
448 MITE_CHOR(counter->mite_chan->channel));
449 mite_sync_input_dma(counter->mite_chan, s);
450 spin_unlock_irqrestore(&counter->lock, flags);
452 EXPORT_SYMBOL_GPL(ni_tio_handle_interrupt);
454 void ni_tio_set_mite_channel(struct ni_gpct *counter,
455 struct mite_channel *mite_chan)
459 spin_lock_irqsave(&counter->lock, flags);
460 counter->mite_chan = mite_chan;
461 spin_unlock_irqrestore(&counter->lock, flags);
463 EXPORT_SYMBOL_GPL(ni_tio_set_mite_channel);
465 static int __init ni_tiocmd_init_module(void)
469 module_init(ni_tiocmd_init_module);
471 static void __exit ni_tiocmd_cleanup_module(void)
474 module_exit(ni_tiocmd_cleanup_module);
476 MODULE_AUTHOR("Comedi <comedi@comedi.org>");
477 MODULE_DESCRIPTION("Comedi command support for NI general-purpose counters");
478 MODULE_LICENSE("GPL");