1 // SPDX-License-Identifier: GPL-2.0+
3 * Register descriptions for NI DAQ-STC chip
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
11 * DAQ-STC Technical Reference Manual
14 #ifndef _COMEDI_NI_STC_H
15 #define _COMEDI_NI_STC_H
20 * Registers in the National Instruments DAQ-STC chip
23 #define NISTC_INTA_ACK_REG 2
24 #define NISTC_INTA_ACK_G0_GATE BIT(15)
25 #define NISTC_INTA_ACK_G0_TC BIT(14)
26 #define NISTC_INTA_ACK_AI_ERR BIT(13)
27 #define NISTC_INTA_ACK_AI_STOP BIT(12)
28 #define NISTC_INTA_ACK_AI_START BIT(11)
29 #define NISTC_INTA_ACK_AI_START2 BIT(10)
30 #define NISTC_INTA_ACK_AI_START1 BIT(9)
31 #define NISTC_INTA_ACK_AI_SC_TC BIT(8)
32 #define NISTC_INTA_ACK_AI_SC_TC_ERR BIT(7)
33 #define NISTC_INTA_ACK_G0_TC_ERR BIT(6)
34 #define NISTC_INTA_ACK_G0_GATE_ERR BIT(5)
35 #define NISTC_INTA_ACK_AI_ALL (NISTC_INTA_ACK_AI_ERR | \
36 NISTC_INTA_ACK_AI_STOP | \
37 NISTC_INTA_ACK_AI_START | \
38 NISTC_INTA_ACK_AI_START2 | \
39 NISTC_INTA_ACK_AI_START1 | \
40 NISTC_INTA_ACK_AI_SC_TC | \
41 NISTC_INTA_ACK_AI_SC_TC_ERR)
43 #define NISTC_INTB_ACK_REG 3
44 #define NISTC_INTB_ACK_G1_GATE BIT(15)
45 #define NISTC_INTB_ACK_G1_TC BIT(14)
46 #define NISTC_INTB_ACK_AO_ERR BIT(13)
47 #define NISTC_INTB_ACK_AO_STOP BIT(12)
48 #define NISTC_INTB_ACK_AO_START BIT(11)
49 #define NISTC_INTB_ACK_AO_UPDATE BIT(10)
50 #define NISTC_INTB_ACK_AO_START1 BIT(9)
51 #define NISTC_INTB_ACK_AO_BC_TC BIT(8)
52 #define NISTC_INTB_ACK_AO_UC_TC BIT(7)
53 #define NISTC_INTB_ACK_AO_UI2_TC BIT(6)
54 #define NISTC_INTB_ACK_AO_UI2_TC_ERR BIT(5)
55 #define NISTC_INTB_ACK_AO_BC_TC_ERR BIT(4)
56 #define NISTC_INTB_ACK_AO_BC_TC_TRIG_ERR BIT(3)
57 #define NISTC_INTB_ACK_G1_TC_ERR BIT(2)
58 #define NISTC_INTB_ACK_G1_GATE_ERR BIT(1)
59 #define NISTC_INTB_ACK_AO_ALL (NISTC_INTB_ACK_AO_ERR | \
60 NISTC_INTB_ACK_AO_STOP | \
61 NISTC_INTB_ACK_AO_START | \
62 NISTC_INTB_ACK_AO_UPDATE | \
63 NISTC_INTB_ACK_AO_START1 | \
64 NISTC_INTB_ACK_AO_BC_TC | \
65 NISTC_INTB_ACK_AO_UC_TC | \
66 NISTC_INTB_ACK_AO_BC_TC_ERR | \
67 NISTC_INTB_ACK_AO_BC_TC_TRIG_ERR)
69 #define NISTC_AI_CMD2_REG 4
70 #define NISTC_AI_CMD2_END_ON_SC_TC BIT(15)
71 #define NISTC_AI_CMD2_END_ON_EOS BIT(14)
72 #define NISTC_AI_CMD2_START1_DISABLE BIT(11)
73 #define NISTC_AI_CMD2_SC_SAVE_TRACE BIT(10)
74 #define NISTC_AI_CMD2_SI_SW_ON_SC_TC BIT(9)
75 #define NISTC_AI_CMD2_SI_SW_ON_STOP BIT(8)
76 #define NISTC_AI_CMD2_SI_SW_ON_TC BIT(7)
77 #define NISTC_AI_CMD2_SC_SW_ON_TC BIT(4)
78 #define NISTC_AI_CMD2_STOP_PULSE BIT(3)
79 #define NISTC_AI_CMD2_START_PULSE BIT(2)
80 #define NISTC_AI_CMD2_START2_PULSE BIT(1)
81 #define NISTC_AI_CMD2_START1_PULSE BIT(0)
83 #define NISTC_AO_CMD2_REG 5
84 #define NISTC_AO_CMD2_END_ON_BC_TC(x) (((x) & 0x3) << 14)
85 #define NISTC_AO_CMD2_START_STOP_GATE_ENA BIT(13)
86 #define NISTC_AO_CMD2_UC_SAVE_TRACE BIT(12)
87 #define NISTC_AO_CMD2_BC_GATE_ENA BIT(11)
88 #define NISTC_AO_CMD2_BC_SAVE_TRACE BIT(10)
89 #define NISTC_AO_CMD2_UI_SW_ON_BC_TC BIT(9)
90 #define NISTC_AO_CMD2_UI_SW_ON_STOP BIT(8)
91 #define NISTC_AO_CMD2_UI_SW_ON_TC BIT(7)
92 #define NISTC_AO_CMD2_UC_SW_ON_BC_TC BIT(6)
93 #define NISTC_AO_CMD2_UC_SW_ON_TC BIT(5)
94 #define NISTC_AO_CMD2_BC_SW_ON_TC BIT(4)
95 #define NISTC_AO_CMD2_MUTE_B BIT(3)
96 #define NISTC_AO_CMD2_MUTE_A BIT(2)
97 #define NISTC_AO_CMD2_UPDATE2_PULSE BIT(1)
98 #define NISTC_AO_CMD2_START1_PULSE BIT(0)
100 #define NISTC_G0_CMD_REG 6
101 #define NISTC_G1_CMD_REG 7
103 #define NISTC_AI_CMD1_REG 8
104 #define NISTC_AI_CMD1_ATRIG_RESET BIT(14)
105 #define NISTC_AI_CMD1_DISARM BIT(13)
106 #define NISTC_AI_CMD1_SI2_ARM BIT(12)
107 #define NISTC_AI_CMD1_SI2_LOAD BIT(11)
108 #define NISTC_AI_CMD1_SI_ARM BIT(10)
109 #define NISTC_AI_CMD1_SI_LOAD BIT(9)
110 #define NISTC_AI_CMD1_DIV_ARM BIT(8)
111 #define NISTC_AI_CMD1_DIV_LOAD BIT(7)
112 #define NISTC_AI_CMD1_SC_ARM BIT(6)
113 #define NISTC_AI_CMD1_SC_LOAD BIT(5)
114 #define NISTC_AI_CMD1_SCAN_IN_PROG_PULSE BIT(4)
115 #define NISTC_AI_CMD1_EXTMUX_CLK_PULSE BIT(3)
116 #define NISTC_AI_CMD1_LOCALMUX_CLK_PULSE BIT(2)
117 #define NISTC_AI_CMD1_SC_TC_PULSE BIT(1)
118 #define NISTC_AI_CMD1_CONVERT_PULSE BIT(0)
120 #define NISTC_AO_CMD1_REG 9
121 #define NISTC_AO_CMD1_ATRIG_RESET BIT(15)
122 #define NISTC_AO_CMD1_START_PULSE BIT(14)
123 #define NISTC_AO_CMD1_DISARM BIT(13)
124 #define NISTC_AO_CMD1_UI2_ARM_DISARM BIT(12)
125 #define NISTC_AO_CMD1_UI2_LOAD BIT(11)
126 #define NISTC_AO_CMD1_UI_ARM BIT(10)
127 #define NISTC_AO_CMD1_UI_LOAD BIT(9)
128 #define NISTC_AO_CMD1_UC_ARM BIT(8)
129 #define NISTC_AO_CMD1_UC_LOAD BIT(7)
130 #define NISTC_AO_CMD1_BC_ARM BIT(6)
131 #define NISTC_AO_CMD1_BC_LOAD BIT(5)
132 #define NISTC_AO_CMD1_DAC1_UPDATE_MODE BIT(4)
133 #define NISTC_AO_CMD1_LDAC1_SRC_SEL BIT(3)
134 #define NISTC_AO_CMD1_DAC0_UPDATE_MODE BIT(2)
135 #define NISTC_AO_CMD1_LDAC0_SRC_SEL BIT(1)
136 #define NISTC_AO_CMD1_UPDATE_PULSE BIT(0)
138 #define NISTC_DIO_OUT_REG 10
139 #define NISTC_DIO_OUT_SERIAL(x) (((x) & 0xff) << 8)
140 #define NISTC_DIO_OUT_SERIAL_MASK NISTC_DIO_OUT_SERIAL(0xff)
141 #define NISTC_DIO_OUT_PARALLEL(x) ((x) & 0xff)
142 #define NISTC_DIO_OUT_PARALLEL_MASK NISTC_DIO_OUT_PARALLEL(0xff)
143 #define NISTC_DIO_SDIN BIT(4)
144 #define NISTC_DIO_SDOUT BIT(0)
146 #define NISTC_DIO_CTRL_REG 11
147 #define NISTC_DIO_SDCLK BIT(11)
148 #define NISTC_DIO_CTRL_HW_SER_TIMEBASE BIT(10)
149 #define NISTC_DIO_CTRL_HW_SER_ENA BIT(9)
150 #define NISTC_DIO_CTRL_HW_SER_START BIT(8)
151 #define NISTC_DIO_CTRL_DIR(x) ((x) & 0xff)
152 #define NISTC_DIO_CTRL_DIR_MASK NISTC_DIO_CTRL_DIR(0xff)
154 #define NISTC_AI_MODE1_REG 12
155 #define NISTC_AI_MODE1_CONVERT_SRC(x) (((x) & 0x1f) << 11)
156 #define NISTC_AI_MODE1_SI_SRC(x) (((x) & 0x1f) << 6)
157 #define NISTC_AI_MODE1_CONVERT_POLARITY BIT(5)
158 #define NISTC_AI_MODE1_SI_POLARITY BIT(4)
159 #define NISTC_AI_MODE1_START_STOP BIT(3)
160 #define NISTC_AI_MODE1_RSVD BIT(2)
161 #define NISTC_AI_MODE1_CONTINUOUS BIT(1)
162 #define NISTC_AI_MODE1_TRIGGER_ONCE BIT(0)
164 #define NISTC_AI_MODE2_REG 13
165 #define NISTC_AI_MODE2_SC_GATE_ENA BIT(15)
166 #define NISTC_AI_MODE2_START_STOP_GATE_ENA BIT(14)
167 #define NISTC_AI_MODE2_PRE_TRIGGER BIT(13)
168 #define NISTC_AI_MODE2_EXTMUX_PRESENT BIT(12)
169 #define NISTC_AI_MODE2_SI2_INIT_LOAD_SRC BIT(9)
170 #define NISTC_AI_MODE2_SI2_RELOAD_MODE BIT(8)
171 #define NISTC_AI_MODE2_SI_INIT_LOAD_SRC BIT(7)
172 #define NISTC_AI_MODE2_SI_RELOAD_MODE(x) (((x) & 0x7) << 4)
173 #define NISTC_AI_MODE2_SI_WR_SWITCH BIT(3)
174 #define NISTC_AI_MODE2_SC_INIT_LOAD_SRC BIT(2)
175 #define NISTC_AI_MODE2_SC_RELOAD_MODE BIT(1)
176 #define NISTC_AI_MODE2_SC_WR_SWITCH BIT(0)
178 #define NISTC_AI_SI_LOADA_REG 14
179 #define NISTC_AI_SI_LOADB_REG 16
180 #define NISTC_AI_SC_LOADA_REG 18
181 #define NISTC_AI_SC_LOADB_REG 20
182 #define NISTC_AI_SI2_LOADA_REG 23
183 #define NISTC_AI_SI2_LOADB_REG 25
185 #define NISTC_G0_MODE_REG 26
186 #define NISTC_G1_MODE_REG 27
187 #define NISTC_G0_LOADA_REG 28
188 #define NISTC_G0_LOADB_REG 30
189 #define NISTC_G1_LOADA_REG 32
190 #define NISTC_G1_LOADB_REG 34
191 #define NISTC_G0_INPUT_SEL_REG 36
192 #define NISTC_G1_INPUT_SEL_REG 37
194 #define NISTC_AO_MODE1_REG 38
195 #define NISTC_AO_MODE1_UPDATE_SRC(x) (((x) & 0x1f) << 11)
196 #define NISTC_AO_MODE1_UPDATE_SRC_MASK NISTC_AO_MODE1_UPDATE_SRC(0x1f)
197 #define NISTC_AO_MODE1_UI_SRC(x) (((x) & 0x1f) << 6)
198 #define NISTC_AO_MODE1_UI_SRC_MASK NISTC_AO_MODE1_UI_SRC(0x1f)
199 #define NISTC_AO_MODE1_MULTI_CHAN BIT(5)
200 #define NISTC_AO_MODE1_UPDATE_SRC_POLARITY BIT(4)
201 #define NISTC_AO_MODE1_UI_SRC_POLARITY BIT(3)
202 #define NISTC_AO_MODE1_UC_SW_EVERY_TC BIT(2)
203 #define NISTC_AO_MODE1_CONTINUOUS BIT(1)
204 #define NISTC_AO_MODE1_TRIGGER_ONCE BIT(0)
206 #define NISTC_AO_MODE2_REG 39
207 #define NISTC_AO_MODE2_FIFO_MODE(x) (((x) & 0x3) << 14)
208 #define NISTC_AO_MODE2_FIFO_MODE_MASK NISTC_AO_MODE2_FIFO_MODE(3)
209 #define NISTC_AO_MODE2_FIFO_MODE_E NISTC_AO_MODE2_FIFO_MODE(0)
210 #define NISTC_AO_MODE2_FIFO_MODE_HF NISTC_AO_MODE2_FIFO_MODE(1)
211 #define NISTC_AO_MODE2_FIFO_MODE_F NISTC_AO_MODE2_FIFO_MODE(2)
212 #define NISTC_AO_MODE2_FIFO_MODE_HF_F NISTC_AO_MODE2_FIFO_MODE(3)
213 #define NISTC_AO_MODE2_FIFO_REXMIT_ENA BIT(13)
214 #define NISTC_AO_MODE2_START1_DISABLE BIT(12)
215 #define NISTC_AO_MODE2_UC_INIT_LOAD_SRC BIT(11)
216 #define NISTC_AO_MODE2_UC_WR_SWITCH BIT(10)
217 #define NISTC_AO_MODE2_UI2_INIT_LOAD_SRC BIT(9)
218 #define NISTC_AO_MODE2_UI2_RELOAD_MODE BIT(8)
219 #define NISTC_AO_MODE2_UI_INIT_LOAD_SRC BIT(7)
220 #define NISTC_AO_MODE2_UI_RELOAD_MODE(x) (((x) & 0x7) << 4)
221 #define NISTC_AO_MODE2_UI_WR_SWITCH BIT(3)
222 #define NISTC_AO_MODE2_BC_INIT_LOAD_SRC BIT(2)
223 #define NISTC_AO_MODE2_BC_RELOAD_MODE BIT(1)
224 #define NISTC_AO_MODE2_BC_WR_SWITCH BIT(0)
226 #define NISTC_AO_UI_LOADA_REG 40
227 #define NISTC_AO_UI_LOADB_REG 42
228 #define NISTC_AO_BC_LOADA_REG 44
229 #define NISTC_AO_BC_LOADB_REG 46
230 #define NISTC_AO_UC_LOADA_REG 48
231 #define NISTC_AO_UC_LOADB_REG 50
233 #define NISTC_CLK_FOUT_REG 56
234 #define NISTC_CLK_FOUT_ENA BIT(15)
235 #define NISTC_CLK_FOUT_TIMEBASE_SEL BIT(14)
236 #define NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 BIT(13)
237 #define NISTC_CLK_FOUT_SLOW_DIV2 BIT(12)
238 #define NISTC_CLK_FOUT_SLOW_TIMEBASE BIT(11)
239 #define NISTC_CLK_FOUT_G_SRC_DIV2 BIT(10)
240 #define NISTC_CLK_FOUT_TO_BOARD_DIV2 BIT(9)
241 #define NISTC_CLK_FOUT_TO_BOARD BIT(8)
242 #define NISTC_CLK_FOUT_AI_OUT_DIV2 BIT(7)
243 #define NISTC_CLK_FOUT_AI_SRC_DIV2 BIT(6)
244 #define NISTC_CLK_FOUT_AO_OUT_DIV2 BIT(5)
245 #define NISTC_CLK_FOUT_AO_SRC_DIV2 BIT(4)
246 #define NISTC_CLK_FOUT_DIVIDER(x) (((x) & 0xf) << 0)
247 #define NISTC_CLK_FOUT_TO_DIVIDER(x) (((x) >> 0) & 0xf)
248 #define NISTC_CLK_FOUT_DIVIDER_MASK NISTC_CLK_FOUT_DIVIDER(0xf)
250 #define NISTC_IO_BIDIR_PIN_REG 57
252 #define NISTC_RTSI_TRIG_DIR_REG 58
253 #define NISTC_RTSI_TRIG_OLD_CLK_CHAN 7
254 #define NISTC_RTSI_TRIG_NUM_CHAN(_m) ((_m) ? 8 : 7)
255 #define NISTC_RTSI_TRIG_DIR(_c, _m) ((_m) ? BIT(8 + (_c)) : BIT(7 + (_c)))
256 #define NISTC_RTSI_TRIG_USE_CLK BIT(1)
257 #define NISTC_RTSI_TRIG_DRV_CLK BIT(0)
259 #define NISTC_INT_CTRL_REG 59
260 #define NISTC_INT_CTRL_INTB_ENA BIT(15)
261 #define NISTC_INT_CTRL_INTB_SEL(x) (((x) & 0x7) << 12)
262 #define NISTC_INT_CTRL_INTA_ENA BIT(11)
263 #define NISTC_INT_CTRL_INTA_SEL(x) (((x) & 0x7) << 8)
264 #define NISTC_INT_CTRL_PASSTHRU0_POL BIT(3)
265 #define NISTC_INT_CTRL_PASSTHRU1_POL BIT(2)
266 #define NISTC_INT_CTRL_3PIN_INT BIT(1)
267 #define NISTC_INT_CTRL_INT_POL BIT(0)
269 #define NISTC_AI_OUT_CTRL_REG 60
270 #define NISTC_AI_OUT_CTRL_START_SEL BIT(10)
271 #define NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(x) (((x) & 0x3) << 8)
272 #define NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(x) (((x) & 0x3) << 6)
273 #define NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(x) (((x) & 0x3) << 4)
274 #define NISTC_AI_OUT_CTRL_SC_TC_SEL(x) (((x) & 0x3) << 2)
275 #define NISTC_AI_OUT_CTRL_CONVERT_SEL(x) (((x) & 0x3) << 0)
276 #define NISTC_AI_OUT_CTRL_CONVERT_HIGH_Z NISTC_AI_OUT_CTRL_CONVERT_SEL(0)
277 #define NISTC_AI_OUT_CTRL_CONVERT_GND NISTC_AI_OUT_CTRL_CONVERT_SEL(1)
278 #define NISTC_AI_OUT_CTRL_CONVERT_LOW NISTC_AI_OUT_CTRL_CONVERT_SEL(2)
279 #define NISTC_AI_OUT_CTRL_CONVERT_HIGH NISTC_AI_OUT_CTRL_CONVERT_SEL(3)
281 #define NISTC_ATRIG_ETC_REG 61
282 #define NISTC_ATRIG_ETC_GPFO_1_ENA BIT(15)
283 #define NISTC_ATRIG_ETC_GPFO_0_ENA BIT(14)
284 #define NISTC_ATRIG_ETC_GPFO_0_SEL(x) (((x) & 0x3) << 11)
285 #define NISTC_ATRIG_ETC_GPFO_1_SEL BIT(7)
286 #define NISTC_ATRIG_ETC_DRV BIT(4)
287 #define NISTC_ATRIG_ETC_ENA BIT(3)
288 #define NISTC_ATRIG_ETC_MODE(x) (((x) & 0x7) << 0)
290 #define NISTC_AI_START_STOP_REG 62
291 #define NISTC_AI_START_POLARITY BIT(15)
292 #define NISTC_AI_STOP_POLARITY BIT(14)
293 #define NISTC_AI_STOP_SYNC BIT(13)
294 #define NISTC_AI_STOP_EDGE BIT(12)
295 #define NISTC_AI_STOP_SEL(x) (((x) & 0x1f) << 7)
296 #define NISTC_AI_START_SYNC BIT(6)
297 #define NISTC_AI_START_EDGE BIT(5)
298 #define NISTC_AI_START_SEL(x) (((x) & 0x1f) << 0)
300 #define NISTC_AI_TRIG_SEL_REG 63
301 #define NISTC_AI_TRIG_START1_POLARITY BIT(15)
302 #define NISTC_AI_TRIG_START2_POLARITY BIT(14)
303 #define NISTC_AI_TRIG_START2_SYNC BIT(13)
304 #define NISTC_AI_TRIG_START2_EDGE BIT(12)
305 #define NISTC_AI_TRIG_START2_SEL(x) (((x) & 0x1f) << 7)
306 #define NISTC_AI_TRIG_START1_SYNC BIT(6)
307 #define NISTC_AI_TRIG_START1_EDGE BIT(5)
308 #define NISTC_AI_TRIG_START1_SEL(x) (((x) & 0x1f) << 0)
310 #define NISTC_AI_DIV_LOADA_REG 64
312 #define NISTC_AO_START_SEL_REG 66
313 #define NISTC_AO_START_UI2_SW_GATE BIT(15)
314 #define NISTC_AO_START_UI2_EXT_GATE_POL BIT(14)
315 #define NISTC_AO_START_POLARITY BIT(13)
316 #define NISTC_AO_START_AOFREQ_ENA BIT(12)
317 #define NISTC_AO_START_UI2_EXT_GATE_SEL(x) (((x) & 0x1f) << 7)
318 #define NISTC_AO_START_SYNC BIT(6)
319 #define NISTC_AO_START_EDGE BIT(5)
320 #define NISTC_AO_START_SEL(x) (((x) & 0x1f) << 0)
322 #define NISTC_AO_TRIG_SEL_REG 67
323 #define NISTC_AO_TRIG_UI2_EXT_GATE_ENA BIT(15)
324 #define NISTC_AO_TRIG_DELAYED_START1 BIT(14)
325 #define NISTC_AO_TRIG_START1_POLARITY BIT(13)
326 #define NISTC_AO_TRIG_UI2_SRC_POLARITY BIT(12)
327 #define NISTC_AO_TRIG_UI2_SRC_SEL(x) (((x) & 0x1f) << 7)
328 #define NISTC_AO_TRIG_START1_SYNC BIT(6)
329 #define NISTC_AO_TRIG_START1_EDGE BIT(5)
330 #define NISTC_AO_TRIG_START1_SEL(x) (((x) & 0x1f) << 0)
331 #define NISTC_AO_TRIG_START1_SEL_MASK NISTC_AO_TRIG_START1_SEL(0x1f)
333 #define NISTC_G0_AUTOINC_REG 68
334 #define NISTC_G1_AUTOINC_REG 69
336 #define NISTC_AO_MODE3_REG 70
337 #define NISTC_AO_MODE3_UI2_SW_NEXT_TC BIT(13)
338 #define NISTC_AO_MODE3_UC_SW_EVERY_BC_TC BIT(12)
339 #define NISTC_AO_MODE3_TRIG_LEN BIT(11)
340 #define NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR BIT(5)
341 #define NISTC_AO_MODE3_STOP_ON_BC_TC_TRIG_ERR BIT(4)
342 #define NISTC_AO_MODE3_STOP_ON_BC_TC_ERR BIT(3)
343 #define NISTC_AO_MODE3_NOT_AN_UPDATE BIT(2)
344 #define NISTC_AO_MODE3_SW_GATE BIT(1)
345 #define NISTC_AO_MODE3_LAST_GATE_DISABLE BIT(0) /* M-Series only */
347 #define NISTC_RESET_REG 72
348 #define NISTC_RESET_SOFTWARE BIT(11)
349 #define NISTC_RESET_AO_CFG_END BIT(9)
350 #define NISTC_RESET_AI_CFG_END BIT(8)
351 #define NISTC_RESET_AO_CFG_START BIT(5)
352 #define NISTC_RESET_AI_CFG_START BIT(4)
353 #define NISTC_RESET_G1 BIT(3)
354 #define NISTC_RESET_G0 BIT(2)
355 #define NISTC_RESET_AO BIT(1)
356 #define NISTC_RESET_AI BIT(0)
358 #define NISTC_INTA_ENA_REG 73
359 #define NISTC_INTA2_ENA_REG 74
360 #define NISTC_INTA_ENA_PASSTHRU0 BIT(9)
361 #define NISTC_INTA_ENA_G0_GATE BIT(8)
362 #define NISTC_INTA_ENA_AI_FIFO BIT(7)
363 #define NISTC_INTA_ENA_G0_TC BIT(6)
364 #define NISTC_INTA_ENA_AI_ERR BIT(5)
365 #define NISTC_INTA_ENA_AI_STOP BIT(4)
366 #define NISTC_INTA_ENA_AI_START BIT(3)
367 #define NISTC_INTA_ENA_AI_START2 BIT(2)
368 #define NISTC_INTA_ENA_AI_START1 BIT(1)
369 #define NISTC_INTA_ENA_AI_SC_TC BIT(0)
370 #define NISTC_INTA_ENA_AI_MASK (NISTC_INTA_ENA_AI_FIFO | \
371 NISTC_INTA_ENA_AI_ERR | \
372 NISTC_INTA_ENA_AI_STOP | \
373 NISTC_INTA_ENA_AI_START | \
374 NISTC_INTA_ENA_AI_START2 | \
375 NISTC_INTA_ENA_AI_START1 | \
376 NISTC_INTA_ENA_AI_SC_TC)
378 #define NISTC_INTB_ENA_REG 75
379 #define NISTC_INTB2_ENA_REG 76
380 #define NISTC_INTB_ENA_PASSTHRU1 BIT(11)
381 #define NISTC_INTB_ENA_G1_GATE BIT(10)
382 #define NISTC_INTB_ENA_G1_TC BIT(9)
383 #define NISTC_INTB_ENA_AO_FIFO BIT(8)
384 #define NISTC_INTB_ENA_AO_UI2_TC BIT(7)
385 #define NISTC_INTB_ENA_AO_UC_TC BIT(6)
386 #define NISTC_INTB_ENA_AO_ERR BIT(5)
387 #define NISTC_INTB_ENA_AO_STOP BIT(4)
388 #define NISTC_INTB_ENA_AO_START BIT(3)
389 #define NISTC_INTB_ENA_AO_UPDATE BIT(2)
390 #define NISTC_INTB_ENA_AO_START1 BIT(1)
391 #define NISTC_INTB_ENA_AO_BC_TC BIT(0)
393 #define NISTC_AI_PERSONAL_REG 77
394 #define NISTC_AI_PERSONAL_SHIFTIN_PW BIT(15)
395 #define NISTC_AI_PERSONAL_EOC_POLARITY BIT(14)
396 #define NISTC_AI_PERSONAL_SOC_POLARITY BIT(13)
397 #define NISTC_AI_PERSONAL_SHIFTIN_POL BIT(12)
398 #define NISTC_AI_PERSONAL_CONVERT_TIMEBASE BIT(11)
399 #define NISTC_AI_PERSONAL_CONVERT_PW BIT(10)
400 #define NISTC_AI_PERSONAL_CONVERT_ORIG_PULSE BIT(9)
401 #define NISTC_AI_PERSONAL_FIFO_FLAGS_POL BIT(8)
402 #define NISTC_AI_PERSONAL_OVERRUN_MODE BIT(7)
403 #define NISTC_AI_PERSONAL_EXTMUX_CLK_PW BIT(6)
404 #define NISTC_AI_PERSONAL_LOCALMUX_CLK_PW BIT(5)
405 #define NISTC_AI_PERSONAL_AIFREQ_POL BIT(4)
407 #define NISTC_AO_PERSONAL_REG 78
408 #define NISTC_AO_PERSONAL_MULTI_DACS BIT(15) /* M-Series only */
409 #define NISTC_AO_PERSONAL_NUM_DAC BIT(14) /* 1:single; 0:dual */
410 #define NISTC_AO_PERSONAL_FAST_CPU BIT(13) /* M-Series reserved */
411 #define NISTC_AO_PERSONAL_TMRDACWR_PW BIT(12)
412 #define NISTC_AO_PERSONAL_FIFO_FLAGS_POL BIT(11) /* M-Series reserved */
413 #define NISTC_AO_PERSONAL_FIFO_ENA BIT(10)
414 #define NISTC_AO_PERSONAL_AOFREQ_POL BIT(9) /* M-Series reserved */
415 #define NISTC_AO_PERSONAL_DMA_PIO_CTRL BIT(8) /* M-Series reserved */
416 #define NISTC_AO_PERSONAL_UPDATE_ORIG_PULSE BIT(7)
417 #define NISTC_AO_PERSONAL_UPDATE_TIMEBASE BIT(6)
418 #define NISTC_AO_PERSONAL_UPDATE_PW BIT(5)
419 #define NISTC_AO_PERSONAL_BC_SRC_SEL BIT(4)
420 #define NISTC_AO_PERSONAL_INTERVAL_BUFFER_MODE BIT(3)
422 #define NISTC_RTSI_TRIGA_OUT_REG 79
423 #define NISTC_RTSI_TRIGB_OUT_REG 80
424 #define NISTC_RTSI_TRIGB_SUB_SEL1 BIT(15) /* not for M-Series */
425 #define NISTC_RTSI_TRIG(_c, _s) (((_s) & 0xf) << (((_c) % 4) * 4))
426 #define NISTC_RTSI_TRIG_MASK(_c) NISTC_RTSI_TRIG((_c), 0xf)
427 #define NISTC_RTSI_TRIG_TO_SRC(_c, _b) (((_b) >> (((_c) % 4) * 4)) & 0xf)
429 #define NISTC_RTSI_BOARD_REG 81
431 #define NISTC_CFG_MEM_CLR_REG 82
432 #define NISTC_ADC_FIFO_CLR_REG 83
433 #define NISTC_DAC_FIFO_CLR_REG 84
434 #define NISTC_WR_STROBE3_REG 85
436 #define NISTC_AO_OUT_CTRL_REG 86
437 #define NISTC_AO_OUT_CTRL_EXT_GATE_ENA BIT(15)
438 #define NISTC_AO_OUT_CTRL_EXT_GATE_SEL(x) (((x) & 0x1f) << 10)
439 #define NISTC_AO_OUT_CTRL_CHANS(x) (((x) & 0xf) << 6)
440 #define NISTC_AO_OUT_CTRL_UPDATE2_SEL(x) (((x) & 0x3) << 4)
441 #define NISTC_AO_OUT_CTRL_EXT_GATE_POL BIT(3)
442 #define NISTC_AO_OUT_CTRL_UPDATE2_TOGGLE BIT(2)
443 #define NISTC_AO_OUT_CTRL_UPDATE_SEL(x) (((x) & 0x3) << 0)
444 #define NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ NISTC_AO_OUT_CTRL_UPDATE_SEL(0)
445 #define NISTC_AO_OUT_CTRL_UPDATE_SEL_GND NISTC_AO_OUT_CTRL_UPDATE_SEL(1)
446 #define NISTC_AO_OUT_CTRL_UPDATE_SEL_LOW NISTC_AO_OUT_CTRL_UPDATE_SEL(2)
447 #define NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGH NISTC_AO_OUT_CTRL_UPDATE_SEL(3)
449 #define NISTC_AI_MODE3_REG 87
450 #define NISTC_AI_MODE3_TRIG_LEN BIT(15)
451 #define NISTC_AI_MODE3_DELAY_START BIT(14)
452 #define NISTC_AI_MODE3_SOFTWARE_GATE BIT(13)
453 #define NISTC_AI_MODE3_SI_TRIG_DELAY BIT(12)
454 #define NISTC_AI_MODE3_SI2_SRC_SEL BIT(11)
455 #define NISTC_AI_MODE3_DELAYED_START2 BIT(10)
456 #define NISTC_AI_MODE3_DELAYED_START1 BIT(9)
457 #define NISTC_AI_MODE3_EXT_GATE_MODE BIT(8)
458 #define NISTC_AI_MODE3_FIFO_MODE(x) (((x) & 0x3) << 6)
459 #define NISTC_AI_MODE3_FIFO_MODE_NE NISTC_AI_MODE3_FIFO_MODE(0)
460 #define NISTC_AI_MODE3_FIFO_MODE_HF NISTC_AI_MODE3_FIFO_MODE(1)
461 #define NISTC_AI_MODE3_FIFO_MODE_F NISTC_AI_MODE3_FIFO_MODE(2)
462 #define NISTC_AI_MODE3_FIFO_MODE_HF_E NISTC_AI_MODE3_FIFO_MODE(3)
463 #define NISTC_AI_MODE3_EXT_GATE_POL BIT(5)
464 #define NISTC_AI_MODE3_EXT_GATE_SEL(x) (((x) & 0x1f) << 0)
466 #define NISTC_AI_STATUS1_REG 2
467 #define NISTC_AI_STATUS1_INTA BIT(15)
468 #define NISTC_AI_STATUS1_FIFO_F BIT(14)
469 #define NISTC_AI_STATUS1_FIFO_HF BIT(13)
470 #define NISTC_AI_STATUS1_FIFO_E BIT(12)
471 #define NISTC_AI_STATUS1_OVERRUN BIT(11)
472 #define NISTC_AI_STATUS1_OVERFLOW BIT(10)
473 #define NISTC_AI_STATUS1_SC_TC_ERR BIT(9)
474 #define NISTC_AI_STATUS1_OVER (NISTC_AI_STATUS1_OVERRUN | \
475 NISTC_AI_STATUS1_OVERFLOW)
476 #define NISTC_AI_STATUS1_ERR (NISTC_AI_STATUS1_OVER | \
477 NISTC_AI_STATUS1_SC_TC_ERR)
478 #define NISTC_AI_STATUS1_START2 BIT(8)
479 #define NISTC_AI_STATUS1_START1 BIT(7)
480 #define NISTC_AI_STATUS1_SC_TC BIT(6)
481 #define NISTC_AI_STATUS1_START BIT(5)
482 #define NISTC_AI_STATUS1_STOP BIT(4)
483 #define NISTC_AI_STATUS1_G0_TC BIT(3)
484 #define NISTC_AI_STATUS1_G0_GATE BIT(2)
485 #define NISTC_AI_STATUS1_FIFO_REQ BIT(1)
486 #define NISTC_AI_STATUS1_PASSTHRU0 BIT(0)
488 #define NISTC_AO_STATUS1_REG 3
489 #define NISTC_AO_STATUS1_INTB BIT(15)
490 #define NISTC_AO_STATUS1_FIFO_F BIT(14)
491 #define NISTC_AO_STATUS1_FIFO_HF BIT(13)
492 #define NISTC_AO_STATUS1_FIFO_E BIT(12)
493 #define NISTC_AO_STATUS1_BC_TC_ERR BIT(11)
494 #define NISTC_AO_STATUS1_START BIT(10)
495 #define NISTC_AO_STATUS1_OVERRUN BIT(9)
496 #define NISTC_AO_STATUS1_START1 BIT(8)
497 #define NISTC_AO_STATUS1_BC_TC BIT(7)
498 #define NISTC_AO_STATUS1_UC_TC BIT(6)
499 #define NISTC_AO_STATUS1_UPDATE BIT(5)
500 #define NISTC_AO_STATUS1_UI2_TC BIT(4)
501 #define NISTC_AO_STATUS1_G1_TC BIT(3)
502 #define NISTC_AO_STATUS1_G1_GATE BIT(2)
503 #define NISTC_AO_STATUS1_FIFO_REQ BIT(1)
504 #define NISTC_AO_STATUS1_PASSTHRU1 BIT(0)
506 #define NISTC_G01_STATUS_REG 4
508 #define NISTC_AI_STATUS2_REG 5
510 #define NISTC_AO_STATUS2_REG 6
512 #define NISTC_DIO_IN_REG 7
514 #define NISTC_G0_HW_SAVE_REG 8
515 #define NISTC_G1_HW_SAVE_REG 10
517 #define NISTC_G0_SAVE_REG 12
518 #define NISTC_G1_SAVE_REG 14
520 #define NISTC_AO_UI_SAVE_REG 16
521 #define NISTC_AO_BC_SAVE_REG 18
522 #define NISTC_AO_UC_SAVE_REG 20
524 #define NISTC_STATUS1_REG 27
525 #define NISTC_STATUS1_SERIO_IN_PROG BIT(12)
527 #define NISTC_DIO_SERIAL_IN_REG 28
529 #define NISTC_STATUS2_REG 29
530 #define NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS BIT(5)
532 #define NISTC_AI_SI_SAVE_REG 64
533 #define NISTC_AI_SC_SAVE_REG 66
536 * PCI E Series Registers
538 #define NI_E_STC_WINDOW_ADDR_REG 0x00 /* rw16 */
539 #define NI_E_STC_WINDOW_DATA_REG 0x02 /* rw16 */
541 #define NI_E_STATUS_REG 0x01 /* r8 */
542 #define NI_E_STATUS_AI_FIFO_LOWER_NE BIT(3)
543 #define NI_E_STATUS_PROMOUT BIT(0)
545 #define NI_E_DMA_AI_AO_SEL_REG 0x09 /* w8 */
546 #define NI_E_DMA_AI_SEL(x) (((x) & 0xf) << 0)
547 #define NI_E_DMA_AI_SEL_MASK NI_E_DMA_AI_SEL(0xf)
548 #define NI_E_DMA_AO_SEL(x) (((x) & 0xf) << 4)
549 #define NI_E_DMA_AO_SEL_MASK NI_E_DMA_AO_SEL(0xf)
551 #define NI_E_DMA_G0_G1_SEL_REG 0x0b /* w8 */
552 #define NI_E_DMA_G0_G1_SEL(_g, _c) (((_c) & 0xf) << ((_g) * 4))
553 #define NI_E_DMA_G0_G1_SEL_MASK(_g) NI_E_DMA_G0_G1_SEL((_g), 0xf)
555 #define NI_E_SERIAL_CMD_REG 0x0d /* w8 */
556 #define NI_E_SERIAL_CMD_DAC_LD(x) BIT(3 + (x))
557 #define NI_E_SERIAL_CMD_EEPROM_CS BIT(2)
558 #define NI_E_SERIAL_CMD_SDATA BIT(1)
559 #define NI_E_SERIAL_CMD_SCLK BIT(0)
561 #define NI_E_MISC_CMD_REG 0x0f /* w8 */
562 #define NI_E_MISC_CMD_INTEXT_ATRIG(x) (((x) & 0x1) << 7)
563 #define NI_E_MISC_CMD_EXT_ATRIG NI_E_MISC_CMD_INTEXT_ATRIG(0)
564 #define NI_E_MISC_CMD_INT_ATRIG NI_E_MISC_CMD_INTEXT_ATRIG(1)
566 #define NI_E_AI_CFG_LO_REG 0x10 /* w16 */
567 #define NI_E_AI_CFG_LO_LAST_CHAN BIT(15)
568 #define NI_E_AI_CFG_LO_GEN_TRIG BIT(12)
569 #define NI_E_AI_CFG_LO_DITHER BIT(9)
570 #define NI_E_AI_CFG_LO_UNI BIT(8)
571 #define NI_E_AI_CFG_LO_GAIN(x) ((x) << 0)
573 #define NI_E_AI_CFG_HI_REG 0x12 /* w16 */
574 #define NI_E_AI_CFG_HI_TYPE(x) (((x) & 0x7) << 12)
575 #define NI_E_AI_CFG_HI_TYPE_DIFF NI_E_AI_CFG_HI_TYPE(1)
576 #define NI_E_AI_CFG_HI_TYPE_COMMON NI_E_AI_CFG_HI_TYPE(2)
577 #define NI_E_AI_CFG_HI_TYPE_GROUND NI_E_AI_CFG_HI_TYPE(3)
578 #define NI_E_AI_CFG_HI_AC_COUPLE BIT(11)
579 #define NI_E_AI_CFG_HI_CHAN(x) (((x) & 0x3f) << 0)
581 #define NI_E_AO_CFG_REG 0x16 /* w16 */
582 #define NI_E_AO_DACSEL(x) ((x) << 8)
583 #define NI_E_AO_GROUND_REF BIT(3)
584 #define NI_E_AO_EXT_REF BIT(2)
585 #define NI_E_AO_DEGLITCH BIT(1)
586 #define NI_E_AO_CFG_BIP BIT(0)
588 #define NI_E_DAC_DIRECT_DATA_REG(x) (0x18 + ((x) * 2)) /* w16 */
590 #define NI_E_8255_BASE 0x19 /* rw8 */
592 #define NI_E_AI_FIFO_DATA_REG 0x1c /* r16 */
594 #define NI_E_AO_FIFO_DATA_REG 0x1e /* w16 */
597 * 611x registers (these boards differ from the e-series)
599 #define NI611X_MAGIC_REG 0x19 /* w8 (new) */
600 #define NI611X_CALIB_CHAN_SEL_REG 0x1a /* w16 (new) */
601 #define NI611X_AI_FIFO_DATA_REG 0x1c /* r32 (incompatible) */
602 #define NI611X_AI_FIFO_OFFSET_LOAD_REG 0x05 /* r8 (new) */
603 #define NI611X_AO_FIFO_DATA_REG 0x14 /* w32 (incompatible) */
604 #define NI611X_CAL_GAIN_SEL_REG 0x05 /* w8 (new) */
606 #define NI611X_AO_WINDOW_ADDR_REG 0x18
607 #define NI611X_AO_WINDOW_DATA_REG 0x1e
612 #define NI6143_MAGIC_REG 0x19 /* w8 */
613 #define NI6143_DMA_G0_G1_SEL_REG 0x0b /* w8 */
614 #define NI6143_PIPELINE_DELAY_REG 0x1f /* w8 */
615 #define NI6143_EOC_SET_REG 0x1d /* w8 */
616 #define NI6143_DMA_AI_SEL_REG 0x09 /* w8 */
617 #define NI6143_AI_FIFO_DATA_REG 0x8c /* r32 */
618 #define NI6143_AI_FIFO_FLAG_REG 0x84 /* w32 */
619 #define NI6143_AI_FIFO_CTRL_REG 0x88 /* w32 */
620 #define NI6143_AI_FIFO_STATUS_REG 0x88 /* r32 */
621 #define NI6143_AI_FIFO_DMA_THRESH_REG 0x90 /* w32 */
622 #define NI6143_AI_FIFO_WORDS_AVAIL_REG 0x94 /* w32 */
624 #define NI6143_CALIB_CHAN_REG 0x42 /* w16 */
625 #define NI6143_CALIB_CHAN_RELAY_ON BIT(15)
626 #define NI6143_CALIB_CHAN_RELAY_OFF BIT(14)
627 #define NI6143_CALIB_CHAN(x) (((x) & 0xf) << 0)
628 #define NI6143_CALIB_CHAN_GND_GND NI6143_CALIB_CHAN(0) /* Offset Cal */
629 #define NI6143_CALIB_CHAN_2V5_GND NI6143_CALIB_CHAN(2) /* 2.5V ref */
630 #define NI6143_CALIB_CHAN_PWM_GND NI6143_CALIB_CHAN(5) /* +-5V Self Cal */
631 #define NI6143_CALIB_CHAN_2V5_PWM NI6143_CALIB_CHAN(10) /* PWM Cal */
632 #define NI6143_CALIB_CHAN_PWM_PWM NI6143_CALIB_CHAN(13) /* CMRR */
633 #define NI6143_CALIB_CHAN_GND_PWM NI6143_CALIB_CHAN(14) /* PWM Cal */
634 #define NI6143_CALIB_LO_TIME_REG 0x20 /* w16 */
635 #define NI6143_CALIB_HI_TIME_REG 0x22 /* w16 */
636 #define NI6143_RELAY_COUNTER_LOAD_REG 0x4c /* w32 */
637 #define NI6143_SIGNATURE_REG 0x50 /* w32 */
638 #define NI6143_RELEASE_DATE_REG 0x54 /* w32 */
639 #define NI6143_RELEASE_OLDEST_DATE_REG 0x58 /* w32 */
642 * 671x, 611x windowed ao registers
644 #define NI671X_DAC_DIRECT_DATA_REG(x) (0x00 + (x)) /* w16 */
645 #define NI611X_AO_TIMED_REG 0x10 /* w16 */
646 #define NI671X_AO_IMMEDIATE_REG 0x11 /* w16 */
647 #define NI611X_AO_FIFO_OFFSET_LOAD_REG 0x13 /* w32 */
648 #define NI67XX_AO_SP_UPDATES_REG 0x14 /* w16 */
649 #define NI611X_AO_WAVEFORM_GEN_REG 0x15 /* w16 */
650 #define NI611X_AO_MISC_REG 0x16 /* w16 */
651 #define NI611X_AO_MISC_CLEAR_WG BIT(0)
652 #define NI67XX_AO_CAL_CHAN_SEL_REG 0x17 /* w16 */
653 #define NI67XX_AO_CFG2_REG 0x18 /* w16 */
654 #define NI67XX_CAL_CMD_REG 0x19 /* w16 */
655 #define NI67XX_CAL_STATUS_REG 0x1a /* r8 */
656 #define NI67XX_CAL_STATUS_BUSY BIT(0)
657 #define NI67XX_CAL_STATUS_OSC_DETECT BIT(1)
658 #define NI67XX_CAL_STATUS_OVERRANGE BIT(2)
659 #define NI67XX_CAL_DATA_REG 0x1b /* r16 */
660 #define NI67XX_CAL_CFG_HI_REG 0x1c /* rw16 */
661 #define NI67XX_CAL_CFG_LO_REG 0x1d /* rw16 */
663 #define CS5529_CMD_CB BIT(7)
664 #define CS5529_CMD_SINGLE_CONV BIT(6)
665 #define CS5529_CMD_CONT_CONV BIT(5)
666 #define CS5529_CMD_READ BIT(4)
667 #define CS5529_CMD_REG(x) (((x) & 0x7) << 1)
668 #define CS5529_CMD_REG_MASK CS5529_CMD_REG(7)
669 #define CS5529_CMD_PWR_SAVE BIT(0)
671 #define CS5529_OFFSET_REG CS5529_CMD_REG(0)
672 #define CS5529_GAIN_REG CS5529_CMD_REG(1)
673 #define CS5529_CONV_DATA_REG CS5529_CMD_REG(3)
674 #define CS5529_SETUP_REG CS5529_CMD_REG(4)
676 #define CS5529_CFG_REG CS5529_CMD_REG(2)
677 #define CS5529_CFG_AOUT(x) BIT(22 + (x))
678 #define CS5529_CFG_DOUT(x) BIT(18 + (x))
679 #define CS5529_CFG_LOW_PWR_MODE BIT(16)
680 #define CS5529_CFG_WORD_RATE(x) (((x) & 0x7) << 13)
681 #define CS5529_CFG_WORD_RATE_MASK CS5529_CFG_WORD_RATE(0x7)
682 #define CS5529_CFG_WORD_RATE_2180 CS5529_CFG_WORD_RATE(0)
683 #define CS5529_CFG_WORD_RATE_1092 CS5529_CFG_WORD_RATE(1)
684 #define CS5529_CFG_WORD_RATE_532 CS5529_CFG_WORD_RATE(2)
685 #define CS5529_CFG_WORD_RATE_388 CS5529_CFG_WORD_RATE(3)
686 #define CS5529_CFG_WORD_RATE_324 CS5529_CFG_WORD_RATE(4)
687 #define CS5529_CFG_WORD_RATE_17444 CS5529_CFG_WORD_RATE(5)
688 #define CS5529_CFG_WORD_RATE_8724 CS5529_CFG_WORD_RATE(6)
689 #define CS5529_CFG_WORD_RATE_4364 CS5529_CFG_WORD_RATE(7)
690 #define CS5529_CFG_UNIPOLAR BIT(12)
691 #define CS5529_CFG_RESET BIT(7)
692 #define CS5529_CFG_RESET_VALID BIT(6)
693 #define CS5529_CFG_PORT_FLAG BIT(5)
694 #define CS5529_CFG_PWR_SAVE_SEL BIT(4)
695 #define CS5529_CFG_DONE_FLAG BIT(3)
696 #define CS5529_CFG_CALIB(x) (((x) & 0x7) << 0)
697 #define CS5529_CFG_CALIB_NONE CS5529_CFG_CALIB(0)
698 #define CS5529_CFG_CALIB_OFFSET_SELF CS5529_CFG_CALIB(1)
699 #define CS5529_CFG_CALIB_GAIN_SELF CS5529_CFG_CALIB(2)
700 #define CS5529_CFG_CALIB_BOTH_SELF CS5529_CFG_CALIB(3)
701 #define CS5529_CFG_CALIB_OFFSET_SYS CS5529_CFG_CALIB(5)
702 #define CS5529_CFG_CALIB_GAIN_SYS CS5529_CFG_CALIB(6)
705 * M-Series specific registers not handled by the DAQ-STC and GPCT register
708 #define NI_M_CDIO_DMA_SEL_REG 0x007
709 #define NI_M_CDIO_DMA_SEL_CDO(x) (((x) & 0xf) << 4)
710 #define NI_M_CDIO_DMA_SEL_CDO_MASK NI_M_CDIO_DMA_SEL_CDO(0xf)
711 #define NI_M_CDIO_DMA_SEL_CDI(x) (((x) & 0xf) << 0)
712 #define NI_M_CDIO_DMA_SEL_CDI_MASK NI_M_CDIO_DMA_SEL_CDI(0xf)
713 #define NI_M_SCXI_STATUS_REG 0x007
714 #define NI_M_AI_AO_SEL_REG 0x009
715 #define NI_M_G0_G1_SEL_REG 0x00b
716 #define NI_M_MISC_CMD_REG 0x00f
717 #define NI_M_SCXI_SER_DO_REG 0x011
718 #define NI_M_SCXI_CTRL_REG 0x013
719 #define NI_M_SCXI_OUT_ENA_REG 0x015
720 #define NI_M_AI_FIFO_DATA_REG 0x01c
721 #define NI_M_DIO_REG 0x024
722 #define NI_M_DIO_DIR_REG 0x028
723 #define NI_M_CAL_PWM_REG 0x040
724 #define NI_M_CAL_PWM_HIGH_TIME(x) (((x) & 0xffff) << 16)
725 #define NI_M_CAL_PWM_LOW_TIME(x) (((x) & 0xffff) << 0)
726 #define NI_M_GEN_PWM_REG(x) (0x044 + ((x) * 2))
727 #define NI_M_AI_CFG_FIFO_DATA_REG 0x05e
728 #define NI_M_AI_CFG_LAST_CHAN BIT(14)
729 #define NI_M_AI_CFG_DITHER BIT(13)
730 #define NI_M_AI_CFG_POLARITY BIT(12)
731 #define NI_M_AI_CFG_GAIN(x) (((x) & 0x7) << 9)
732 #define NI_M_AI_CFG_CHAN_TYPE(x) (((x) & 0x7) << 6)
733 #define NI_M_AI_CFG_CHAN_TYPE_MASK NI_M_AI_CFG_CHAN_TYPE(7)
734 #define NI_M_AI_CFG_CHAN_TYPE_CALIB NI_M_AI_CFG_CHAN_TYPE(0)
735 #define NI_M_AI_CFG_CHAN_TYPE_DIFF NI_M_AI_CFG_CHAN_TYPE(1)
736 #define NI_M_AI_CFG_CHAN_TYPE_COMMON NI_M_AI_CFG_CHAN_TYPE(2)
737 #define NI_M_AI_CFG_CHAN_TYPE_GROUND NI_M_AI_CFG_CHAN_TYPE(3)
738 #define NI_M_AI_CFG_CHAN_TYPE_AUX NI_M_AI_CFG_CHAN_TYPE(5)
739 #define NI_M_AI_CFG_CHAN_TYPE_GHOST NI_M_AI_CFG_CHAN_TYPE(7)
740 #define NI_M_AI_CFG_BANK_SEL(x) ((((x) & 0x40) << 4) | ((x) & 0x30))
741 #define NI_M_AI_CFG_CHAN_SEL(x) (((x) & 0xf) << 0)
742 #define NI_M_INTC_ENA_REG 0x088
743 #define NI_M_INTC_ENA BIT(0)
744 #define NI_M_INTC_STATUS_REG 0x088
745 #define NI_M_INTC_STATUS BIT(0)
746 #define NI_M_ATRIG_CTRL_REG 0x08c
747 #define NI_M_AO_SER_INT_ENA_REG 0x0a0
748 #define NI_M_AO_SER_INT_ACK_REG 0x0a1
749 #define NI_M_AO_SER_INT_STATUS_REG 0x0a1
750 #define NI_M_AO_CALIB_REG 0x0a3
751 #define NI_M_AO_FIFO_DATA_REG 0x0a4
752 #define NI_M_PFI_FILTER_REG 0x0b0
753 #define NI_M_PFI_FILTER_SEL(_c, _f) (((_f) & 0x3) << ((_c) * 2))
754 #define NI_M_PFI_FILTER_SEL_MASK(_c) NI_M_PFI_FILTER_SEL((_c), 0x3)
755 #define NI_M_RTSI_FILTER_REG 0x0b4
756 #define NI_M_SCXI_LEGACY_COMPAT_REG 0x0bc
757 #define NI_M_DAC_DIRECT_DATA_REG(x) (0x0c0 + ((x) * 4))
758 #define NI_M_AO_WAVEFORM_ORDER_REG(x) (0x0c2 + ((x) * 4))
759 #define NI_M_AO_CFG_BANK_REG(x) (0x0c3 + ((x) * 4))
760 #define NI_M_AO_CFG_BANK_BIPOLAR BIT(7)
761 #define NI_M_AO_CFG_BANK_UPDATE_TIMED BIT(6)
762 #define NI_M_AO_CFG_BANK_REF(x) (((x) & 0x7) << 3)
763 #define NI_M_AO_CFG_BANK_REF_MASK NI_M_AO_CFG_BANK_REF(7)
764 #define NI_M_AO_CFG_BANK_REF_INT_10V NI_M_AO_CFG_BANK_REF(0)
765 #define NI_M_AO_CFG_BANK_REF_INT_5V NI_M_AO_CFG_BANK_REF(1)
766 #define NI_M_AO_CFG_BANK_OFFSET(x) (((x) & 0x7) << 0)
767 #define NI_M_AO_CFG_BANK_OFFSET_MASK NI_M_AO_CFG_BANK_OFFSET(7)
768 #define NI_M_AO_CFG_BANK_OFFSET_0V NI_M_AO_CFG_BANK_OFFSET(0)
769 #define NI_M_AO_CFG_BANK_OFFSET_5V NI_M_AO_CFG_BANK_OFFSET(1)
770 #define NI_M_RTSI_SHARED_MUX_REG 0x1a2
771 #define NI_M_CLK_FOUT2_REG 0x1c4
772 #define NI_M_CLK_FOUT2_RTSI_10MHZ BIT(7)
773 #define NI_M_CLK_FOUT2_TIMEBASE3_PLL BIT(6)
774 #define NI_M_CLK_FOUT2_TIMEBASE1_PLL BIT(5)
775 #define NI_M_CLK_FOUT2_PLL_SRC(x) (((x) & 0x1f) << 0)
776 #define NI_M_CLK_FOUT2_PLL_SRC_MASK NI_M_CLK_FOUT2_PLL_SRC(0x1f)
777 #define NI_M_MAX_RTSI_CHAN 7
778 #define NI_M_CLK_FOUT2_PLL_SRC_RTSI(x) (((x) == NI_M_MAX_RTSI_CHAN) \
779 ? NI_M_CLK_FOUT2_PLL_SRC(0x1b) \
780 : NI_M_CLK_FOUT2_PLL_SRC(0xb + (x)))
781 #define NI_M_CLK_FOUT2_PLL_SRC_STAR NI_M_CLK_FOUT2_PLL_SRC(0x14)
782 #define NI_M_CLK_FOUT2_PLL_SRC_PXI10 NI_M_CLK_FOUT2_PLL_SRC(0x1d)
783 #define NI_M_PLL_CTRL_REG 0x1c6
784 #define NI_M_PLL_CTRL_VCO_MODE(x) (((x) & 0x3) << 13)
785 #define NI_M_PLL_CTRL_VCO_MODE_200_325MHZ NI_M_PLL_CTRL_VCO_MODE(0)
786 #define NI_M_PLL_CTRL_VCO_MODE_175_225MHZ NI_M_PLL_CTRL_VCO_MODE(1)
787 #define NI_M_PLL_CTRL_VCO_MODE_100_225MHZ NI_M_PLL_CTRL_VCO_MODE(2)
788 #define NI_M_PLL_CTRL_VCO_MODE_75_150MHZ NI_M_PLL_CTRL_VCO_MODE(3)
789 #define NI_M_PLL_CTRL_ENA BIT(12)
790 #define NI_M_PLL_MAX_DIVISOR 0x10
791 #define NI_M_PLL_CTRL_DIVISOR(x) (((x) & 0xf) << 8)
792 #define NI_M_PLL_MAX_MULTIPLIER 0x100
793 #define NI_M_PLL_CTRL_MULTIPLIER(x) (((x) & 0xff) << 0)
794 #define NI_M_PLL_STATUS_REG 0x1c8
795 #define NI_M_PLL_STATUS_LOCKED BIT(0)
796 #define NI_M_PFI_OUT_SEL_REG(x) (0x1d0 + ((x) * 2))
797 #define NI_M_PFI_CHAN(_c) (((_c) % 3) * 5)
798 #define NI_M_PFI_OUT_SEL(_c, _s) (((_s) & 0x1f) << NI_M_PFI_CHAN(_c))
799 #define NI_M_PFI_OUT_SEL_MASK(_c) (0x1f << NI_M_PFI_CHAN(_c))
800 #define NI_M_PFI_OUT_SEL_TO_SRC(_c, _b) (((_b) >> NI_M_PFI_CHAN(_c)) & 0x1f)
801 #define NI_M_PFI_DI_REG 0x1dc
802 #define NI_M_PFI_DO_REG 0x1de
803 #define NI_M_CFG_BYPASS_FIFO_REG 0x218
804 #define NI_M_CFG_BYPASS_FIFO BIT(31)
805 #define NI_M_CFG_BYPASS_AI_POLARITY BIT(22)
806 #define NI_M_CFG_BYPASS_AI_DITHER BIT(21)
807 #define NI_M_CFG_BYPASS_AI_GAIN(x) (((x) & 0x7) << 18)
808 #define NI_M_CFG_BYPASS_AO_CAL(x) (((x) & 0xf) << 15)
809 #define NI_M_CFG_BYPASS_AO_CAL_MASK NI_M_CFG_BYPASS_AO_CAL(0xf)
810 #define NI_M_CFG_BYPASS_AI_MODE_MUX(x) (((x) & 0x3) << 13)
811 #define NI_M_CFG_BYPASS_AI_MODE_MUX_MASK NI_M_CFG_BYPASS_AI_MODE_MUX(3)
812 #define NI_M_CFG_BYPASS_AI_CAL_NEG(x) (((x) & 0x7) << 10)
813 #define NI_M_CFG_BYPASS_AI_CAL_NEG_MASK NI_M_CFG_BYPASS_AI_CAL_NEG(7)
814 #define NI_M_CFG_BYPASS_AI_CAL_POS(x) (((x) & 0x7) << 7)
815 #define NI_M_CFG_BYPASS_AI_CAL_POS_MASK NI_M_CFG_BYPASS_AI_CAL_POS(7)
816 #define NI_M_CFG_BYPASS_AI_CAL_MASK (NI_M_CFG_BYPASS_AI_CAL_POS_MASK | \
817 NI_M_CFG_BYPASS_AI_CAL_NEG_MASK | \
818 NI_M_CFG_BYPASS_AI_MODE_MUX_MASK | \
819 NI_M_CFG_BYPASS_AO_CAL_MASK)
820 #define NI_M_CFG_BYPASS_AI_BANK(x) (((x) & 0xf) << 3)
821 #define NI_M_CFG_BYPASS_AI_BANK_MASK NI_M_CFG_BYPASS_AI_BANK(0xf)
822 #define NI_M_CFG_BYPASS_AI_CHAN(x) (((x) & 0x7) << 0)
823 #define NI_M_CFG_BYPASS_AI_CHAN_MASK NI_M_CFG_BYPASS_AI_CHAN(7)
824 #define NI_M_SCXI_DIO_ENA_REG 0x21c
825 #define NI_M_CDI_FIFO_DATA_REG 0x220
826 #define NI_M_CDO_FIFO_DATA_REG 0x220
827 #define NI_M_CDIO_STATUS_REG 0x224
828 #define NI_M_CDIO_STATUS_CDI_OVERFLOW BIT(20)
829 #define NI_M_CDIO_STATUS_CDI_OVERRUN BIT(19)
830 #define NI_M_CDIO_STATUS_CDI_ERROR (NI_M_CDIO_STATUS_CDI_OVERFLOW | \
831 NI_M_CDIO_STATUS_CDI_OVERRUN)
832 #define NI_M_CDIO_STATUS_CDI_FIFO_REQ BIT(18)
833 #define NI_M_CDIO_STATUS_CDI_FIFO_FULL BIT(17)
834 #define NI_M_CDIO_STATUS_CDI_FIFO_EMPTY BIT(16)
835 #define NI_M_CDIO_STATUS_CDO_UNDERFLOW BIT(4)
836 #define NI_M_CDIO_STATUS_CDO_OVERRUN BIT(3)
837 #define NI_M_CDIO_STATUS_CDO_ERROR (NI_M_CDIO_STATUS_CDO_UNDERFLOW | \
838 NI_M_CDIO_STATUS_CDO_OVERRUN)
839 #define NI_M_CDIO_STATUS_CDO_FIFO_REQ BIT(2)
840 #define NI_M_CDIO_STATUS_CDO_FIFO_FULL BIT(1)
841 #define NI_M_CDIO_STATUS_CDO_FIFO_EMPTY BIT(0)
842 #define NI_M_CDIO_CMD_REG 0x224
843 #define NI_M_CDI_CMD_SW_UPDATE BIT(20)
844 #define NI_M_CDO_CMD_SW_UPDATE BIT(19)
845 #define NI_M_CDO_CMD_F_E_INT_ENA_CLR BIT(17)
846 #define NI_M_CDO_CMD_F_E_INT_ENA_SET BIT(16)
847 #define NI_M_CDI_CMD_ERR_INT_CONFIRM BIT(15)
848 #define NI_M_CDO_CMD_ERR_INT_CONFIRM BIT(14)
849 #define NI_M_CDI_CMD_F_REQ_INT_ENA_CLR BIT(13)
850 #define NI_M_CDI_CMD_F_REQ_INT_ENA_SET BIT(12)
851 #define NI_M_CDO_CMD_F_REQ_INT_ENA_CLR BIT(11)
852 #define NI_M_CDO_CMD_F_REQ_INT_ENA_SET BIT(10)
853 #define NI_M_CDI_CMD_ERR_INT_ENA_CLR BIT(9)
854 #define NI_M_CDI_CMD_ERR_INT_ENA_SET BIT(8)
855 #define NI_M_CDO_CMD_ERR_INT_ENA_CLR BIT(7)
856 #define NI_M_CDO_CMD_ERR_INT_ENA_SET BIT(6)
857 #define NI_M_CDI_CMD_RESET BIT(5)
858 #define NI_M_CDO_CMD_RESET BIT(4)
859 #define NI_M_CDI_CMD_ARM BIT(3)
860 #define NI_M_CDI_CMD_DISARM BIT(2)
861 #define NI_M_CDO_CMD_ARM BIT(1)
862 #define NI_M_CDO_CMD_DISARM BIT(0)
863 #define NI_M_CDI_MODE_REG 0x228
864 #define NI_M_CDI_MODE_DATA_LANE(x) (((x) & 0x3) << 12)
865 #define NI_M_CDI_MODE_DATA_LANE_MASK NI_M_CDI_MODE_DATA_LANE(3)
866 #define NI_M_CDI_MODE_DATA_LANE_0_15 NI_M_CDI_MODE_DATA_LANE(0)
867 #define NI_M_CDI_MODE_DATA_LANE_16_31 NI_M_CDI_MODE_DATA_LANE(1)
868 #define NI_M_CDI_MODE_DATA_LANE_0_7 NI_M_CDI_MODE_DATA_LANE(0)
869 #define NI_M_CDI_MODE_DATA_LANE_8_15 NI_M_CDI_MODE_DATA_LANE(1)
870 #define NI_M_CDI_MODE_DATA_LANE_16_23 NI_M_CDI_MODE_DATA_LANE(2)
871 #define NI_M_CDI_MODE_DATA_LANE_24_31 NI_M_CDI_MODE_DATA_LANE(3)
872 #define NI_M_CDI_MODE_FIFO_MODE BIT(11)
873 #define NI_M_CDI_MODE_POLARITY BIT(10)
874 #define NI_M_CDI_MODE_HALT_ON_ERROR BIT(9)
875 #define NI_M_CDI_MODE_SAMPLE_SRC(x) (((x) & 0x3f) << 0)
876 #define NI_M_CDI_MODE_SAMPLE_SRC_MASK NI_M_CDI_MODE_SAMPLE_SRC(0x3f)
877 #define NI_M_CDO_MODE_REG 0x22c
878 #define NI_M_CDO_MODE_DATA_LANE(x) (((x) & 0x3) << 12)
879 #define NI_M_CDO_MODE_DATA_LANE_MASK NI_M_CDO_MODE_DATA_LANE(3)
880 #define NI_M_CDO_MODE_DATA_LANE_0_15 NI_M_CDO_MODE_DATA_LANE(0)
881 #define NI_M_CDO_MODE_DATA_LANE_16_31 NI_M_CDO_MODE_DATA_LANE(1)
882 #define NI_M_CDO_MODE_DATA_LANE_0_7 NI_M_CDO_MODE_DATA_LANE(0)
883 #define NI_M_CDO_MODE_DATA_LANE_8_15 NI_M_CDO_MODE_DATA_LANE(1)
884 #define NI_M_CDO_MODE_DATA_LANE_16_23 NI_M_CDO_MODE_DATA_LANE(2)
885 #define NI_M_CDO_MODE_DATA_LANE_24_31 NI_M_CDO_MODE_DATA_LANE(3)
886 #define NI_M_CDO_MODE_FIFO_MODE BIT(11)
887 #define NI_M_CDO_MODE_POLARITY BIT(10)
888 #define NI_M_CDO_MODE_HALT_ON_ERROR BIT(9)
889 #define NI_M_CDO_MODE_RETRANSMIT BIT(8)
890 #define NI_M_CDO_MODE_SAMPLE_SRC(x) (((x) & 0x3f) << 0)
891 #define NI_M_CDO_MODE_SAMPLE_SRC_MASK NI_M_CDO_MODE_SAMPLE_SRC(0x3f)
892 #define NI_M_CDI_MASK_ENA_REG 0x230
893 #define NI_M_CDO_MASK_ENA_REG 0x234
894 #define NI_M_STATIC_AI_CTRL_REG(x) ((x) ? (0x260 + (x)) : 0x064)
895 #define NI_M_AO_REF_ATTENUATION_REG(x) (0x264 + (x))
896 #define NI_M_AO_REF_ATTENUATION_X5 BIT(0)
925 ni_reg_67xx_mask = 0x6,
926 ni_reg_6xxx_mask = 0x7,
930 ni_reg_m_series_mask = 0x18,
934 struct ni_board_struct {
940 unsigned int ai_maxdata;
943 unsigned int alwaysdither:1;
948 unsigned int ao_maxdata;
950 const struct comedi_lrange *ao_range_table;
951 unsigned int ao_speed;
954 unsigned int has_8255:1;
955 unsigned int has_32dio_chan:1;
957 enum caldac_enum caldac[3];
960 #define MAX_N_CALDACS 34
961 #define MAX_N_AO_CHAN 8
964 #define NUM_PFI_OUTPUT_SELECT_REGS 6
966 #define M_SERIES_EEPROM_SIZE 1024
969 unsigned short dio_output;
970 unsigned short dio_control;
972 unsigned int ai_calib_source;
973 unsigned int ai_calib_source_enabled;
974 /* protects access to windowed registers */
975 spinlock_t window_lock;
976 /* protects interrupt/dma register access */
977 spinlock_t soft_reg_copy_lock;
978 /* protects mite DMA channel request/release */
979 spinlock_t mite_channel_lock;
982 unsigned int changain_spec;
984 unsigned int caldac_maxdata_list[MAX_N_CALDACS];
985 unsigned short caldacs[MAX_N_CALDACS];
987 unsigned short ai_cmd2;
989 unsigned short ao_conf[MAX_N_AO_CHAN];
990 unsigned short ao_mode1;
991 unsigned short ao_mode2;
992 unsigned short ao_mode3;
993 unsigned short ao_cmd1;
994 unsigned short ao_cmd2;
996 struct ni_gpct_device *counter_dev;
997 unsigned short an_trig_etc_reg;
999 unsigned int ai_offset[512];
1001 unsigned long serial_interval_ns;
1002 unsigned char serial_hw_mode;
1003 unsigned short clock_and_fout;
1004 unsigned short clock_and_fout2;
1006 unsigned short int_a_enable_reg;
1007 unsigned short int_b_enable_reg;
1008 unsigned short io_bidirection_pin_reg;
1009 unsigned short rtsi_trig_direction_reg;
1010 unsigned short rtsi_trig_a_output_reg;
1011 unsigned short rtsi_trig_b_output_reg;
1012 unsigned short pfi_output_select_reg[NUM_PFI_OUTPUT_SELECT_REGS];
1013 unsigned short ai_ao_select_reg;
1014 unsigned short g0_g1_select_reg;
1015 unsigned short cdio_dma_select_reg;
1017 unsigned int clock_ns;
1018 unsigned int clock_source;
1020 unsigned short pwm_up_count;
1021 unsigned short pwm_down_count;
1023 unsigned short ai_fifo_buffer[0x2000];
1024 u8 eeprom_buffer[M_SERIES_EEPROM_SIZE];
1027 struct mite_channel *ai_mite_chan;
1028 struct mite_channel *ao_mite_chan;
1029 struct mite_channel *cdo_mite_chan;
1030 struct mite_ring *ai_mite_ring;
1031 struct mite_ring *ao_mite_ring;
1032 struct mite_ring *cdo_mite_ring;
1033 struct mite_ring *gpct_mite_ring[NUM_GPCT];
1035 /* ni_pcimio board type flags (based on the boardinfo reg_type) */
1036 unsigned int is_m_series:1;
1037 unsigned int is_6xxx:1;
1038 unsigned int is_611x:1;
1039 unsigned int is_6143:1;
1040 unsigned int is_622x:1;
1041 unsigned int is_625x:1;
1042 unsigned int is_628x:1;
1043 unsigned int is_67xx:1;
1044 unsigned int is_6711:1;
1045 unsigned int is_6713:1;
1048 * Boolean value of whether device needs to be armed.
1050 * Currently, only NI AO devices are known to be needing arming, since
1051 * the DAC registers must be preloaded before triggering.
1052 * This variable should only be set true during a command operation
1053 * (e.g ni_ao_cmd) and should then be set false by the arming
1054 * function (e.g. ni_ao_arm).
1056 * This variable helps to ensure that multiple DMA allocations are not
1059 unsigned int ao_needs_arming:1;
1062 static const struct comedi_lrange range_ni_E_ao_ext;
1064 #endif /* _COMEDI_NI_STC_H */