2 * Comedi driver for NI PCI-MIO E series cards
4 * COMEDI - Linux Control and Measurement Device Interface
5 * Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
20 * Description: National Instruments PCI-MIO-E series and M series (all boards)
21 * Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans,
22 * Herman Bruyninckx, Terry Barnaby
24 * Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio),
25 * PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014,
26 * PCI-6040E, PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E,
27 * PCI-6071E, PCI-6023E, PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E,
28 * PCI-6035E, PCI-6052E, PCI-6110, PCI-6111, PCI-6220, PXI-6220,
29 * PCI-6221, PXI-6221, PCI-6224, PXI-6224, PCI-6225, PXI-6225,
30 * PCI-6229, PXI-6229, PCI-6250, PXI-6250, PCI-6251, PXI-6251,
31 * PCIe-6251, PXIe-6251, PCI-6254, PXI-6254, PCI-6259, PXI-6259,
32 * PCIe-6259, PXIe-6259, PCI-6280, PXI-6280, PCI-6281, PXI-6281,
33 * PCI-6284, PXI-6284, PCI-6289, PXI-6289, PCI-6711, PXI-6711,
34 * PCI-6713, PXI-6713, PXI-6071E, PCI-6070E, PXI-6070E,
35 * PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733,
37 * Updated: Mon, 16 Jan 2017 12:56:04 +0000
39 * These boards are almost identical to the AT-MIO E series, except that
40 * they use the PCI bus instead of ISA (i.e., AT). See the notes for the
41 * ni_atmio.o driver for additional information about these boards.
43 * Autocalibration is supported on many of the devices, using the
44 * comedi_calibrate (or comedi_soft_calibrate for m-series) utility.
45 * M-Series boards do analog input and analog output calibration entirely
46 * in software. The software calibration corrects the analog input for
47 * offset, gain and nonlinearity. The analog outputs are corrected for
48 * offset and gain. See the comedilib documentation on
49 * comedi_get_softcal_converter() for more information.
51 * By default, the driver uses DMA to transfer analog input data to
52 * memory. When DMA is enabled, not all triggering features are
55 * Digital I/O may not work on 673x.
57 * Note that the PCI-6143 is a simultaineous sampling device with 8
58 * convertors. With this board all of the convertors perform one
59 * simultaineous sample during a scan interval. The period for a scan
60 * is used for the convert time in a Comedi cmd. The convert trigger
61 * source is normally set to TRIG_NOW by default.
63 * The RTSI trigger bus is supported on these cards on subdevice 10.
64 * See the comedilib documentation for details.
66 * Information (number of channels, bits, etc.) for some devices may be
67 * incorrect. Please check this and submit a bug if there are problems
70 * SCXI is probably broken for m-series boards.
73 * - When DMA is enabled, COMEDI_EV_CONVERT does not work correctly.
77 * The PCI-MIO E series driver was originally written by
78 * Tomasz Motylewski <...>, and ported to comedi by ds.
81 * 341079b.pdf PCI E Series Register-Level Programmer Manual
82 * 340934b.pdf DAQ-STC reference manual
84 * 322080b.pdf 6711/6713/6715 User Manual
86 * 320945c.pdf PCI E Series User Manual
87 * 322138a.pdf PCI-6052E and DAQPad-6052E User Manual
90 * - need to deal with external reference for DAC, and other DAC
91 * properties in board properties
92 * - deal with at-mio-16de-10 revision D to N changes, etc.
93 * - need to add other CALDAC type
94 * - need to slow down DAC loading. I don't trust NI's claim that
95 * two writes to the PCI bus slows IO enough. I would prefer to
97 * Timing specs: (clock)
104 #include <linux/module.h>
105 #include <linux/delay.h>
107 #include "../comedi_pci.h"
109 #include <asm/byteorder.h>
117 * These are not all the possible ao ranges for 628x boards.
118 * They can do OFFSET +- REFERENCE where OFFSET can be
119 * 0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can
120 * be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>. That's
121 * 63 different possibilities. An AO channel
122 * can not act as it's own OFFSET or REFERENCE.
124 static const struct comedi_lrange range_ni_M_628x_ao = {
138 static const struct comedi_lrange range_ni_M_625x_ao = {
146 enum ni_pcimio_boardid {
147 BOARD_PCIMIO_16XE_50,
148 BOARD_PCIMIO_16XE_10,
217 static const struct ni_board_struct ni_boards[] = {
218 [BOARD_PCIMIO_16XE_50] = {
219 .name = "pci-mio-16xe-50",
221 .ai_maxdata = 0xffff,
222 .ai_fifo_depth = 2048,
224 .gainlkup = ai_gain_8,
227 .ao_maxdata = 0x0fff,
228 .ao_range_table = &range_bipolar10,
230 .caldac = { dac8800, dac8043 },
232 [BOARD_PCIMIO_16XE_10] = {
233 .name = "pci-mio-16xe-10", /* aka pci-6030E */
235 .ai_maxdata = 0xffff,
236 .ai_fifo_depth = 512,
238 .gainlkup = ai_gain_14,
241 .ao_maxdata = 0xffff,
242 .ao_fifo_depth = 2048,
243 .ao_range_table = &range_ni_E_ao_ext,
245 .caldac = { dac8800, dac8043, ad8522 },
250 .ai_maxdata = 0xffff,
251 .ai_fifo_depth = 512,
253 .gainlkup = ai_gain_4,
256 .ao_maxdata = 0xffff,
257 .ao_range_table = &range_bipolar10,
259 .caldac = { ad8804_debug },
264 .ai_maxdata = 0xffff,
265 .ai_fifo_depth = 512,
267 .gainlkup = ai_gain_14,
270 .ao_maxdata = 0xffff,
271 .ao_fifo_depth = 2048,
272 .ao_range_table = &range_ni_E_ao_ext,
274 .caldac = { dac8800, dac8043, ad8522 },
276 [BOARD_PCIMIO_16E_1] = {
277 .name = "pci-mio-16e-1", /* aka pci-6070e */
279 .ai_maxdata = 0x0fff,
280 .ai_fifo_depth = 512,
281 .gainlkup = ai_gain_16,
284 .ao_maxdata = 0x0fff,
285 .ao_fifo_depth = 2048,
286 .ao_range_table = &range_ni_E_ao_ext,
288 .caldac = { mb88341 },
290 [BOARD_PCIMIO_16E_4] = {
291 .name = "pci-mio-16e-4", /* aka pci-6040e */
293 .ai_maxdata = 0x0fff,
294 .ai_fifo_depth = 512,
295 .gainlkup = ai_gain_16,
297 * there have been reported problems with
298 * full speed on this board
302 .ao_maxdata = 0x0fff,
303 .ao_fifo_depth = 512,
304 .ao_range_table = &range_ni_E_ao_ext,
306 .caldac = { ad8804_debug }, /* doc says mb88341 */
311 .ai_maxdata = 0x0fff,
312 .ai_fifo_depth = 512,
313 .gainlkup = ai_gain_16,
316 .ao_maxdata = 0x0fff,
317 .ao_fifo_depth = 512,
318 .ao_range_table = &range_ni_E_ao_ext,
320 .caldac = { mb88341 },
325 .ai_maxdata = 0xffff,
326 .ai_fifo_depth = 512,
328 .gainlkup = ai_gain_14,
331 .ao_maxdata = 0xffff,
332 .ao_fifo_depth = 2048,
333 .ao_range_table = &range_ni_E_ao_ext,
335 .caldac = { dac8800, dac8043, ad8522 },
340 .ai_maxdata = 0xffff,
341 .ai_fifo_depth = 512,
343 .gainlkup = ai_gain_14,
345 .caldac = { dac8800, dac8043, ad8522 },
350 .ai_maxdata = 0xffff,
351 .ai_fifo_depth = 512,
353 .gainlkup = ai_gain_14,
355 .caldac = { dac8800, dac8043, ad8522 },
360 .ai_maxdata = 0x0fff,
361 .ai_fifo_depth = 512,
363 .gainlkup = ai_gain_16,
366 .ao_maxdata = 0x0fff,
367 .ao_fifo_depth = 2048,
368 .ao_range_table = &range_ni_E_ao_ext,
370 .caldac = { ad8804_debug },
375 .ai_maxdata = 0x0fff,
376 .ai_fifo_depth = 512,
377 .gainlkup = ai_gain_4,
379 .caldac = { ad8804_debug }, /* manual is wrong */
384 .ai_maxdata = 0x0fff,
385 .ai_fifo_depth = 512,
386 .gainlkup = ai_gain_4,
389 .ao_maxdata = 0x0fff,
390 .ao_range_table = &range_bipolar10,
392 .caldac = { ad8804_debug }, /* manual is wrong */
397 .ai_maxdata = 0x0fff,
398 .ai_fifo_depth = 512,
399 .gainlkup = ai_gain_4,
402 .ao_maxdata = 0x0fff,
403 .ao_range_table = &range_bipolar10,
405 .caldac = { ad8804_debug }, /* manual is wrong */
411 .ai_maxdata = 0x0fff,
412 .ai_fifo_depth = 512,
413 .gainlkup = ai_gain_4,
416 .ao_maxdata = 0x0fff,
417 .ao_range_table = &range_ni_E_ao_ext,
419 .caldac = { ad8804_debug }, /* manual is wrong */
425 .ai_maxdata = 0xffff,
426 .ai_fifo_depth = 512,
428 .gainlkup = ai_gain_4,
430 .caldac = { ad8804_debug },
435 .ai_maxdata = 0xffff,
436 .ai_fifo_depth = 512,
438 .gainlkup = ai_gain_4,
441 .ao_maxdata = 0x0fff,
442 .ao_range_table = &range_bipolar10,
444 .caldac = { ad8804_debug },
449 .ai_maxdata = 0xffff,
450 .ai_fifo_depth = 512,
452 .gainlkup = ai_gain_16,
455 .ao_maxdata = 0xffff,
456 .ao_fifo_depth = 2048,
457 .ao_range_table = &range_ni_E_ao_ext,
459 /* manual is wrong */
460 .caldac = { ad8804_debug, ad8804_debug, ad8522 },
465 .ai_maxdata = 0x0fff,
466 .ai_fifo_depth = 8192,
468 .gainlkup = ai_gain_611x,
471 .ao_maxdata = 0xffff,
472 .reg_type = ni_reg_611x,
473 .ao_range_table = &range_bipolar10,
474 .ao_fifo_depth = 2048,
476 .caldac = { ad8804, ad8804 },
481 .ai_maxdata = 0x0fff,
482 .ai_fifo_depth = 8192,
483 .gainlkup = ai_gain_611x,
486 .ao_maxdata = 0xffff,
487 .reg_type = ni_reg_611x,
488 .ao_range_table = &range_bipolar10,
489 .ao_fifo_depth = 2048,
491 .caldac = { ad8804, ad8804 },
494 /* The 6115 boards probably need their own driver */
495 [BOARD_PCI6115] = { /* .device_id = 0x2ed0, */
498 .ai_maxdata = 0x0fff,
499 .ai_fifo_depth = 8192,
500 .gainlkup = ai_gain_611x,
503 .ao_maxdata = 0xffff,
505 .ao_fifo_depth = 2048,
509 .caldac = { ad8804_debug, ad8804_debug, ad8804_debug },
513 [BOARD_PXI6115] = { /* .device_id = ????, */
516 .ai_maxdata = 0x0fff,
517 .ai_fifo_depth = 8192,
518 .gainlkup = ai_gain_611x,
521 .ao_maxdata = 0xffff,
523 .ao_fifo_depth = 2048,
527 .caldac = { ad8804_debug, ad8804_debug, ad8804_debug },
533 .ao_maxdata = 0x0fff,
534 /* data sheet says 8192, but fifo really holds 16384 samples */
535 .ao_fifo_depth = 16384,
536 .ao_range_table = &range_bipolar10,
538 .reg_type = ni_reg_6711,
539 .caldac = { ad8804_debug },
544 .ao_maxdata = 0x0fff,
545 .ao_fifo_depth = 16384,
546 .ao_range_table = &range_bipolar10,
548 .reg_type = ni_reg_6711,
549 .caldac = { ad8804_debug },
554 .ao_maxdata = 0x0fff,
555 .ao_fifo_depth = 16384,
556 .ao_range_table = &range_bipolar10,
558 .reg_type = ni_reg_6713,
559 .caldac = { ad8804_debug, ad8804_debug },
564 .ao_maxdata = 0x0fff,
565 .ao_fifo_depth = 16384,
566 .ao_range_table = &range_bipolar10,
568 .reg_type = ni_reg_6713,
569 .caldac = { ad8804_debug, ad8804_debug },
574 .ao_maxdata = 0xffff,
575 .ao_fifo_depth = 8192,
576 .ao_range_table = &range_bipolar10,
578 .reg_type = ni_reg_6711,
579 .caldac = { ad8804_debug },
582 [BOARD_PXI6731] = { /* .device_id = ????, */
585 .ao_maxdata = 0xffff,
586 .ao_fifo_depth = 8192,
587 .ao_range_table = &range_bipolar10,
588 .reg_type = ni_reg_6711,
589 .caldac = { ad8804_debug },
595 .ao_maxdata = 0xffff,
596 .ao_fifo_depth = 16384,
597 .ao_range_table = &range_bipolar10,
599 .reg_type = ni_reg_6713,
600 .caldac = { ad8804_debug, ad8804_debug },
605 .ao_maxdata = 0xffff,
606 .ao_fifo_depth = 16384,
607 .ao_range_table = &range_bipolar10,
609 .reg_type = ni_reg_6713,
610 .caldac = { ad8804_debug, ad8804_debug },
615 .ai_maxdata = 0x0fff,
616 .ai_fifo_depth = 512,
618 .gainlkup = ai_gain_16,
621 .ao_maxdata = 0x0fff,
622 .ao_fifo_depth = 2048,
623 .ao_range_table = &range_ni_E_ao_ext,
625 .caldac = { ad8804_debug },
630 .ai_maxdata = 0x0fff,
631 .ai_fifo_depth = 512,
633 .gainlkup = ai_gain_16,
636 .ao_maxdata = 0x0fff,
637 .ao_fifo_depth = 2048,
638 .ao_range_table = &range_ni_E_ao_ext,
640 .caldac = { ad8804_debug },
645 .ai_maxdata = 0xffff,
646 .ai_fifo_depth = 512,
648 .gainlkup = ai_gain_16,
651 .ao_maxdata = 0xffff,
652 .ao_fifo_depth = 2048,
653 .ao_range_table = &range_ni_E_ao_ext,
655 .caldac = { mb88341, mb88341, ad8522 },
660 .ai_maxdata = 0xffff,
661 .ai_fifo_depth = 512,
663 .gainlkup = ai_gain_14,
666 .ao_maxdata = 0xffff,
667 .ao_fifo_depth = 2048,
668 .ao_range_table = &range_ni_E_ao_ext,
670 .caldac = { dac8800, dac8043, ad8522 },
675 .ai_maxdata = 0xffff,
676 .ai_fifo_depth = 512,
678 .gainlkup = ai_gain_4,
681 .ao_maxdata = 0xffff,
682 .ao_range_table = &range_bipolar10,
684 .caldac = { ad8804_debug },
689 .ai_maxdata = 0xffff,
690 .ai_fifo_depth = 512, /* FIXME: guess */
691 .gainlkup = ai_gain_622x,
693 .reg_type = ni_reg_622x,
694 .caldac = { caldac_none },
699 .ai_maxdata = 0xffff,
700 .ai_fifo_depth = 512, /* FIXME: guess */
701 .gainlkup = ai_gain_622x,
703 .reg_type = ni_reg_622x,
704 .caldac = { caldac_none },
709 .ai_maxdata = 0xffff,
710 .ai_fifo_depth = 4095,
711 .gainlkup = ai_gain_622x,
714 .ao_maxdata = 0xffff,
715 .ao_fifo_depth = 8191,
716 .ao_range_table = &range_bipolar10,
717 .reg_type = ni_reg_622x,
719 .caldac = { caldac_none },
721 [BOARD_PCI6221_37PIN] = {
722 .name = "pci-6221_37pin",
724 .ai_maxdata = 0xffff,
725 .ai_fifo_depth = 4095,
726 .gainlkup = ai_gain_622x,
729 .ao_maxdata = 0xffff,
730 .ao_fifo_depth = 8191,
731 .ao_range_table = &range_bipolar10,
732 .reg_type = ni_reg_622x,
734 .caldac = { caldac_none },
739 .ai_maxdata = 0xffff,
740 .ai_fifo_depth = 4095,
741 .gainlkup = ai_gain_622x,
744 .ao_maxdata = 0xffff,
745 .ao_fifo_depth = 8191,
746 .ao_range_table = &range_bipolar10,
747 .reg_type = ni_reg_622x,
749 .caldac = { caldac_none },
754 .ai_maxdata = 0xffff,
755 .ai_fifo_depth = 4095,
756 .gainlkup = ai_gain_622x,
758 .reg_type = ni_reg_622x,
760 .caldac = { caldac_none },
765 .ai_maxdata = 0xffff,
766 .ai_fifo_depth = 4095,
767 .gainlkup = ai_gain_622x,
769 .reg_type = ni_reg_622x,
771 .caldac = { caldac_none },
776 .ai_maxdata = 0xffff,
777 .ai_fifo_depth = 4095,
778 .gainlkup = ai_gain_622x,
781 .ao_maxdata = 0xffff,
782 .ao_fifo_depth = 8191,
783 .ao_range_table = &range_bipolar10,
784 .reg_type = ni_reg_622x,
787 .caldac = { caldac_none },
792 .ai_maxdata = 0xffff,
793 .ai_fifo_depth = 4095,
794 .gainlkup = ai_gain_622x,
797 .ao_maxdata = 0xffff,
798 .ao_fifo_depth = 8191,
799 .ao_range_table = &range_bipolar10,
800 .reg_type = ni_reg_622x,
803 .caldac = { caldac_none },
808 .ai_maxdata = 0xffff,
809 .ai_fifo_depth = 4095,
810 .gainlkup = ai_gain_622x,
813 .ao_maxdata = 0xffff,
814 .ao_fifo_depth = 8191,
815 .ao_range_table = &range_bipolar10,
816 .reg_type = ni_reg_622x,
819 .caldac = { caldac_none },
824 .ai_maxdata = 0xffff,
825 .ai_fifo_depth = 4095,
826 .gainlkup = ai_gain_622x,
829 .ao_maxdata = 0xffff,
830 .ao_fifo_depth = 8191,
831 .ao_range_table = &range_bipolar10,
832 .reg_type = ni_reg_622x,
835 .caldac = { caldac_none },
840 .ai_maxdata = 0xffff,
841 .ai_fifo_depth = 4095,
842 .gainlkup = ai_gain_628x,
844 .reg_type = ni_reg_625x,
845 .caldac = { caldac_none },
850 .ai_maxdata = 0xffff,
851 .ai_fifo_depth = 4095,
852 .gainlkup = ai_gain_628x,
854 .reg_type = ni_reg_625x,
855 .caldac = { caldac_none },
860 .ai_maxdata = 0xffff,
861 .ai_fifo_depth = 4095,
862 .gainlkup = ai_gain_628x,
865 .ao_maxdata = 0xffff,
866 .ao_fifo_depth = 8191,
867 .ao_range_table = &range_ni_M_625x_ao,
868 .reg_type = ni_reg_625x,
870 .caldac = { caldac_none },
875 .ai_maxdata = 0xffff,
876 .ai_fifo_depth = 4095,
877 .gainlkup = ai_gain_628x,
880 .ao_maxdata = 0xffff,
881 .ao_fifo_depth = 8191,
882 .ao_range_table = &range_ni_M_625x_ao,
883 .reg_type = ni_reg_625x,
885 .caldac = { caldac_none },
890 .ai_maxdata = 0xffff,
891 .ai_fifo_depth = 4095,
892 .gainlkup = ai_gain_628x,
895 .ao_maxdata = 0xffff,
896 .ao_fifo_depth = 8191,
897 .ao_range_table = &range_ni_M_625x_ao,
898 .reg_type = ni_reg_625x,
900 .caldac = { caldac_none },
905 .ai_maxdata = 0xffff,
906 .ai_fifo_depth = 4095,
907 .gainlkup = ai_gain_628x,
910 .ao_maxdata = 0xffff,
911 .ao_fifo_depth = 8191,
912 .ao_range_table = &range_ni_M_625x_ao,
913 .reg_type = ni_reg_625x,
915 .caldac = { caldac_none },
920 .ai_maxdata = 0xffff,
921 .ai_fifo_depth = 4095,
922 .gainlkup = ai_gain_628x,
924 .reg_type = ni_reg_625x,
926 .caldac = { caldac_none },
931 .ai_maxdata = 0xffff,
932 .ai_fifo_depth = 4095,
933 .gainlkup = ai_gain_628x,
935 .reg_type = ni_reg_625x,
937 .caldac = { caldac_none },
942 .ai_maxdata = 0xffff,
943 .ai_fifo_depth = 4095,
944 .gainlkup = ai_gain_628x,
947 .ao_maxdata = 0xffff,
948 .ao_fifo_depth = 8191,
949 .ao_range_table = &range_ni_M_625x_ao,
950 .reg_type = ni_reg_625x,
953 .caldac = { caldac_none },
958 .ai_maxdata = 0xffff,
959 .ai_fifo_depth = 4095,
960 .gainlkup = ai_gain_628x,
963 .ao_maxdata = 0xffff,
964 .ao_fifo_depth = 8191,
965 .ao_range_table = &range_ni_M_625x_ao,
966 .reg_type = ni_reg_625x,
969 .caldac = { caldac_none },
974 .ai_maxdata = 0xffff,
975 .ai_fifo_depth = 4095,
976 .gainlkup = ai_gain_628x,
979 .ao_maxdata = 0xffff,
980 .ao_fifo_depth = 8191,
981 .ao_range_table = &range_ni_M_625x_ao,
982 .reg_type = ni_reg_625x,
985 .caldac = { caldac_none },
990 .ai_maxdata = 0xffff,
991 .ai_fifo_depth = 4095,
992 .gainlkup = ai_gain_628x,
995 .ao_maxdata = 0xffff,
996 .ao_fifo_depth = 8191,
997 .ao_range_table = &range_ni_M_625x_ao,
998 .reg_type = ni_reg_625x,
1000 .has_32dio_chan = 1,
1001 .caldac = { caldac_none },
1006 .ai_maxdata = 0x3ffff,
1007 .ai_fifo_depth = 2047,
1008 .gainlkup = ai_gain_628x,
1010 .ao_fifo_depth = 8191,
1011 .reg_type = ni_reg_628x,
1012 .caldac = { caldac_none },
1017 .ai_maxdata = 0x3ffff,
1018 .ai_fifo_depth = 2047,
1019 .gainlkup = ai_gain_628x,
1021 .ao_fifo_depth = 8191,
1022 .reg_type = ni_reg_628x,
1023 .caldac = { caldac_none },
1028 .ai_maxdata = 0x3ffff,
1029 .ai_fifo_depth = 2047,
1030 .gainlkup = ai_gain_628x,
1033 .ao_maxdata = 0xffff,
1034 .ao_fifo_depth = 8191,
1035 .ao_range_table = &range_ni_M_628x_ao,
1036 .reg_type = ni_reg_628x,
1038 .caldac = { caldac_none },
1043 .ai_maxdata = 0x3ffff,
1044 .ai_fifo_depth = 2047,
1045 .gainlkup = ai_gain_628x,
1048 .ao_maxdata = 0xffff,
1049 .ao_fifo_depth = 8191,
1050 .ao_range_table = &range_ni_M_628x_ao,
1051 .reg_type = ni_reg_628x,
1053 .caldac = { caldac_none },
1058 .ai_maxdata = 0x3ffff,
1059 .ai_fifo_depth = 2047,
1060 .gainlkup = ai_gain_628x,
1062 .reg_type = ni_reg_628x,
1063 .has_32dio_chan = 1,
1064 .caldac = { caldac_none },
1069 .ai_maxdata = 0x3ffff,
1070 .ai_fifo_depth = 2047,
1071 .gainlkup = ai_gain_628x,
1073 .reg_type = ni_reg_628x,
1074 .has_32dio_chan = 1,
1075 .caldac = { caldac_none },
1080 .ai_maxdata = 0x3ffff,
1081 .ai_fifo_depth = 2047,
1082 .gainlkup = ai_gain_628x,
1085 .ao_maxdata = 0xffff,
1086 .ao_fifo_depth = 8191,
1087 .ao_range_table = &range_ni_M_628x_ao,
1088 .reg_type = ni_reg_628x,
1090 .has_32dio_chan = 1,
1091 .caldac = { caldac_none },
1096 .ai_maxdata = 0x3ffff,
1097 .ai_fifo_depth = 2047,
1098 .gainlkup = ai_gain_628x,
1101 .ao_maxdata = 0xffff,
1102 .ao_fifo_depth = 8191,
1103 .ao_range_table = &range_ni_M_628x_ao,
1104 .reg_type = ni_reg_628x,
1106 .has_32dio_chan = 1,
1107 .caldac = { caldac_none },
1112 .ai_maxdata = 0xffff,
1113 .ai_fifo_depth = 1024,
1114 .gainlkup = ai_gain_6143,
1116 .reg_type = ni_reg_6143,
1117 .caldac = { ad8804_debug, ad8804_debug },
1122 .ai_maxdata = 0xffff,
1123 .ai_fifo_depth = 1024,
1124 .gainlkup = ai_gain_6143,
1126 .reg_type = ni_reg_6143,
1127 .caldac = { ad8804_debug, ad8804_debug },
1131 #include "ni_mio_common.c"
1133 static int pcimio_ai_change(struct comedi_device *dev,
1134 struct comedi_subdevice *s)
1136 struct ni_private *devpriv = dev->private;
1139 ret = mite_buf_change(devpriv->ai_mite_ring, s);
1146 static int pcimio_ao_change(struct comedi_device *dev,
1147 struct comedi_subdevice *s)
1149 struct ni_private *devpriv = dev->private;
1152 ret = mite_buf_change(devpriv->ao_mite_ring, s);
1159 static int pcimio_gpct0_change(struct comedi_device *dev,
1160 struct comedi_subdevice *s)
1162 struct ni_private *devpriv = dev->private;
1165 ret = mite_buf_change(devpriv->gpct_mite_ring[0], s);
1172 static int pcimio_gpct1_change(struct comedi_device *dev,
1173 struct comedi_subdevice *s)
1175 struct ni_private *devpriv = dev->private;
1178 ret = mite_buf_change(devpriv->gpct_mite_ring[1], s);
1185 static int pcimio_dio_change(struct comedi_device *dev,
1186 struct comedi_subdevice *s)
1188 struct ni_private *devpriv = dev->private;
1191 ret = mite_buf_change(devpriv->cdo_mite_ring, s);
1198 static void m_series_init_eeprom_buffer(struct comedi_device *dev)
1200 struct ni_private *devpriv = dev->private;
1201 struct mite *mite = devpriv->mite;
1202 resource_size_t daq_phys_addr;
1203 static const int Start_Cal_EEPROM = 0x400;
1204 static const unsigned int window_size = 10;
1205 unsigned int old_iodwbsr_bits;
1206 unsigned int old_iodwbsr1_bits;
1207 unsigned int old_iodwcr1_bits;
1210 /* IO Window 1 needs to be temporarily mapped to read the eeprom */
1211 daq_phys_addr = pci_resource_start(mite->pcidev, 1);
1213 old_iodwbsr_bits = readl(mite->mmio + MITE_IODWBSR);
1214 old_iodwbsr1_bits = readl(mite->mmio + MITE_IODWBSR_1);
1215 old_iodwcr1_bits = readl(mite->mmio + MITE_IODWCR_1);
1216 writel(0x0, mite->mmio + MITE_IODWBSR);
1217 writel(((0x80 | window_size) | daq_phys_addr),
1218 mite->mmio + MITE_IODWBSR_1);
1219 writel(0x1 | old_iodwcr1_bits, mite->mmio + MITE_IODWCR_1);
1220 writel(0xf, mite->mmio + 0x30);
1222 for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i)
1223 devpriv->eeprom_buffer[i] = ni_readb(dev, Start_Cal_EEPROM + i);
1225 writel(old_iodwbsr1_bits, mite->mmio + MITE_IODWBSR_1);
1226 writel(old_iodwbsr_bits, mite->mmio + MITE_IODWBSR);
1227 writel(old_iodwcr1_bits, mite->mmio + MITE_IODWCR_1);
1228 writel(0x0, mite->mmio + 0x30);
1231 static void init_6143(struct comedi_device *dev)
1233 const struct ni_board_struct *board = dev->board_ptr;
1234 struct ni_private *devpriv = dev->private;
1236 /* Disable interrupts */
1237 ni_stc_writew(dev, 0, NISTC_INT_CTRL_REG);
1239 /* Initialise 6143 AI specific bits */
1241 /* Set G0,G1 DMA mode to E series version */
1242 ni_writeb(dev, 0x00, NI6143_MAGIC_REG);
1243 /* Set EOCMode, ADCMode and pipelinedelay */
1244 ni_writeb(dev, 0x80, NI6143_PIPELINE_DELAY_REG);
1246 ni_writeb(dev, 0x00, NI6143_EOC_SET_REG);
1248 /* Set the FIFO half full level */
1249 ni_writel(dev, board->ai_fifo_depth / 2, NI6143_AI_FIFO_FLAG_REG);
1251 /* Strobe Relay disable bit */
1252 devpriv->ai_calib_source_enabled = 0;
1253 ni_writew(dev, devpriv->ai_calib_source | NI6143_CALIB_CHAN_RELAY_OFF,
1254 NI6143_CALIB_CHAN_REG);
1255 ni_writew(dev, devpriv->ai_calib_source, NI6143_CALIB_CHAN_REG);
1258 static void pcimio_detach(struct comedi_device *dev)
1260 struct ni_private *devpriv = dev->private;
1262 mio_common_detach(dev);
1264 free_irq(dev->irq, dev);
1266 mite_free_ring(devpriv->ai_mite_ring);
1267 mite_free_ring(devpriv->ao_mite_ring);
1268 mite_free_ring(devpriv->cdo_mite_ring);
1269 mite_free_ring(devpriv->gpct_mite_ring[0]);
1270 mite_free_ring(devpriv->gpct_mite_ring[1]);
1271 mite_detach(devpriv->mite);
1275 comedi_pci_disable(dev);
1278 static int pcimio_auto_attach(struct comedi_device *dev,
1279 unsigned long context)
1281 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1282 const struct ni_board_struct *board = NULL;
1283 struct ni_private *devpriv;
1287 if (context < ARRAY_SIZE(ni_boards))
1288 board = &ni_boards[context];
1291 dev->board_ptr = board;
1292 dev->board_name = board->name;
1294 ret = comedi_pci_enable(dev);
1298 ret = ni_alloc_private(dev);
1301 devpriv = dev->private;
1303 devpriv->mite = mite_attach(dev, false); /* use win0 */
1307 if (board->reg_type & ni_reg_m_series_mask)
1308 devpriv->is_m_series = 1;
1309 if (board->reg_type & ni_reg_6xxx_mask)
1310 devpriv->is_6xxx = 1;
1311 if (board->reg_type == ni_reg_611x)
1312 devpriv->is_611x = 1;
1313 if (board->reg_type == ni_reg_6143)
1314 devpriv->is_6143 = 1;
1315 if (board->reg_type == ni_reg_622x)
1316 devpriv->is_622x = 1;
1317 if (board->reg_type == ni_reg_625x)
1318 devpriv->is_625x = 1;
1319 if (board->reg_type == ni_reg_628x)
1320 devpriv->is_628x = 1;
1321 if (board->reg_type & ni_reg_67xx_mask)
1322 devpriv->is_67xx = 1;
1323 if (board->reg_type == ni_reg_6711)
1324 devpriv->is_6711 = 1;
1325 if (board->reg_type == ni_reg_6713)
1326 devpriv->is_6713 = 1;
1328 devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite);
1329 if (!devpriv->ai_mite_ring)
1331 devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite);
1332 if (!devpriv->ao_mite_ring)
1334 devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite);
1335 if (!devpriv->cdo_mite_ring)
1337 devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite);
1338 if (!devpriv->gpct_mite_ring[0])
1340 devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite);
1341 if (!devpriv->gpct_mite_ring[1])
1344 if (devpriv->is_m_series)
1345 m_series_init_eeprom_buffer(dev);
1346 if (devpriv->is_6143)
1351 ret = request_irq(irq, ni_E_interrupt, IRQF_SHARED,
1352 dev->board_name, dev);
1357 ret = ni_E_init(dev, 0, 1);
1361 dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change;
1362 dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change;
1363 dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change;
1364 dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change;
1365 dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change;
1370 static struct comedi_driver ni_pcimio_driver = {
1371 .driver_name = "ni_pcimio",
1372 .module = THIS_MODULE,
1373 .auto_attach = pcimio_auto_attach,
1374 .detach = pcimio_detach,
1377 static int ni_pcimio_pci_probe(struct pci_dev *dev,
1378 const struct pci_device_id *id)
1380 return comedi_pci_auto_config(dev, &ni_pcimio_driver, id->driver_data);
1383 static const struct pci_device_id ni_pcimio_pci_table[] = {
1384 { PCI_VDEVICE(NI, 0x0162), BOARD_PCIMIO_16XE_50 }, /* 0x1620? */
1385 { PCI_VDEVICE(NI, 0x1170), BOARD_PCIMIO_16XE_10 },
1386 { PCI_VDEVICE(NI, 0x1180), BOARD_PCIMIO_16E_1 },
1387 { PCI_VDEVICE(NI, 0x1190), BOARD_PCIMIO_16E_4 },
1388 { PCI_VDEVICE(NI, 0x11b0), BOARD_PXI6070E },
1389 { PCI_VDEVICE(NI, 0x11c0), BOARD_PXI6040E },
1390 { PCI_VDEVICE(NI, 0x11d0), BOARD_PXI6030E },
1391 { PCI_VDEVICE(NI, 0x1270), BOARD_PCI6032E },
1392 { PCI_VDEVICE(NI, 0x1330), BOARD_PCI6031E },
1393 { PCI_VDEVICE(NI, 0x1340), BOARD_PCI6033E },
1394 { PCI_VDEVICE(NI, 0x1350), BOARD_PCI6071E },
1395 { PCI_VDEVICE(NI, 0x14e0), BOARD_PCI6110 },
1396 { PCI_VDEVICE(NI, 0x14f0), BOARD_PCI6111 },
1397 { PCI_VDEVICE(NI, 0x1580), BOARD_PXI6031E },
1398 { PCI_VDEVICE(NI, 0x15b0), BOARD_PXI6071E },
1399 { PCI_VDEVICE(NI, 0x1880), BOARD_PCI6711 },
1400 { PCI_VDEVICE(NI, 0x1870), BOARD_PCI6713 },
1401 { PCI_VDEVICE(NI, 0x18b0), BOARD_PCI6052E },
1402 { PCI_VDEVICE(NI, 0x18c0), BOARD_PXI6052E },
1403 { PCI_VDEVICE(NI, 0x2410), BOARD_PCI6733 },
1404 { PCI_VDEVICE(NI, 0x2420), BOARD_PXI6733 },
1405 { PCI_VDEVICE(NI, 0x2430), BOARD_PCI6731 },
1406 { PCI_VDEVICE(NI, 0x2890), BOARD_PCI6036E },
1407 { PCI_VDEVICE(NI, 0x28c0), BOARD_PCI6014 },
1408 { PCI_VDEVICE(NI, 0x2a60), BOARD_PCI6023E },
1409 { PCI_VDEVICE(NI, 0x2a70), BOARD_PCI6024E },
1410 { PCI_VDEVICE(NI, 0x2a80), BOARD_PCI6025E },
1411 { PCI_VDEVICE(NI, 0x2ab0), BOARD_PXI6025E },
1412 { PCI_VDEVICE(NI, 0x2b80), BOARD_PXI6713 },
1413 { PCI_VDEVICE(NI, 0x2b90), BOARD_PXI6711 },
1414 { PCI_VDEVICE(NI, 0x2c80), BOARD_PCI6035E },
1415 { PCI_VDEVICE(NI, 0x2ca0), BOARD_PCI6034E },
1416 { PCI_VDEVICE(NI, 0x70aa), BOARD_PCI6229 },
1417 { PCI_VDEVICE(NI, 0x70ab), BOARD_PCI6259 },
1418 { PCI_VDEVICE(NI, 0x70ac), BOARD_PCI6289 },
1419 { PCI_VDEVICE(NI, 0x70ad), BOARD_PXI6251 },
1420 { PCI_VDEVICE(NI, 0x70ae), BOARD_PXI6220 },
1421 { PCI_VDEVICE(NI, 0x70af), BOARD_PCI6221 },
1422 { PCI_VDEVICE(NI, 0x70b0), BOARD_PCI6220 },
1423 { PCI_VDEVICE(NI, 0x70b1), BOARD_PXI6229 },
1424 { PCI_VDEVICE(NI, 0x70b2), BOARD_PXI6259 },
1425 { PCI_VDEVICE(NI, 0x70b3), BOARD_PXI6289 },
1426 { PCI_VDEVICE(NI, 0x70b4), BOARD_PCI6250 },
1427 { PCI_VDEVICE(NI, 0x70b5), BOARD_PXI6221 },
1428 { PCI_VDEVICE(NI, 0x70b6), BOARD_PCI6280 },
1429 { PCI_VDEVICE(NI, 0x70b7), BOARD_PCI6254 },
1430 { PCI_VDEVICE(NI, 0x70b8), BOARD_PCI6251 },
1431 { PCI_VDEVICE(NI, 0x70b9), BOARD_PXI6250 },
1432 { PCI_VDEVICE(NI, 0x70ba), BOARD_PXI6254 },
1433 { PCI_VDEVICE(NI, 0x70bb), BOARD_PXI6280 },
1434 { PCI_VDEVICE(NI, 0x70bc), BOARD_PCI6284 },
1435 { PCI_VDEVICE(NI, 0x70bd), BOARD_PCI6281 },
1436 { PCI_VDEVICE(NI, 0x70be), BOARD_PXI6284 },
1437 { PCI_VDEVICE(NI, 0x70bf), BOARD_PXI6281 },
1438 { PCI_VDEVICE(NI, 0x70c0), BOARD_PCI6143 },
1439 { PCI_VDEVICE(NI, 0x70f2), BOARD_PCI6224 },
1440 { PCI_VDEVICE(NI, 0x70f3), BOARD_PXI6224 },
1441 { PCI_VDEVICE(NI, 0x710d), BOARD_PXI6143 },
1442 { PCI_VDEVICE(NI, 0x716c), BOARD_PCI6225 },
1443 { PCI_VDEVICE(NI, 0x716d), BOARD_PXI6225 },
1444 { PCI_VDEVICE(NI, 0x717d), BOARD_PCIE6251 },
1445 { PCI_VDEVICE(NI, 0x717f), BOARD_PCIE6259 },
1446 { PCI_VDEVICE(NI, 0x71bc), BOARD_PCI6221_37PIN },
1447 { PCI_VDEVICE(NI, 0x72e8), BOARD_PXIE6251 },
1448 { PCI_VDEVICE(NI, 0x72e9), BOARD_PXIE6259 },
1451 MODULE_DEVICE_TABLE(pci, ni_pcimio_pci_table);
1453 static struct pci_driver ni_pcimio_pci_driver = {
1454 .name = "ni_pcimio",
1455 .id_table = ni_pcimio_pci_table,
1456 .probe = ni_pcimio_pci_probe,
1457 .remove = comedi_pci_auto_unconfig,
1459 module_comedi_pci_driver(ni_pcimio_driver, ni_pcimio_pci_driver);
1461 MODULE_AUTHOR("Comedi http://www.comedi.org");
1462 MODULE_DESCRIPTION("Comedi low-level driver");
1463 MODULE_LICENSE("GPL");