2 * Comedi driver for National Instruments PCI-DIO-32HS
4 * COMEDI - Linux Control and Measurement Device Interface
5 * Copyright (C) 1999,2002 David A. Schleef <ds@schleef.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
20 * Description: National Instruments PCI-DIO32HS, PCI-6533
23 * Devices: [National Instruments] PCI-DIO-32HS (ni_pcidio)
24 * [National Instruments] PXI-6533, PCI-6533 (pxi-6533)
25 * [National Instruments] PCI-6534 (pci-6534)
26 * Updated: Mon, 09 Jan 2012 14:27:23 +0000
28 * The DIO32HS board appears as one subdevice, with 32 channels. Each
29 * channel is individually I/O configurable. The channel order is 0=A0,
30 * 1=A1, 2=A2, ... 8=B0, 16=C0, 24=D0. The driver only supports simple
31 * digital I/O; no handshaking is supported.
33 * DMA mostly works for the PCI-DIO32HS, but only in timed input mode.
35 * The PCI-DIO-32HS/PCI-6533 has a configurable external trigger. Setting
36 * scan_begin_arg to 0 or CR_EDGE triggers on the leading edge. Setting
37 * scan_begin_arg to CR_INVERT or (CR_EDGE | CR_INVERT) triggers on the
40 * This driver could be easily modified to support AT-MIO32HS and AT-MIO96.
42 * The PCI-6534 requires a firmware upload after power-up to work, the
43 * firmware data and instructions for loading it with comedi_config
44 * it are contained in the comedi_nonfree_firmware tarball available from
45 * http://www.comedi.org
50 #include <linux/module.h>
51 #include <linux/delay.h>
52 #include <linux/interrupt.h>
53 #include <linux/sched.h>
55 #include "../comedi_pci.h"
59 /* defines for the PCI-DIO-32HS */
61 #define Window_Address 4 /* W */
62 #define Interrupt_And_Window_Status 4 /* R */
63 #define IntStatus1 BIT(0)
64 #define IntStatus2 BIT(1)
65 #define WindowAddressStatus_mask 0x7c
67 #define Master_DMA_And_Interrupt_Control 5 /* W */
68 #define InterruptLine(x) ((x)&3)
69 #define OpenInt BIT(2)
70 #define Group_Status 5 /* R */
71 #define DataLeft BIT(0)
73 #define StopTrig BIT(3)
75 #define Group_1_Flags 6 /* R */
76 #define Group_2_Flags 7 /* R */
77 #define TransferReady BIT(0)
78 #define CountExpired BIT(1)
80 #define PrimaryTC BIT(6)
81 #define SecondaryTC BIT(7)
82 /* #define SerialRose */
86 #define Group_1_First_Clear 6 /* W */
87 #define Group_2_First_Clear 7 /* W */
88 #define ClearWaited BIT(3)
89 #define ClearPrimaryTC BIT(4)
90 #define ClearSecondaryTC BIT(5)
91 #define DMAReset BIT(6)
92 #define FIFOReset BIT(7)
95 #define Group_1_FIFO 8 /* W */
96 #define Group_2_FIFO 12 /* W */
98 #define Transfer_Count 20
102 #define Chip_Version 27
103 #define Port_IO(x) (28+(x))
104 #define Port_Pin_Directions(x) (32+(x))
105 #define Port_Pin_Mask(x) (36+(x))
106 #define Port_Pin_Polarities(x) (40+(x))
108 #define Master_Clock_Routing 45
109 #define RTSIClocking(x) (((x)&3)<<4)
111 #define Group_1_Second_Clear 46 /* W */
112 #define Group_2_Second_Clear 47 /* W */
113 #define ClearExpired BIT(0)
115 #define Port_Pattern(x) (48+(x))
118 #define FIFOEnableA BIT(0)
119 #define FIFOEnableB BIT(1)
120 #define FIFOEnableC BIT(2)
121 #define FIFOEnableD BIT(3)
122 #define Funneling(x) (((x)&3)<<4)
123 #define GroupDirection BIT(7)
125 #define Protocol_Register_1 65
126 #define OpMode Protocol_Register_1
127 #define RunMode(x) ((x)&7)
128 #define Numbered BIT(3)
130 #define Protocol_Register_2 66
131 #define ClockReg Protocol_Register_2
132 #define ClockLine(x) (((x)&3)<<5)
133 #define InvertStopTrig BIT(7)
134 #define DataLatching(x) (((x)&3)<<5)
136 #define Protocol_Register_3 67
137 #define Sequence Protocol_Register_3
139 #define Protocol_Register_14 68 /* 16 bit */
140 #define ClockSpeed Protocol_Register_14
142 #define Protocol_Register_4 70
143 #define ReqReg Protocol_Register_4
144 #define ReqConditioning(x) (((x)&7)<<3)
146 #define Protocol_Register_5 71
147 #define BlockMode Protocol_Register_5
149 #define FIFO_Control 72
150 #define ReadyLevel(x) ((x)&7)
152 #define Protocol_Register_6 73
153 #define LinePolarities Protocol_Register_6
154 #define InvertAck BIT(0)
155 #define InvertReq BIT(1)
156 #define InvertClock BIT(2)
157 #define InvertSerial BIT(3)
158 #define OpenAck BIT(4)
159 #define OpenClock BIT(5)
161 #define Protocol_Register_7 74
162 #define AckSer Protocol_Register_7
163 #define AckLine(x) (((x)&3)<<2)
164 #define ExchangePins BIT(7)
166 #define Interrupt_Control 75
167 /* bits same as flags */
169 #define DMA_Line_Control_Group1 76
170 #define DMA_Line_Control_Group2 108
171 /* channel zero is none */
172 static inline unsigned int primary_DMAChannel_bits(unsigned int channel)
174 return channel & 0x3;
177 static inline unsigned int secondary_DMAChannel_bits(unsigned int channel)
179 return (channel << 2) & 0xc;
182 #define Transfer_Size_Control 77
183 #define TransferWidth(x) ((x)&3)
184 #define TransferLength(x) (((x)&3)<<3)
185 #define RequireRLevel BIT(5)
187 #define Protocol_Register_15 79
188 #define DAQOptions Protocol_Register_15
189 #define StartSource(x) ((x)&0x3)
190 #define InvertStart BIT(2)
191 #define StopSource(x) (((x)&0x3)<<3)
192 #define ReqStart BIT(6)
193 #define PreStart BIT(7)
195 #define Pattern_Detection 81
196 #define DetectionMethod BIT(0)
197 #define InvertMatch BIT(1)
198 #define IE_Pattern_Detection BIT(2)
200 #define Protocol_Register_9 82
201 #define ReqDelay Protocol_Register_9
203 #define Protocol_Register_10 83
204 #define ReqNotDelay Protocol_Register_10
206 #define Protocol_Register_11 84
207 #define AckDelay Protocol_Register_11
209 #define Protocol_Register_12 85
210 #define AckNotDelay Protocol_Register_12
212 #define Protocol_Register_13 86
213 #define Data1Delay Protocol_Register_13
215 #define Protocol_Register_8 88 /* 32 bit */
216 #define StartDelay Protocol_Register_8
218 /* Firmware files for PCI-6524 */
219 #define FW_PCI_6534_MAIN "/*(DEBLOBBED)*/"
220 #define FW_PCI_6534_SCARAB_DI "/*(DEBLOBBED)*/"
221 #define FW_PCI_6534_SCARAB_DO "/*(DEBLOBBED)*/"
224 enum pci_6534_firmware_registers { /* 16 bit */
225 Firmware_Control_Register = 0x100,
226 Firmware_Status_Register = 0x104,
227 Firmware_Data_Register = 0x108,
228 Firmware_Mask_Register = 0x10c,
229 Firmware_Debug_Register = 0x110,
231 /* main fpga registers (32 bit)*/
232 enum pci_6534_fpga_registers {
233 FPGA_Control1_Register = 0x200,
234 FPGA_Control2_Register = 0x204,
235 FPGA_Irq_Mask_Register = 0x208,
236 FPGA_Status_Register = 0x20c,
237 FPGA_Signature_Register = 0x210,
238 FPGA_SCALS_Counter_Register = 0x280, /*write-clear */
239 FPGA_SCAMS_Counter_Register = 0x284, /*write-clear */
240 FPGA_SCBLS_Counter_Register = 0x288, /*write-clear */
241 FPGA_SCBMS_Counter_Register = 0x28c, /*write-clear */
242 FPGA_Temp_Control_Register = 0x2a0,
243 FPGA_DAR_Register = 0x2a8,
244 FPGA_ELC_Read_Register = 0x2b8,
245 FPGA_ELC_Write_Register = 0x2bc,
247 enum FPGA_Control_Bits {
248 FPGA_Enable_Bit = 0x8000,
251 #define TIMER_BASE 50 /* nanoseconds */
254 #define IntEn (CountExpired|Waited|PrimaryTC|SecondaryTC)
256 #define IntEn (TransferReady|CountExpired|Waited|PrimaryTC|SecondaryTC)
267 unsigned int uses_firmware:1;
270 static const struct nidio_board nidio_boards[] = {
271 [BOARD_PCIDIO_32HS] = {
272 .name = "pci-dio-32hs",
283 struct nidio96_private {
287 unsigned short OpModeBits;
288 struct mite_channel *di_mite_chan;
289 struct mite_ring *di_mite_ring;
290 spinlock_t mite_channel_lock;
293 static int ni_pcidio_request_di_mite_channel(struct comedi_device *dev)
295 struct nidio96_private *devpriv = dev->private;
298 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
299 BUG_ON(devpriv->di_mite_chan);
300 devpriv->di_mite_chan =
301 mite_request_channel_in_range(devpriv->mite,
302 devpriv->di_mite_ring, 1, 2);
303 if (!devpriv->di_mite_chan) {
304 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
305 dev_err(dev->class_dev, "failed to reserve mite dma channel\n");
308 devpriv->di_mite_chan->dir = COMEDI_INPUT;
309 writeb(primary_DMAChannel_bits(devpriv->di_mite_chan->channel) |
310 secondary_DMAChannel_bits(devpriv->di_mite_chan->channel),
311 dev->mmio + DMA_Line_Control_Group1);
313 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
317 static void ni_pcidio_release_di_mite_channel(struct comedi_device *dev)
319 struct nidio96_private *devpriv = dev->private;
322 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
323 if (devpriv->di_mite_chan) {
324 mite_release_channel(devpriv->di_mite_chan);
325 devpriv->di_mite_chan = NULL;
326 writeb(primary_DMAChannel_bits(0) |
327 secondary_DMAChannel_bits(0),
328 dev->mmio + DMA_Line_Control_Group1);
331 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
334 static int setup_mite_dma(struct comedi_device *dev, struct comedi_subdevice *s)
336 struct nidio96_private *devpriv = dev->private;
340 retval = ni_pcidio_request_di_mite_channel(dev);
344 /* write alloc the entire buffer */
345 comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
347 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
348 if (devpriv->di_mite_chan) {
349 mite_prep_dma(devpriv->di_mite_chan, 32, 32);
350 mite_dma_arm(devpriv->di_mite_chan);
354 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
359 static int ni_pcidio_poll(struct comedi_device *dev, struct comedi_subdevice *s)
361 struct nidio96_private *devpriv = dev->private;
362 unsigned long irq_flags;
365 spin_lock_irqsave(&dev->spinlock, irq_flags);
366 spin_lock(&devpriv->mite_channel_lock);
367 if (devpriv->di_mite_chan)
368 mite_sync_dma(devpriv->di_mite_chan, s);
369 spin_unlock(&devpriv->mite_channel_lock);
370 count = comedi_buf_n_bytes_ready(s);
371 spin_unlock_irqrestore(&dev->spinlock, irq_flags);
375 static irqreturn_t nidio_interrupt(int irq, void *d)
377 struct comedi_device *dev = d;
378 struct nidio96_private *devpriv = dev->private;
379 struct comedi_subdevice *s = dev->read_subdev;
380 struct comedi_async *async = s->async;
381 unsigned int auxdata;
386 /* interrupcions parasites */
387 if (!dev->attached) {
388 /* assume it's from another card */
392 /* Lock to avoid race with comedi_poll */
393 spin_lock(&dev->spinlock);
395 status = readb(dev->mmio + Interrupt_And_Window_Status);
396 flags = readb(dev->mmio + Group_1_Flags);
398 spin_lock(&devpriv->mite_channel_lock);
399 if (devpriv->di_mite_chan) {
400 mite_ack_linkc(devpriv->di_mite_chan, s, false);
401 /* XXX need to byteswap sync'ed dma */
403 spin_unlock(&devpriv->mite_channel_lock);
405 while (status & DataLeft) {
408 dev_dbg(dev->class_dev, "too much work in interrupt\n");
410 dev->mmio + Master_DMA_And_Interrupt_Control);
416 if (flags & TransferReady) {
417 while (flags & TransferReady) {
420 dev_dbg(dev->class_dev,
421 "too much work in interrupt\n");
422 writeb(0x00, dev->mmio +
423 Master_DMA_And_Interrupt_Control
427 auxdata = readl(dev->mmio + Group_1_FIFO);
428 comedi_buf_write_samples(s, &auxdata, 1);
429 flags = readb(dev->mmio + Group_1_Flags);
433 if (flags & CountExpired) {
434 writeb(ClearExpired, dev->mmio + Group_1_Second_Clear);
435 async->events |= COMEDI_CB_EOA;
437 writeb(0x00, dev->mmio + OpMode);
439 } else if (flags & Waited) {
440 writeb(ClearWaited, dev->mmio + Group_1_First_Clear);
441 async->events |= COMEDI_CB_ERROR;
443 } else if (flags & PrimaryTC) {
444 writeb(ClearPrimaryTC,
445 dev->mmio + Group_1_First_Clear);
446 async->events |= COMEDI_CB_EOA;
447 } else if (flags & SecondaryTC) {
448 writeb(ClearSecondaryTC,
449 dev->mmio + Group_1_First_Clear);
450 async->events |= COMEDI_CB_EOA;
453 flags = readb(dev->mmio + Group_1_Flags);
454 status = readb(dev->mmio + Interrupt_And_Window_Status);
458 comedi_handle_events(dev, s);
461 writeb(0x03, dev->mmio + Master_DMA_And_Interrupt_Control);
464 spin_unlock(&dev->spinlock);
468 static int ni_pcidio_insn_config(struct comedi_device *dev,
469 struct comedi_subdevice *s,
470 struct comedi_insn *insn,
475 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
479 writel(s->io_bits, dev->mmio + Port_Pin_Directions(0));
484 static int ni_pcidio_insn_bits(struct comedi_device *dev,
485 struct comedi_subdevice *s,
486 struct comedi_insn *insn,
489 if (comedi_dio_update_state(s, data))
490 writel(s->state, dev->mmio + Port_IO(0));
492 data[1] = readl(dev->mmio + Port_IO(0));
497 static int ni_pcidio_ns_to_timer(int *nanosec, unsigned int flags)
503 switch (flags & CMDF_ROUND_MASK) {
504 case CMDF_ROUND_NEAREST:
506 divider = DIV_ROUND_CLOSEST(*nanosec, base);
508 case CMDF_ROUND_DOWN:
509 divider = (*nanosec) / base;
512 divider = DIV_ROUND_UP(*nanosec, base);
516 *nanosec = base * divider;
520 static int ni_pcidio_cmdtest(struct comedi_device *dev,
521 struct comedi_subdevice *s, struct comedi_cmd *cmd)
526 /* Step 1 : check if triggers are trivially valid */
528 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
529 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
530 TRIG_TIMER | TRIG_EXT);
531 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
532 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
533 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
538 /* Step 2a : make sure trigger sources are unique */
540 err |= comedi_check_trigger_is_unique(cmd->start_src);
541 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
542 err |= comedi_check_trigger_is_unique(cmd->stop_src);
544 /* Step 2b : and mutually compatible */
549 /* Step 3: check if arguments are trivially valid */
551 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
553 #define MAX_SPEED (TIMER_BASE) /* in nanoseconds */
555 if (cmd->scan_begin_src == TRIG_TIMER) {
556 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
558 /* no minimum speed */
561 /* should be level/edge, hi/lo specification here */
562 if ((cmd->scan_begin_arg & ~(CR_EDGE | CR_INVERT)) != 0) {
563 cmd->scan_begin_arg &= (CR_EDGE | CR_INVERT);
568 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
569 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
572 if (cmd->stop_src == TRIG_COUNT)
573 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
575 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
580 /* step 4: fix up any arguments */
582 if (cmd->scan_begin_src == TRIG_TIMER) {
583 arg = cmd->scan_begin_arg;
584 ni_pcidio_ns_to_timer(&arg, cmd->flags);
585 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
594 static int ni_pcidio_inttrig(struct comedi_device *dev,
595 struct comedi_subdevice *s,
596 unsigned int trig_num)
598 struct nidio96_private *devpriv = dev->private;
599 struct comedi_cmd *cmd = &s->async->cmd;
601 if (trig_num != cmd->start_arg)
604 writeb(devpriv->OpModeBits, dev->mmio + OpMode);
605 s->async->inttrig = NULL;
610 static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
612 struct nidio96_private *devpriv = dev->private;
613 struct comedi_cmd *cmd = &s->async->cmd;
615 /* XXX configure ports for input */
616 writel(0x0000, dev->mmio + Port_Pin_Directions(0));
619 /* enable fifos A B C D */
620 writeb(0x0f, dev->mmio + Data_Path);
622 /* set transfer width a 32 bits */
623 writeb(TransferWidth(0) | TransferLength(0),
624 dev->mmio + Transfer_Size_Control);
626 writeb(0x03, dev->mmio + Data_Path);
627 writeb(TransferWidth(3) | TransferLength(0),
628 dev->mmio + Transfer_Size_Control);
631 /* protocol configuration */
632 if (cmd->scan_begin_src == TRIG_TIMER) {
633 /* page 4-5, "input with internal REQs" */
634 writeb(0, dev->mmio + OpMode);
635 writeb(0x00, dev->mmio + ClockReg);
636 writeb(1, dev->mmio + Sequence);
637 writeb(0x04, dev->mmio + ReqReg);
638 writeb(4, dev->mmio + BlockMode);
639 writeb(3, dev->mmio + LinePolarities);
640 writeb(0xc0, dev->mmio + AckSer);
641 writel(ni_pcidio_ns_to_timer(&cmd->scan_begin_arg,
643 dev->mmio + StartDelay);
644 writeb(1, dev->mmio + ReqDelay);
645 writeb(1, dev->mmio + ReqNotDelay);
646 writeb(1, dev->mmio + AckDelay);
647 writeb(0x0b, dev->mmio + AckNotDelay);
648 writeb(0x01, dev->mmio + Data1Delay);
651 * ClockSpeed comment is incorrectly listed on DAQOptions
653 writew(0, dev->mmio + ClockSpeed);
654 writeb(0, dev->mmio + DAQOptions);
657 /* page 4-5, "input with external REQs" */
658 writeb(0, dev->mmio + OpMode);
659 writeb(0x00, dev->mmio + ClockReg);
660 writeb(0, dev->mmio + Sequence);
661 writeb(0x00, dev->mmio + ReqReg);
662 writeb(4, dev->mmio + BlockMode);
663 if (!(cmd->scan_begin_arg & CR_INVERT)) /* Leading Edge */
664 writeb(0, dev->mmio + LinePolarities);
665 else /* Trailing Edge */
666 writeb(2, dev->mmio + LinePolarities);
667 writeb(0x00, dev->mmio + AckSer);
668 writel(1, dev->mmio + StartDelay);
669 writeb(1, dev->mmio + ReqDelay);
670 writeb(1, dev->mmio + ReqNotDelay);
671 writeb(1, dev->mmio + AckDelay);
672 writeb(0x0C, dev->mmio + AckNotDelay);
673 writeb(0x10, dev->mmio + Data1Delay);
674 writew(0, dev->mmio + ClockSpeed);
675 writeb(0x60, dev->mmio + DAQOptions);
678 if (cmd->stop_src == TRIG_COUNT) {
679 writel(cmd->stop_arg,
680 dev->mmio + Transfer_Count);
686 writeb(ClearPrimaryTC | ClearSecondaryTC,
687 dev->mmio + Group_1_First_Clear);
690 int retval = setup_mite_dma(dev, s);
696 writeb(0x00, dev->mmio + DMA_Line_Control_Group1);
698 writeb(0x00, dev->mmio + DMA_Line_Control_Group2);
700 /* clear and enable interrupts */
701 writeb(0xff, dev->mmio + Group_1_First_Clear);
702 /* writeb(ClearExpired, dev->mmio+Group_1_Second_Clear); */
704 writeb(IntEn, dev->mmio + Interrupt_Control);
705 writeb(0x03, dev->mmio + Master_DMA_And_Interrupt_Control);
707 if (cmd->stop_src == TRIG_NONE) {
708 devpriv->OpModeBits = DataLatching(0) | RunMode(7);
709 } else { /* TRIG_TIMER */
710 devpriv->OpModeBits = Numbered | RunMode(7);
712 if (cmd->start_src == TRIG_NOW) {
714 writeb(devpriv->OpModeBits, dev->mmio + OpMode);
715 s->async->inttrig = NULL;
718 s->async->inttrig = ni_pcidio_inttrig;
724 static int ni_pcidio_cancel(struct comedi_device *dev,
725 struct comedi_subdevice *s)
727 writeb(0x00, dev->mmio + Master_DMA_And_Interrupt_Control);
728 ni_pcidio_release_di_mite_channel(dev);
733 static int ni_pcidio_change(struct comedi_device *dev,
734 struct comedi_subdevice *s)
736 struct nidio96_private *devpriv = dev->private;
739 ret = mite_buf_change(devpriv->di_mite_ring, s);
743 memset(s->async->prealloc_buf, 0xaa, s->async->prealloc_bufsz);
748 static int pci_6534_load_fpga(struct comedi_device *dev,
749 const u8 *data, size_t data_len,
750 unsigned long context)
752 static const int timeout = 1000;
753 int fpga_index = context;
757 writew(0x80 | fpga_index, dev->mmio + Firmware_Control_Register);
758 writew(0xc0 | fpga_index, dev->mmio + Firmware_Control_Register);
760 (readw(dev->mmio + Firmware_Status_Register) & 0x2) == 0 &&
765 dev_warn(dev->class_dev,
766 "ni_pcidio: failed to load fpga %i, waiting for status 0x2\n",
770 writew(0x80 | fpga_index, dev->mmio + Firmware_Control_Register);
772 readw(dev->mmio + Firmware_Status_Register) != 0x3 &&
777 dev_warn(dev->class_dev,
778 "ni_pcidio: failed to load fpga %i, waiting for status 0x3\n",
782 for (j = 0; j + 1 < data_len;) {
783 unsigned int value = data[j++];
785 value |= data[j++] << 8;
786 writew(value, dev->mmio + Firmware_Data_Register);
788 (readw(dev->mmio + Firmware_Status_Register) & 0x2) == 0
789 && i < timeout; ++i) {
793 dev_warn(dev->class_dev,
794 "ni_pcidio: failed to load word into fpga %i\n",
801 writew(0x0, dev->mmio + Firmware_Control_Register);
805 static int pci_6534_reset_fpga(struct comedi_device *dev, int fpga_index)
807 return pci_6534_load_fpga(dev, NULL, 0, fpga_index);
810 static int pci_6534_reset_fpgas(struct comedi_device *dev)
815 writew(0x0, dev->mmio + Firmware_Control_Register);
816 for (i = 0; i < 3; ++i) {
817 ret = pci_6534_reset_fpga(dev, i);
821 writew(0x0, dev->mmio + Firmware_Mask_Register);
825 static void pci_6534_init_main_fpga(struct comedi_device *dev)
827 writel(0, dev->mmio + FPGA_Control1_Register);
828 writel(0, dev->mmio + FPGA_Control2_Register);
829 writel(0, dev->mmio + FPGA_SCALS_Counter_Register);
830 writel(0, dev->mmio + FPGA_SCAMS_Counter_Register);
831 writel(0, dev->mmio + FPGA_SCBLS_Counter_Register);
832 writel(0, dev->mmio + FPGA_SCBMS_Counter_Register);
835 static int pci_6534_upload_firmware(struct comedi_device *dev)
837 struct nidio96_private *devpriv = dev->private;
838 static const char *const fw_file[3] = {
839 FW_PCI_6534_SCARAB_DI, /* loaded into scarab A for DI */
840 FW_PCI_6534_SCARAB_DO, /* loaded into scarab B for DO */
841 FW_PCI_6534_MAIN, /* loaded into main FPGA */
846 ret = pci_6534_reset_fpgas(dev);
849 /* load main FPGA first, then the two scarabs */
850 for (n = 2; n >= 0; n--) {
851 ret = comedi_load_firmware(dev, &devpriv->mite->pcidev->dev,
853 pci_6534_load_fpga, n);
854 if (ret == 0 && n == 2)
855 pci_6534_init_main_fpga(dev);
862 static void nidio_reset_board(struct comedi_device *dev)
864 writel(0, dev->mmio + Port_IO(0));
865 writel(0, dev->mmio + Port_Pin_Directions(0));
866 writel(0, dev->mmio + Port_Pin_Mask(0));
868 /* disable interrupts on board */
869 writeb(0, dev->mmio + Master_DMA_And_Interrupt_Control);
872 static int nidio_auto_attach(struct comedi_device *dev,
873 unsigned long context)
875 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
876 const struct nidio_board *board = NULL;
877 struct nidio96_private *devpriv;
878 struct comedi_subdevice *s;
882 if (context < ARRAY_SIZE(nidio_boards))
883 board = &nidio_boards[context];
886 dev->board_ptr = board;
887 dev->board_name = board->name;
889 ret = comedi_pci_enable(dev);
893 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
897 spin_lock_init(&devpriv->mite_channel_lock);
899 devpriv->mite = mite_attach(dev, false); /* use win0 */
903 devpriv->di_mite_ring = mite_alloc_ring(devpriv->mite);
904 if (!devpriv->di_mite_ring)
907 if (board->uses_firmware) {
908 ret = pci_6534_upload_firmware(dev);
913 nidio_reset_board(dev);
915 ret = comedi_alloc_subdevices(dev, 1);
919 dev_info(dev->class_dev, "%s rev=%d\n", dev->board_name,
920 readb(dev->mmio + Chip_Version));
922 s = &dev->subdevices[0];
924 dev->read_subdev = s;
925 s->type = COMEDI_SUBD_DIO;
927 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_PACKED |
930 s->range_table = &range_digital;
932 s->insn_config = &ni_pcidio_insn_config;
933 s->insn_bits = &ni_pcidio_insn_bits;
934 s->do_cmd = &ni_pcidio_cmd;
935 s->do_cmdtest = &ni_pcidio_cmdtest;
936 s->cancel = &ni_pcidio_cancel;
937 s->len_chanlist = 32; /* XXX */
938 s->buf_change = &ni_pcidio_change;
939 s->async_dma_dir = DMA_BIDIRECTIONAL;
940 s->poll = &ni_pcidio_poll;
944 ret = request_irq(irq, nidio_interrupt, IRQF_SHARED,
945 dev->board_name, dev);
953 static void nidio_detach(struct comedi_device *dev)
955 struct nidio96_private *devpriv = dev->private;
958 free_irq(dev->irq, dev);
960 if (devpriv->di_mite_ring) {
961 mite_free_ring(devpriv->di_mite_ring);
962 devpriv->di_mite_ring = NULL;
964 mite_detach(devpriv->mite);
968 comedi_pci_disable(dev);
971 static struct comedi_driver ni_pcidio_driver = {
972 .driver_name = "ni_pcidio",
973 .module = THIS_MODULE,
974 .auto_attach = nidio_auto_attach,
975 .detach = nidio_detach,
978 static int ni_pcidio_pci_probe(struct pci_dev *dev,
979 const struct pci_device_id *id)
981 return comedi_pci_auto_config(dev, &ni_pcidio_driver, id->driver_data);
984 static const struct pci_device_id ni_pcidio_pci_table[] = {
985 { PCI_VDEVICE(NI, 0x1150), BOARD_PCIDIO_32HS },
986 { PCI_VDEVICE(NI, 0x12b0), BOARD_PCI6534 },
987 { PCI_VDEVICE(NI, 0x1320), BOARD_PXI6533 },
990 MODULE_DEVICE_TABLE(pci, ni_pcidio_pci_table);
992 static struct pci_driver ni_pcidio_pci_driver = {
994 .id_table = ni_pcidio_pci_table,
995 .probe = ni_pcidio_pci_probe,
996 .remove = comedi_pci_auto_unconfig,
998 module_comedi_pci_driver(ni_pcidio_driver, ni_pcidio_pci_driver);
1000 MODULE_AUTHOR("Comedi http://www.comedi.org");
1001 MODULE_DESCRIPTION("Comedi low-level driver");
1002 MODULE_LICENSE("GPL");