drivers/staging/comedi/drivers/ni_pcidio.c

   1 /*
   2     comedi/drivers/ni_pcidio.c
   3     driver for National Instruments PCI-DIO-32HS
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1999,2002 David A. Schleef <ds@schleef.org>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17 */
  18 /*
  19 Driver: ni_pcidio
  20 Description: National Instruments PCI-DIO32HS, PCI-6533
  21 Author: ds
  22 Status: works
  23 Devices: [National Instruments] PCI-DIO-32HS (ni_pcidio)
  24          [National Instruments] PXI-6533, PCI-6533 (pxi-6533)
  25          [National Instruments] PCI-6534 (pci-6534)
  26 Updated: Mon, 09 Jan 2012 14:27:23 +0000
  27
  28 The DIO32HS board appears as one subdevice, with 32 channels.
  29 Each channel is individually I/O configurable.  The channel order
  30 is 0=A0, 1=A1, 2=A2, ... 8=B0, 16=C0, 24=D0.  The driver only
  31 supports simple digital I/O; no handshaking is supported.
  32
  33 DMA mostly works for the PCI-DIO32HS, but only in timed input mode.
  34
  35 The PCI-DIO-32HS/PCI-6533 has a configurable external trigger. Setting
  36 scan_begin_arg to 0 or CR_EDGE triggers on the leading edge. Setting
  37 scan_begin_arg to CR_INVERT or (CR_EDGE | CR_INVERT) triggers on the
  38 trailing edge.
  39
  40 This driver could be easily modified to support AT-MIO32HS and
  41 AT-MIO96.
  42
  43 The PCI-6534 requires a firmware upload after power-up to work, the
  44 firmware data and instructions for loading it with comedi_config
  45 it are contained in the
  46 comedi_nonfree_firmware tarball available from http://www.comedi.org
  47 */
  48
  49 #define USE_DMA
  50
  51 #include <linux/module.h>
  52 #include <linux/delay.h>
  53 #include <linux/interrupt.h>
  54 #include <linux/sched.h>
  55
  56 #include "../comedi_pci.h"
  57
  58 #include "mite.h"
  59
  60 /* defines for the PCI-DIO-32HS */
  61
  62 #define Window_Address                  4       /* W */
  63 #define Interrupt_And_Window_Status     4       /* R */
  64 #define IntStatus1                              (1<<0)
  65 #define IntStatus2                              (1<<1)
  66 #define WindowAddressStatus_mask                0x7c
  67
  68 #define Master_DMA_And_Interrupt_Control 5      /* W */
  69 #define InterruptLine(x)                        ((x)&3)
  70 #define OpenInt                         (1<<2)
  71 #define Group_Status                    5       /* R */
  72 #define DataLeft                                (1<<0)
  73 #define Req                                     (1<<2)
  74 #define StopTrig                                (1<<3)
  75
  76 #define Group_1_Flags                   6       /* R */
  77 #define Group_2_Flags                   7       /* R */
  78 #define TransferReady                           (1<<0)
  79 #define CountExpired                            (1<<1)
  80 #define Waited                          (1<<5)
  81 #define PrimaryTC                               (1<<6)
  82 #define SecondaryTC                             (1<<7)
  83   /* #define SerialRose */
  84   /* #define ReqRose */
  85   /* #define Paused */
  86
  87 #define Group_1_First_Clear             6       /* W */
  88 #define Group_2_First_Clear             7       /* W */
  89 #define ClearWaited                             (1<<3)
  90 #define ClearPrimaryTC                  (1<<4)
  91 #define ClearSecondaryTC                        (1<<5)
  92 #define DMAReset                                (1<<6)
  93 #define FIFOReset                               (1<<7)
  94 #define ClearAll                                0xf8
  95
  96 #define Group_1_FIFO                    8       /* W */
  97 #define Group_2_FIFO                    12      /* W */
  98
  99 #define Transfer_Count                  20
 100 #define Chip_ID_D                       24
 101 #define Chip_ID_I                       25
 102 #define Chip_ID_O                       26
 103 #define Chip_Version                    27
 104 #define Port_IO(x)                      (28+(x))
 105 #define Port_Pin_Directions(x)          (32+(x))
 106 #define Port_Pin_Mask(x)                (36+(x))
 107 #define Port_Pin_Polarities(x)          (40+(x))
 108
 109 #define Master_Clock_Routing            45
 110 #define RTSIClocking(x)                 (((x)&3)<<4)
 111
 112 #define Group_1_Second_Clear            46      /* W */
 113 #define Group_2_Second_Clear            47      /* W */
 114 #define ClearExpired                            (1<<0)
 115
 116 #define Port_Pattern(x)                 (48+(x))
 117
 118 #define Data_Path                       64
 119 #define FIFOEnableA             (1<<0)
 120 #define FIFOEnableB             (1<<1)
 121 #define FIFOEnableC             (1<<2)
 122 #define FIFOEnableD             (1<<3)
 123 #define Funneling(x)            (((x)&3)<<4)
 124 #define GroupDirection  (1<<7)
 125
 126 #define Protocol_Register_1             65
 127 #define OpMode                          Protocol_Register_1
 128 #define RunMode(x)              ((x)&7)
 129 #define Numbered                (1<<3)
 130
 131 #define Protocol_Register_2             66
 132 #define ClockReg                        Protocol_Register_2
 133 #define ClockLine(x)            (((x)&3)<<5)
 134 #define InvertStopTrig  (1<<7)
 135 #define DataLatching(x)       (((x)&3)<<5)
 136
 137 #define Protocol_Register_3             67
 138 #define Sequence                        Protocol_Register_3
 139
 140 #define Protocol_Register_14            68      /* 16 bit */
 141 #define ClockSpeed                      Protocol_Register_14
 142
 143 #define Protocol_Register_4             70
 144 #define ReqReg                          Protocol_Register_4
 145 #define ReqConditioning(x)      (((x)&7)<<3)
 146
 147 #define Protocol_Register_5             71
 148 #define BlockMode                       Protocol_Register_5
 149
 150 #define FIFO_Control                    72
 151 #define ReadyLevel(x)           ((x)&7)
 152
 153 #define Protocol_Register_6             73
 154 #define LinePolarities                  Protocol_Register_6
 155 #define InvertAck               (1<<0)
 156 #define InvertReq               (1<<1)
 157 #define InvertClock             (1<<2)
 158 #define InvertSerial            (1<<3)
 159 #define OpenAck         (1<<4)
 160 #define OpenClock               (1<<5)
 161
 162 #define Protocol_Register_7             74
 163 #define AckSer                          Protocol_Register_7
 164 #define AckLine(x)              (((x)&3)<<2)
 165 #define ExchangePins            (1<<7)
 166
 167 #define Interrupt_Control               75
 168   /* bits same as flags */
 169
 170 #define DMA_Line_Control_Group1         76
 171 #define DMA_Line_Control_Group2         108
 172 /* channel zero is none */
 173 static inline unsigned primary_DMAChannel_bits(unsigned channel)
 174 {
 175         return channel & 0x3;
 176 }
 177
 178 static inline unsigned secondary_DMAChannel_bits(unsigned channel)
 179 {
 180         return (channel << 2) & 0xc;
 181 }
 182
 183 #define Transfer_Size_Control           77
 184 #define TransferWidth(x)        ((x)&3)
 185 #define TransferLength(x)       (((x)&3)<<3)
 186 #define RequireRLevel           (1<<5)
 187
 188 #define Protocol_Register_15            79
 189 #define DAQOptions                      Protocol_Register_15
 190 #define StartSource(x)                  ((x)&0x3)
 191 #define InvertStart                             (1<<2)
 192 #define StopSource(x)                           (((x)&0x3)<<3)
 193 #define ReqStart                                (1<<6)
 194 #define PreStart                                (1<<7)
 195
 196 #define Pattern_Detection               81
 197 #define DetectionMethod                 (1<<0)
 198 #define InvertMatch                             (1<<1)
 199 #define IE_Pattern_Detection                    (1<<2)
 200
 201 #define Protocol_Register_9             82
 202 #define ReqDelay                        Protocol_Register_9
 203
 204 #define Protocol_Register_10            83
 205 #define ReqNotDelay                     Protocol_Register_10
 206
 207 #define Protocol_Register_11            84
 208 #define AckDelay                        Protocol_Register_11
 209
 210 #define Protocol_Register_12            85
 211 #define AckNotDelay                     Protocol_Register_12
 212
 213 #define Protocol_Register_13            86
 214 #define Data1Delay                      Protocol_Register_13
 215
 216 #define Protocol_Register_8             88      /* 32 bit */
 217 #define StartDelay                      Protocol_Register_8
 218
 219 /* Firmware files for PCI-6524 */
 220 #define FW_PCI_6534_MAIN                "/*(DEBLOBBED)*/"
 221 #define FW_PCI_6534_SCARAB_DI           "/*(DEBLOBBED)*/"
 222 #define FW_PCI_6534_SCARAB_DO           "/*(DEBLOBBED)*/"
 223 /*(DEBLOBBED)*/
 224
 225 enum pci_6534_firmware_registers {      /* 16 bit */
 226         Firmware_Control_Register = 0x100,
 227         Firmware_Status_Register = 0x104,
 228         Firmware_Data_Register = 0x108,
 229         Firmware_Mask_Register = 0x10c,
 230         Firmware_Debug_Register = 0x110,
 231 };
 232 /* main fpga registers (32 bit)*/
 233 enum pci_6534_fpga_registers {
 234         FPGA_Control1_Register = 0x200,
 235         FPGA_Control2_Register = 0x204,
 236         FPGA_Irq_Mask_Register = 0x208,
 237         FPGA_Status_Register = 0x20c,
 238         FPGA_Signature_Register = 0x210,
 239         FPGA_SCALS_Counter_Register = 0x280,    /*write-clear */
 240         FPGA_SCAMS_Counter_Register = 0x284,    /*write-clear */
 241         FPGA_SCBLS_Counter_Register = 0x288,    /*write-clear */
 242         FPGA_SCBMS_Counter_Register = 0x28c,    /*write-clear */
 243         FPGA_Temp_Control_Register = 0x2a0,
 244         FPGA_DAR_Register = 0x2a8,
 245         FPGA_ELC_Read_Register = 0x2b8,
 246         FPGA_ELC_Write_Register = 0x2bc,
 247 };
 248 enum FPGA_Control_Bits {
 249         FPGA_Enable_Bit = 0x8000,
 250 };
 251
 252 #define TIMER_BASE 50           /* nanoseconds */
 253
 254 #ifdef USE_DMA
 255 #define IntEn (CountExpired|Waited|PrimaryTC|SecondaryTC)
 256 #else
 257 #define IntEn (TransferReady|CountExpired|Waited|PrimaryTC|SecondaryTC)
 258 #endif
 259
 260 enum nidio_boardid {
 261         BOARD_PCIDIO_32HS,
 262         BOARD_PXI6533,
 263         BOARD_PCI6534,
 264 };
 265
 266 struct nidio_board {
 267         const char *name;
 268         unsigned int uses_firmware:1;
 269 };
 270
 271 static const struct nidio_board nidio_boards[] = {
 272         [BOARD_PCIDIO_32HS] = {
 273                 .name           = "pci-dio-32hs",
 274         },
 275         [BOARD_PXI6533] = {
 276                 .name           = "pxi-6533",
 277         },
 278         [BOARD_PCI6534] = {
 279                 .name           = "pci-6534",
 280                 .uses_firmware  = 1,
 281         },
 282 };
 283
 284 struct nidio96_private {
 285         struct mite_struct *mite;
 286         int boardtype;
 287         int dio;
 288         unsigned short OpModeBits;
 289         struct mite_channel *di_mite_chan;
 290         struct mite_dma_descriptor_ring *di_mite_ring;
 291         spinlock_t mite_channel_lock;
 292 };
 293
 294 static int ni_pcidio_request_di_mite_channel(struct comedi_device *dev)
 295 {
 296         struct nidio96_private *devpriv = dev->private;
 297         unsigned long flags;
 298
 299         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 300         BUG_ON(devpriv->di_mite_chan);
 301         devpriv->di_mite_chan =
 302             mite_request_channel_in_range(devpriv->mite,
 303                                           devpriv->di_mite_ring, 1, 2);
 304         if (!devpriv->di_mite_chan) {
 305                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 306                 dev_err(dev->class_dev, "failed to reserve mite dma channel\n");
 307                 return -EBUSY;
 308         }
 309         devpriv->di_mite_chan->dir = COMEDI_INPUT;
 310         writeb(primary_DMAChannel_bits(devpriv->di_mite_chan->channel) |
 311                secondary_DMAChannel_bits(devpriv->di_mite_chan->channel),
 312                dev->mmio + DMA_Line_Control_Group1);
 313         mmiowb();
 314         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 315         return 0;
 316 }
 317
 318 static void ni_pcidio_release_di_mite_channel(struct comedi_device *dev)
 319 {
 320         struct nidio96_private *devpriv = dev->private;
 321         unsigned long flags;
 322
 323         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 324         if (devpriv->di_mite_chan) {
 325                 mite_dma_disarm(devpriv->di_mite_chan);
 326                 mite_dma_reset(devpriv->di_mite_chan);
 327                 mite_release_channel(devpriv->di_mite_chan);
 328                 devpriv->di_mite_chan = NULL;
 329                 writeb(primary_DMAChannel_bits(0) |
 330                        secondary_DMAChannel_bits(0),
 331                        dev->mmio + DMA_Line_Control_Group1);
 332                 mmiowb();
 333         }
 334         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 335 }
 336
 337 static int setup_mite_dma(struct comedi_device *dev, struct comedi_subdevice *s)
 338 {
 339         struct nidio96_private *devpriv = dev->private;
 340         int retval;
 341         unsigned long flags;
 342
 343         retval = ni_pcidio_request_di_mite_channel(dev);
 344         if (retval)
 345                 return retval;
 346
 347         /* write alloc the entire buffer */
 348         comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
 349
 350         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 351         if (devpriv->di_mite_chan) {
 352                 mite_prep_dma(devpriv->di_mite_chan, 32, 32);
 353                 mite_dma_arm(devpriv->di_mite_chan);
 354         } else {
 355                 retval = -EIO;
 356         }
 357         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 358
 359         return retval;
 360 }
 361
 362 static int ni_pcidio_poll(struct comedi_device *dev, struct comedi_subdevice *s)
 363 {
 364         struct nidio96_private *devpriv = dev->private;
 365         unsigned long irq_flags;
 366         int count;
 367
 368         spin_lock_irqsave(&dev->spinlock, irq_flags);
 369         spin_lock(&devpriv->mite_channel_lock);
 370         if (devpriv->di_mite_chan)
 371                 mite_sync_input_dma(devpriv->di_mite_chan, s);
 372         spin_unlock(&devpriv->mite_channel_lock);
 373         count = comedi_buf_n_bytes_ready(s);
 374         spin_unlock_irqrestore(&dev->spinlock, irq_flags);
 375         return count;
 376 }
 377
 378 static irqreturn_t nidio_interrupt(int irq, void *d)
 379 {
 380         struct comedi_device *dev = d;
 381         struct nidio96_private *devpriv = dev->private;
 382         struct comedi_subdevice *s = dev->read_subdev;
 383         struct comedi_async *async = s->async;
 384         struct mite_struct *mite = devpriv->mite;
 385         unsigned int auxdata;
 386         int flags;
 387         int status;
 388         int work = 0;
 389         unsigned int m_status = 0;
 390
 391         /* interrupcions parasites */
 392         if (!dev->attached) {
 393                 /* assume it's from another card */
 394                 return IRQ_NONE;
 395         }
 396
 397         /* Lock to avoid race with comedi_poll */
 398         spin_lock(&dev->spinlock);
 399
 400         status = readb(dev->mmio + Interrupt_And_Window_Status);
 401         flags = readb(dev->mmio + Group_1_Flags);
 402
 403         spin_lock(&devpriv->mite_channel_lock);
 404         if (devpriv->di_mite_chan)
 405                 m_status = mite_get_status(devpriv->di_mite_chan);
 406
 407         if (m_status & CHSR_INT) {
 408                 if (m_status & CHSR_LINKC) {
 409                         writel(CHOR_CLRLC,
 410                                mite->mite_io_addr +
 411                                MITE_CHOR(devpriv->di_mite_chan->channel));
 412                         mite_sync_input_dma(devpriv->di_mite_chan, s);
 413                         /* XXX need to byteswap */
 414                 }
 415                 if (m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_DRDY |
 416                                  CHSR_DRQ1 | CHSR_MRDY)) {
 417                         dev_dbg(dev->class_dev,
 418                                 "unknown mite interrupt, disabling IRQ\n");
 419                         async->events |= COMEDI_CB_ERROR;
 420                         disable_irq(dev->irq);
 421                 }
 422         }
 423         spin_unlock(&devpriv->mite_channel_lock);
 424
 425         while (status & DataLeft) {
 426                 work++;
 427                 if (work > 20) {
 428                         dev_dbg(dev->class_dev, "too much work in interrupt\n");
 429                         writeb(0x00,
 430                                dev->mmio + Master_DMA_And_Interrupt_Control);
 431                         break;
 432                 }
 433
 434                 flags &= IntEn;
 435
 436                 if (flags & TransferReady) {
 437                         while (flags & TransferReady) {
 438                                 work++;
 439                                 if (work > 100) {
 440                                         dev_dbg(dev->class_dev,
 441                                                 "too much work in interrupt\n");
 442                                         writeb(0x00, dev->mmio +
 443                                                Master_DMA_And_Interrupt_Control
 444                                               );
 445                                         goto out;
 446                                 }
 447                                 auxdata = readl(dev->mmio + Group_1_FIFO);
 448                                 comedi_buf_write_samples(s, &auxdata, 1);
 449                                 flags = readb(dev->mmio + Group_1_Flags);
 450                         }
 451                 }
 452
 453                 if (flags & CountExpired) {
 454                         writeb(ClearExpired, dev->mmio + Group_1_Second_Clear);
 455                         async->events |= COMEDI_CB_EOA;
 456
 457                         writeb(0x00, dev->mmio + OpMode);
 458                         break;
 459                 } else if (flags & Waited) {
 460                         writeb(ClearWaited, dev->mmio + Group_1_First_Clear);
 461                         async->events |= COMEDI_CB_ERROR;
 462                         break;
 463                 } else if (flags & PrimaryTC) {
 464                         writeb(ClearPrimaryTC,
 465                                dev->mmio + Group_1_First_Clear);
 466                         async->events |= COMEDI_CB_EOA;
 467                 } else if (flags & SecondaryTC) {
 468                         writeb(ClearSecondaryTC,
 469                                dev->mmio + Group_1_First_Clear);
 470                         async->events |= COMEDI_CB_EOA;
 471                 }
 472
 473                 flags = readb(dev->mmio + Group_1_Flags);
 474                 status = readb(dev->mmio + Interrupt_And_Window_Status);
 475         }
 476
 477 out:
 478         comedi_handle_events(dev, s);
 479 #if 0
 480         if (!tag)
 481                 writeb(0x03, dev->mmio + Master_DMA_And_Interrupt_Control);
 482 #endif
 483
 484         spin_unlock(&dev->spinlock);
 485         return IRQ_HANDLED;
 486 }
 487
 488 static int ni_pcidio_insn_config(struct comedi_device *dev,
 489                                  struct comedi_subdevice *s,
 490                                  struct comedi_insn *insn,
 491                                  unsigned int *data)
 492 {
 493         int ret;
 494
 495         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
 496         if (ret)
 497                 return ret;
 498
 499         writel(s->io_bits, dev->mmio + Port_Pin_Directions(0));
 500
 501         return insn->n;
 502 }
 503
 504 static int ni_pcidio_insn_bits(struct comedi_device *dev,
 505                                struct comedi_subdevice *s,
 506                                struct comedi_insn *insn,
 507                                unsigned int *data)
 508 {
 509         if (comedi_dio_update_state(s, data))
 510                 writel(s->state, dev->mmio + Port_IO(0));
 511
 512         data[1] = readl(dev->mmio + Port_IO(0));
 513
 514         return insn->n;
 515 }
 516
 517 static int ni_pcidio_ns_to_timer(int *nanosec, unsigned int flags)
 518 {
 519         int divider, base;
 520
 521         base = TIMER_BASE;
 522
 523         switch (flags & CMDF_ROUND_MASK) {
 524         case CMDF_ROUND_NEAREST:
 525         default:
 526                 divider = (*nanosec + base / 2) / base;
 527                 break;
 528         case CMDF_ROUND_DOWN:
 529                 divider = (*nanosec) / base;
 530                 break;
 531         case CMDF_ROUND_UP:
 532                 divider = (*nanosec + base - 1) / base;
 533                 break;
 534         }
 535
 536         *nanosec = base * divider;
 537         return divider;
 538 }
 539
 540 static int ni_pcidio_cmdtest(struct comedi_device *dev,
 541                              struct comedi_subdevice *s, struct comedi_cmd *cmd)
 542 {
 543         int err = 0;
 544         unsigned int arg;
 545
 546         /* Step 1 : check if triggers are trivially valid */
 547
 548         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
 549         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
 550                                         TRIG_TIMER | TRIG_EXT);
 551         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
 552         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
 553         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
 554
 555         if (err)
 556                 return 1;
 557
 558         /* Step 2a : make sure trigger sources are unique */
 559
 560         err |= comedi_check_trigger_is_unique(cmd->start_src);
 561         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
 562         err |= comedi_check_trigger_is_unique(cmd->stop_src);
 563
 564         /* Step 2b : and mutually compatible */
 565
 566         if (err)
 567                 return 2;
 568
 569         /* Step 3: check if arguments are trivially valid */
 570
 571         err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
 572
 573 #define MAX_SPEED       (TIMER_BASE)    /* in nanoseconds */
 574
 575         if (cmd->scan_begin_src == TRIG_TIMER) {
 576                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
 577                                                     MAX_SPEED);
 578                 /* no minimum speed */
 579         } else {
 580                 /* TRIG_EXT */
 581                 /* should be level/edge, hi/lo specification here */
 582                 if ((cmd->scan_begin_arg & ~(CR_EDGE | CR_INVERT)) != 0) {
 583                         cmd->scan_begin_arg &= (CR_EDGE | CR_INVERT);
 584                         err |= -EINVAL;
 585                 }
 586         }
 587
 588         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
 589         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
 590                                            cmd->chanlist_len);
 591
 592         if (cmd->stop_src == TRIG_COUNT)
 593                 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
 594         else    /* TRIG_NONE */
 595                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
 596
 597         if (err)
 598                 return 3;
 599
 600         /* step 4: fix up any arguments */
 601
 602         if (cmd->scan_begin_src == TRIG_TIMER) {
 603                 arg = cmd->scan_begin_arg;
 604                 ni_pcidio_ns_to_timer(&arg, cmd->flags);
 605                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
 606         }
 607
 608         if (err)
 609                 return 4;
 610
 611         return 0;
 612 }
 613
 614 static int ni_pcidio_inttrig(struct comedi_device *dev,
 615                              struct comedi_subdevice *s,
 616                              unsigned int trig_num)
 617 {
 618         struct nidio96_private *devpriv = dev->private;
 619         struct comedi_cmd *cmd = &s->async->cmd;
 620
 621         if (trig_num != cmd->start_arg)
 622                 return -EINVAL;
 623
 624         writeb(devpriv->OpModeBits, dev->mmio + OpMode);
 625         s->async->inttrig = NULL;
 626
 627         return 1;
 628 }
 629
 630 static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
 631 {
 632         struct nidio96_private *devpriv = dev->private;
 633         struct comedi_cmd *cmd = &s->async->cmd;
 634
 635         /* XXX configure ports for input */
 636         writel(0x0000, dev->mmio + Port_Pin_Directions(0));
 637
 638         if (1) {
 639                 /* enable fifos A B C D */
 640                 writeb(0x0f, dev->mmio + Data_Path);
 641
 642                 /* set transfer width a 32 bits */
 643                 writeb(TransferWidth(0) | TransferLength(0),
 644                        dev->mmio + Transfer_Size_Control);
 645         } else {
 646                 writeb(0x03, dev->mmio + Data_Path);
 647                 writeb(TransferWidth(3) | TransferLength(0),
 648                        dev->mmio + Transfer_Size_Control);
 649         }
 650
 651         /* protocol configuration */
 652         if (cmd->scan_begin_src == TRIG_TIMER) {
 653                 /* page 4-5, "input with internal REQs" */
 654                 writeb(0, dev->mmio + OpMode);
 655                 writeb(0x00, dev->mmio + ClockReg);
 656                 writeb(1, dev->mmio + Sequence);
 657                 writeb(0x04, dev->mmio + ReqReg);
 658                 writeb(4, dev->mmio + BlockMode);
 659                 writeb(3, dev->mmio + LinePolarities);
 660                 writeb(0xc0, dev->mmio + AckSer);
 661                 writel(ni_pcidio_ns_to_timer(&cmd->scan_begin_arg,
 662                                              CMDF_ROUND_NEAREST),
 663                        dev->mmio + StartDelay);
 664                 writeb(1, dev->mmio + ReqDelay);
 665                 writeb(1, dev->mmio + ReqNotDelay);
 666                 writeb(1, dev->mmio + AckDelay);
 667                 writeb(0x0b, dev->mmio + AckNotDelay);
 668                 writeb(0x01, dev->mmio + Data1Delay);
 669                 /* manual, page 4-5: ClockSpeed comment is incorrectly listed
 670                  * on DAQOptions */
 671                 writew(0, dev->mmio + ClockSpeed);
 672                 writeb(0, dev->mmio + DAQOptions);
 673         } else {
 674                 /* TRIG_EXT */
 675                 /* page 4-5, "input with external REQs" */
 676                 writeb(0, dev->mmio + OpMode);
 677                 writeb(0x00, dev->mmio + ClockReg);
 678                 writeb(0, dev->mmio + Sequence);
 679                 writeb(0x00, dev->mmio + ReqReg);
 680                 writeb(4, dev->mmio + BlockMode);
 681                 if (!(cmd->scan_begin_arg & CR_INVERT)) /* Leading Edge */
 682                         writeb(0, dev->mmio + LinePolarities);
 683                 else                                    /* Trailing Edge */
 684                         writeb(2, dev->mmio + LinePolarities);
 685                 writeb(0x00, dev->mmio + AckSer);
 686                 writel(1, dev->mmio + StartDelay);
 687                 writeb(1, dev->mmio + ReqDelay);
 688                 writeb(1, dev->mmio + ReqNotDelay);
 689                 writeb(1, dev->mmio + AckDelay);
 690                 writeb(0x0C, dev->mmio + AckNotDelay);
 691                 writeb(0x10, dev->mmio + Data1Delay);
 692                 writew(0, dev->mmio + ClockSpeed);
 693                 writeb(0x60, dev->mmio + DAQOptions);
 694         }
 695
 696         if (cmd->stop_src == TRIG_COUNT) {
 697                 writel(cmd->stop_arg,
 698                        dev->mmio + Transfer_Count);
 699         } else {
 700                 /* XXX */
 701         }
 702
 703 #ifdef USE_DMA
 704         writeb(ClearPrimaryTC | ClearSecondaryTC,
 705                dev->mmio + Group_1_First_Clear);
 706
 707         {
 708                 int retval = setup_mite_dma(dev, s);
 709
 710                 if (retval)
 711                         return retval;
 712         }
 713 #else
 714         writeb(0x00, dev->mmio + DMA_Line_Control_Group1);
 715 #endif
 716         writeb(0x00, dev->mmio + DMA_Line_Control_Group2);
 717
 718         /* clear and enable interrupts */
 719         writeb(0xff, dev->mmio + Group_1_First_Clear);
 720         /* writeb(ClearExpired, dev->mmio+Group_1_Second_Clear); */
 721
 722         writeb(IntEn, dev->mmio + Interrupt_Control);
 723         writeb(0x03, dev->mmio + Master_DMA_And_Interrupt_Control);
 724
 725         if (cmd->stop_src == TRIG_NONE) {
 726                 devpriv->OpModeBits = DataLatching(0) | RunMode(7);
 727         } else {                /* TRIG_TIMER */
 728                 devpriv->OpModeBits = Numbered | RunMode(7);
 729         }
 730         if (cmd->start_src == TRIG_NOW) {
 731                 /* start */
 732                 writeb(devpriv->OpModeBits, dev->mmio + OpMode);
 733                 s->async->inttrig = NULL;
 734         } else {
 735                 /* TRIG_INT */
 736                 s->async->inttrig = ni_pcidio_inttrig;
 737         }
 738
 739         return 0;
 740 }
 741
 742 static int ni_pcidio_cancel(struct comedi_device *dev,
 743                             struct comedi_subdevice *s)
 744 {
 745         writeb(0x00, dev->mmio + Master_DMA_And_Interrupt_Control);
 746         ni_pcidio_release_di_mite_channel(dev);
 747
 748         return 0;
 749 }
 750
 751 static int ni_pcidio_change(struct comedi_device *dev,
 752                             struct comedi_subdevice *s)
 753 {
 754         struct nidio96_private *devpriv = dev->private;
 755         int ret;
 756
 757         ret = mite_buf_change(devpriv->di_mite_ring, s);
 758         if (ret < 0)
 759                 return ret;
 760
 761         memset(s->async->prealloc_buf, 0xaa, s->async->prealloc_bufsz);
 762
 763         return 0;
 764 }
 765
 766 static int pci_6534_load_fpga(struct comedi_device *dev,
 767                               const u8 *data, size_t data_len,
 768                               unsigned long context)
 769 {
 770         static const int timeout = 1000;
 771         int fpga_index = context;
 772         int i;
 773         size_t j;
 774
 775         writew(0x80 | fpga_index, dev->mmio + Firmware_Control_Register);
 776         writew(0xc0 | fpga_index, dev->mmio + Firmware_Control_Register);
 777         for (i = 0;
 778              (readw(dev->mmio + Firmware_Status_Register) & 0x2) == 0 &&
 779              i < timeout; ++i) {
 780                 udelay(1);
 781         }
 782         if (i == timeout) {
 783                 dev_warn(dev->class_dev,
 784                          "ni_pcidio: failed to load fpga %i, waiting for status 0x2\n",
 785                          fpga_index);
 786                 return -EIO;
 787         }
 788         writew(0x80 | fpga_index, dev->mmio + Firmware_Control_Register);
 789         for (i = 0;
 790              readw(dev->mmio + Firmware_Status_Register) != 0x3 &&
 791              i < timeout; ++i) {
 792                 udelay(1);
 793         }
 794         if (i == timeout) {
 795                 dev_warn(dev->class_dev,
 796                          "ni_pcidio: failed to load fpga %i, waiting for status 0x3\n",
 797                          fpga_index);
 798                 return -EIO;
 799         }
 800         for (j = 0; j + 1 < data_len;) {
 801                 unsigned int value = data[j++];
 802
 803                 value |= data[j++] << 8;
 804                 writew(value, dev->mmio + Firmware_Data_Register);
 805                 for (i = 0;
 806                      (readw(dev->mmio + Firmware_Status_Register) & 0x2) == 0
 807                      && i < timeout; ++i) {
 808                         udelay(1);
 809                 }
 810                 if (i == timeout) {
 811                         dev_warn(dev->class_dev,
 812                                  "ni_pcidio: failed to load word into fpga %i\n",
 813                                  fpga_index);
 814                         return -EIO;
 815                 }
 816                 if (need_resched())
 817                         schedule();
 818         }
 819         writew(0x0, dev->mmio + Firmware_Control_Register);
 820         return 0;
 821 }
 822
 823 static int pci_6534_reset_fpga(struct comedi_device *dev, int fpga_index)
 824 {
 825         return pci_6534_load_fpga(dev, NULL, 0, fpga_index);
 826 }
 827
 828 static int pci_6534_reset_fpgas(struct comedi_device *dev)
 829 {
 830         int ret;
 831         int i;
 832
 833         writew(0x0, dev->mmio + Firmware_Control_Register);
 834         for (i = 0; i < 3; ++i) {
 835                 ret = pci_6534_reset_fpga(dev, i);
 836                 if (ret < 0)
 837                         break;
 838         }
 839         writew(0x0, dev->mmio + Firmware_Mask_Register);
 840         return ret;
 841 }
 842
 843 static void pci_6534_init_main_fpga(struct comedi_device *dev)
 844 {
 845         writel(0, dev->mmio + FPGA_Control1_Register);
 846         writel(0, dev->mmio + FPGA_Control2_Register);
 847         writel(0, dev->mmio + FPGA_SCALS_Counter_Register);
 848         writel(0, dev->mmio + FPGA_SCAMS_Counter_Register);
 849         writel(0, dev->mmio + FPGA_SCBLS_Counter_Register);
 850         writel(0, dev->mmio + FPGA_SCBMS_Counter_Register);
 851 }
 852
 853 static int pci_6534_upload_firmware(struct comedi_device *dev)
 854 {
 855         struct nidio96_private *devpriv = dev->private;
 856         static const char *const fw_file[3] = {
 857                 FW_PCI_6534_SCARAB_DI,  /* loaded into scarab A for DI */
 858                 FW_PCI_6534_SCARAB_DO,  /* loaded into scarab B for DO */
 859                 FW_PCI_6534_MAIN,       /* loaded into main FPGA */
 860         };
 861         int ret;
 862         int n;
 863
 864         ret = pci_6534_reset_fpgas(dev);
 865         if (ret < 0)
 866                 return ret;
 867         /* load main FPGA first, then the two scarabs */
 868         for (n = 2; n >= 0; n--) {
 869                 ret = comedi_load_firmware(dev, &devpriv->mite->pcidev->dev,
 870                                            fw_file[n],
 871                                            pci_6534_load_fpga, n);
 872                 if (ret == 0 && n == 2)
 873                         pci_6534_init_main_fpga(dev);
 874                 if (ret < 0)
 875                         break;
 876         }
 877         return ret;
 878 }
 879
 880 static void nidio_reset_board(struct comedi_device *dev)
 881 {
 882         writel(0, dev->mmio + Port_IO(0));
 883         writel(0, dev->mmio + Port_Pin_Directions(0));
 884         writel(0, dev->mmio + Port_Pin_Mask(0));
 885
 886         /* disable interrupts on board */
 887         writeb(0, dev->mmio + Master_DMA_And_Interrupt_Control);
 888 }
 889
 890 static int nidio_auto_attach(struct comedi_device *dev,
 891                              unsigned long context)
 892 {
 893         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
 894         const struct nidio_board *board = NULL;
 895         struct nidio96_private *devpriv;
 896         struct comedi_subdevice *s;
 897         int ret;
 898         unsigned int irq;
 899
 900         if (context < ARRAY_SIZE(nidio_boards))
 901                 board = &nidio_boards[context];
 902         if (!board)
 903                 return -ENODEV;
 904         dev->board_ptr = board;
 905         dev->board_name = board->name;
 906
 907         ret = comedi_pci_enable(dev);
 908         if (ret)
 909                 return ret;
 910
 911         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
 912         if (!devpriv)
 913                 return -ENOMEM;
 914
 915         spin_lock_init(&devpriv->mite_channel_lock);
 916
 917         devpriv->mite = mite_alloc(pcidev);
 918         if (!devpriv->mite)
 919                 return -ENOMEM;
 920
 921         ret = mite_setup(dev, devpriv->mite);
 922         if (ret < 0)
 923                 return ret;
 924
 925         devpriv->di_mite_ring = mite_alloc_ring(devpriv->mite);
 926         if (!devpriv->di_mite_ring)
 927                 return -ENOMEM;
 928
 929         if (board->uses_firmware) {
 930                 ret = pci_6534_upload_firmware(dev);
 931                 if (ret < 0)
 932                         return ret;
 933         }
 934
 935         nidio_reset_board(dev);
 936
 937         ret = comedi_alloc_subdevices(dev, 1);
 938         if (ret)
 939                 return ret;
 940
 941         dev_info(dev->class_dev, "%s rev=%d\n", dev->board_name,
 942                  readb(dev->mmio + Chip_Version));
 943
 944         s = &dev->subdevices[0];
 945
 946         dev->read_subdev = s;
 947         s->type = COMEDI_SUBD_DIO;
 948         s->subdev_flags =
 949                 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_PACKED |
 950                 SDF_CMD_READ;
 951         s->n_chan = 32;
 952         s->range_table = &range_digital;
 953         s->maxdata = 1;
 954         s->insn_config = &ni_pcidio_insn_config;
 955         s->insn_bits = &ni_pcidio_insn_bits;
 956         s->do_cmd = &ni_pcidio_cmd;
 957         s->do_cmdtest = &ni_pcidio_cmdtest;
 958         s->cancel = &ni_pcidio_cancel;
 959         s->len_chanlist = 32;   /* XXX */
 960         s->buf_change = &ni_pcidio_change;
 961         s->async_dma_dir = DMA_BIDIRECTIONAL;
 962         s->poll = &ni_pcidio_poll;
 963
 964         irq = pcidev->irq;
 965         if (irq) {
 966                 ret = request_irq(irq, nidio_interrupt, IRQF_SHARED,
 967                                   dev->board_name, dev);
 968                 if (ret == 0)
 969                         dev->irq = irq;
 970         }
 971
 972         return 0;
 973 }
 974
 975 static void nidio_detach(struct comedi_device *dev)
 976 {
 977         struct nidio96_private *devpriv = dev->private;
 978
 979         if (dev->irq)
 980                 free_irq(dev->irq, dev);
 981         if (devpriv) {
 982                 if (devpriv->di_mite_ring) {
 983                         mite_free_ring(devpriv->di_mite_ring);
 984                         devpriv->di_mite_ring = NULL;
 985                 }
 986                 mite_detach(devpriv->mite);
 987         }
 988         if (dev->mmio)
 989                 iounmap(dev->mmio);
 990         comedi_pci_disable(dev);
 991 }
 992
 993 static struct comedi_driver ni_pcidio_driver = {
 994         .driver_name    = "ni_pcidio",
 995         .module         = THIS_MODULE,
 996         .auto_attach    = nidio_auto_attach,
 997         .detach         = nidio_detach,
 998 };
 999
1000 static int ni_pcidio_pci_probe(struct pci_dev *dev,
1001                                const struct pci_device_id *id)
1002 {
1003         return comedi_pci_auto_config(dev, &ni_pcidio_driver, id->driver_data);
1004 }
1005
1006 static const struct pci_device_id ni_pcidio_pci_table[] = {
1007         { PCI_VDEVICE(NI, 0x1150), BOARD_PCIDIO_32HS },
1008         { PCI_VDEVICE(NI, 0x12b0), BOARD_PCI6534 },
1009         { PCI_VDEVICE(NI, 0x1320), BOARD_PXI6533 },
1010         { 0 }
1011 };
1012 MODULE_DEVICE_TABLE(pci, ni_pcidio_pci_table);
1013
1014 static struct pci_driver ni_pcidio_pci_driver = {
1015         .name           = "ni_pcidio",
1016         .id_table       = ni_pcidio_pci_table,
1017         .probe          = ni_pcidio_pci_probe,
1018         .remove         = comedi_pci_auto_unconfig,
1019 };
1020 module_comedi_pci_driver(ni_pcidio_driver, ni_pcidio_pci_driver);
1021
1022 MODULE_AUTHOR("Comedi http://www.comedi.org");
1023 MODULE_DESCRIPTION("Comedi low-level driver");
1024 MODULE_LICENSE("GPL");