2 * Comedi driver for National Instruments PCI-DIO-32HS
4 * COMEDI - Linux Control and Measurement Device Interface
5 * Copyright (C) 1999,2002 David A. Schleef <ds@schleef.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
20 * Description: National Instruments PCI-DIO32HS, PCI-6533
23 * Devices: [National Instruments] PCI-DIO-32HS (ni_pcidio)
24 * [National Instruments] PXI-6533, PCI-6533 (pxi-6533)
25 * [National Instruments] PCI-6534 (pci-6534)
26 * Updated: Mon, 09 Jan 2012 14:27:23 +0000
28 * The DIO32HS board appears as one subdevice, with 32 channels. Each
29 * channel is individually I/O configurable. The channel order is 0=A0,
30 * 1=A1, 2=A2, ... 8=B0, 16=C0, 24=D0. The driver only supports simple
31 * digital I/O; no handshaking is supported.
33 * DMA mostly works for the PCI-DIO32HS, but only in timed input mode.
35 * The PCI-DIO-32HS/PCI-6533 has a configurable external trigger. Setting
36 * scan_begin_arg to 0 or CR_EDGE triggers on the leading edge. Setting
37 * scan_begin_arg to CR_INVERT or (CR_EDGE | CR_INVERT) triggers on the
40 * This driver could be easily modified to support AT-MIO32HS and AT-MIO96.
42 * The PCI-6534 requires a firmware upload after power-up to work, the
43 * firmware data and instructions for loading it with comedi_config
44 * it are contained in the comedi_nonfree_firmware tarball available from
45 * http://www.comedi.org
50 #include <linux/module.h>
51 #include <linux/delay.h>
52 #include <linux/interrupt.h>
53 #include <linux/sched.h>
55 #include "../comedi_pci.h"
59 /* defines for the PCI-DIO-32HS */
61 #define Window_Address 4 /* W */
62 #define Interrupt_And_Window_Status 4 /* R */
63 #define IntStatus1 BIT(0)
64 #define IntStatus2 BIT(1)
65 #define WindowAddressStatus_mask 0x7c
67 #define Master_DMA_And_Interrupt_Control 5 /* W */
68 #define InterruptLine(x) ((x) & 3)
69 #define OpenInt BIT(2)
70 #define Group_Status 5 /* R */
71 #define DataLeft BIT(0)
73 #define StopTrig BIT(3)
75 #define Group_1_Flags 6 /* R */
76 #define Group_2_Flags 7 /* R */
77 #define TransferReady BIT(0)
78 #define CountExpired BIT(1)
80 #define PrimaryTC BIT(6)
81 #define SecondaryTC BIT(7)
82 /* #define SerialRose */
86 #define Group_1_First_Clear 6 /* W */
87 #define Group_2_First_Clear 7 /* W */
88 #define ClearWaited BIT(3)
89 #define ClearPrimaryTC BIT(4)
90 #define ClearSecondaryTC BIT(5)
91 #define DMAReset BIT(6)
92 #define FIFOReset BIT(7)
95 #define Group_1_FIFO 8 /* W */
96 #define Group_2_FIFO 12 /* W */
98 #define Transfer_Count 20
102 #define Chip_Version 27
103 #define Port_IO(x) (28 + (x))
104 #define Port_Pin_Directions(x) (32 + (x))
105 #define Port_Pin_Mask(x) (36 + (x))
106 #define Port_Pin_Polarities(x) (40 + (x))
108 #define Master_Clock_Routing 45
109 #define RTSIClocking(x) (((x) & 3) << 4)
111 #define Group_1_Second_Clear 46 /* W */
112 #define Group_2_Second_Clear 47 /* W */
113 #define ClearExpired BIT(0)
115 #define Port_Pattern(x) (48 + (x))
118 #define FIFOEnableA BIT(0)
119 #define FIFOEnableB BIT(1)
120 #define FIFOEnableC BIT(2)
121 #define FIFOEnableD BIT(3)
122 #define Funneling(x) (((x) & 3) << 4)
123 #define GroupDirection BIT(7)
125 #define Protocol_Register_1 65
126 #define OpMode Protocol_Register_1
127 #define RunMode(x) ((x) & 7)
128 #define Numbered BIT(3)
130 #define Protocol_Register_2 66
131 #define ClockReg Protocol_Register_2
132 #define ClockLine(x) (((x) & 3) << 5)
133 #define InvertStopTrig BIT(7)
134 #define DataLatching(x) (((x) & 3) << 5)
136 #define Protocol_Register_3 67
137 #define Sequence Protocol_Register_3
139 #define Protocol_Register_14 68 /* 16 bit */
140 #define ClockSpeed Protocol_Register_14
142 #define Protocol_Register_4 70
143 #define ReqReg Protocol_Register_4
144 #define ReqConditioning(x) (((x) & 7) << 3)
146 #define Protocol_Register_5 71
147 #define BlockMode Protocol_Register_5
149 #define FIFO_Control 72
150 #define ReadyLevel(x) ((x) & 7)
152 #define Protocol_Register_6 73
153 #define LinePolarities Protocol_Register_6
154 #define InvertAck BIT(0)
155 #define InvertReq BIT(1)
156 #define InvertClock BIT(2)
157 #define InvertSerial BIT(3)
158 #define OpenAck BIT(4)
159 #define OpenClock BIT(5)
161 #define Protocol_Register_7 74
162 #define AckSer Protocol_Register_7
163 #define AckLine(x) (((x) & 3) << 2)
164 #define ExchangePins BIT(7)
166 #define Interrupt_Control 75
167 /* bits same as flags */
169 #define DMA_Line_Control_Group1 76
170 #define DMA_Line_Control_Group2 108
171 /* channel zero is none */
172 static inline unsigned int primary_DMAChannel_bits(unsigned int channel)
174 return channel & 0x3;
177 static inline unsigned int secondary_DMAChannel_bits(unsigned int channel)
179 return (channel << 2) & 0xc;
182 #define Transfer_Size_Control 77
183 #define TransferWidth(x) ((x) & 3)
184 #define TransferLength(x) (((x) & 3) << 3)
185 #define RequireRLevel BIT(5)
187 #define Protocol_Register_15 79
188 #define DAQOptions Protocol_Register_15
189 #define StartSource(x) ((x) & 0x3)
190 #define InvertStart BIT(2)
191 #define StopSource(x) (((x) & 0x3) << 3)
192 #define ReqStart BIT(6)
193 #define PreStart BIT(7)
195 #define Pattern_Detection 81
196 #define DetectionMethod BIT(0)
197 #define InvertMatch BIT(1)
198 #define IE_Pattern_Detection BIT(2)
200 #define Protocol_Register_9 82
201 #define ReqDelay Protocol_Register_9
203 #define Protocol_Register_10 83
204 #define ReqNotDelay Protocol_Register_10
206 #define Protocol_Register_11 84
207 #define AckDelay Protocol_Register_11
209 #define Protocol_Register_12 85
210 #define AckNotDelay Protocol_Register_12
212 #define Protocol_Register_13 86
213 #define Data1Delay Protocol_Register_13
215 #define Protocol_Register_8 88 /* 32 bit */
216 #define StartDelay Protocol_Register_8
218 /* Firmware files for PCI-6524 */
219 #define FW_PCI_6534_MAIN "/*(DEBLOBBED)*/"
220 #define FW_PCI_6534_SCARAB_DI "/*(DEBLOBBED)*/"
221 #define FW_PCI_6534_SCARAB_DO "/*(DEBLOBBED)*/"
224 enum pci_6534_firmware_registers { /* 16 bit */
225 Firmware_Control_Register = 0x100,
226 Firmware_Status_Register = 0x104,
227 Firmware_Data_Register = 0x108,
228 Firmware_Mask_Register = 0x10c,
229 Firmware_Debug_Register = 0x110,
232 /* main fpga registers (32 bit)*/
233 enum pci_6534_fpga_registers {
234 FPGA_Control1_Register = 0x200,
235 FPGA_Control2_Register = 0x204,
236 FPGA_Irq_Mask_Register = 0x208,
237 FPGA_Status_Register = 0x20c,
238 FPGA_Signature_Register = 0x210,
239 FPGA_SCALS_Counter_Register = 0x280, /*write-clear */
240 FPGA_SCAMS_Counter_Register = 0x284, /*write-clear */
241 FPGA_SCBLS_Counter_Register = 0x288, /*write-clear */
242 FPGA_SCBMS_Counter_Register = 0x28c, /*write-clear */
243 FPGA_Temp_Control_Register = 0x2a0,
244 FPGA_DAR_Register = 0x2a8,
245 FPGA_ELC_Read_Register = 0x2b8,
246 FPGA_ELC_Write_Register = 0x2bc,
249 enum FPGA_Control_Bits {
250 FPGA_Enable_Bit = 0x8000,
253 #define TIMER_BASE 50 /* nanoseconds */
256 #define IntEn (CountExpired | Waited | PrimaryTC | SecondaryTC)
258 #define IntEn (TransferReady | CountExpired | Waited | PrimaryTC | SecondaryTC)
269 unsigned int uses_firmware:1;
272 static const struct nidio_board nidio_boards[] = {
273 [BOARD_PCIDIO_32HS] = {
274 .name = "pci-dio-32hs",
285 struct nidio96_private {
289 unsigned short OpModeBits;
290 struct mite_channel *di_mite_chan;
291 struct mite_ring *di_mite_ring;
292 spinlock_t mite_channel_lock;
295 static int ni_pcidio_request_di_mite_channel(struct comedi_device *dev)
297 struct nidio96_private *devpriv = dev->private;
300 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
301 BUG_ON(devpriv->di_mite_chan);
302 devpriv->di_mite_chan =
303 mite_request_channel_in_range(devpriv->mite,
304 devpriv->di_mite_ring, 1, 2);
305 if (!devpriv->di_mite_chan) {
306 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
307 dev_err(dev->class_dev, "failed to reserve mite dma channel\n");
310 devpriv->di_mite_chan->dir = COMEDI_INPUT;
311 writeb(primary_DMAChannel_bits(devpriv->di_mite_chan->channel) |
312 secondary_DMAChannel_bits(devpriv->di_mite_chan->channel),
313 dev->mmio + DMA_Line_Control_Group1);
315 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
319 static void ni_pcidio_release_di_mite_channel(struct comedi_device *dev)
321 struct nidio96_private *devpriv = dev->private;
324 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
325 if (devpriv->di_mite_chan) {
326 mite_release_channel(devpriv->di_mite_chan);
327 devpriv->di_mite_chan = NULL;
328 writeb(primary_DMAChannel_bits(0) |
329 secondary_DMAChannel_bits(0),
330 dev->mmio + DMA_Line_Control_Group1);
333 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
336 static int setup_mite_dma(struct comedi_device *dev, struct comedi_subdevice *s)
338 struct nidio96_private *devpriv = dev->private;
342 retval = ni_pcidio_request_di_mite_channel(dev);
346 /* write alloc the entire buffer */
347 comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
349 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
350 if (devpriv->di_mite_chan) {
351 mite_prep_dma(devpriv->di_mite_chan, 32, 32);
352 mite_dma_arm(devpriv->di_mite_chan);
356 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
361 static int ni_pcidio_poll(struct comedi_device *dev, struct comedi_subdevice *s)
363 struct nidio96_private *devpriv = dev->private;
364 unsigned long irq_flags;
367 spin_lock_irqsave(&dev->spinlock, irq_flags);
368 spin_lock(&devpriv->mite_channel_lock);
369 if (devpriv->di_mite_chan)
370 mite_sync_dma(devpriv->di_mite_chan, s);
371 spin_unlock(&devpriv->mite_channel_lock);
372 count = comedi_buf_n_bytes_ready(s);
373 spin_unlock_irqrestore(&dev->spinlock, irq_flags);
377 static irqreturn_t nidio_interrupt(int irq, void *d)
379 struct comedi_device *dev = d;
380 struct nidio96_private *devpriv = dev->private;
381 struct comedi_subdevice *s = dev->read_subdev;
382 struct comedi_async *async = s->async;
383 unsigned int auxdata;
388 /* interrupcions parasites */
389 if (!dev->attached) {
390 /* assume it's from another card */
394 /* Lock to avoid race with comedi_poll */
395 spin_lock(&dev->spinlock);
397 status = readb(dev->mmio + Interrupt_And_Window_Status);
398 flags = readb(dev->mmio + Group_1_Flags);
400 spin_lock(&devpriv->mite_channel_lock);
401 if (devpriv->di_mite_chan) {
402 mite_ack_linkc(devpriv->di_mite_chan, s, false);
403 /* XXX need to byteswap sync'ed dma */
405 spin_unlock(&devpriv->mite_channel_lock);
407 while (status & DataLeft) {
410 dev_dbg(dev->class_dev, "too much work in interrupt\n");
412 dev->mmio + Master_DMA_And_Interrupt_Control);
418 if (flags & TransferReady) {
419 while (flags & TransferReady) {
422 dev_dbg(dev->class_dev,
423 "too much work in interrupt\n");
424 writeb(0x00, dev->mmio +
425 Master_DMA_And_Interrupt_Control
429 auxdata = readl(dev->mmio + Group_1_FIFO);
430 comedi_buf_write_samples(s, &auxdata, 1);
431 flags = readb(dev->mmio + Group_1_Flags);
435 if (flags & CountExpired) {
436 writeb(ClearExpired, dev->mmio + Group_1_Second_Clear);
437 async->events |= COMEDI_CB_EOA;
439 writeb(0x00, dev->mmio + OpMode);
441 } else if (flags & Waited) {
442 writeb(ClearWaited, dev->mmio + Group_1_First_Clear);
443 async->events |= COMEDI_CB_ERROR;
445 } else if (flags & PrimaryTC) {
446 writeb(ClearPrimaryTC,
447 dev->mmio + Group_1_First_Clear);
448 async->events |= COMEDI_CB_EOA;
449 } else if (flags & SecondaryTC) {
450 writeb(ClearSecondaryTC,
451 dev->mmio + Group_1_First_Clear);
452 async->events |= COMEDI_CB_EOA;
455 flags = readb(dev->mmio + Group_1_Flags);
456 status = readb(dev->mmio + Interrupt_And_Window_Status);
460 comedi_handle_events(dev, s);
463 writeb(0x03, dev->mmio + Master_DMA_And_Interrupt_Control);
466 spin_unlock(&dev->spinlock);
470 static int ni_pcidio_insn_config(struct comedi_device *dev,
471 struct comedi_subdevice *s,
472 struct comedi_insn *insn,
477 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
481 writel(s->io_bits, dev->mmio + Port_Pin_Directions(0));
486 static int ni_pcidio_insn_bits(struct comedi_device *dev,
487 struct comedi_subdevice *s,
488 struct comedi_insn *insn,
491 if (comedi_dio_update_state(s, data))
492 writel(s->state, dev->mmio + Port_IO(0));
494 data[1] = readl(dev->mmio + Port_IO(0));
499 static int ni_pcidio_ns_to_timer(int *nanosec, unsigned int flags)
505 switch (flags & CMDF_ROUND_MASK) {
506 case CMDF_ROUND_NEAREST:
508 divider = DIV_ROUND_CLOSEST(*nanosec, base);
510 case CMDF_ROUND_DOWN:
511 divider = (*nanosec) / base;
514 divider = DIV_ROUND_UP(*nanosec, base);
518 *nanosec = base * divider;
522 static int ni_pcidio_cmdtest(struct comedi_device *dev,
523 struct comedi_subdevice *s, struct comedi_cmd *cmd)
528 /* Step 1 : check if triggers are trivially valid */
530 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
531 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
532 TRIG_TIMER | TRIG_EXT);
533 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
534 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
535 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
540 /* Step 2a : make sure trigger sources are unique */
542 err |= comedi_check_trigger_is_unique(cmd->start_src);
543 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
544 err |= comedi_check_trigger_is_unique(cmd->stop_src);
546 /* Step 2b : and mutually compatible */
551 /* Step 3: check if arguments are trivially valid */
553 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
555 #define MAX_SPEED (TIMER_BASE) /* in nanoseconds */
557 if (cmd->scan_begin_src == TRIG_TIMER) {
558 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
560 /* no minimum speed */
563 /* should be level/edge, hi/lo specification here */
564 if ((cmd->scan_begin_arg & ~(CR_EDGE | CR_INVERT)) != 0) {
565 cmd->scan_begin_arg &= (CR_EDGE | CR_INVERT);
570 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
571 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
574 if (cmd->stop_src == TRIG_COUNT)
575 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
577 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
582 /* step 4: fix up any arguments */
584 if (cmd->scan_begin_src == TRIG_TIMER) {
585 arg = cmd->scan_begin_arg;
586 ni_pcidio_ns_to_timer(&arg, cmd->flags);
587 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
596 static int ni_pcidio_inttrig(struct comedi_device *dev,
597 struct comedi_subdevice *s,
598 unsigned int trig_num)
600 struct nidio96_private *devpriv = dev->private;
601 struct comedi_cmd *cmd = &s->async->cmd;
603 if (trig_num != cmd->start_arg)
606 writeb(devpriv->OpModeBits, dev->mmio + OpMode);
607 s->async->inttrig = NULL;
612 static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
614 struct nidio96_private *devpriv = dev->private;
615 struct comedi_cmd *cmd = &s->async->cmd;
617 /* XXX configure ports for input */
618 writel(0x0000, dev->mmio + Port_Pin_Directions(0));
621 /* enable fifos A B C D */
622 writeb(0x0f, dev->mmio + Data_Path);
624 /* set transfer width a 32 bits */
625 writeb(TransferWidth(0) | TransferLength(0),
626 dev->mmio + Transfer_Size_Control);
628 writeb(0x03, dev->mmio + Data_Path);
629 writeb(TransferWidth(3) | TransferLength(0),
630 dev->mmio + Transfer_Size_Control);
633 /* protocol configuration */
634 if (cmd->scan_begin_src == TRIG_TIMER) {
635 /* page 4-5, "input with internal REQs" */
636 writeb(0, dev->mmio + OpMode);
637 writeb(0x00, dev->mmio + ClockReg);
638 writeb(1, dev->mmio + Sequence);
639 writeb(0x04, dev->mmio + ReqReg);
640 writeb(4, dev->mmio + BlockMode);
641 writeb(3, dev->mmio + LinePolarities);
642 writeb(0xc0, dev->mmio + AckSer);
643 writel(ni_pcidio_ns_to_timer(&cmd->scan_begin_arg,
645 dev->mmio + StartDelay);
646 writeb(1, dev->mmio + ReqDelay);
647 writeb(1, dev->mmio + ReqNotDelay);
648 writeb(1, dev->mmio + AckDelay);
649 writeb(0x0b, dev->mmio + AckNotDelay);
650 writeb(0x01, dev->mmio + Data1Delay);
653 * ClockSpeed comment is incorrectly listed on DAQOptions
655 writew(0, dev->mmio + ClockSpeed);
656 writeb(0, dev->mmio + DAQOptions);
659 /* page 4-5, "input with external REQs" */
660 writeb(0, dev->mmio + OpMode);
661 writeb(0x00, dev->mmio + ClockReg);
662 writeb(0, dev->mmio + Sequence);
663 writeb(0x00, dev->mmio + ReqReg);
664 writeb(4, dev->mmio + BlockMode);
665 if (!(cmd->scan_begin_arg & CR_INVERT)) /* Leading Edge */
666 writeb(0, dev->mmio + LinePolarities);
667 else /* Trailing Edge */
668 writeb(2, dev->mmio + LinePolarities);
669 writeb(0x00, dev->mmio + AckSer);
670 writel(1, dev->mmio + StartDelay);
671 writeb(1, dev->mmio + ReqDelay);
672 writeb(1, dev->mmio + ReqNotDelay);
673 writeb(1, dev->mmio + AckDelay);
674 writeb(0x0C, dev->mmio + AckNotDelay);
675 writeb(0x10, dev->mmio + Data1Delay);
676 writew(0, dev->mmio + ClockSpeed);
677 writeb(0x60, dev->mmio + DAQOptions);
680 if (cmd->stop_src == TRIG_COUNT) {
681 writel(cmd->stop_arg,
682 dev->mmio + Transfer_Count);
688 writeb(ClearPrimaryTC | ClearSecondaryTC,
689 dev->mmio + Group_1_First_Clear);
692 int retval = setup_mite_dma(dev, s);
698 writeb(0x00, dev->mmio + DMA_Line_Control_Group1);
700 writeb(0x00, dev->mmio + DMA_Line_Control_Group2);
702 /* clear and enable interrupts */
703 writeb(0xff, dev->mmio + Group_1_First_Clear);
704 /* writeb(ClearExpired, dev->mmio+Group_1_Second_Clear); */
706 writeb(IntEn, dev->mmio + Interrupt_Control);
707 writeb(0x03, dev->mmio + Master_DMA_And_Interrupt_Control);
709 if (cmd->stop_src == TRIG_NONE) {
710 devpriv->OpModeBits = DataLatching(0) | RunMode(7);
711 } else { /* TRIG_TIMER */
712 devpriv->OpModeBits = Numbered | RunMode(7);
714 if (cmd->start_src == TRIG_NOW) {
716 writeb(devpriv->OpModeBits, dev->mmio + OpMode);
717 s->async->inttrig = NULL;
720 s->async->inttrig = ni_pcidio_inttrig;
726 static int ni_pcidio_cancel(struct comedi_device *dev,
727 struct comedi_subdevice *s)
729 writeb(0x00, dev->mmio + Master_DMA_And_Interrupt_Control);
730 ni_pcidio_release_di_mite_channel(dev);
735 static int ni_pcidio_change(struct comedi_device *dev,
736 struct comedi_subdevice *s)
738 struct nidio96_private *devpriv = dev->private;
741 ret = mite_buf_change(devpriv->di_mite_ring, s);
745 memset(s->async->prealloc_buf, 0xaa, s->async->prealloc_bufsz);
750 static int pci_6534_load_fpga(struct comedi_device *dev,
751 const u8 *data, size_t data_len,
752 unsigned long context)
754 static const int timeout = 1000;
755 int fpga_index = context;
759 writew(0x80 | fpga_index, dev->mmio + Firmware_Control_Register);
760 writew(0xc0 | fpga_index, dev->mmio + Firmware_Control_Register);
762 (readw(dev->mmio + Firmware_Status_Register) & 0x2) == 0 &&
767 dev_warn(dev->class_dev,
768 "ni_pcidio: failed to load fpga %i, waiting for status 0x2\n",
772 writew(0x80 | fpga_index, dev->mmio + Firmware_Control_Register);
774 readw(dev->mmio + Firmware_Status_Register) != 0x3 &&
779 dev_warn(dev->class_dev,
780 "ni_pcidio: failed to load fpga %i, waiting for status 0x3\n",
784 for (j = 0; j + 1 < data_len;) {
785 unsigned int value = data[j++];
787 value |= data[j++] << 8;
788 writew(value, dev->mmio + Firmware_Data_Register);
790 (readw(dev->mmio + Firmware_Status_Register) & 0x2) == 0
791 && i < timeout; ++i) {
795 dev_warn(dev->class_dev,
796 "ni_pcidio: failed to load word into fpga %i\n",
803 writew(0x0, dev->mmio + Firmware_Control_Register);
807 static int pci_6534_reset_fpga(struct comedi_device *dev, int fpga_index)
809 return pci_6534_load_fpga(dev, NULL, 0, fpga_index);
812 static int pci_6534_reset_fpgas(struct comedi_device *dev)
817 writew(0x0, dev->mmio + Firmware_Control_Register);
818 for (i = 0; i < 3; ++i) {
819 ret = pci_6534_reset_fpga(dev, i);
823 writew(0x0, dev->mmio + Firmware_Mask_Register);
827 static void pci_6534_init_main_fpga(struct comedi_device *dev)
829 writel(0, dev->mmio + FPGA_Control1_Register);
830 writel(0, dev->mmio + FPGA_Control2_Register);
831 writel(0, dev->mmio + FPGA_SCALS_Counter_Register);
832 writel(0, dev->mmio + FPGA_SCAMS_Counter_Register);
833 writel(0, dev->mmio + FPGA_SCBLS_Counter_Register);
834 writel(0, dev->mmio + FPGA_SCBMS_Counter_Register);
837 static int pci_6534_upload_firmware(struct comedi_device *dev)
839 struct nidio96_private *devpriv = dev->private;
840 static const char *const fw_file[3] = {
841 FW_PCI_6534_SCARAB_DI, /* loaded into scarab A for DI */
842 FW_PCI_6534_SCARAB_DO, /* loaded into scarab B for DO */
843 FW_PCI_6534_MAIN, /* loaded into main FPGA */
848 ret = pci_6534_reset_fpgas(dev);
851 /* load main FPGA first, then the two scarabs */
852 for (n = 2; n >= 0; n--) {
853 ret = comedi_load_firmware(dev, &devpriv->mite->pcidev->dev,
855 pci_6534_load_fpga, n);
856 if (ret == 0 && n == 2)
857 pci_6534_init_main_fpga(dev);
864 static void nidio_reset_board(struct comedi_device *dev)
866 writel(0, dev->mmio + Port_IO(0));
867 writel(0, dev->mmio + Port_Pin_Directions(0));
868 writel(0, dev->mmio + Port_Pin_Mask(0));
870 /* disable interrupts on board */
871 writeb(0, dev->mmio + Master_DMA_And_Interrupt_Control);
874 static int nidio_auto_attach(struct comedi_device *dev,
875 unsigned long context)
877 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
878 const struct nidio_board *board = NULL;
879 struct nidio96_private *devpriv;
880 struct comedi_subdevice *s;
884 if (context < ARRAY_SIZE(nidio_boards))
885 board = &nidio_boards[context];
888 dev->board_ptr = board;
889 dev->board_name = board->name;
891 ret = comedi_pci_enable(dev);
895 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
899 spin_lock_init(&devpriv->mite_channel_lock);
901 devpriv->mite = mite_attach(dev, false); /* use win0 */
905 devpriv->di_mite_ring = mite_alloc_ring(devpriv->mite);
906 if (!devpriv->di_mite_ring)
909 if (board->uses_firmware) {
910 ret = pci_6534_upload_firmware(dev);
915 nidio_reset_board(dev);
917 ret = comedi_alloc_subdevices(dev, 1);
921 dev_info(dev->class_dev, "%s rev=%d\n", dev->board_name,
922 readb(dev->mmio + Chip_Version));
924 s = &dev->subdevices[0];
926 dev->read_subdev = s;
927 s->type = COMEDI_SUBD_DIO;
929 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_PACKED |
932 s->range_table = &range_digital;
934 s->insn_config = &ni_pcidio_insn_config;
935 s->insn_bits = &ni_pcidio_insn_bits;
936 s->do_cmd = &ni_pcidio_cmd;
937 s->do_cmdtest = &ni_pcidio_cmdtest;
938 s->cancel = &ni_pcidio_cancel;
939 s->len_chanlist = 32; /* XXX */
940 s->buf_change = &ni_pcidio_change;
941 s->async_dma_dir = DMA_BIDIRECTIONAL;
942 s->poll = &ni_pcidio_poll;
946 ret = request_irq(irq, nidio_interrupt, IRQF_SHARED,
947 dev->board_name, dev);
955 static void nidio_detach(struct comedi_device *dev)
957 struct nidio96_private *devpriv = dev->private;
960 free_irq(dev->irq, dev);
962 if (devpriv->di_mite_ring) {
963 mite_free_ring(devpriv->di_mite_ring);
964 devpriv->di_mite_ring = NULL;
966 mite_detach(devpriv->mite);
970 comedi_pci_disable(dev);
973 static struct comedi_driver ni_pcidio_driver = {
974 .driver_name = "ni_pcidio",
975 .module = THIS_MODULE,
976 .auto_attach = nidio_auto_attach,
977 .detach = nidio_detach,
980 static int ni_pcidio_pci_probe(struct pci_dev *dev,
981 const struct pci_device_id *id)
983 return comedi_pci_auto_config(dev, &ni_pcidio_driver, id->driver_data);
986 static const struct pci_device_id ni_pcidio_pci_table[] = {
987 { PCI_VDEVICE(NI, 0x1150), BOARD_PCIDIO_32HS },
988 { PCI_VDEVICE(NI, 0x12b0), BOARD_PCI6534 },
989 { PCI_VDEVICE(NI, 0x1320), BOARD_PXI6533 },
992 MODULE_DEVICE_TABLE(pci, ni_pcidio_pci_table);
994 static struct pci_driver ni_pcidio_pci_driver = {
996 .id_table = ni_pcidio_pci_table,
997 .probe = ni_pcidio_pci_probe,
998 .remove = comedi_pci_auto_unconfig,
1000 module_comedi_pci_driver(ni_pcidio_driver, ni_pcidio_pci_driver);
1002 MODULE_AUTHOR("Comedi http://www.comedi.org");
1003 MODULE_DESCRIPTION("Comedi low-level driver");
1004 MODULE_LICENSE("GPL");