drivers/staging/comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21         This file is meant to be included by another file, e.g.,
  22         ni_atmio.c or ni_pcimio.c.
  23
  24         Interrupt support originally added by Truxton Fulton
  25         <trux@truxton.com>
  26
  27         References (from ftp://ftp.natinst.com/support/manuals):
  28
  29            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  30            341079b.pdf  PCI E Series RLPM
  31            340934b.pdf  DAQ-STC reference manual
  32         67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
  33         release_ni611x.pdf
  34         release_ni67xx.pdf
  35         Other possibly relevant info:
  36
  37            320517c.pdf  User manual (obsolete)
  38            320517f.pdf  User manual (new)
  39            320889a.pdf  delete
  40            320906c.pdf  maximum signal ratings
  41            321066a.pdf  about 16x
  42            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  43            321808a.pdf  about at-mio-16e-10 rev P
  44            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  45            321838a.pdf  about at-mio-16de-10 rev N
  46
  47         ISSUES:
  48
  49          - the interrupt routine needs to be cleaned up
  50
  51         2006-02-07: S-Series PCI-6143: Support has been added but is not
  52                 fully tested as yet. Terry Barnaby, BEAM Ltd.
  53 */
  54
  55 #include <linux/interrupt.h>
  56 #include <linux/sched.h>
  57 #include <linux/delay.h>
  58 #include "8255.h"
  59 #include "mite.h"
  60
  61 /* A timeout count */
  62 #define NI_TIMEOUT 1000
  63
  64 /* Note: this table must match the ai_gain_* definitions */
  65 static const short ni_gainlkup[][16] = {
  66         [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
  67                         0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  68         [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
  69         [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
  70                         0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  71         [ai_gain_4] = {0, 1, 4, 7},
  72         [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
  73                           0x003, 0x004, 0x005, 0x006},
  74         [ai_gain_622x] = {0, 1, 4, 5},
  75         [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
  76         [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  77 };
  78
  79 static const struct comedi_lrange range_ni_E_ai = {
  80         16, {
  81                 BIP_RANGE(10),
  82                 BIP_RANGE(5),
  83                 BIP_RANGE(2.5),
  84                 BIP_RANGE(1),
  85                 BIP_RANGE(0.5),
  86                 BIP_RANGE(0.25),
  87                 BIP_RANGE(0.1),
  88                 BIP_RANGE(0.05),
  89                 UNI_RANGE(20),
  90                 UNI_RANGE(10),
  91                 UNI_RANGE(5),
  92                 UNI_RANGE(2),
  93                 UNI_RANGE(1),
  94                 UNI_RANGE(0.5),
  95                 UNI_RANGE(0.2),
  96                 UNI_RANGE(0.1)
  97         }
  98 };
  99
 100 static const struct comedi_lrange range_ni_E_ai_limited = {
 101         8, {
 102                 BIP_RANGE(10),
 103                 BIP_RANGE(5),
 104                 BIP_RANGE(1),
 105                 BIP_RANGE(0.1),
 106                 UNI_RANGE(10),
 107                 UNI_RANGE(5),
 108                 UNI_RANGE(1),
 109                 UNI_RANGE(0.1)
 110         }
 111 };
 112
 113 static const struct comedi_lrange range_ni_E_ai_limited14 = {
 114         14, {
 115                 BIP_RANGE(10),
 116                 BIP_RANGE(5),
 117                 BIP_RANGE(2),
 118                 BIP_RANGE(1),
 119                 BIP_RANGE(0.5),
 120                 BIP_RANGE(0.2),
 121                 BIP_RANGE(0.1),
 122                 UNI_RANGE(10),
 123                 UNI_RANGE(5),
 124                 UNI_RANGE(2),
 125                 UNI_RANGE(1),
 126                 UNI_RANGE(0.5),
 127                 UNI_RANGE(0.2),
 128                 UNI_RANGE(0.1)
 129         }
 130 };
 131
 132 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
 133         4, {
 134                 BIP_RANGE(10),
 135                 BIP_RANGE(5),
 136                 BIP_RANGE(0.5),
 137                 BIP_RANGE(0.05)
 138         }
 139 };
 140
 141 static const struct comedi_lrange range_ni_E_ai_611x = {
 142         8, {
 143                 BIP_RANGE(50),
 144                 BIP_RANGE(20),
 145                 BIP_RANGE(10),
 146                 BIP_RANGE(5),
 147                 BIP_RANGE(2),
 148                 BIP_RANGE(1),
 149                 BIP_RANGE(0.5),
 150                 BIP_RANGE(0.2)
 151         }
 152 };
 153
 154 static const struct comedi_lrange range_ni_M_ai_622x = {
 155         4, {
 156                 BIP_RANGE(10),
 157                 BIP_RANGE(5),
 158                 BIP_RANGE(1),
 159                 BIP_RANGE(0.2)
 160         }
 161 };
 162
 163 static const struct comedi_lrange range_ni_M_ai_628x = {
 164         7, {
 165                 BIP_RANGE(10),
 166                 BIP_RANGE(5),
 167                 BIP_RANGE(2),
 168                 BIP_RANGE(1),
 169                 BIP_RANGE(0.5),
 170                 BIP_RANGE(0.2),
 171                 BIP_RANGE(0.1)
 172         }
 173 };
 174
 175 static const struct comedi_lrange range_ni_E_ao_ext = {
 176         4, {
 177                 BIP_RANGE(10),
 178                 UNI_RANGE(10),
 179                 RANGE_ext(-1, 1),
 180                 RANGE_ext(0, 1)
 181         }
 182 };
 183
 184 static const struct comedi_lrange *const ni_range_lkup[] = {
 185         [ai_gain_16] = &range_ni_E_ai,
 186         [ai_gain_8] = &range_ni_E_ai_limited,
 187         [ai_gain_14] = &range_ni_E_ai_limited14,
 188         [ai_gain_4] = &range_ni_E_ai_bipolar4,
 189         [ai_gain_611x] = &range_ni_E_ai_611x,
 190         [ai_gain_622x] = &range_ni_M_ai_622x,
 191         [ai_gain_628x] = &range_ni_M_ai_628x,
 192         [ai_gain_6143] = &range_bipolar5
 193 };
 194
 195 enum aimodes {
 196         AIMODE_NONE = 0,
 197         AIMODE_HALF_FULL = 1,
 198         AIMODE_SCAN = 2,
 199         AIMODE_SAMPLE = 3,
 200 };
 201
 202 enum ni_common_subdevices {
 203         NI_AI_SUBDEV,
 204         NI_AO_SUBDEV,
 205         NI_DIO_SUBDEV,
 206         NI_8255_DIO_SUBDEV,
 207         NI_UNUSED_SUBDEV,
 208         NI_CALIBRATION_SUBDEV,
 209         NI_EEPROM_SUBDEV,
 210         NI_PFI_DIO_SUBDEV,
 211         NI_CS5529_CALIBRATION_SUBDEV,
 212         NI_SERIAL_SUBDEV,
 213         NI_RTSI_SUBDEV,
 214         NI_GPCT0_SUBDEV,
 215         NI_GPCT1_SUBDEV,
 216         NI_FREQ_OUT_SUBDEV,
 217         NI_NUM_SUBDEVICES
 218 };
 219 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
 220 {
 221         switch (counter_index) {
 222         case 0:
 223                 return NI_GPCT0_SUBDEV;
 224         case 1:
 225                 return NI_GPCT1_SUBDEV;
 226         default:
 227                 break;
 228         }
 229         BUG();
 230         return NI_GPCT0_SUBDEV;
 231 }
 232
 233 enum timebase_nanoseconds {
 234         TIMEBASE_1_NS = 50,
 235         TIMEBASE_2_NS = 10000
 236 };
 237
 238 #define SERIAL_DISABLED         0
 239 #define SERIAL_600NS            600
 240 #define SERIAL_1_2US            1200
 241 #define SERIAL_10US                     10000
 242
 243 static const int num_adc_stages_611x = 3;
 244
 245 static void ni_writel(struct comedi_device *dev, uint32_t data, int reg)
 246 {
 247         if (dev->mmio)
 248                 writel(data, dev->mmio + reg);
 249         else
 250                 outl(data, dev->iobase + reg);
 251 }
 252
 253 static void ni_writew(struct comedi_device *dev, uint16_t data, int reg)
 254 {
 255         if (dev->mmio)
 256                 writew(data, dev->mmio + reg);
 257         else
 258                 outw(data, dev->iobase + reg);
 259 }
 260
 261 static void ni_writeb(struct comedi_device *dev, uint8_t data, int reg)
 262 {
 263         if (dev->mmio)
 264                 writeb(data, dev->mmio + reg);
 265         else
 266                 outb(data, dev->iobase + reg);
 267 }
 268
 269 static uint32_t ni_readl(struct comedi_device *dev, int reg)
 270 {
 271         if (dev->mmio)
 272                 return readl(dev->mmio + reg);
 273
 274         return inl(dev->iobase + reg);
 275 }
 276
 277 static uint16_t ni_readw(struct comedi_device *dev, int reg)
 278 {
 279         if (dev->mmio)
 280                 return readw(dev->mmio + reg);
 281
 282         return inw(dev->iobase + reg);
 283 }
 284
 285 static uint8_t ni_readb(struct comedi_device *dev, int reg)
 286 {
 287         if (dev->mmio)
 288                 return readb(dev->mmio + reg);
 289
 290         return inb(dev->iobase + reg);
 291 }
 292
 293 /*
 294  * We automatically take advantage of STC registers that can be
 295  * read/written directly in the I/O space of the board.
 296  *
 297  * The AT-MIO and DAQCard devices map the low 8 STC registers to
 298  * iobase+reg*2.
 299  *
 300  * Most PCIMIO devices also map the low 8 STC registers but the
 301  * 611x devices map the read registers to iobase+(addr-1)*2.
 302  * For now non-windowed STC access is disabled if a PCIMIO device
 303  * is detected (devpriv->mite has been initialized).
 304  *
 305  * The M series devices do not used windowed registers for the
 306  * STC registers. The functions below handle the mapping of the
 307  * windowed STC registers to the m series register offsets.
 308  */
 309
 310 struct mio_regmap {
 311         unsigned int mio_reg;
 312         int size;
 313 };
 314
 315 static const struct mio_regmap m_series_stc_write_regmap[] = {
 316         [NISTC_INTA_ACK_REG]            = { 0x104, 2 },
 317         [NISTC_INTB_ACK_REG]            = { 0x106, 2 },
 318         [NISTC_AI_CMD2_REG]             = { 0x108, 2 },
 319         [NISTC_AO_CMD2_REG]             = { 0x10a, 2 },
 320         [NISTC_G0_CMD_REG]              = { 0x10c, 2 },
 321         [NISTC_G1_CMD_REG]              = { 0x10e, 2 },
 322         [NISTC_AI_CMD1_REG]             = { 0x110, 2 },
 323         [NISTC_AO_CMD1_REG]             = { 0x112, 2 },
 324         /*
 325          * NISTC_DIO_OUT_REG maps to:
 326          * { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 }
 327          */
 328         [NISTC_DIO_OUT_REG]             = { 0, 0 }, /* DOES NOT MAP CLEANLY */
 329         [NISTC_DIO_CTRL_REG]            = { 0, 0 }, /* DOES NOT MAP CLEANLY */
 330         [NISTC_AI_MODE1_REG]            = { 0x118, 2 },
 331         [NISTC_AI_MODE2_REG]            = { 0x11a, 2 },
 332         [NISTC_AI_SI_LOADA_REG]         = { 0x11c, 4 },
 333         [NISTC_AI_SI_LOADB_REG]         = { 0x120, 4 },
 334         [NISTC_AI_SC_LOADA_REG]         = { 0x124, 4 },
 335         [NISTC_AI_SC_LOADB_REG]         = { 0x128, 4 },
 336         [NISTC_AI_SI2_LOADA_REG]        = { 0x12c, 4 },
 337         [NISTC_AI_SI2_LOADB_REG]        = { 0x130, 4 },
 338         [NISTC_G0_MODE_REG]             = { 0x134, 2 },
 339         [NISTC_G1_MODE_REG]             = { 0x136, 2 },
 340         [NISTC_G0_LOADA_REG]            = { 0x138, 4 },
 341         [NISTC_G0_LOADB_REG]            = { 0x13c, 4 },
 342         [NISTC_G1_LOADA_REG]            = { 0x140, 4 },
 343         [NISTC_G1_LOADB_REG]            = { 0x144, 4 },
 344         [NISTC_G0_INPUT_SEL_REG]        = { 0x148, 2 },
 345         [NISTC_G1_INPUT_SEL_REG]        = { 0x14a, 2 },
 346         [NISTC_AO_MODE1_REG]            = { 0x14c, 2 },
 347         [NISTC_AO_MODE2_REG]            = { 0x14e, 2 },
 348         [NISTC_AO_UI_LOADA_REG]         = { 0x150, 4 },
 349         [NISTC_AO_UI_LOADB_REG]         = { 0x154, 4 },
 350         [NISTC_AO_BC_LOADA_REG]         = { 0x158, 4 },
 351         [NISTC_AO_BC_LOADB_REG]         = { 0x15c, 4 },
 352         [NISTC_AO_UC_LOADA_REG]         = { 0x160, 4 },
 353         [NISTC_AO_UC_LOADB_REG]         = { 0x164, 4 },
 354         [NISTC_CLK_FOUT_REG]            = { 0x170, 2 },
 355         [NISTC_IO_BIDIR_PIN_REG]        = { 0x172, 2 },
 356         [NISTC_RTSI_TRIG_DIR_REG]       = { 0x174, 2 },
 357         [NISTC_INT_CTRL_REG]            = { 0x176, 2 },
 358         [NISTC_AI_OUT_CTRL_REG]         = { 0x178, 2 },
 359         [NISTC_ATRIG_ETC_REG]           = { 0x17a, 2 },
 360         [NISTC_AI_START_STOP_REG]       = { 0x17c, 2 },
 361         [NISTC_AI_TRIG_SEL_REG]         = { 0x17e, 2 },
 362         [NISTC_AI_DIV_LOADA_REG]        = { 0x180, 4 },
 363         [NISTC_AO_START_SEL_REG]        = { 0x184, 2 },
 364         [NISTC_AO_TRIG_SEL_REG]         = { 0x186, 2 },
 365         [NISTC_G0_AUTOINC_REG]          = { 0x188, 2 },
 366         [NISTC_G1_AUTOINC_REG]          = { 0x18a, 2 },
 367         [NISTC_AO_MODE3_REG]            = { 0x18c, 2 },
 368         [NISTC_RESET_REG]               = { 0x190, 2 },
 369         [NISTC_INTA_ENA_REG]            = { 0x192, 2 },
 370         [NISTC_INTA2_ENA_REG]           = { 0, 0 }, /* E-Series only */
 371         [NISTC_INTB_ENA_REG]            = { 0x196, 2 },
 372         [NISTC_INTB2_ENA_REG]           = { 0, 0 }, /* E-Series only */
 373         [NISTC_AI_PERSONAL_REG]         = { 0x19a, 2 },
 374         [NISTC_AO_PERSONAL_REG]         = { 0x19c, 2 },
 375         [NISTC_RTSI_TRIGA_OUT_REG]      = { 0x19e, 2 },
 376         [NISTC_RTSI_TRIGB_OUT_REG]      = { 0x1a0, 2 },
 377         [NISTC_RTSI_BOARD_REG]          = { 0, 0 }, /* Unknown */
 378         [NISTC_CFG_MEM_CLR_REG]         = { 0x1a4, 2 },
 379         [NISTC_ADC_FIFO_CLR_REG]        = { 0x1a6, 2 },
 380         [NISTC_DAC_FIFO_CLR_REG]        = { 0x1a8, 2 },
 381         [NISTC_AO_OUT_CTRL_REG]         = { 0x1ac, 2 },
 382         [NISTC_AI_MODE3_REG]            = { 0x1ae, 2 },
 383 };
 384
 385 static void m_series_stc_write(struct comedi_device *dev,
 386                                unsigned int data, unsigned int reg)
 387 {
 388         const struct mio_regmap *regmap;
 389
 390         if (reg < ARRAY_SIZE(m_series_stc_write_regmap)) {
 391                 regmap = &m_series_stc_write_regmap[reg];
 392         } else {
 393                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
 394                          __func__, reg);
 395                 return;
 396         }
 397
 398         switch (regmap->size) {
 399         case 4:
 400                 ni_writel(dev, data, regmap->mio_reg);
 401                 break;
 402         case 2:
 403                 ni_writew(dev, data, regmap->mio_reg);
 404                 break;
 405         default:
 406                 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
 407                          __func__, reg);
 408                 break;
 409         }
 410 }
 411
 412 static const struct mio_regmap m_series_stc_read_regmap[] = {
 413         [NISTC_AI_STATUS1_REG]          = { 0x104, 2 },
 414         [NISTC_AO_STATUS1_REG]          = { 0x106, 2 },
 415         [NISTC_G01_STATUS_REG]          = { 0x108, 2 },
 416         [NISTC_AI_STATUS2_REG]          = { 0, 0 }, /* Unknown */
 417         [NISTC_AO_STATUS2_REG]          = { 0x10c, 2 },
 418         [NISTC_DIO_IN_REG]              = { 0, 0 }, /* Unknown */
 419         [NISTC_G0_HW_SAVE_REG]          = { 0x110, 4 },
 420         [NISTC_G1_HW_SAVE_REG]          = { 0x114, 4 },
 421         [NISTC_G0_SAVE_REG]             = { 0x118, 4 },
 422         [NISTC_G1_SAVE_REG]             = { 0x11c, 4 },
 423         [NISTC_AO_UI_SAVE_REG]          = { 0x120, 4 },
 424         [NISTC_AO_BC_SAVE_REG]          = { 0x124, 4 },
 425         [NISTC_AO_UC_SAVE_REG]          = { 0x128, 4 },
 426         [NISTC_STATUS1_REG]             = { 0x136, 2 },
 427         [NISTC_DIO_SERIAL_IN_REG]       = { 0x009, 1 },
 428         [NISTC_STATUS2_REG]             = { 0x13a, 2 },
 429         [NISTC_AI_SI_SAVE_REG]          = { 0x180, 4 },
 430         [NISTC_AI_SC_SAVE_REG]          = { 0x184, 4 },
 431 };
 432
 433 static unsigned int m_series_stc_read(struct comedi_device *dev,
 434                                       unsigned int reg)
 435 {
 436         const struct mio_regmap *regmap;
 437
 438         if (reg < ARRAY_SIZE(m_series_stc_read_regmap)) {
 439                 regmap = &m_series_stc_read_regmap[reg];
 440         } else {
 441                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
 442                          __func__, reg);
 443                 return 0;
 444         }
 445
 446         switch (regmap->size) {
 447         case 4:
 448                 return ni_readl(dev, regmap->mio_reg);
 449         case 2:
 450                 return ni_readw(dev, regmap->mio_reg);
 451         case 1:
 452                 return ni_readb(dev, regmap->mio_reg);
 453         default:
 454                 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
 455                          __func__, reg);
 456                 return 0;
 457         }
 458 }
 459
 460 static void ni_stc_writew(struct comedi_device *dev, uint16_t data, int reg)
 461 {
 462         struct ni_private *devpriv = dev->private;
 463         unsigned long flags;
 464
 465         if (devpriv->is_m_series) {
 466                 m_series_stc_write(dev, data, reg);
 467         } else {
 468                 spin_lock_irqsave(&devpriv->window_lock, flags);
 469                 if (!devpriv->mite && reg < 8) {
 470                         ni_writew(dev, data, reg * 2);
 471                 } else {
 472                         ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
 473                         ni_writew(dev, data, NI_E_STC_WINDOW_DATA_REG);
 474                 }
 475                 spin_unlock_irqrestore(&devpriv->window_lock, flags);
 476         }
 477 }
 478
 479 static void ni_stc_writel(struct comedi_device *dev, uint32_t data, int reg)
 480 {
 481         struct ni_private *devpriv = dev->private;
 482
 483         if (devpriv->is_m_series) {
 484                 m_series_stc_write(dev, data, reg);
 485         } else {
 486                 ni_stc_writew(dev, data >> 16, reg);
 487                 ni_stc_writew(dev, data & 0xffff, reg + 1);
 488         }
 489 }
 490
 491 static uint16_t ni_stc_readw(struct comedi_device *dev, int reg)
 492 {
 493         struct ni_private *devpriv = dev->private;
 494         unsigned long flags;
 495         uint16_t val;
 496
 497         if (devpriv->is_m_series) {
 498                 val = m_series_stc_read(dev, reg);
 499         } else {
 500                 spin_lock_irqsave(&devpriv->window_lock, flags);
 501                 if (!devpriv->mite && reg < 8) {
 502                         val = ni_readw(dev, reg * 2);
 503                 } else {
 504                         ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
 505                         val = ni_readw(dev, NI_E_STC_WINDOW_DATA_REG);
 506                 }
 507                 spin_unlock_irqrestore(&devpriv->window_lock, flags);
 508         }
 509         return val;
 510 }
 511
 512 static uint32_t ni_stc_readl(struct comedi_device *dev, int reg)
 513 {
 514         struct ni_private *devpriv = dev->private;
 515         uint32_t val;
 516
 517         if (devpriv->is_m_series) {
 518                 val = m_series_stc_read(dev, reg);
 519         } else {
 520                 val = ni_stc_readw(dev, reg) << 16;
 521                 val |= ni_stc_readw(dev, reg + 1);
 522         }
 523         return val;
 524 }
 525
 526 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
 527                                    unsigned bit_mask, unsigned bit_values)
 528 {
 529         struct ni_private *devpriv = dev->private;
 530         unsigned long flags;
 531
 532         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 533         switch (reg) {
 534         case NISTC_INTA_ENA_REG:
 535                 devpriv->int_a_enable_reg &= ~bit_mask;
 536                 devpriv->int_a_enable_reg |= bit_values & bit_mask;
 537                 ni_stc_writew(dev, devpriv->int_a_enable_reg, reg);
 538                 break;
 539         case NISTC_INTB_ENA_REG:
 540                 devpriv->int_b_enable_reg &= ~bit_mask;
 541                 devpriv->int_b_enable_reg |= bit_values & bit_mask;
 542                 ni_stc_writew(dev, devpriv->int_b_enable_reg, reg);
 543                 break;
 544         case NISTC_IO_BIDIR_PIN_REG:
 545                 devpriv->io_bidirection_pin_reg &= ~bit_mask;
 546                 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
 547                 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg);
 548                 break;
 549         case NI_E_DMA_AI_AO_SEL_REG:
 550                 devpriv->ai_ao_select_reg &= ~bit_mask;
 551                 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
 552                 ni_writeb(dev, devpriv->ai_ao_select_reg, reg);
 553                 break;
 554         case NI_E_DMA_G0_G1_SEL_REG:
 555                 devpriv->g0_g1_select_reg &= ~bit_mask;
 556                 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
 557                 ni_writeb(dev, devpriv->g0_g1_select_reg, reg);
 558                 break;
 559         default:
 560                 dev_err(dev->class_dev, "called with invalid register %d\n",
 561                         reg);
 562                 break;
 563         }
 564         mmiowb();
 565         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 566 }
 567
 568 #ifdef PCIDMA
 569 /* DMA channel setup */
 570 static inline unsigned ni_stc_dma_channel_select_bitfield(unsigned channel)
 571 {
 572         if (channel < 4)
 573                 return 1 << channel;
 574         if (channel == 4)
 575                 return 0x3;
 576         if (channel == 5)
 577                 return 0x5;
 578         BUG();
 579         return 0;
 580 }
 581
 582 /* negative channel means no channel */
 583 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
 584 {
 585         unsigned bits = 0;
 586
 587         if (channel >= 0)
 588                 bits = ni_stc_dma_channel_select_bitfield(channel);
 589
 590         ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 591                         NI_E_DMA_AI_SEL_MASK, NI_E_DMA_AI_SEL(bits));
 592 }
 593
 594 /* negative channel means no channel */
 595 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
 596 {
 597         unsigned bits = 0;
 598
 599         if (channel >= 0)
 600                 bits = ni_stc_dma_channel_select_bitfield(channel);
 601
 602         ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 603                         NI_E_DMA_AO_SEL_MASK, NI_E_DMA_AO_SEL(bits));
 604 }
 605
 606 /* negative channel means no channel */
 607 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
 608                                            unsigned gpct_index,
 609                                            int channel)
 610 {
 611         unsigned bits = 0;
 612
 613         if (channel >= 0)
 614                 bits = ni_stc_dma_channel_select_bitfield(channel);
 615
 616         ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
 617                         NI_E_DMA_G0_G1_SEL_MASK(gpct_index),
 618                         NI_E_DMA_G0_G1_SEL(gpct_index, bits));
 619 }
 620
 621 /* negative mite_channel means no channel */
 622 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
 623                                           int mite_channel)
 624 {
 625         struct ni_private *devpriv = dev->private;
 626         unsigned long flags;
 627         unsigned bits;
 628
 629         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 630         devpriv->cdio_dma_select_reg &= ~NI_M_CDIO_DMA_SEL_CDO_MASK;
 631         if (mite_channel >= 0) {
 632                 /*
 633                  * XXX just guessing ni_stc_dma_channel_select_bitfield()
 634                  * returns the right bits, under the assumption the cdio dma
 635                  * selection works just like ai/ao/gpct.
 636                  * Definitely works for dma channels 0 and 1.
 637                  */
 638                 bits = ni_stc_dma_channel_select_bitfield(mite_channel);
 639                 devpriv->cdio_dma_select_reg |= NI_M_CDIO_DMA_SEL_CDO(bits);
 640         }
 641         ni_writeb(dev, devpriv->cdio_dma_select_reg, NI_M_CDIO_DMA_SEL_REG);
 642         mmiowb();
 643         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 644 }
 645
 646 static int ni_request_ai_mite_channel(struct comedi_device *dev)
 647 {
 648         struct ni_private *devpriv = dev->private;
 649         unsigned long flags;
 650
 651         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 652         BUG_ON(devpriv->ai_mite_chan);
 653         devpriv->ai_mite_chan =
 654             mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
 655         if (!devpriv->ai_mite_chan) {
 656                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 657                 dev_err(dev->class_dev,
 658                         "failed to reserve mite dma channel for analog input\n");
 659                 return -EBUSY;
 660         }
 661         devpriv->ai_mite_chan->dir = COMEDI_INPUT;
 662         ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
 663         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 664         return 0;
 665 }
 666
 667 static int ni_request_ao_mite_channel(struct comedi_device *dev)
 668 {
 669         struct ni_private *devpriv = dev->private;
 670         unsigned long flags;
 671
 672         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 673         BUG_ON(devpriv->ao_mite_chan);
 674         devpriv->ao_mite_chan =
 675             mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
 676         if (!devpriv->ao_mite_chan) {
 677                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 678                 dev_err(dev->class_dev,
 679                         "failed to reserve mite dma channel for analog outut\n");
 680                 return -EBUSY;
 681         }
 682         devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
 683         ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
 684         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 685         return 0;
 686 }
 687
 688 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
 689                                         unsigned gpct_index,
 690                                         enum comedi_io_direction direction)
 691 {
 692         struct ni_private *devpriv = dev->private;
 693         unsigned long flags;
 694         struct mite_channel *mite_chan;
 695
 696         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 697         BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
 698         mite_chan =
 699             mite_request_channel(devpriv->mite,
 700                                  devpriv->gpct_mite_ring[gpct_index]);
 701         if (!mite_chan) {
 702                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 703                 dev_err(dev->class_dev,
 704                         "failed to reserve mite dma channel for counter\n");
 705                 return -EBUSY;
 706         }
 707         mite_chan->dir = direction;
 708         ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
 709                                 mite_chan);
 710         ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
 711         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 712         return 0;
 713 }
 714
 715 #endif /*  PCIDMA */
 716
 717 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
 718 {
 719 #ifdef PCIDMA
 720         struct ni_private *devpriv = dev->private;
 721         unsigned long flags;
 722
 723         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 724         BUG_ON(devpriv->cdo_mite_chan);
 725         devpriv->cdo_mite_chan =
 726             mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
 727         if (!devpriv->cdo_mite_chan) {
 728                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 729                 dev_err(dev->class_dev,
 730                         "failed to reserve mite dma channel for correlated digital output\n");
 731                 return -EBUSY;
 732         }
 733         devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
 734         ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
 735         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 736 #endif /*  PCIDMA */
 737         return 0;
 738 }
 739
 740 static void ni_release_ai_mite_channel(struct comedi_device *dev)
 741 {
 742 #ifdef PCIDMA
 743         struct ni_private *devpriv = dev->private;
 744         unsigned long flags;
 745
 746         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 747         if (devpriv->ai_mite_chan) {
 748                 ni_set_ai_dma_channel(dev, -1);
 749                 mite_release_channel(devpriv->ai_mite_chan);
 750                 devpriv->ai_mite_chan = NULL;
 751         }
 752         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 753 #endif /*  PCIDMA */
 754 }
 755
 756 static void ni_release_ao_mite_channel(struct comedi_device *dev)
 757 {
 758 #ifdef PCIDMA
 759         struct ni_private *devpriv = dev->private;
 760         unsigned long flags;
 761
 762         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 763         if (devpriv->ao_mite_chan) {
 764                 ni_set_ao_dma_channel(dev, -1);
 765                 mite_release_channel(devpriv->ao_mite_chan);
 766                 devpriv->ao_mite_chan = NULL;
 767         }
 768         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 769 #endif /*  PCIDMA */
 770 }
 771
 772 #ifdef PCIDMA
 773 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
 774                                          unsigned gpct_index)
 775 {
 776         struct ni_private *devpriv = dev->private;
 777         unsigned long flags;
 778
 779         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 780         if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
 781                 struct mite_channel *mite_chan =
 782                     devpriv->counter_dev->counters[gpct_index].mite_chan;
 783
 784                 ni_set_gpct_dma_channel(dev, gpct_index, -1);
 785                 ni_tio_set_mite_channel(&devpriv->
 786                                         counter_dev->counters[gpct_index],
 787                                         NULL);
 788                 mite_release_channel(mite_chan);
 789         }
 790         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 791 }
 792 #endif /*  PCIDMA */
 793
 794 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
 795 {
 796 #ifdef PCIDMA
 797         struct ni_private *devpriv = dev->private;
 798         unsigned long flags;
 799
 800         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 801         if (devpriv->cdo_mite_chan) {
 802                 ni_set_cdo_dma_channel(dev, -1);
 803                 mite_release_channel(devpriv->cdo_mite_chan);
 804                 devpriv->cdo_mite_chan = NULL;
 805         }
 806         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 807 #endif /*  PCIDMA */
 808 }
 809
 810 #ifdef PCIDMA
 811 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
 812                                           unsigned gpct_index, short enable)
 813 {
 814         struct ni_private *devpriv = dev->private;
 815         uint16_t val = 0;
 816         int reg;
 817
 818         if (devpriv->is_m_series || gpct_index > 1)
 819                 return;
 820
 821         /*
 822          * e-series boards use the second irq signals to generate
 823          * dma requests for their counters
 824          */
 825         if (gpct_index == 0) {
 826                 reg = NISTC_INTA2_ENA_REG;
 827                 if (enable)
 828                         val = NISTC_INTA_ENA_G0_GATE;
 829         } else {
 830                 reg = NISTC_INTB2_ENA_REG;
 831                 if (enable)
 832                         val = NISTC_INTB_ENA_G1_GATE;
 833         }
 834         ni_stc_writew(dev, val, reg);
 835 }
 836 #endif /*  PCIDMA */
 837
 838 static void ni_clear_ai_fifo(struct comedi_device *dev)
 839 {
 840         struct ni_private *devpriv = dev->private;
 841         static const int timeout = 10000;
 842         int i;
 843
 844         if (devpriv->is_6143) {
 845                 /*  Flush the 6143 data FIFO */
 846                 ni_writel(dev, 0x10, NI6143_AI_FIFO_CTRL_REG);
 847                 ni_writel(dev, 0x00, NI6143_AI_FIFO_CTRL_REG);
 848                 /*  Wait for complete */
 849                 for (i = 0; i < timeout; i++) {
 850                         if (!(ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x10))
 851                                 break;
 852                         udelay(1);
 853                 }
 854                 if (i == timeout)
 855                         dev_err(dev->class_dev, "FIFO flush timeout\n");
 856         } else {
 857                 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
 858                 if (devpriv->is_625x) {
 859                         ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0));
 860                         ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0));
 861 #if 0
 862                         /* the NI example code does 3 convert pulses for 625x boards,
 863                            but that appears to be wrong in practice. */
 864                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 865                                       NISTC_AI_CMD1_REG);
 866                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 867                                       NISTC_AI_CMD1_REG);
 868                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 869                                       NISTC_AI_CMD1_REG);
 870 #endif
 871                 }
 872         }
 873 }
 874
 875 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
 876                                   int addr)
 877 {
 878         struct ni_private *devpriv = dev->private;
 879         unsigned long flags;
 880
 881         spin_lock_irqsave(&devpriv->window_lock, flags);
 882         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 883         ni_writew(dev, data, NI611X_AO_WINDOW_DATA_REG);
 884         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 885 }
 886
 887 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
 888                                   int addr)
 889 {
 890         struct ni_private *devpriv = dev->private;
 891         unsigned long flags;
 892
 893         spin_lock_irqsave(&devpriv->window_lock, flags);
 894         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 895         ni_writel(dev, data, NI611X_AO_WINDOW_DATA_REG);
 896         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 897 }
 898
 899 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
 900 {
 901         struct ni_private *devpriv = dev->private;
 902         unsigned long flags;
 903         unsigned short data;
 904
 905         spin_lock_irqsave(&devpriv->window_lock, flags);
 906         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 907         data = ni_readw(dev, NI611X_AO_WINDOW_DATA_REG);
 908         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 909         return data;
 910 }
 911
 912 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 913 * share registers (such as Interrupt_A_Register) without interfering with
 914 * each other.
 915 *
 916 * NOTE: the switch/case statements are optimized out for a constant argument
 917 * so this is actually quite fast---  If you must wrap another function around this
 918 * make it inline to avoid a large speed penalty.
 919 *
 920 * value should only be 1 or 0.
 921 */
 922 static inline void ni_set_bits(struct comedi_device *dev, int reg,
 923                                unsigned bits, unsigned value)
 924 {
 925         unsigned bit_values;
 926
 927         if (value)
 928                 bit_values = bits;
 929         else
 930                 bit_values = 0;
 931         ni_set_bitfield(dev, reg, bits, bit_values);
 932 }
 933
 934 #ifdef PCIDMA
 935 static void ni_sync_ai_dma(struct comedi_device *dev)
 936 {
 937         struct ni_private *devpriv = dev->private;
 938         struct comedi_subdevice *s = dev->read_subdev;
 939         unsigned long flags;
 940
 941         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 942         if (devpriv->ai_mite_chan)
 943                 mite_sync_input_dma(devpriv->ai_mite_chan, s);
 944         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 945 }
 946
 947 static int ni_ai_drain_dma(struct comedi_device *dev)
 948 {
 949         struct ni_private *devpriv = dev->private;
 950         int i;
 951         static const int timeout = 10000;
 952         unsigned long flags;
 953         int retval = 0;
 954
 955         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 956         if (devpriv->ai_mite_chan) {
 957                 for (i = 0; i < timeout; i++) {
 958                         if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
 959                              NISTC_AI_STATUS1_FIFO_E)
 960                             && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
 961                             0)
 962                                 break;
 963                         udelay(5);
 964                 }
 965                 if (i == timeout) {
 966                         dev_err(dev->class_dev, "timed out\n");
 967                         dev_err(dev->class_dev,
 968                                 "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
 969                                 mite_bytes_in_transit(devpriv->ai_mite_chan),
 970                                 ni_stc_readw(dev, NISTC_AI_STATUS1_REG));
 971                         retval = -1;
 972                 }
 973         }
 974         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 975
 976         ni_sync_ai_dma(dev);
 977
 978         return retval;
 979 }
 980
 981 static void mite_handle_b_linkc(struct mite_struct *mite,
 982                                 struct comedi_device *dev)
 983 {
 984         struct ni_private *devpriv = dev->private;
 985         struct comedi_subdevice *s = dev->write_subdev;
 986         unsigned long flags;
 987
 988         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 989         if (devpriv->ao_mite_chan)
 990                 mite_sync_output_dma(devpriv->ao_mite_chan, s);
 991         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 992 }
 993
 994 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
 995 {
 996         static const int timeout = 10000;
 997         int i;
 998
 999         for (i = 0; i < timeout; i++) {
1000                 unsigned short b_status;
1001
1002                 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
1003                 if (b_status & NISTC_AO_STATUS1_FIFO_HF)
1004                         break;
1005                 /* if we poll too often, the pci bus activity seems
1006                    to slow the dma transfer down */
1007                 udelay(10);
1008         }
1009         if (i == timeout) {
1010                 dev_err(dev->class_dev, "timed out waiting for dma load\n");
1011                 return -EPIPE;
1012         }
1013         return 0;
1014 }
1015 #endif /* PCIDMA */
1016
1017 #ifndef PCIDMA
1018
1019 static void ni_ao_fifo_load(struct comedi_device *dev,
1020                             struct comedi_subdevice *s, int n)
1021 {
1022         struct ni_private *devpriv = dev->private;
1023         int i;
1024         unsigned short d;
1025         u32 packed_data;
1026
1027         for (i = 0; i < n; i++) {
1028                 comedi_buf_read_samples(s, &d, 1);
1029
1030                 if (devpriv->is_6xxx) {
1031                         packed_data = d & 0xffff;
1032                         /* 6711 only has 16 bit wide ao fifo */
1033                         if (!devpriv->is_6711) {
1034                                 comedi_buf_read_samples(s, &d, 1);
1035                                 i++;
1036                                 packed_data |= (d << 16) & 0xffff0000;
1037                         }
1038                         ni_writel(dev, packed_data, NI611X_AO_FIFO_DATA_REG);
1039                 } else {
1040                         ni_writew(dev, d, NI_E_AO_FIFO_DATA_REG);
1041                 }
1042         }
1043 }
1044
1045 /*
1046  *  There's a small problem if the FIFO gets really low and we
1047  *  don't have the data to fill it.  Basically, if after we fill
1048  *  the FIFO with all the data available, the FIFO is _still_
1049  *  less than half full, we never clear the interrupt.  If the
1050  *  IRQ is in edge mode, we never get another interrupt, because
1051  *  this one wasn't cleared.  If in level mode, we get flooded
1052  *  with interrupts that we can't fulfill, because nothing ever
1053  *  gets put into the buffer.
1054  *
1055  *  This kind of situation is recoverable, but it is easier to
1056  *  just pretend we had a FIFO underrun, since there is a good
1057  *  chance it will happen anyway.  This is _not_ the case for
1058  *  RT code, as RT code might purposely be running close to the
1059  *  metal.  Needs to be fixed eventually.
1060  */
1061 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1062                                  struct comedi_subdevice *s)
1063 {
1064         const struct ni_board_struct *board = dev->board_ptr;
1065         unsigned int nbytes;
1066         unsigned int nsamples;
1067
1068         nbytes = comedi_buf_read_n_available(s);
1069         if (nbytes == 0) {
1070                 s->async->events |= COMEDI_CB_OVERFLOW;
1071                 return 0;
1072         }
1073
1074         nsamples = comedi_bytes_to_samples(s, nbytes);
1075         if (nsamples > board->ao_fifo_depth / 2)
1076                 nsamples = board->ao_fifo_depth / 2;
1077
1078         ni_ao_fifo_load(dev, s, nsamples);
1079
1080         return 1;
1081 }
1082
1083 static int ni_ao_prep_fifo(struct comedi_device *dev,
1084                            struct comedi_subdevice *s)
1085 {
1086         const struct ni_board_struct *board = dev->board_ptr;
1087         struct ni_private *devpriv = dev->private;
1088         unsigned int nbytes;
1089         unsigned int nsamples;
1090
1091         /* reset fifo */
1092         ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
1093         if (devpriv->is_6xxx)
1094                 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
1095
1096         /* load some data */
1097         nbytes = comedi_buf_read_n_available(s);
1098         if (nbytes == 0)
1099                 return 0;
1100
1101         nsamples = comedi_bytes_to_samples(s, nbytes);
1102         if (nsamples > board->ao_fifo_depth)
1103                 nsamples = board->ao_fifo_depth;
1104
1105         ni_ao_fifo_load(dev, s, nsamples);
1106
1107         return nsamples;
1108 }
1109
1110 static void ni_ai_fifo_read(struct comedi_device *dev,
1111                             struct comedi_subdevice *s, int n)
1112 {
1113         struct ni_private *devpriv = dev->private;
1114         struct comedi_async *async = s->async;
1115         u32 dl;
1116         unsigned short data;
1117         int i;
1118
1119         if (devpriv->is_611x) {
1120                 for (i = 0; i < n / 2; i++) {
1121                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1122                         /* This may get the hi/lo data in the wrong order */
1123                         data = (dl >> 16) & 0xffff;
1124                         comedi_buf_write_samples(s, &data, 1);
1125                         data = dl & 0xffff;
1126                         comedi_buf_write_samples(s, &data, 1);
1127                 }
1128                 /* Check if there's a single sample stuck in the FIFO */
1129                 if (n % 2) {
1130                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1131                         data = dl & 0xffff;
1132                         comedi_buf_write_samples(s, &data, 1);
1133                 }
1134         } else if (devpriv->is_6143) {
1135                 /*  This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1136                 for (i = 0; i < n / 2; i++) {
1137                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1138
1139                         data = (dl >> 16) & 0xffff;
1140                         comedi_buf_write_samples(s, &data, 1);
1141                         data = dl & 0xffff;
1142                         comedi_buf_write_samples(s, &data, 1);
1143                 }
1144                 if (n % 2) {
1145                         /* Assume there is a single sample stuck in the FIFO */
1146                         /* Get stranded sample into FIFO */
1147                         ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1148                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1149                         data = (dl >> 16) & 0xffff;
1150                         comedi_buf_write_samples(s, &data, 1);
1151                 }
1152         } else {
1153                 if (n > sizeof(devpriv->ai_fifo_buffer) /
1154                     sizeof(devpriv->ai_fifo_buffer[0])) {
1155                         dev_err(dev->class_dev,
1156                                 "bug! ai_fifo_buffer too small\n");
1157                         async->events |= COMEDI_CB_ERROR;
1158                         return;
1159                 }
1160                 for (i = 0; i < n; i++) {
1161                         devpriv->ai_fifo_buffer[i] =
1162                             ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1163                 }
1164                 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n);
1165         }
1166 }
1167
1168 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1169 {
1170         const struct ni_board_struct *board = dev->board_ptr;
1171         struct comedi_subdevice *s = dev->read_subdev;
1172         int n;
1173
1174         n = board->ai_fifo_depth / 2;
1175
1176         ni_ai_fifo_read(dev, s, n);
1177 }
1178 #endif
1179
1180 /*
1181    Empties the AI fifo
1182 */
1183 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1184 {
1185         struct ni_private *devpriv = dev->private;
1186         struct comedi_subdevice *s = dev->read_subdev;
1187         u32 dl;
1188         unsigned short data;
1189         unsigned short fifo_empty;
1190         int i;
1191
1192         if (devpriv->is_611x) {
1193                 while ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1194                         NISTC_AI_STATUS1_FIFO_E) == 0) {
1195                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1196
1197                         /* This may get the hi/lo data in the wrong order */
1198                         data = dl >> 16;
1199                         comedi_buf_write_samples(s, &data, 1);
1200                         data = dl & 0xffff;
1201                         comedi_buf_write_samples(s, &data, 1);
1202                 }
1203         } else if (devpriv->is_6143) {
1204                 i = 0;
1205                 while (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x04) {
1206                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1207
1208                         /* This may get the hi/lo data in the wrong order */
1209                         data = dl >> 16;
1210                         comedi_buf_write_samples(s, &data, 1);
1211                         data = dl & 0xffff;
1212                         comedi_buf_write_samples(s, &data, 1);
1213                         i += 2;
1214                 }
1215                 /*  Check if stranded sample is present */
1216                 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1217                         /* Get stranded sample into FIFO */
1218                         ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1219                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1220                         data = (dl >> 16) & 0xffff;
1221                         comedi_buf_write_samples(s, &data, 1);
1222                 }
1223
1224         } else {
1225                 fifo_empty = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1226                              NISTC_AI_STATUS1_FIFO_E;
1227                 while (fifo_empty == 0) {
1228                         for (i = 0;
1229                              i <
1230                              sizeof(devpriv->ai_fifo_buffer) /
1231                              sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1232                                 fifo_empty = ni_stc_readw(dev,
1233                                                           NISTC_AI_STATUS1_REG) &
1234                                                 NISTC_AI_STATUS1_FIFO_E;
1235                                 if (fifo_empty)
1236                                         break;
1237                                 devpriv->ai_fifo_buffer[i] =
1238                                     ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1239                         }
1240                         comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i);
1241                 }
1242         }
1243 }
1244
1245 static void get_last_sample_611x(struct comedi_device *dev)
1246 {
1247         struct ni_private *devpriv = dev->private;
1248         struct comedi_subdevice *s = dev->read_subdev;
1249         unsigned short data;
1250         u32 dl;
1251
1252         if (!devpriv->is_611x)
1253                 return;
1254
1255         /* Check if there's a single sample stuck in the FIFO */
1256         if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1257                 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1258                 data = dl & 0xffff;
1259                 comedi_buf_write_samples(s, &data, 1);
1260         }
1261 }
1262
1263 static void get_last_sample_6143(struct comedi_device *dev)
1264 {
1265         struct ni_private *devpriv = dev->private;
1266         struct comedi_subdevice *s = dev->read_subdev;
1267         unsigned short data;
1268         u32 dl;
1269
1270         if (!devpriv->is_6143)
1271                 return;
1272
1273         /* Check if there's a single sample stuck in the FIFO */
1274         if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1275                 /* Get stranded sample into FIFO */
1276                 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1277                 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1278
1279                 /* This may get the hi/lo data in the wrong order */
1280                 data = (dl >> 16) & 0xffff;
1281                 comedi_buf_write_samples(s, &data, 1);
1282         }
1283 }
1284
1285 static void shutdown_ai_command(struct comedi_device *dev)
1286 {
1287         struct comedi_subdevice *s = dev->read_subdev;
1288
1289 #ifdef PCIDMA
1290         ni_ai_drain_dma(dev);
1291 #endif
1292         ni_handle_fifo_dregs(dev);
1293         get_last_sample_611x(dev);
1294         get_last_sample_6143(dev);
1295
1296         s->async->events |= COMEDI_CB_EOA;
1297 }
1298
1299 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
1300 {
1301         struct ni_private *devpriv = dev->private;
1302
1303         if (devpriv->aimode == AIMODE_SCAN) {
1304 #ifdef PCIDMA
1305                 static const int timeout = 10;
1306                 int i;
1307
1308                 for (i = 0; i < timeout; i++) {
1309                         ni_sync_ai_dma(dev);
1310                         if ((s->async->events & COMEDI_CB_EOS))
1311                                 break;
1312                         udelay(1);
1313                 }
1314 #else
1315                 ni_handle_fifo_dregs(dev);
1316                 s->async->events |= COMEDI_CB_EOS;
1317 #endif
1318         }
1319         /* handle special case of single scan */
1320         if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)
1321                 shutdown_ai_command(dev);
1322 }
1323
1324 static void handle_gpct_interrupt(struct comedi_device *dev,
1325                                   unsigned short counter_index)
1326 {
1327 #ifdef PCIDMA
1328         struct ni_private *devpriv = dev->private;
1329         struct comedi_subdevice *s;
1330
1331         s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1332
1333         ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1334                                 s);
1335         comedi_handle_events(dev, s);
1336 #endif
1337 }
1338
1339 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1340 {
1341         unsigned short ack = 0;
1342
1343         if (a_status & NISTC_AI_STATUS1_SC_TC)
1344                 ack |= NISTC_INTA_ACK_AI_SC_TC;
1345         if (a_status & NISTC_AI_STATUS1_START1)
1346                 ack |= NISTC_INTA_ACK_AI_START1;
1347         if (a_status & NISTC_AI_STATUS1_START)
1348                 ack |= NISTC_INTA_ACK_AI_START;
1349         if (a_status & NISTC_AI_STATUS1_STOP)
1350                 ack |= NISTC_INTA_ACK_AI_STOP;
1351         if (a_status & NISTC_AI_STATUS1_OVER)
1352                 ack |= NISTC_INTA_ACK_AI_ERR;
1353         if (ack)
1354                 ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG);
1355 }
1356
1357 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1358                                unsigned ai_mite_status)
1359 {
1360         struct comedi_subdevice *s = dev->read_subdev;
1361         struct comedi_cmd *cmd = &s->async->cmd;
1362
1363         /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1364         if (s->type == COMEDI_SUBD_UNUSED)
1365                 return;
1366
1367 #ifdef PCIDMA
1368         if (ai_mite_status & CHSR_LINKC)
1369                 ni_sync_ai_dma(dev);
1370
1371         if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1372                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1373                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1374                 dev_err(dev->class_dev,
1375                         "unknown mite interrupt (ai_mite_status=%08x)\n",
1376                         ai_mite_status);
1377                 s->async->events |= COMEDI_CB_ERROR;
1378                 /* disable_irq(dev->irq); */
1379         }
1380 #endif
1381
1382         /* test for all uncommon interrupt events at the same time */
1383         if (status & (NISTC_AI_STATUS1_ERR |
1384                       NISTC_AI_STATUS1_SC_TC | NISTC_AI_STATUS1_START1)) {
1385                 if (status == 0xffff) {
1386                         dev_err(dev->class_dev, "Card removed?\n");
1387                         /* we probably aren't even running a command now,
1388                          * so it's a good idea to be careful. */
1389                         if (comedi_is_subdevice_running(s)) {
1390                                 s->async->events |= COMEDI_CB_ERROR;
1391                                 comedi_handle_events(dev, s);
1392                         }
1393                         return;
1394                 }
1395                 if (status & NISTC_AI_STATUS1_ERR) {
1396                         dev_err(dev->class_dev, "ai error a_status=%04x\n",
1397                                 status);
1398
1399                         shutdown_ai_command(dev);
1400
1401                         s->async->events |= COMEDI_CB_ERROR;
1402                         if (status & NISTC_AI_STATUS1_OVER)
1403                                 s->async->events |= COMEDI_CB_OVERFLOW;
1404
1405                         comedi_handle_events(dev, s);
1406                         return;
1407                 }
1408                 if (status & NISTC_AI_STATUS1_SC_TC) {
1409                         if (cmd->stop_src == TRIG_COUNT)
1410                                 shutdown_ai_command(dev);
1411                 }
1412         }
1413 #ifndef PCIDMA
1414         if (status & NISTC_AI_STATUS1_FIFO_HF) {
1415                 int i;
1416                 static const int timeout = 10;
1417                 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1418                  *fail to get the fifo less than half full, so loop to be sure.*/
1419                 for (i = 0; i < timeout; ++i) {
1420                         ni_handle_fifo_half_full(dev);
1421                         if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1422                              NISTC_AI_STATUS1_FIFO_HF) == 0)
1423                                 break;
1424                 }
1425         }
1426 #endif /*  !PCIDMA */
1427
1428         if (status & NISTC_AI_STATUS1_STOP)
1429                 ni_handle_eos(dev, s);
1430
1431         comedi_handle_events(dev, s);
1432 }
1433
1434 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1435 {
1436         unsigned short ack = 0;
1437
1438         if (b_status & NISTC_AO_STATUS1_BC_TC)
1439                 ack |= NISTC_INTB_ACK_AO_BC_TC;
1440         if (b_status & NISTC_AO_STATUS1_OVERRUN)
1441                 ack |= NISTC_INTB_ACK_AO_ERR;
1442         if (b_status & NISTC_AO_STATUS1_START)
1443                 ack |= NISTC_INTB_ACK_AO_START;
1444         if (b_status & NISTC_AO_STATUS1_START1)
1445                 ack |= NISTC_INTB_ACK_AO_START1;
1446         if (b_status & NISTC_AO_STATUS1_UC_TC)
1447                 ack |= NISTC_INTB_ACK_AO_UC_TC;
1448         if (b_status & NISTC_AO_STATUS1_UI2_TC)
1449                 ack |= NISTC_INTB_ACK_AO_UI2_TC;
1450         if (b_status & NISTC_AO_STATUS1_UPDATE)
1451                 ack |= NISTC_INTB_ACK_AO_UPDATE;
1452         if (ack)
1453                 ni_stc_writew(dev, ack, NISTC_INTB_ACK_REG);
1454 }
1455
1456 static void handle_b_interrupt(struct comedi_device *dev,
1457                                unsigned short b_status, unsigned ao_mite_status)
1458 {
1459         struct comedi_subdevice *s = dev->write_subdev;
1460         /* unsigned short ack=0; */
1461
1462 #ifdef PCIDMA
1463         /* Currently, mite.c requires us to handle LINKC */
1464         if (ao_mite_status & CHSR_LINKC) {
1465                 struct ni_private *devpriv = dev->private;
1466
1467                 mite_handle_b_linkc(devpriv->mite, dev);
1468         }
1469
1470         if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1471                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1472                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1473                 dev_err(dev->class_dev,
1474                         "unknown mite interrupt (ao_mite_status=%08x)\n",
1475                         ao_mite_status);
1476                 s->async->events |= COMEDI_CB_ERROR;
1477         }
1478 #endif
1479
1480         if (b_status == 0xffff)
1481                 return;
1482         if (b_status & NISTC_AO_STATUS1_OVERRUN) {
1483                 dev_err(dev->class_dev,
1484                         "AO FIFO underrun status=0x%04x status2=0x%04x\n",
1485                         b_status, ni_stc_readw(dev, NISTC_AO_STATUS2_REG));
1486                 s->async->events |= COMEDI_CB_OVERFLOW;
1487         }
1488
1489         if (b_status & NISTC_AO_STATUS1_BC_TC)
1490                 s->async->events |= COMEDI_CB_EOA;
1491
1492 #ifndef PCIDMA
1493         if (b_status & NISTC_AO_STATUS1_FIFO_REQ) {
1494                 int ret;
1495
1496                 ret = ni_ao_fifo_half_empty(dev, s);
1497                 if (!ret) {
1498                         dev_err(dev->class_dev, "AO buffer underrun\n");
1499                         ni_set_bits(dev, NISTC_INTB_ENA_REG,
1500                                     NISTC_INTB_ENA_AO_FIFO |
1501                                     NISTC_INTB_ENA_AO_ERR, 0);
1502                         s->async->events |= COMEDI_CB_OVERFLOW;
1503                 }
1504         }
1505 #endif
1506
1507         comedi_handle_events(dev, s);
1508 }
1509
1510 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1511                         void *data, unsigned int num_bytes,
1512                         unsigned int chan_index)
1513 {
1514         struct ni_private *devpriv = dev->private;
1515         struct comedi_async *async = s->async;
1516         struct comedi_cmd *cmd = &async->cmd;
1517         unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
1518         unsigned short *array = data;
1519         unsigned int *larray = data;
1520         unsigned int i;
1521
1522         for (i = 0; i < nsamples; i++) {
1523 #ifdef PCIDMA
1524                 if (s->subdev_flags & SDF_LSAMPL)
1525                         larray[i] = le32_to_cpu(larray[i]);
1526                 else
1527                         array[i] = le16_to_cpu(array[i]);
1528 #endif
1529                 if (s->subdev_flags & SDF_LSAMPL)
1530                         larray[i] += devpriv->ai_offset[chan_index];
1531                 else
1532                         array[i] += devpriv->ai_offset[chan_index];
1533                 chan_index++;
1534                 chan_index %= cmd->chanlist_len;
1535         }
1536 }
1537
1538 #ifdef PCIDMA
1539
1540 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1541 {
1542         struct ni_private *devpriv = dev->private;
1543         struct comedi_subdevice *s = dev->read_subdev;
1544         int retval;
1545         unsigned long flags;
1546
1547         retval = ni_request_ai_mite_channel(dev);
1548         if (retval)
1549                 return retval;
1550
1551         /* write alloc the entire buffer */
1552         comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
1553
1554         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1555         if (!devpriv->ai_mite_chan) {
1556                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1557                 return -EIO;
1558         }
1559
1560         if (devpriv->is_611x || devpriv->is_6143)
1561                 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1562         else if (devpriv->is_628x)
1563                 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1564         else
1565                 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1566
1567         /*start the MITE */
1568         mite_dma_arm(devpriv->ai_mite_chan);
1569         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1570
1571         return 0;
1572 }
1573
1574 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1575 {
1576         struct ni_private *devpriv = dev->private;
1577         struct comedi_subdevice *s = dev->write_subdev;
1578         int retval;
1579         unsigned long flags;
1580
1581         retval = ni_request_ao_mite_channel(dev);
1582         if (retval)
1583                 return retval;
1584
1585         /* read alloc the entire buffer */
1586         comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
1587
1588         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1589         if (devpriv->ao_mite_chan) {
1590                 if (devpriv->is_611x || devpriv->is_6713) {
1591                         mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1592                 } else {
1593                         /* doing 32 instead of 16 bit wide transfers from memory
1594                            makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1595                         mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1596                 }
1597                 mite_dma_arm(devpriv->ao_mite_chan);
1598         } else {
1599                 retval = -EIO;
1600         }
1601         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1602
1603         return retval;
1604 }
1605
1606 #endif /*  PCIDMA */
1607
1608 /*
1609    used for both cancel ioctl and board initialization
1610
1611    this is pretty harsh for a cancel, but it works...
1612  */
1613
1614 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1615 {
1616         struct ni_private *devpriv = dev->private;
1617         unsigned ai_personal;
1618         unsigned ai_out_ctrl;
1619
1620         ni_release_ai_mite_channel(dev);
1621         /* ai configuration */
1622         ni_stc_writew(dev, NISTC_RESET_AI_CFG_START | NISTC_RESET_AI,
1623                       NISTC_RESET_REG);
1624
1625         ni_set_bits(dev, NISTC_INTA_ENA_REG, NISTC_INTA_ENA_AI_MASK, 0);
1626
1627         ni_clear_ai_fifo(dev);
1628
1629         if (!devpriv->is_6143)
1630                 ni_writeb(dev, NI_E_MISC_CMD_EXT_ATRIG, NI_E_MISC_CMD_REG);
1631
1632         ni_stc_writew(dev, NISTC_AI_CMD1_DISARM, NISTC_AI_CMD1_REG);
1633         ni_stc_writew(dev, NISTC_AI_MODE1_START_STOP |
1634                            NISTC_AI_MODE1_RSVD
1635                             /*| NISTC_AI_MODE1_TRIGGER_ONCE */,
1636                       NISTC_AI_MODE1_REG);
1637         ni_stc_writew(dev, 0, NISTC_AI_MODE2_REG);
1638         /* generate FIFO interrupts on non-empty */
1639         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
1640                       NISTC_AI_MODE3_REG);
1641
1642         ai_personal = NISTC_AI_PERSONAL_SHIFTIN_PW |
1643                       NISTC_AI_PERSONAL_SOC_POLARITY |
1644                       NISTC_AI_PERSONAL_LOCALMUX_CLK_PW;
1645         ai_out_ctrl = NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(3) |
1646                       NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(0) |
1647                       NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(2) |
1648                       NISTC_AI_OUT_CTRL_SC_TC_SEL(3);
1649         if (devpriv->is_611x) {
1650                 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1651         } else if (devpriv->is_6143) {
1652                 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1653         } else {
1654                 ai_personal |= NISTC_AI_PERSONAL_CONVERT_PW;
1655                 if (devpriv->is_622x)
1656                         ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1657                 else
1658                         ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1659         }
1660         ni_stc_writew(dev, ai_personal, NISTC_AI_PERSONAL_REG);
1661         ni_stc_writew(dev, ai_out_ctrl, NISTC_AI_OUT_CTRL_REG);
1662
1663         /* the following registers should not be changed, because there
1664          * are no backup registers in devpriv.  If you want to change
1665          * any of these, add a backup register and other appropriate code:
1666          *      NISTC_AI_MODE1_REG
1667          *      NISTC_AI_MODE3_REG
1668          *      NISTC_AI_PERSONAL_REG
1669          *      NISTC_AI_OUT_CTRL_REG
1670          */
1671
1672         /* clear interrupts */
1673         ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
1674
1675         ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
1676
1677         return 0;
1678 }
1679
1680 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1681 {
1682         unsigned long flags;
1683         int count;
1684
1685         /*  lock to avoid race with interrupt handler */
1686         spin_lock_irqsave(&dev->spinlock, flags);
1687 #ifndef PCIDMA
1688         ni_handle_fifo_dregs(dev);
1689 #else
1690         ni_sync_ai_dma(dev);
1691 #endif
1692         count = comedi_buf_n_bytes_ready(s);
1693         spin_unlock_irqrestore(&dev->spinlock, flags);
1694
1695         return count;
1696 }
1697
1698 static void ni_prime_channelgain_list(struct comedi_device *dev)
1699 {
1700         int i;
1701
1702         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG);
1703         for (i = 0; i < NI_TIMEOUT; ++i) {
1704                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1705                       NISTC_AI_STATUS1_FIFO_E)) {
1706                         ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
1707                         return;
1708                 }
1709                 udelay(1);
1710         }
1711         dev_err(dev->class_dev, "timeout loading channel/gain list\n");
1712 }
1713
1714 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1715                                               unsigned int n_chan,
1716                                               unsigned int *list)
1717 {
1718         const struct ni_board_struct *board = dev->board_ptr;
1719         struct ni_private *devpriv = dev->private;
1720         unsigned int chan, range, aref;
1721         unsigned int i;
1722         unsigned int dither;
1723         unsigned range_code;
1724
1725         ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1726
1727         if ((list[0] & CR_ALT_SOURCE)) {
1728                 unsigned bypass_bits;
1729
1730                 chan = CR_CHAN(list[0]);
1731                 range = CR_RANGE(list[0]);
1732                 range_code = ni_gainlkup[board->gainlkup][range];
1733                 dither = (list[0] & CR_ALT_FILTER) != 0;
1734                 bypass_bits = NI_M_CFG_BYPASS_FIFO |
1735                               NI_M_CFG_BYPASS_AI_CHAN(chan) |
1736                               NI_M_CFG_BYPASS_AI_GAIN(range_code) |
1737                               devpriv->ai_calib_source;
1738                 if (dither)
1739                         bypass_bits |= NI_M_CFG_BYPASS_AI_DITHER;
1740                 /*  don't use 2's complement encoding */
1741                 bypass_bits |= NI_M_CFG_BYPASS_AI_POLARITY;
1742                 ni_writel(dev, bypass_bits, NI_M_CFG_BYPASS_FIFO_REG);
1743         } else {
1744                 ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG);
1745         }
1746         for (i = 0; i < n_chan; i++) {
1747                 unsigned config_bits = 0;
1748
1749                 chan = CR_CHAN(list[i]);
1750                 aref = CR_AREF(list[i]);
1751                 range = CR_RANGE(list[i]);
1752                 dither = (list[i] & CR_ALT_FILTER) != 0;
1753
1754                 range_code = ni_gainlkup[board->gainlkup][range];
1755                 devpriv->ai_offset[i] = 0;
1756                 switch (aref) {
1757                 case AREF_DIFF:
1758                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_DIFF;
1759                         break;
1760                 case AREF_COMMON:
1761                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_COMMON;
1762                         break;
1763                 case AREF_GROUND:
1764                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_GROUND;
1765                         break;
1766                 case AREF_OTHER:
1767                         break;
1768                 }
1769                 config_bits |= NI_M_AI_CFG_CHAN_SEL(chan);
1770                 config_bits |= NI_M_AI_CFG_BANK_SEL(chan);
1771                 config_bits |= NI_M_AI_CFG_GAIN(range_code);
1772                 if (i == n_chan - 1)
1773                         config_bits |= NI_M_AI_CFG_LAST_CHAN;
1774                 if (dither)
1775                         config_bits |= NI_M_AI_CFG_DITHER;
1776                 /*  don't use 2's complement encoding */
1777                 config_bits |= NI_M_AI_CFG_POLARITY;
1778                 ni_writew(dev, config_bits, NI_M_AI_CFG_FIFO_DATA_REG);
1779         }
1780         ni_prime_channelgain_list(dev);
1781 }
1782
1783 /*
1784  * Notes on the 6110 and 6111:
1785  * These boards a slightly different than the rest of the series, since
1786  * they have multiple A/D converters.
1787  * From the driver side, the configuration memory is a
1788  * little different.
1789  * Configuration Memory Low:
1790  *   bits 15-9: same
1791  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1792  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1793  *       1001 gain=0.1 (+/- 50)
1794  *       1010 0.2
1795  *       1011 0.1
1796  *       0001 1
1797  *       0010 2
1798  *       0011 5
1799  *       0100 10
1800  *       0101 20
1801  *       0110 50
1802  * Configuration Memory High:
1803  *   bits 12-14: Channel Type
1804  *       001 for differential
1805  *       000 for calibration
1806  *   bit 11: coupling  (this is not currently handled)
1807  *       1 AC coupling
1808  *       0 DC coupling
1809  *   bits 0-2: channel
1810  *       valid channels are 0-3
1811  */
1812 static void ni_load_channelgain_list(struct comedi_device *dev,
1813                                      struct comedi_subdevice *s,
1814                                      unsigned int n_chan, unsigned int *list)
1815 {
1816         const struct ni_board_struct *board = dev->board_ptr;
1817         struct ni_private *devpriv = dev->private;
1818         unsigned int offset = (s->maxdata + 1) >> 1;
1819         unsigned int chan, range, aref;
1820         unsigned int i;
1821         unsigned int hi, lo;
1822         unsigned int dither;
1823
1824         if (devpriv->is_m_series) {
1825                 ni_m_series_load_channelgain_list(dev, n_chan, list);
1826                 return;
1827         }
1828         if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) {
1829                 if (devpriv->changain_state
1830                     && devpriv->changain_spec == list[0]) {
1831                         /*  ready to go. */
1832                         return;
1833                 }
1834                 devpriv->changain_state = 1;
1835                 devpriv->changain_spec = list[0];
1836         } else {
1837                 devpriv->changain_state = 0;
1838         }
1839
1840         ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1841
1842         /*  Set up Calibration mode if required */
1843         if (devpriv->is_6143) {
1844                 if ((list[0] & CR_ALT_SOURCE)
1845                     && !devpriv->ai_calib_source_enabled) {
1846                         /*  Strobe Relay enable bit */
1847                         ni_writew(dev, devpriv->ai_calib_source |
1848                                        NI6143_CALIB_CHAN_RELAY_ON,
1849                                   NI6143_CALIB_CHAN_REG);
1850                         ni_writew(dev, devpriv->ai_calib_source,
1851                                   NI6143_CALIB_CHAN_REG);
1852                         devpriv->ai_calib_source_enabled = 1;
1853                         msleep_interruptible(100);      /*  Allow relays to change */
1854                 } else if (!(list[0] & CR_ALT_SOURCE)
1855                            && devpriv->ai_calib_source_enabled) {
1856                         /*  Strobe Relay disable bit */
1857                         ni_writew(dev, devpriv->ai_calib_source |
1858                                        NI6143_CALIB_CHAN_RELAY_OFF,
1859                                   NI6143_CALIB_CHAN_REG);
1860                         ni_writew(dev, devpriv->ai_calib_source,
1861                                   NI6143_CALIB_CHAN_REG);
1862                         devpriv->ai_calib_source_enabled = 0;
1863                         msleep_interruptible(100);      /*  Allow relays to change */
1864                 }
1865         }
1866
1867         for (i = 0; i < n_chan; i++) {
1868                 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE))
1869                         chan = devpriv->ai_calib_source;
1870                 else
1871                         chan = CR_CHAN(list[i]);
1872                 aref = CR_AREF(list[i]);
1873                 range = CR_RANGE(list[i]);
1874                 dither = (list[i] & CR_ALT_FILTER) != 0;
1875
1876                 /* fix the external/internal range differences */
1877                 range = ni_gainlkup[board->gainlkup][range];
1878                 if (devpriv->is_611x)
1879                         devpriv->ai_offset[i] = offset;
1880                 else
1881                         devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
1882
1883                 hi = 0;
1884                 if ((list[i] & CR_ALT_SOURCE)) {
1885                         if (devpriv->is_611x)
1886                                 ni_writew(dev, CR_CHAN(list[i]) & 0x0003,
1887                                           NI611X_CALIB_CHAN_SEL_REG);
1888                 } else {
1889                         if (devpriv->is_611x)
1890                                 aref = AREF_DIFF;
1891                         else if (devpriv->is_6143)
1892                                 aref = AREF_OTHER;
1893                         switch (aref) {
1894                         case AREF_DIFF:
1895                                 hi |= NI_E_AI_CFG_HI_TYPE_DIFF;
1896                                 break;
1897                         case AREF_COMMON:
1898                                 hi |= NI_E_AI_CFG_HI_TYPE_COMMON;
1899                                 break;
1900                         case AREF_GROUND:
1901                                 hi |= NI_E_AI_CFG_HI_TYPE_GROUND;
1902                                 break;
1903                         case AREF_OTHER:
1904                                 break;
1905                         }
1906                 }
1907                 hi |= NI_E_AI_CFG_HI_CHAN(chan);
1908
1909                 ni_writew(dev, hi, NI_E_AI_CFG_HI_REG);
1910
1911                 if (!devpriv->is_6143) {
1912                         lo = NI_E_AI_CFG_LO_GAIN(range);
1913
1914                         if (i == n_chan - 1)
1915                                 lo |= NI_E_AI_CFG_LO_LAST_CHAN;
1916                         if (dither)
1917                                 lo |= NI_E_AI_CFG_LO_DITHER;
1918
1919                         ni_writew(dev, lo, NI_E_AI_CFG_LO_REG);
1920                 }
1921         }
1922
1923         /* prime the channel/gain list */
1924         if (!devpriv->is_611x && !devpriv->is_6143)
1925                 ni_prime_channelgain_list(dev);
1926 }
1927
1928 static int ni_ai_insn_read(struct comedi_device *dev,
1929                            struct comedi_subdevice *s,
1930                            struct comedi_insn *insn,
1931                            unsigned int *data)
1932 {
1933         struct ni_private *devpriv = dev->private;
1934         unsigned int mask = s->maxdata;
1935         int i, n;
1936         unsigned signbits;
1937         unsigned int d;
1938         unsigned long dl;
1939
1940         ni_load_channelgain_list(dev, s, 1, &insn->chanspec);
1941
1942         ni_clear_ai_fifo(dev);
1943
1944         signbits = devpriv->ai_offset[0];
1945         if (devpriv->is_611x) {
1946                 for (n = 0; n < num_adc_stages_611x; n++) {
1947                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1948                                       NISTC_AI_CMD1_REG);
1949                         udelay(1);
1950                 }
1951                 for (n = 0; n < insn->n; n++) {
1952                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1953                                       NISTC_AI_CMD1_REG);
1954                         /* The 611x has screwy 32-bit FIFOs. */
1955                         d = 0;
1956                         for (i = 0; i < NI_TIMEOUT; i++) {
1957                                 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1958                                         d = ni_readl(dev,
1959                                                      NI611X_AI_FIFO_DATA_REG);
1960                                         d >>= 16;
1961                                         d &= 0xffff;
1962                                         break;
1963                                 }
1964                                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1965                                       NISTC_AI_STATUS1_FIFO_E)) {
1966                                         d = ni_readl(dev,
1967                                                      NI611X_AI_FIFO_DATA_REG);
1968                                         d &= 0xffff;
1969                                         break;
1970                                 }
1971                         }
1972                         if (i == NI_TIMEOUT) {
1973                                 dev_err(dev->class_dev, "timeout\n");
1974                                 return -ETIME;
1975                         }
1976                         d += signbits;
1977                         data[n] = d & 0xffff;
1978                 }
1979         } else if (devpriv->is_6143) {
1980                 for (n = 0; n < insn->n; n++) {
1981                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1982                                       NISTC_AI_CMD1_REG);
1983
1984                         /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1985                         dl = 0;
1986                         for (i = 0; i < NI_TIMEOUT; i++) {
1987                                 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) &
1988                                     0x01) {
1989                                         /* Get stranded sample into FIFO */
1990                                         ni_writel(dev, 0x01,
1991                                                   NI6143_AI_FIFO_CTRL_REG);
1992                                         dl = ni_readl(dev,
1993                                                       NI6143_AI_FIFO_DATA_REG);
1994                                         break;
1995                                 }
1996                         }
1997                         if (i == NI_TIMEOUT) {
1998                                 dev_err(dev->class_dev, "timeout\n");
1999                                 return -ETIME;
2000                         }
2001                         data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
2002                 }
2003         } else {
2004                 for (n = 0; n < insn->n; n++) {
2005                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
2006                                       NISTC_AI_CMD1_REG);
2007                         for (i = 0; i < NI_TIMEOUT; i++) {
2008                                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
2009                                       NISTC_AI_STATUS1_FIFO_E))
2010                                         break;
2011                         }
2012                         if (i == NI_TIMEOUT) {
2013                                 dev_err(dev->class_dev, "timeout\n");
2014                                 return -ETIME;
2015                         }
2016                         if (devpriv->is_m_series) {
2017                                 dl = ni_readl(dev, NI_M_AI_FIFO_DATA_REG);
2018                                 dl &= mask;
2019                                 data[n] = dl;
2020                         } else {
2021                                 d = ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
2022                                 d += signbits;
2023                                 data[n] = d & 0xffff;
2024                         }
2025                 }
2026         }
2027         return insn->n;
2028 }
2029
2030 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2031                           unsigned int flags)
2032 {
2033         struct ni_private *devpriv = dev->private;
2034         int divider;
2035
2036         switch (flags & CMDF_ROUND_MASK) {
2037         case CMDF_ROUND_NEAREST:
2038         default:
2039                 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2040                 break;
2041         case CMDF_ROUND_DOWN:
2042                 divider = (nanosec) / devpriv->clock_ns;
2043                 break;
2044         case CMDF_ROUND_UP:
2045                 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2046                 break;
2047         }
2048         return divider - 1;
2049 }
2050
2051 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2052 {
2053         struct ni_private *devpriv = dev->private;
2054
2055         return devpriv->clock_ns * (timer + 1);
2056 }
2057
2058 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2059                                          unsigned num_channels)
2060 {
2061         const struct ni_board_struct *board = dev->board_ptr;
2062         struct ni_private *devpriv = dev->private;
2063
2064         /* simultaneously-sampled inputs */
2065         if (devpriv->is_611x || devpriv->is_6143)
2066                 return board->ai_speed;
2067
2068         /* multiplexed inputs */
2069         return board->ai_speed * num_channels;
2070 }
2071
2072 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2073                          struct comedi_cmd *cmd)
2074 {
2075         const struct ni_board_struct *board = dev->board_ptr;
2076         struct ni_private *devpriv = dev->private;
2077         int err = 0;
2078         unsigned int tmp;
2079         unsigned int sources;
2080
2081         /* Step 1 : check if triggers are trivially valid */
2082
2083         err |= comedi_check_trigger_src(&cmd->start_src,
2084                                         TRIG_NOW | TRIG_INT | TRIG_EXT);
2085         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
2086                                         TRIG_TIMER | TRIG_EXT);
2087
2088         sources = TRIG_TIMER | TRIG_EXT;
2089         if (devpriv->is_611x || devpriv->is_6143)
2090                 sources |= TRIG_NOW;
2091         err |= comedi_check_trigger_src(&cmd->convert_src, sources);
2092
2093         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2094         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2095
2096         if (err)
2097                 return 1;
2098
2099         /* Step 2a : make sure trigger sources are unique */
2100
2101         err |= comedi_check_trigger_is_unique(cmd->start_src);
2102         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2103         err |= comedi_check_trigger_is_unique(cmd->convert_src);
2104         err |= comedi_check_trigger_is_unique(cmd->stop_src);
2105
2106         /* Step 2b : and mutually compatible */
2107
2108         if (err)
2109                 return 2;
2110
2111         /* Step 3: check if arguments are trivially valid */
2112
2113         switch (cmd->start_src) {
2114         case TRIG_NOW:
2115         case TRIG_INT:
2116                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2117                 break;
2118         case TRIG_EXT:
2119                 tmp = CR_CHAN(cmd->start_arg);
2120
2121                 if (tmp > 16)
2122                         tmp = 16;
2123                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2124                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
2125                 break;
2126         }
2127
2128         if (cmd->scan_begin_src == TRIG_TIMER) {
2129                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
2130                         ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2131                 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
2132                                                     devpriv->clock_ns *
2133                                                     0xffffff);
2134         } else if (cmd->scan_begin_src == TRIG_EXT) {
2135                 /* external trigger */
2136                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2137
2138                 if (tmp > 16)
2139                         tmp = 16;
2140                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2141                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2142         } else {                /* TRIG_OTHER */
2143                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2144         }
2145
2146         if (cmd->convert_src == TRIG_TIMER) {
2147                 if (devpriv->is_611x || devpriv->is_6143) {
2148                         err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2149                                                            0);
2150                 } else {
2151                         err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2152                                                             board->ai_speed);
2153                         err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
2154                                                             devpriv->clock_ns *
2155                                                             0xffff);
2156                 }
2157         } else if (cmd->convert_src == TRIG_EXT) {
2158                 /* external trigger */
2159                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2160
2161                 if (tmp > 16)
2162                         tmp = 16;
2163                 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2164                 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, tmp);
2165         } else if (cmd->convert_src == TRIG_NOW) {
2166                 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
2167         }
2168
2169         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2170                                            cmd->chanlist_len);
2171
2172         if (cmd->stop_src == TRIG_COUNT) {
2173                 unsigned int max_count = 0x01000000;
2174
2175                 if (devpriv->is_611x)
2176                         max_count -= num_adc_stages_611x;
2177                 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count);
2178                 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2179         } else {
2180                 /* TRIG_NONE */
2181                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2182         }
2183
2184         if (err)
2185                 return 3;
2186
2187         /* step 4: fix up any arguments */
2188
2189         if (cmd->scan_begin_src == TRIG_TIMER) {
2190                 tmp = cmd->scan_begin_arg;
2191                 cmd->scan_begin_arg =
2192                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2193                                                        cmd->scan_begin_arg,
2194                                                        cmd->flags));
2195                 if (tmp != cmd->scan_begin_arg)
2196                         err++;
2197         }
2198         if (cmd->convert_src == TRIG_TIMER) {
2199                 if (!devpriv->is_611x && !devpriv->is_6143) {
2200                         tmp = cmd->convert_arg;
2201                         cmd->convert_arg =
2202                             ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2203                                                                cmd->convert_arg,
2204                                                                cmd->flags));
2205                         if (tmp != cmd->convert_arg)
2206                                 err++;
2207                         if (cmd->scan_begin_src == TRIG_TIMER &&
2208                             cmd->scan_begin_arg <
2209                             cmd->convert_arg * cmd->scan_end_arg) {
2210                                 cmd->scan_begin_arg =
2211                                     cmd->convert_arg * cmd->scan_end_arg;
2212                                 err++;
2213                         }
2214                 }
2215         }
2216
2217         if (err)
2218                 return 4;
2219
2220         return 0;
2221 }
2222
2223 static int ni_ai_inttrig(struct comedi_device *dev,
2224                          struct comedi_subdevice *s,
2225                          unsigned int trig_num)
2226 {
2227         struct ni_private *devpriv = dev->private;
2228         struct comedi_cmd *cmd = &s->async->cmd;
2229
2230         if (trig_num != cmd->start_arg)
2231                 return -EINVAL;
2232
2233         ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2,
2234                       NISTC_AI_CMD2_REG);
2235         s->async->inttrig = NULL;
2236
2237         return 1;
2238 }
2239
2240 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2241 {
2242         struct ni_private *devpriv = dev->private;
2243         const struct comedi_cmd *cmd = &s->async->cmd;
2244         int timer;
2245         int mode1 = 0;          /* mode1 is needed for both stop and convert */
2246         int mode2 = 0;
2247         int start_stop_select = 0;
2248         unsigned int stop_count;
2249         int interrupt_a_enable = 0;
2250         unsigned ai_trig;
2251
2252         if (dev->irq == 0) {
2253                 dev_err(dev->class_dev, "cannot run command without an irq\n");
2254                 return -EIO;
2255         }
2256         ni_clear_ai_fifo(dev);
2257
2258         ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist);
2259
2260         /* start configuration */
2261         ni_stc_writew(dev, NISTC_RESET_AI_CFG_START, NISTC_RESET_REG);
2262
2263         /* disable analog triggering for now, since it
2264          * interferes with the use of pfi0 */
2265         devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA;
2266         ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
2267
2268         ai_trig = NISTC_AI_TRIG_START2_SEL(0) | NISTC_AI_TRIG_START1_SYNC;
2269         switch (cmd->start_src) {
2270         case TRIG_INT:
2271         case TRIG_NOW:
2272                 ai_trig |= NISTC_AI_TRIG_START1_EDGE |
2273                            NISTC_AI_TRIG_START1_SEL(0);
2274                 break;
2275         case TRIG_EXT:
2276                 ai_trig |= NISTC_AI_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) +
2277                                                     1);
2278
2279                 if (cmd->start_arg & CR_INVERT)
2280                         ai_trig |= NISTC_AI_TRIG_START1_POLARITY;
2281                 if (cmd->start_arg & CR_EDGE)
2282                         ai_trig |= NISTC_AI_TRIG_START1_EDGE;
2283                 break;
2284         }
2285         ni_stc_writew(dev, ai_trig, NISTC_AI_TRIG_SEL_REG);
2286
2287         mode2 &= ~NISTC_AI_MODE2_PRE_TRIGGER;
2288         mode2 &= ~NISTC_AI_MODE2_SC_INIT_LOAD_SRC;
2289         mode2 &= ~NISTC_AI_MODE2_SC_RELOAD_MODE;
2290         ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2291
2292         if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) {
2293                 /* logic low */
2294                 start_stop_select |= NISTC_AI_STOP_POLARITY |
2295                                      NISTC_AI_STOP_SEL(31) |
2296                                      NISTC_AI_STOP_SYNC;
2297         } else {
2298                 /*  ai configuration memory */
2299                 start_stop_select |= NISTC_AI_STOP_SEL(19);
2300         }
2301         ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2302
2303         devpriv->ai_cmd2 = 0;
2304         switch (cmd->stop_src) {
2305         case TRIG_COUNT:
2306                 stop_count = cmd->stop_arg - 1;
2307
2308                 if (devpriv->is_611x) {
2309                         /*  have to take 3 stage adc pipeline into account */
2310                         stop_count += num_adc_stages_611x;
2311                 }
2312                 /* stage number of scans */
2313                 ni_stc_writel(dev, stop_count, NISTC_AI_SC_LOADA_REG);
2314
2315                 mode1 |= NISTC_AI_MODE1_START_STOP |
2316                          NISTC_AI_MODE1_RSVD |
2317                          NISTC_AI_MODE1_TRIGGER_ONCE;
2318                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2319                 /* load SC (Scan Count) */
2320                 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2321
2322                 if (stop_count == 0) {
2323                         devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS;
2324                         interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2325                         /*  this is required to get the last sample for chanlist_len > 1, not sure why */
2326                         if (cmd->chanlist_len > 1)
2327                                 start_stop_select |= NISTC_AI_STOP_POLARITY |
2328                                                      NISTC_AI_STOP_EDGE;
2329                 }
2330                 break;
2331         case TRIG_NONE:
2332                 /* stage number of scans */
2333                 ni_stc_writel(dev, 0, NISTC_AI_SC_LOADA_REG);
2334
2335                 mode1 |= NISTC_AI_MODE1_START_STOP |
2336                          NISTC_AI_MODE1_RSVD |
2337                          NISTC_AI_MODE1_CONTINUOUS;
2338                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2339
2340                 /* load SC (Scan Count) */
2341                 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2342                 break;
2343         }
2344
2345         switch (cmd->scan_begin_src) {
2346         case TRIG_TIMER:
2347                 /*
2348                  * stop bits for non 611x boards
2349                  * NISTC_AI_MODE3_SI_TRIG_DELAY=0
2350                  * NISTC_AI_MODE2_PRE_TRIGGER=0
2351                  * NISTC_AI_START_STOP_REG:
2352                  * NISTC_AI_START_POLARITY=0    (?) rising edge
2353                  * NISTC_AI_START_EDGE=1        edge triggered
2354                  * NISTC_AI_START_SYNC=1        (?)
2355                  * NISTC_AI_START_SEL=0         SI_TC
2356                  * NISTC_AI_STOP_POLARITY=0     rising edge
2357                  * NISTC_AI_STOP_EDGE=0         level
2358                  * NISTC_AI_STOP_SYNC=1
2359                  * NISTC_AI_STOP_SEL=19         external pin (configuration mem)
2360                  */
2361                 start_stop_select |= NISTC_AI_START_EDGE | NISTC_AI_START_SYNC;
2362                 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2363
2364                 mode2 &= ~NISTC_AI_MODE2_SI_INIT_LOAD_SRC;      /* A */
2365                 mode2 |= NISTC_AI_MODE2_SI_RELOAD_MODE(0);
2366                 /* mode2 |= NISTC_AI_MODE2_SC_RELOAD_MODE; */
2367                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2368
2369                 /* load SI */
2370                 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2371                                        CMDF_ROUND_NEAREST);
2372                 ni_stc_writel(dev, timer, NISTC_AI_SI_LOADA_REG);
2373                 ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG);
2374                 break;
2375         case TRIG_EXT:
2376                 if (cmd->scan_begin_arg & CR_EDGE)
2377                         start_stop_select |= NISTC_AI_START_EDGE;
2378                 if (cmd->scan_begin_arg & CR_INVERT)    /* falling edge */
2379                         start_stop_select |= NISTC_AI_START_POLARITY;
2380                 if (cmd->scan_begin_src != cmd->convert_src ||
2381                     (cmd->scan_begin_arg & ~CR_EDGE) !=
2382                     (cmd->convert_arg & ~CR_EDGE))
2383                         start_stop_select |= NISTC_AI_START_SYNC;
2384                 start_stop_select |=
2385                     NISTC_AI_START_SEL(1 + CR_CHAN(cmd->scan_begin_arg));
2386                 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2387                 break;
2388         }
2389
2390         switch (cmd->convert_src) {
2391         case TRIG_TIMER:
2392         case TRIG_NOW:
2393                 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2394                         timer = 1;
2395                 else
2396                         timer = ni_ns_to_timer(dev, cmd->convert_arg,
2397                                                CMDF_ROUND_NEAREST);
2398                 /* 0,0 does not work */
2399                 ni_stc_writew(dev, 1, NISTC_AI_SI2_LOADA_REG);
2400                 ni_stc_writew(dev, timer, NISTC_AI_SI2_LOADB_REG);
2401
2402                 mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC;     /* A */
2403                 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE;        /* alternate */
2404                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2405
2406                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_LOAD, NISTC_AI_CMD1_REG);
2407
2408                 mode2 |= NISTC_AI_MODE2_SI2_INIT_LOAD_SRC;      /* B */
2409                 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE;        /* alternate */
2410                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2411                 break;
2412         case TRIG_EXT:
2413                 mode1 |= NISTC_AI_MODE1_CONVERT_SRC(1 + cmd->convert_arg);
2414                 if ((cmd->convert_arg & CR_INVERT) == 0)
2415                         mode1 |= NISTC_AI_MODE1_CONVERT_POLARITY;
2416                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2417
2418                 mode2 |= NISTC_AI_MODE2_SC_GATE_ENA |
2419                          NISTC_AI_MODE2_START_STOP_GATE_ENA;
2420                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2421
2422                 break;
2423         }
2424
2425         if (dev->irq) {
2426                 /* interrupt on FIFO, errors, SC_TC */
2427                 interrupt_a_enable |= NISTC_INTA_ENA_AI_ERR |
2428                                       NISTC_INTA_ENA_AI_SC_TC;
2429
2430 #ifndef PCIDMA
2431                 interrupt_a_enable |= NISTC_INTA_ENA_AI_FIFO;
2432 #endif
2433
2434                 if ((cmd->flags & CMDF_WAKE_EOS) ||
2435                     (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) {
2436                         /* wake on end-of-scan */
2437                         devpriv->aimode = AIMODE_SCAN;
2438                 } else {
2439                         devpriv->aimode = AIMODE_HALF_FULL;
2440                 }
2441
2442                 switch (devpriv->aimode) {
2443                 case AIMODE_HALF_FULL:
2444                         /*generate FIFO interrupts and DMA requests on half-full */
2445 #ifdef PCIDMA
2446                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF_E,
2447                                       NISTC_AI_MODE3_REG);
2448 #else
2449                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2450                                       NISTC_AI_MODE3_REG);
2451 #endif
2452                         break;
2453                 case AIMODE_SAMPLE:
2454                         /*generate FIFO interrupts on non-empty */
2455                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2456                                       NISTC_AI_MODE3_REG);
2457                         break;
2458                 case AIMODE_SCAN:
2459 #ifdef PCIDMA
2460                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2461                                       NISTC_AI_MODE3_REG);
2462 #else
2463                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2464                                       NISTC_AI_MODE3_REG);
2465 #endif
2466                         interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2467                         break;
2468                 default:
2469                         break;
2470                 }
2471
2472                 /* clear interrupts */
2473                 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
2474
2475                 ni_set_bits(dev, NISTC_INTA_ENA_REG, interrupt_a_enable, 1);
2476         } else {
2477                 /* interrupt on nothing */
2478                 ni_set_bits(dev, NISTC_INTA_ENA_REG, ~0, 0);
2479
2480                 /* XXX start polling if necessary */
2481         }
2482
2483         /* end configuration */
2484         ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
2485
2486         switch (cmd->scan_begin_src) {
2487         case TRIG_TIMER:
2488                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2489                                    NISTC_AI_CMD1_SI_ARM |
2490                                    NISTC_AI_CMD1_DIV_ARM |
2491                                    NISTC_AI_CMD1_SC_ARM,
2492                               NISTC_AI_CMD1_REG);
2493                 break;
2494         case TRIG_EXT:
2495                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2496                                    NISTC_AI_CMD1_SI_ARM |       /* XXX ? */
2497                                    NISTC_AI_CMD1_DIV_ARM |
2498                                    NISTC_AI_CMD1_SC_ARM,
2499                               NISTC_AI_CMD1_REG);
2500                 break;
2501         }
2502
2503 #ifdef PCIDMA
2504         {
2505                 int retval = ni_ai_setup_MITE_dma(dev);
2506
2507                 if (retval)
2508                         return retval;
2509         }
2510 #endif
2511
2512         if (cmd->start_src == TRIG_NOW) {
2513                 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE |
2514                                    devpriv->ai_cmd2,
2515                               NISTC_AI_CMD2_REG);
2516                 s->async->inttrig = NULL;
2517         } else if (cmd->start_src == TRIG_EXT) {
2518                 s->async->inttrig = NULL;
2519         } else {        /* TRIG_INT */
2520                 s->async->inttrig = ni_ai_inttrig;
2521         }
2522
2523         return 0;
2524 }
2525
2526 static int ni_ai_insn_config(struct comedi_device *dev,
2527                              struct comedi_subdevice *s,
2528                              struct comedi_insn *insn, unsigned int *data)
2529 {
2530         struct ni_private *devpriv = dev->private;
2531
2532         if (insn->n < 1)
2533                 return -EINVAL;
2534
2535         switch (data[0]) {
2536         case INSN_CONFIG_ALT_SOURCE:
2537                 if (devpriv->is_m_series) {
2538                         if (data[1] & ~NI_M_CFG_BYPASS_AI_CAL_MASK)
2539                                 return -EINVAL;
2540                         devpriv->ai_calib_source = data[1];
2541                 } else if (devpriv->is_6143) {
2542                         unsigned int calib_source;
2543
2544                         calib_source = data[1] & 0xf;
2545
2546                         devpriv->ai_calib_source = calib_source;
2547                         ni_writew(dev, calib_source, NI6143_CALIB_CHAN_REG);
2548                 } else {
2549                         unsigned int calib_source;
2550                         unsigned int calib_source_adjust;
2551
2552                         calib_source = data[1] & 0xf;
2553                         calib_source_adjust = (data[1] >> 4) & 0xff;
2554
2555                         if (calib_source >= 8)
2556                                 return -EINVAL;
2557                         devpriv->ai_calib_source = calib_source;
2558                         if (devpriv->is_611x) {
2559                                 ni_writeb(dev, calib_source_adjust,
2560                                           NI611X_CAL_GAIN_SEL_REG);
2561                         }
2562                 }
2563                 return 2;
2564         default:
2565                 break;
2566         }
2567
2568         return -EINVAL;
2569 }
2570
2571 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2572                         void *data, unsigned int num_bytes,
2573                         unsigned int chan_index)
2574 {
2575         struct comedi_cmd *cmd = &s->async->cmd;
2576         unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
2577         unsigned short *array = data;
2578         unsigned int i;
2579
2580         for (i = 0; i < nsamples; i++) {
2581                 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]);
2582                 unsigned short val = array[i];
2583
2584                 /*
2585                  * Munge data from unsigned to two's complement for
2586                  * bipolar ranges.
2587                  */
2588                 if (comedi_range_is_bipolar(s, range))
2589                         val = comedi_offset_munge(s, val);
2590 #ifdef PCIDMA
2591                 val = cpu_to_le16(val);
2592 #endif
2593                 array[i] = val;
2594
2595                 chan_index++;
2596                 chan_index %= cmd->chanlist_len;
2597         }
2598 }
2599
2600 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2601                                           struct comedi_subdevice *s,
2602                                           unsigned int chanspec[],
2603                                           unsigned int n_chans, int timed)
2604 {
2605         struct ni_private *devpriv = dev->private;
2606         unsigned int range;
2607         unsigned int chan;
2608         unsigned int conf;
2609         int i;
2610         int invert = 0;
2611
2612         if (timed) {
2613                 for (i = 0; i < s->n_chan; ++i) {
2614                         devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED;
2615                         ni_writeb(dev, devpriv->ao_conf[i],
2616                                   NI_M_AO_CFG_BANK_REG(i));
2617                         ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i));
2618                 }
2619         }
2620         for (i = 0; i < n_chans; i++) {
2621                 const struct comedi_krange *krange;
2622
2623                 chan = CR_CHAN(chanspec[i]);
2624                 range = CR_RANGE(chanspec[i]);
2625                 krange = s->range_table->range + range;
2626                 invert = 0;
2627                 conf = 0;
2628                 switch (krange->max - krange->min) {
2629                 case 20000000:
2630                         conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2631                         ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2632                         break;
2633                 case 10000000:
2634                         conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2635                         ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2636                         break;
2637                 case 4000000:
2638                         conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2639                         ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2640                                   NI_M_AO_REF_ATTENUATION_REG(chan));
2641                         break;
2642                 case 2000000:
2643                         conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2644                         ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2645                                   NI_M_AO_REF_ATTENUATION_REG(chan));
2646                         break;
2647                 default:
2648                         dev_err(dev->class_dev,
2649                                 "bug! unhandled ao reference voltage\n");
2650                         break;
2651                 }
2652                 switch (krange->max + krange->min) {
2653                 case 0:
2654                         conf |= NI_M_AO_CFG_BANK_OFFSET_0V;
2655                         break;
2656                 case 10000000:
2657                         conf |= NI_M_AO_CFG_BANK_OFFSET_5V;
2658                         break;
2659                 default:
2660                         dev_err(dev->class_dev,
2661                                 "bug! unhandled ao offset voltage\n");
2662                         break;
2663                 }
2664                 if (timed)
2665                         conf |= NI_M_AO_CFG_BANK_UPDATE_TIMED;
2666                 ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan));
2667                 devpriv->ao_conf[chan] = conf;
2668                 ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan));
2669         }
2670         return invert;
2671 }
2672
2673 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2674                                      struct comedi_subdevice *s,
2675                                      unsigned int chanspec[],
2676                                      unsigned int n_chans)
2677 {
2678         struct ni_private *devpriv = dev->private;
2679         unsigned int range;
2680         unsigned int chan;
2681         unsigned int conf;
2682         int i;
2683         int invert = 0;
2684
2685         for (i = 0; i < n_chans; i++) {
2686                 chan = CR_CHAN(chanspec[i]);
2687                 range = CR_RANGE(chanspec[i]);
2688                 conf = NI_E_AO_DACSEL(chan);
2689
2690                 if (comedi_range_is_bipolar(s, range)) {
2691                         conf |= NI_E_AO_CFG_BIP;
2692                         invert = (s->maxdata + 1) >> 1;
2693                 } else {
2694                         invert = 0;
2695                 }
2696                 if (comedi_range_is_external(s, range))
2697                         conf |= NI_E_AO_EXT_REF;
2698
2699                 /* not all boards can deglitch, but this shouldn't hurt */
2700                 if (chanspec[i] & CR_DEGLITCH)
2701                         conf |= NI_E_AO_DEGLITCH;
2702
2703                 /* analog reference */
2704                 /* AREF_OTHER connects AO ground to AI ground, i think */
2705                 if (CR_AREF(chanspec[i]) == AREF_OTHER)
2706                         conf |= NI_E_AO_GROUND_REF;
2707
2708                 ni_writew(dev, conf, NI_E_AO_CFG_REG);
2709                 devpriv->ao_conf[chan] = conf;
2710         }
2711         return invert;
2712 }
2713
2714 static int ni_ao_config_chanlist(struct comedi_device *dev,
2715                                  struct comedi_subdevice *s,
2716                                  unsigned int chanspec[], unsigned int n_chans,
2717                                  int timed)
2718 {
2719         struct ni_private *devpriv = dev->private;
2720
2721         if (devpriv->is_m_series)
2722                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2723                                                       timed);
2724         else
2725                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2726 }
2727
2728 static int ni_ao_insn_write(struct comedi_device *dev,
2729                             struct comedi_subdevice *s,
2730                             struct comedi_insn *insn,
2731                             unsigned int *data)
2732 {
2733         struct ni_private *devpriv = dev->private;
2734         unsigned int chan = CR_CHAN(insn->chanspec);
2735         unsigned int range = CR_RANGE(insn->chanspec);
2736         int reg;
2737         int i;
2738
2739         if (devpriv->is_6xxx) {
2740                 ni_ao_win_outw(dev, 1 << chan, NI671X_AO_IMMEDIATE_REG);
2741
2742                 reg = NI671X_DAC_DIRECT_DATA_REG(chan);
2743         } else if (devpriv->is_m_series) {
2744                 reg = NI_M_DAC_DIRECT_DATA_REG(chan);
2745         } else {
2746                 reg = NI_E_DAC_DIRECT_DATA_REG(chan);
2747         }
2748
2749         ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2750
2751         for (i = 0; i < insn->n; i++) {
2752                 unsigned int val = data[i];
2753
2754                 s->readback[chan] = val;
2755
2756                 if (devpriv->is_6xxx) {
2757                         /*
2758                          * 6xxx boards have bipolar outputs, munge the
2759                          * unsigned comedi values to 2's complement
2760                          */
2761                         val = comedi_offset_munge(s, val);
2762
2763                         ni_ao_win_outw(dev, val, reg);
2764                 } else if (devpriv->is_m_series) {
2765                         /*
2766                          * M-series boards use offset binary values for
2767                          * bipolar and uinpolar outputs
2768                          */
2769                         ni_writew(dev, val, reg);
2770                 } else {
2771                         /*
2772                          * Non-M series boards need two's complement values
2773                          * for bipolar ranges.
2774                          */
2775                         if (comedi_range_is_bipolar(s, range))
2776                                 val = comedi_offset_munge(s, val);
2777
2778                         ni_writew(dev, val, reg);
2779                 }
2780         }
2781
2782         return insn->n;
2783 }
2784
2785 static int ni_ao_insn_config(struct comedi_device *dev,
2786                              struct comedi_subdevice *s,
2787                              struct comedi_insn *insn, unsigned int *data)
2788 {
2789         const struct ni_board_struct *board = dev->board_ptr;
2790         struct ni_private *devpriv = dev->private;
2791         unsigned int nbytes;
2792
2793         switch (data[0]) {
2794         case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2795                 switch (data[1]) {
2796                 case COMEDI_OUTPUT:
2797                         nbytes = comedi_samples_to_bytes(s,
2798                                                          board->ao_fifo_depth);
2799                         data[2] = 1 + nbytes;
2800                         if (devpriv->mite)
2801                                 data[2] += devpriv->mite->fifo_size;
2802                         break;
2803                 case COMEDI_INPUT:
2804                         data[2] = 0;
2805                         break;
2806                 default:
2807                         return -EINVAL;
2808                 }
2809                 return 0;
2810         default:
2811                 break;
2812         }
2813
2814         return -EINVAL;
2815 }
2816
2817 static int ni_ao_inttrig(struct comedi_device *dev,
2818                          struct comedi_subdevice *s,
2819                          unsigned int trig_num)
2820 {
2821         struct ni_private *devpriv = dev->private;
2822         struct comedi_cmd *cmd = &s->async->cmd;
2823         int ret;
2824         int interrupt_b_bits;
2825         int i;
2826         static const int timeout = 1000;
2827
2828         /*
2829          * Require trig_num == cmd->start_arg when cmd->start_src == TRIG_INT.
2830          * For backwards compatibility, also allow trig_num == 0 when
2831          * cmd->start_src != TRIG_INT (i.e. when cmd->start_src == TRIG_EXT);
2832          * in that case, the internal trigger is being used as a pre-trigger
2833          * before the external trigger.
2834          */
2835         if (!(trig_num == cmd->start_arg ||
2836               (trig_num == 0 && cmd->start_src != TRIG_INT)))
2837                 return -EINVAL;
2838
2839         /* Null trig at beginning prevent ao start trigger from executing more than
2840            once per command (and doing things like trying to allocate the ao dma channel
2841            multiple times) */
2842         s->async->inttrig = NULL;
2843
2844         ni_set_bits(dev, NISTC_INTB_ENA_REG,
2845                     NISTC_INTB_ENA_AO_FIFO | NISTC_INTB_ENA_AO_ERR, 0);
2846         interrupt_b_bits = NISTC_INTB_ENA_AO_ERR;
2847 #ifdef PCIDMA
2848         ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
2849         if (devpriv->is_6xxx)
2850                 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
2851         ret = ni_ao_setup_MITE_dma(dev);
2852         if (ret)
2853                 return ret;
2854         ret = ni_ao_wait_for_dma_load(dev);
2855         if (ret < 0)
2856                 return ret;
2857 #else
2858         ret = ni_ao_prep_fifo(dev, s);
2859         if (ret == 0)
2860                 return -EPIPE;
2861
2862         interrupt_b_bits |= NISTC_INTB_ENA_AO_FIFO;
2863 #endif
2864
2865         ni_stc_writew(dev, devpriv->ao_mode3 | NISTC_AO_MODE3_NOT_AN_UPDATE,
2866                       NISTC_AO_MODE3_REG);
2867         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2868         /* wait for DACs to be loaded */
2869         for (i = 0; i < timeout; i++) {
2870                 udelay(1);
2871                 if ((ni_stc_readw(dev, NISTC_STATUS2_REG) &
2872                      NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS) == 0)
2873                         break;
2874         }
2875         if (i == timeout) {
2876                 dev_err(dev->class_dev,
2877                         "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n");
2878                 return -EIO;
2879         }
2880         /*
2881          * stc manual says we are need to clear error interrupt after
2882          * AO_TMRDACWRs_In_Progress_St clears
2883          */
2884         ni_stc_writew(dev, NISTC_INTB_ACK_AO_ERR, NISTC_INTB_ACK_REG);
2885
2886         ni_set_bits(dev, NISTC_INTB_ENA_REG, interrupt_b_bits, 1);
2887
2888         ni_stc_writew(dev, NISTC_AO_CMD1_UI_ARM |
2889                            NISTC_AO_CMD1_UC_ARM |
2890                            NISTC_AO_CMD1_BC_ARM |
2891                            NISTC_AO_CMD1_DAC1_UPDATE_MODE |
2892                            NISTC_AO_CMD1_DAC0_UPDATE_MODE |
2893                            devpriv->ao_cmd1,
2894                       NISTC_AO_CMD1_REG);
2895
2896         ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2,
2897                       NISTC_AO_CMD2_REG);
2898
2899         return 0;
2900 }
2901
2902 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2903 {
2904         const struct ni_board_struct *board = dev->board_ptr;
2905         struct ni_private *devpriv = dev->private;
2906         const struct comedi_cmd *cmd = &s->async->cmd;
2907         int bits;
2908         int i;
2909         unsigned trigvar;
2910         unsigned val;
2911
2912         if (dev->irq == 0) {
2913                 dev_err(dev->class_dev, "cannot run command without an irq\n");
2914                 return -EIO;
2915         }
2916
2917         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2918
2919         ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
2920
2921         if (devpriv->is_6xxx) {
2922                 ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG,
2923                                NI611X_AO_MISC_REG);
2924
2925                 bits = 0;
2926                 for (i = 0; i < cmd->chanlist_len; i++) {
2927                         int chan;
2928
2929                         chan = CR_CHAN(cmd->chanlist[i]);
2930                         bits |= 1 << chan;
2931                         ni_ao_win_outw(dev, chan, NI611X_AO_WAVEFORM_GEN_REG);
2932                 }
2933                 ni_ao_win_outw(dev, bits, NI611X_AO_TIMED_REG);
2934         }
2935
2936         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
2937
2938         if (cmd->stop_src == TRIG_NONE) {
2939                 devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS;
2940                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE;
2941         } else {
2942                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS;
2943                 devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE;
2944         }
2945         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2946
2947         val = devpriv->ao_trigger_select;
2948         switch (cmd->start_src) {
2949         case TRIG_INT:
2950         case TRIG_NOW:
2951                 val &= ~(NISTC_AO_TRIG_START1_POLARITY |
2952                          NISTC_AO_TRIG_START1_SEL_MASK);
2953                 val |= NISTC_AO_TRIG_START1_EDGE |
2954                        NISTC_AO_TRIG_START1_SYNC;
2955                 break;
2956         case TRIG_EXT:
2957                 val = NISTC_AO_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) + 1);
2958                 if (cmd->start_arg & CR_INVERT) {
2959                         /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
2960                         val |= NISTC_AO_TRIG_START1_POLARITY;
2961                 }
2962                 if (cmd->start_arg & CR_EDGE) {
2963                         /* 0=edge detection disabled, 1=enabled */
2964                         val |= NISTC_AO_TRIG_START1_EDGE;
2965                 }
2966                 ni_stc_writew(dev, devpriv->ao_trigger_select,
2967                               NISTC_AO_TRIG_SEL_REG);
2968                 break;
2969         default:
2970                 BUG();
2971                 break;
2972         }
2973         devpriv->ao_trigger_select = val;
2974         ni_stc_writew(dev, devpriv->ao_trigger_select, NISTC_AO_TRIG_SEL_REG);
2975
2976         devpriv->ao_mode3 &= ~NISTC_AO_MODE3_TRIG_LEN;
2977         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2978
2979         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2980         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC;
2981         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
2982         if (cmd->stop_src == TRIG_NONE)
2983                 ni_stc_writel(dev, 0xffffff, NISTC_AO_BC_LOADA_REG);
2984         else
2985                 ni_stc_writel(dev, 0, NISTC_AO_BC_LOADA_REG);
2986         ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG);
2987         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC;
2988         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
2989         switch (cmd->stop_src) {
2990         case TRIG_COUNT:
2991                 if (devpriv->is_m_series) {
2992                         /*  this is how the NI example code does it for m-series boards, verified correct with 6259 */
2993                         ni_stc_writel(dev, cmd->stop_arg - 1,
2994                                       NISTC_AO_UC_LOADA_REG);
2995                         ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
2996                                       NISTC_AO_CMD1_REG);
2997                 } else {
2998                         ni_stc_writel(dev, cmd->stop_arg,
2999                                       NISTC_AO_UC_LOADA_REG);
3000                         ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3001                                       NISTC_AO_CMD1_REG);
3002                         ni_stc_writel(dev, cmd->stop_arg - 1,
3003                                       NISTC_AO_UC_LOADA_REG);
3004                 }
3005                 break;
3006         case TRIG_NONE:
3007                 ni_stc_writel(dev, 0xffffff, NISTC_AO_UC_LOADA_REG);
3008                 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, NISTC_AO_CMD1_REG);
3009                 ni_stc_writel(dev, 0xffffff, NISTC_AO_UC_LOADA_REG);
3010                 break;
3011         default:
3012                 ni_stc_writel(dev, 0, NISTC_AO_UC_LOADA_REG);
3013                 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, NISTC_AO_CMD1_REG);
3014                 ni_stc_writel(dev, cmd->stop_arg, NISTC_AO_UC_LOADA_REG);
3015         }
3016
3017         devpriv->ao_mode1 &= ~(NISTC_AO_MODE1_UPDATE_SRC_MASK |
3018                                NISTC_AO_MODE1_UI_SRC_MASK |
3019                                NISTC_AO_MODE1_UPDATE_SRC_POLARITY |
3020                                NISTC_AO_MODE1_UI_SRC_POLARITY);
3021         switch (cmd->scan_begin_src) {
3022         case TRIG_TIMER:
3023                 devpriv->ao_cmd2 &= ~NISTC_AO_CMD2_BC_GATE_ENA;
3024                 trigvar =
3025                     ni_ns_to_timer(dev, cmd->scan_begin_arg,
3026                                    CMDF_ROUND_NEAREST);
3027                 ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG);
3028                 ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, NISTC_AO_CMD1_REG);
3029                 ni_stc_writel(dev, trigvar, NISTC_AO_UI_LOADA_REG);
3030                 break;
3031         case TRIG_EXT:
3032                 devpriv->ao_mode1 |=
3033                     NISTC_AO_MODE1_UPDATE_SRC(cmd->scan_begin_arg);
3034                 if (cmd->scan_begin_arg & CR_INVERT)
3035                         devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY;
3036                 devpriv->ao_cmd2 |= NISTC_AO_CMD2_BC_GATE_ENA;
3037                 break;
3038         default:
3039                 BUG();
3040                 break;
3041         }
3042         ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3043         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3044         devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) |
3045                                NISTC_AO_MODE2_UI_INIT_LOAD_SRC);
3046         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3047
3048         if (cmd->scan_end_arg > 1) {
3049                 devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN;
3050                 ni_stc_writew(dev,
3051                               NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1) |
3052                               NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ,
3053                               NISTC_AO_OUT_CTRL_REG);
3054         } else {
3055                 unsigned bits;
3056
3057                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN;
3058                 bits = NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3059                 if (devpriv->is_m_series || devpriv->is_6xxx) {
3060                         bits |= NISTC_AO_OUT_CTRL_CHANS(0);
3061                 } else {
3062                         bits |=
3063                             NISTC_AO_OUT_CTRL_CHANS(CR_CHAN(cmd->chanlist[0]));
3064                 }
3065                 ni_stc_writew(dev, bits, NISTC_AO_OUT_CTRL_REG);
3066         }
3067         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3068
3069         ni_stc_writew(dev, NISTC_AO_CMD1_DAC1_UPDATE_MODE |
3070                            NISTC_AO_CMD1_DAC0_UPDATE_MODE,
3071                       NISTC_AO_CMD1_REG);
3072
3073         devpriv->ao_mode3 |= NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR;
3074         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3075
3076         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK;
3077 #ifdef PCIDMA
3078         devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F;
3079 #else
3080         devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF;
3081 #endif
3082         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA;
3083         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3084
3085         bits = NISTC_AO_PERSONAL_BC_SRC_SEL |
3086                NISTC_AO_PERSONAL_UPDATE_PW |
3087                NISTC_AO_PERSONAL_TMRDACWR_PW;
3088         if (board->ao_fifo_depth)
3089                 bits |= NISTC_AO_PERSONAL_FIFO_ENA;
3090         else
3091                 bits |= NISTC_AO_PERSONAL_DMA_PIO_CTRL;
3092 #if 0
3093         /*
3094          * F Hess: windows driver does not set NISTC_AO_PERSONAL_NUM_DAC bit
3095          * for 6281, verified with bus analyzer.
3096          */
3097         if (devpriv->is_m_series)
3098                 bits |= NISTC_AO_PERSONAL_NUM_DAC;
3099 #endif
3100         ni_stc_writew(dev, bits, NISTC_AO_PERSONAL_REG);
3101         /*  enable sending of ao dma requests */
3102         ni_stc_writew(dev, NISTC_AO_START_AOFREQ_ENA, NISTC_AO_START_SEL_REG);
3103
3104         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3105
3106         if (cmd->stop_src == TRIG_COUNT) {
3107                 ni_stc_writew(dev, NISTC_INTB_ACK_AO_BC_TC,
3108                               NISTC_INTB_ACK_REG);
3109                 ni_set_bits(dev, NISTC_INTB_ENA_REG,
3110                             NISTC_INTB_ENA_AO_BC_TC, 1);
3111         }
3112
3113         s->async->inttrig = ni_ao_inttrig;
3114
3115         return 0;
3116 }
3117
3118 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3119                          struct comedi_cmd *cmd)
3120 {
3121         const struct ni_board_struct *board = dev->board_ptr;
3122         struct ni_private *devpriv = dev->private;
3123         int err = 0;
3124         unsigned int tmp;
3125
3126         /* Step 1 : check if triggers are trivially valid */
3127
3128         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3129         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3130                                         TRIG_TIMER | TRIG_EXT);
3131         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3132         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3133         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3134
3135         if (err)
3136                 return 1;
3137
3138         /* Step 2a : make sure trigger sources are unique */
3139
3140         err |= comedi_check_trigger_is_unique(cmd->start_src);
3141         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3142         err |= comedi_check_trigger_is_unique(cmd->stop_src);
3143
3144         /* Step 2b : and mutually compatible */
3145
3146         if (err)
3147                 return 2;
3148
3149         /* Step 3: check if arguments are trivially valid */
3150
3151         switch (cmd->start_src) {
3152         case TRIG_INT:
3153                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3154                 break;
3155         case TRIG_EXT:
3156                 tmp = CR_CHAN(cmd->start_arg);
3157
3158                 if (tmp > 18)
3159                         tmp = 18;
3160                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3161                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
3162                 break;
3163         }
3164
3165         if (cmd->scan_begin_src == TRIG_TIMER) {
3166                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3167                                                     board->ao_speed);
3168                 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
3169                                                     devpriv->clock_ns *
3170                                                     0xffffff);
3171         }
3172
3173         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3174         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3175                                            cmd->chanlist_len);
3176
3177         if (cmd->stop_src == TRIG_COUNT)
3178                 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3179         else    /* TRIG_NONE */
3180                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
3181
3182         if (err)
3183                 return 3;
3184
3185         /* step 4: fix up any arguments */
3186         if (cmd->scan_begin_src == TRIG_TIMER) {
3187                 tmp = cmd->scan_begin_arg;
3188                 cmd->scan_begin_arg =
3189                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3190                                                        cmd->scan_begin_arg,
3191                                                        cmd->flags));
3192                 if (tmp != cmd->scan_begin_arg)
3193                         err++;
3194         }
3195         if (err)
3196                 return 4;
3197
3198         return 0;
3199 }
3200
3201 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3202 {
3203         struct ni_private *devpriv = dev->private;
3204
3205         ni_release_ao_mite_channel(dev);
3206
3207         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3208         ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
3209         ni_set_bits(dev, NISTC_INTB_ENA_REG, ~0, 0);
3210         ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL, NISTC_AO_PERSONAL_REG);
3211         ni_stc_writew(dev, NISTC_INTB_ACK_AO_ALL, NISTC_INTB_ACK_REG);
3212         ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL |
3213                            NISTC_AO_PERSONAL_UPDATE_PW |
3214                            NISTC_AO_PERSONAL_TMRDACWR_PW,
3215                       NISTC_AO_PERSONAL_REG);
3216         ni_stc_writew(dev, 0, NISTC_AO_OUT_CTRL_REG);
3217         ni_stc_writew(dev, 0, NISTC_AO_START_SEL_REG);
3218         devpriv->ao_cmd1 = 0;
3219         ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG);
3220         devpriv->ao_cmd2 = 0;
3221         ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3222         devpriv->ao_mode1 = 0;
3223         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3224         devpriv->ao_mode2 = 0;
3225         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3226         if (devpriv->is_m_series)
3227                 devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE;
3228         else
3229                 devpriv->ao_mode3 = 0;
3230         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3231         devpriv->ao_trigger_select = 0;
3232         ni_stc_writew(dev, devpriv->ao_trigger_select,
3233                       NISTC_AO_TRIG_SEL_REG);
3234         if (devpriv->is_6xxx) {
3235                 unsigned immediate_bits = 0;
3236                 unsigned i;
3237
3238                 for (i = 0; i < s->n_chan; ++i)
3239                         immediate_bits |= 1 << i;
3240                 ni_ao_win_outw(dev, immediate_bits, NI671X_AO_IMMEDIATE_REG);
3241                 ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG,
3242                                NI611X_AO_MISC_REG);
3243         }
3244         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3245
3246         return 0;
3247 }
3248
3249 /* digital io */
3250
3251 static int ni_dio_insn_config(struct comedi_device *dev,
3252                               struct comedi_subdevice *s,
3253                               struct comedi_insn *insn,
3254                               unsigned int *data)
3255 {
3256         struct ni_private *devpriv = dev->private;
3257         int ret;
3258
3259         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3260         if (ret)
3261                 return ret;
3262
3263         devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK;
3264         devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits);
3265         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3266
3267         return insn->n;
3268 }
3269
3270 static int ni_dio_insn_bits(struct comedi_device *dev,
3271                             struct comedi_subdevice *s,
3272                             struct comedi_insn *insn,
3273                             unsigned int *data)
3274 {
3275         struct ni_private *devpriv = dev->private;
3276
3277         /* Make sure we're not using the serial part of the dio */
3278         if ((data[0] & (NISTC_DIO_SDIN | NISTC_DIO_SDOUT)) &&
3279             devpriv->serial_interval_ns)
3280                 return -EBUSY;
3281
3282         if (comedi_dio_update_state(s, data)) {
3283                 devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK;
3284                 devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state);
3285                 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3286         }
3287
3288         data[1] = ni_stc_readw(dev, NISTC_DIO_IN_REG);
3289
3290         return insn->n;
3291 }
3292
3293 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3294                                        struct comedi_subdevice *s,
3295                                        struct comedi_insn *insn,
3296                                        unsigned int *data)
3297 {
3298         int ret;
3299
3300         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3301         if (ret)
3302                 return ret;
3303
3304         ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
3305
3306         return insn->n;
3307 }
3308
3309 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3310                                      struct comedi_subdevice *s,
3311                                      struct comedi_insn *insn,
3312                                      unsigned int *data)
3313 {
3314         if (comedi_dio_update_state(s, data))
3315                 ni_writel(dev, s->state, NI_M_DIO_REG);
3316
3317         data[1] = ni_readl(dev, NI_M_DIO_REG);
3318
3319         return insn->n;
3320 }
3321
3322 static int ni_cdio_check_chanlist(struct comedi_device *dev,
3323                                   struct comedi_subdevice *s,
3324                                   struct comedi_cmd *cmd)
3325 {
3326         int i;
3327
3328         for (i = 0; i < cmd->chanlist_len; ++i) {
3329                 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3330
3331                 if (chan != i)
3332                         return -EINVAL;
3333         }
3334
3335         return 0;
3336 }
3337
3338 static int ni_cdio_cmdtest(struct comedi_device *dev,
3339                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
3340 {
3341         int err = 0;
3342         int tmp;
3343
3344         /* Step 1 : check if triggers are trivially valid */
3345
3346         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT);
3347         err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3348         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3349         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3350         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3351
3352         if (err)
3353                 return 1;
3354
3355         /* Step 2a : make sure trigger sources are unique */
3356         /* Step 2b : and mutually compatible */
3357
3358         /* Step 3: check if arguments are trivially valid */
3359
3360         err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3361
3362         tmp = cmd->scan_begin_arg;
3363         tmp &= CR_PACK_FLAGS(NI_M_CDO_MODE_SAMPLE_SRC_MASK, 0, 0, CR_INVERT);
3364         if (tmp != cmd->scan_begin_arg)
3365                 err |= -EINVAL;
3366
3367         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3368         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3369                                            cmd->chanlist_len);
3370         err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
3371
3372         if (err)
3373                 return 3;
3374
3375         /* Step 4: fix up any arguments */
3376
3377         /* Step 5: check channel list if it exists */
3378
3379         if (cmd->chanlist && cmd->chanlist_len > 0)
3380                 err |= ni_cdio_check_chanlist(dev, s, cmd);
3381
3382         if (err)
3383                 return 5;
3384
3385         return 0;
3386 }
3387
3388 static int ni_cdo_inttrig(struct comedi_device *dev,
3389                           struct comedi_subdevice *s,
3390                           unsigned int trig_num)
3391 {
3392         struct comedi_cmd *cmd = &s->async->cmd;
3393         const unsigned timeout = 1000;
3394         int retval = 0;
3395         unsigned i;
3396 #ifdef PCIDMA
3397         struct ni_private *devpriv = dev->private;
3398         unsigned long flags;
3399 #endif
3400
3401         if (trig_num != cmd->start_arg)
3402                 return -EINVAL;
3403
3404         s->async->inttrig = NULL;
3405
3406         /* read alloc the entire buffer */
3407         comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
3408
3409 #ifdef PCIDMA
3410         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3411         if (devpriv->cdo_mite_chan) {
3412                 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3413                 mite_dma_arm(devpriv->cdo_mite_chan);
3414         } else {
3415                 dev_err(dev->class_dev, "BUG: no cdo mite channel?\n");
3416                 retval = -EIO;
3417         }
3418         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3419         if (retval < 0)
3420                 return retval;
3421 #endif
3422         /*
3423          * XXX not sure what interrupt C group does
3424          * wait for dma to fill output fifo
3425          * ni_writeb(dev, NI_M_INTC_ENA, NI_M_INTC_ENA_REG);
3426          */
3427         for (i = 0; i < timeout; ++i) {
3428                 if (ni_readl(dev, NI_M_CDIO_STATUS_REG) &
3429                     NI_M_CDIO_STATUS_CDO_FIFO_FULL)
3430                         break;
3431                 udelay(10);
3432         }
3433         if (i == timeout) {
3434                 dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n");
3435                 s->cancel(dev, s);
3436                 return -EIO;
3437         }
3438         ni_writel(dev, NI_M_CDO_CMD_ARM |
3439                        NI_M_CDO_CMD_ERR_INT_ENA_SET |
3440                        NI_M_CDO_CMD_F_E_INT_ENA_SET,
3441                   NI_M_CDIO_CMD_REG);
3442         return retval;
3443 }
3444
3445 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3446 {
3447         const struct comedi_cmd *cmd = &s->async->cmd;
3448         unsigned cdo_mode_bits;
3449         int retval;
3450
3451         ni_writel(dev, NI_M_CDO_CMD_RESET, NI_M_CDIO_CMD_REG);
3452         cdo_mode_bits = NI_M_CDO_MODE_FIFO_MODE |
3453                         NI_M_CDO_MODE_HALT_ON_ERROR |
3454                         NI_M_CDO_MODE_SAMPLE_SRC(CR_CHAN(cmd->scan_begin_arg));
3455         if (cmd->scan_begin_arg & CR_INVERT)
3456                 cdo_mode_bits |= NI_M_CDO_MODE_POLARITY;
3457         ni_writel(dev, cdo_mode_bits, NI_M_CDO_MODE_REG);
3458         if (s->io_bits) {
3459                 ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG);
3460                 ni_writel(dev, NI_M_CDO_CMD_SW_UPDATE, NI_M_CDIO_CMD_REG);
3461                 ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG);
3462         } else {
3463                 dev_err(dev->class_dev,
3464                         "attempted to run digital output command with no lines configured as outputs\n");
3465                 return -EIO;
3466         }
3467         retval = ni_request_cdo_mite_channel(dev);
3468         if (retval < 0)
3469                 return retval;
3470
3471         s->async->inttrig = ni_cdo_inttrig;
3472
3473         return 0;
3474 }
3475
3476 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3477 {
3478         ni_writel(dev, NI_M_CDO_CMD_DISARM |
3479                        NI_M_CDO_CMD_ERR_INT_ENA_CLR |
3480                        NI_M_CDO_CMD_F_E_INT_ENA_CLR |
3481                        NI_M_CDO_CMD_F_REQ_INT_ENA_CLR,
3482                   NI_M_CDIO_CMD_REG);
3483         /*
3484          * XXX not sure what interrupt C group does
3485          * ni_writeb(dev, 0, NI_M_INTC_ENA_REG);
3486          */
3487         ni_writel(dev, 0, NI_M_CDO_MASK_ENA_REG);
3488         ni_release_cdo_mite_channel(dev);
3489         return 0;
3490 }
3491
3492 static void handle_cdio_interrupt(struct comedi_device *dev)
3493 {
3494         struct ni_private *devpriv = dev->private;
3495         unsigned cdio_status;
3496         struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3497 #ifdef PCIDMA
3498         unsigned long flags;
3499 #endif
3500
3501         if (!devpriv->is_m_series)
3502                 return;
3503 #ifdef PCIDMA
3504         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3505         if (devpriv->cdo_mite_chan) {
3506                 unsigned cdo_mite_status =
3507                     mite_get_status(devpriv->cdo_mite_chan);
3508                 if (cdo_mite_status & CHSR_LINKC) {
3509                         writel(CHOR_CLRLC,
3510                                devpriv->mite->mite_io_addr +
3511                                MITE_CHOR(devpriv->cdo_mite_chan->channel));
3512                 }
3513                 mite_sync_output_dma(devpriv->cdo_mite_chan, s);
3514         }
3515         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3516 #endif
3517
3518         cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG);
3519         if (cdio_status & NI_M_CDIO_STATUS_CDO_ERROR) {
3520                 /* XXX just guessing this is needed and does something useful */
3521                 ni_writel(dev, NI_M_CDO_CMD_ERR_INT_CONFIRM,
3522                           NI_M_CDIO_CMD_REG);
3523                 s->async->events |= COMEDI_CB_OVERFLOW;
3524         }
3525         if (cdio_status & NI_M_CDIO_STATUS_CDO_FIFO_EMPTY) {
3526                 ni_writel(dev, NI_M_CDO_CMD_F_E_INT_ENA_CLR,
3527                           NI_M_CDIO_CMD_REG);
3528                 /* s->async->events |= COMEDI_CB_EOA; */
3529         }
3530         comedi_handle_events(dev, s);
3531 }
3532
3533 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3534                                    struct comedi_subdevice *s,
3535                                    unsigned char data_out,
3536                                    unsigned char *data_in)
3537 {
3538         struct ni_private *devpriv = dev->private;
3539         unsigned int status1;
3540         int err = 0, count = 20;
3541
3542         devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK;
3543         devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out);
3544         ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3545
3546         status1 = ni_stc_readw(dev, NISTC_STATUS1_REG);
3547         if (status1 & NISTC_STATUS1_SERIO_IN_PROG) {
3548                 err = -EBUSY;
3549                 goto Error;
3550         }
3551
3552         devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START;
3553         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3554         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START;
3555
3556         /* Wait until STC says we're done, but don't loop infinitely. */
3557         while ((status1 = ni_stc_readw(dev, NISTC_STATUS1_REG)) &
3558                NISTC_STATUS1_SERIO_IN_PROG) {
3559                 /* Delay one bit per loop */
3560                 udelay((devpriv->serial_interval_ns + 999) / 1000);
3561                 if (--count < 0) {
3562                         dev_err(dev->class_dev,
3563                                 "SPI serial I/O didn't finish in time!\n");
3564                         err = -ETIME;
3565                         goto Error;
3566                 }
3567         }
3568
3569         /*
3570          * Delay for last bit. This delay is absolutely necessary, because
3571          * NISTC_STATUS1_SERIO_IN_PROG goes high one bit too early.
3572          */
3573         udelay((devpriv->serial_interval_ns + 999) / 1000);
3574
3575         if (data_in)
3576                 *data_in = ni_stc_readw(dev, NISTC_DIO_SERIAL_IN_REG);
3577
3578 Error:
3579         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3580
3581         return err;
3582 }
3583
3584 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3585                                    struct comedi_subdevice *s,
3586                                    unsigned char data_out,
3587                                    unsigned char *data_in)
3588 {
3589         struct ni_private *devpriv = dev->private;
3590         unsigned char mask, input = 0;
3591
3592         /* Wait for one bit before transfer */
3593         udelay((devpriv->serial_interval_ns + 999) / 1000);
3594
3595         for (mask = 0x80; mask; mask >>= 1) {
3596                 /* Output current bit; note that we cannot touch s->state
3597                    because it is a per-subdevice field, and serial is
3598                    a separate subdevice from DIO. */
3599                 devpriv->dio_output &= ~NISTC_DIO_SDOUT;
3600                 if (data_out & mask)
3601                         devpriv->dio_output |= NISTC_DIO_SDOUT;
3602                 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3603
3604                 /* Assert SDCLK (active low, inverted), wait for half of
3605                    the delay, deassert SDCLK, and wait for the other half. */
3606                 devpriv->dio_control |= NISTC_DIO_SDCLK;
3607                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3608
3609                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3610
3611                 devpriv->dio_control &= ~NISTC_DIO_SDCLK;
3612                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3613
3614                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3615
3616                 /* Input current bit */
3617                 if (ni_stc_readw(dev, NISTC_DIO_IN_REG) & NISTC_DIO_SDIN)
3618                         input |= mask;
3619         }
3620
3621         if (data_in)
3622                 *data_in = input;
3623
3624         return 0;
3625 }
3626
3627 static int ni_serial_insn_config(struct comedi_device *dev,
3628                                  struct comedi_subdevice *s,
3629                                  struct comedi_insn *insn,
3630                                  unsigned int *data)
3631 {
3632         struct ni_private *devpriv = dev->private;
3633         unsigned clk_fout = devpriv->clock_and_fout;
3634         int err = insn->n;
3635         unsigned char byte_out, byte_in = 0;
3636
3637         if (insn->n != 2)
3638                 return -EINVAL;
3639
3640         switch (data[0]) {
3641         case INSN_CONFIG_SERIAL_CLOCK:
3642                 devpriv->serial_hw_mode = 1;
3643                 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA;
3644
3645                 if (data[1] == SERIAL_DISABLED) {
3646                         devpriv->serial_hw_mode = 0;
3647                         devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3648                                                   NISTC_DIO_SDCLK);
3649                         data[1] = SERIAL_DISABLED;
3650                         devpriv->serial_interval_ns = data[1];
3651                 } else if (data[1] <= SERIAL_600NS) {
3652                         /* Warning: this clock speed is too fast to reliably
3653                            control SCXI. */
3654                         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3655                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE;
3656                         clk_fout &= ~NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3657                         data[1] = SERIAL_600NS;
3658                         devpriv->serial_interval_ns = data[1];
3659                 } else if (data[1] <= SERIAL_1_2US) {
3660                         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3661                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3662                                     NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3663                         data[1] = SERIAL_1_2US;
3664                         devpriv->serial_interval_ns = data[1];
3665                 } else if (data[1] <= SERIAL_10US) {
3666                         devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3667                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3668                                     NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3669                         /* Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects
3670                            600ns/1.2us. If you turn divide_by_2 off with the
3671                            slow clock, you will still get 10us, except then
3672                            all your delays are wrong. */
3673                         data[1] = SERIAL_10US;
3674                         devpriv->serial_interval_ns = data[1];
3675                 } else {
3676                         devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3677                                                   NISTC_DIO_SDCLK);
3678                         devpriv->serial_hw_mode = 0;
3679                         data[1] = (data[1] / 1000) * 1000;
3680                         devpriv->serial_interval_ns = data[1];
3681                 }
3682                 devpriv->clock_and_fout = clk_fout;
3683
3684                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3685                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3686                 return 1;
3687
3688         case INSN_CONFIG_BIDIRECTIONAL_DATA:
3689
3690                 if (devpriv->serial_interval_ns == 0)
3691                         return -EINVAL;
3692
3693                 byte_out = data[1] & 0xFF;
3694
3695                 if (devpriv->serial_hw_mode) {
3696                         err = ni_serial_hw_readwrite8(dev, s, byte_out,
3697                                                       &byte_in);
3698                 } else if (devpriv->serial_interval_ns > 0) {
3699                         err = ni_serial_sw_readwrite8(dev, s, byte_out,
3700                                                       &byte_in);
3701                 } else {
3702                         dev_err(dev->class_dev, "serial disabled!\n");
3703                         return -EINVAL;
3704                 }
3705                 if (err < 0)
3706                         return err;
3707                 data[1] = byte_in & 0xFF;
3708                 return insn->n;
3709
3710                 break;
3711         default:
3712                 return -EINVAL;
3713         }
3714 }
3715
3716 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3717 {
3718         int i;
3719
3720         for (i = 0; i < s->n_chan; i++) {
3721                 ni_ao_win_outw(dev, NI_E_AO_DACSEL(i) | 0x0,
3722                                NI67XX_AO_CFG2_REG);
3723         }
3724         ni_ao_win_outw(dev, 0x0, NI67XX_AO_SP_UPDATES_REG);
3725 }
3726
3727 static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
3728         [NITIO_G0_AUTO_INC]     = { NISTC_G0_AUTOINC_REG, 2 },
3729         [NITIO_G1_AUTO_INC]     = { NISTC_G1_AUTOINC_REG, 2 },
3730         [NITIO_G0_CMD]          = { NISTC_G0_CMD_REG, 2 },
3731         [NITIO_G1_CMD]          = { NISTC_G1_CMD_REG, 2 },
3732         [NITIO_G0_HW_SAVE]      = { NISTC_G0_HW_SAVE_REG, 4 },
3733         [NITIO_G1_HW_SAVE]      = { NISTC_G1_HW_SAVE_REG, 4 },
3734         [NITIO_G0_SW_SAVE]      = { NISTC_G0_SAVE_REG, 4 },
3735         [NITIO_G1_SW_SAVE]      = { NISTC_G1_SAVE_REG, 4 },
3736         [NITIO_G0_MODE]         = { NISTC_G0_MODE_REG, 2 },
3737         [NITIO_G1_MODE]         = { NISTC_G1_MODE_REG, 2 },
3738         [NITIO_G0_LOADA]        = { NISTC_G0_LOADA_REG, 4 },
3739         [NITIO_G1_LOADA]        = { NISTC_G1_LOADA_REG, 4 },
3740         [NITIO_G0_LOADB]        = { NISTC_G0_LOADB_REG, 4 },
3741         [NITIO_G1_LOADB]        = { NISTC_G1_LOADB_REG, 4 },
3742         [NITIO_G0_INPUT_SEL]    = { NISTC_G0_INPUT_SEL_REG, 2 },
3743         [NITIO_G1_INPUT_SEL]    = { NISTC_G1_INPUT_SEL_REG, 2 },
3744         [NITIO_G0_CNT_MODE]     = { 0x1b0, 2 }, /* M-Series only */
3745         [NITIO_G1_CNT_MODE]     = { 0x1b2, 2 }, /* M-Series only */
3746         [NITIO_G0_GATE2]        = { 0x1b4, 2 }, /* M-Series only */
3747         [NITIO_G1_GATE2]        = { 0x1b6, 2 }, /* M-Series only */
3748         [NITIO_G01_STATUS]      = { NISTC_G01_STATUS_REG, 2 },
3749         [NITIO_G01_RESET]       = { NISTC_RESET_REG, 2 },
3750         [NITIO_G01_STATUS1]     = { NISTC_STATUS1_REG, 2 },
3751         [NITIO_G01_STATUS2]     = { NISTC_STATUS2_REG, 2 },
3752         [NITIO_G0_DMA_CFG]      = { 0x1b8, 2 }, /* M-Series only */
3753         [NITIO_G1_DMA_CFG]      = { 0x1ba, 2 }, /* M-Series only */
3754         [NITIO_G0_DMA_STATUS]   = { 0x1b8, 2 }, /* M-Series only */
3755         [NITIO_G1_DMA_STATUS]   = { 0x1ba, 2 }, /* M-Series only */
3756         [NITIO_G0_ABZ]          = { 0x1c0, 2 }, /* M-Series only */
3757         [NITIO_G1_ABZ]          = { 0x1c2, 2 }, /* M-Series only */
3758         [NITIO_G0_INT_ACK]      = { NISTC_INTA_ACK_REG, 2 },
3759         [NITIO_G1_INT_ACK]      = { NISTC_INTB_ACK_REG, 2 },
3760         [NITIO_G0_STATUS]       = { NISTC_AI_STATUS1_REG, 2 },
3761         [NITIO_G1_STATUS]       = { NISTC_AO_STATUS1_REG, 2 },
3762         [NITIO_G0_INT_ENA]      = { NISTC_INTA_ENA_REG, 2 },
3763         [NITIO_G1_INT_ENA]      = { NISTC_INTB_ENA_REG, 2 },
3764 };
3765
3766 static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev,
3767                                             enum ni_gpct_register reg)
3768 {
3769         const struct mio_regmap *regmap;
3770
3771         if (reg < ARRAY_SIZE(ni_gpct_to_stc_regmap)) {
3772                 regmap = &ni_gpct_to_stc_regmap[reg];
3773         } else {
3774                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
3775                          __func__, reg);
3776                 return 0;
3777         }
3778
3779         return regmap->mio_reg;
3780 }
3781
3782 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
3783                                    enum ni_gpct_register reg)
3784 {
3785         struct comedi_device *dev = counter->counter_dev->dev;
3786         unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
3787         static const unsigned gpct_interrupt_a_enable_mask =
3788             NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC;
3789         static const unsigned gpct_interrupt_b_enable_mask =
3790             NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC;
3791
3792         if (stc_register == 0)
3793                 return;
3794
3795         switch (reg) {
3796                 /* m-series only registers */
3797         case NITIO_G0_CNT_MODE:
3798         case NITIO_G1_CNT_MODE:
3799         case NITIO_G0_GATE2:
3800         case NITIO_G1_GATE2:
3801         case NITIO_G0_DMA_CFG:
3802         case NITIO_G1_DMA_CFG:
3803         case NITIO_G0_ABZ:
3804         case NITIO_G1_ABZ:
3805                 ni_writew(dev, bits, stc_register);
3806                 break;
3807
3808                 /* 32 bit registers */
3809         case NITIO_G0_LOADA:
3810         case NITIO_G1_LOADA:
3811         case NITIO_G0_LOADB:
3812         case NITIO_G1_LOADB:
3813                 ni_stc_writel(dev, bits, stc_register);
3814                 break;
3815
3816                 /* 16 bit registers */
3817         case NITIO_G0_INT_ENA:
3818                 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
3819                 ni_set_bitfield(dev, stc_register,
3820                                 gpct_interrupt_a_enable_mask, bits);
3821                 break;
3822         case NITIO_G1_INT_ENA:
3823                 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
3824                 ni_set_bitfield(dev, stc_register,
3825                                 gpct_interrupt_b_enable_mask, bits);
3826                 break;
3827         case NITIO_G01_RESET:
3828                 BUG_ON(bits & ~(NISTC_RESET_G0 | NISTC_RESET_G1));
3829                 /* fall-through */
3830         default:
3831                 ni_stc_writew(dev, bits, stc_register);
3832         }
3833 }
3834
3835 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
3836                                       enum ni_gpct_register reg)
3837 {
3838         struct comedi_device *dev = counter->counter_dev->dev;
3839         unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
3840
3841         if (stc_register == 0)
3842                 return 0;
3843
3844         switch (reg) {
3845                 /* m-series only registers */
3846         case NITIO_G0_DMA_STATUS:
3847         case NITIO_G1_DMA_STATUS:
3848                 return ni_readw(dev, stc_register);
3849
3850                 /* 32 bit registers */
3851         case NITIO_G0_HW_SAVE:
3852         case NITIO_G1_HW_SAVE:
3853         case NITIO_G0_SW_SAVE:
3854         case NITIO_G1_SW_SAVE:
3855                 return ni_stc_readl(dev, stc_register);
3856
3857                 /* 16 bit registers */
3858         default:
3859                 return ni_stc_readw(dev, stc_register);
3860         }
3861 }
3862
3863 static int ni_freq_out_insn_read(struct comedi_device *dev,
3864                                  struct comedi_subdevice *s,
3865                                  struct comedi_insn *insn,
3866                                  unsigned int *data)
3867 {
3868         struct ni_private *devpriv = dev->private;
3869         unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout);
3870         int i;
3871
3872         for (i = 0; i < insn->n; i++)
3873                 data[i] = val;
3874
3875         return insn->n;
3876 }
3877
3878 static int ni_freq_out_insn_write(struct comedi_device *dev,
3879                                   struct comedi_subdevice *s,
3880                                   struct comedi_insn *insn,
3881                                   unsigned int *data)
3882 {
3883         struct ni_private *devpriv = dev->private;
3884
3885         if (insn->n) {
3886                 unsigned int val = data[insn->n - 1];
3887
3888                 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_ENA;
3889                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3890                 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_DIVIDER_MASK;
3891
3892                 /* use the last data value to set the fout divider */
3893                 devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val);
3894
3895                 devpriv->clock_and_fout |= NISTC_CLK_FOUT_ENA;
3896                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3897         }
3898         return insn->n;
3899 }
3900
3901 static int ni_freq_out_insn_config(struct comedi_device *dev,
3902                                    struct comedi_subdevice *s,
3903                                    struct comedi_insn *insn,
3904                                    unsigned int *data)
3905 {
3906         struct ni_private *devpriv = dev->private;
3907
3908         switch (data[0]) {
3909         case INSN_CONFIG_SET_CLOCK_SRC:
3910                 switch (data[1]) {
3911                 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
3912                         devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_TIMEBASE_SEL;
3913                         break;
3914                 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
3915                         devpriv->clock_and_fout |= NISTC_CLK_FOUT_TIMEBASE_SEL;
3916                         break;
3917                 default:
3918                         return -EINVAL;
3919                 }
3920                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3921                 break;
3922         case INSN_CONFIG_GET_CLOCK_SRC:
3923                 if (devpriv->clock_and_fout & NISTC_CLK_FOUT_TIMEBASE_SEL) {
3924                         data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
3925                         data[2] = TIMEBASE_2_NS;
3926                 } else {
3927                         data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
3928                         data[2] = TIMEBASE_1_NS * 2;
3929                 }
3930                 break;
3931         default:
3932                 return -EINVAL;
3933         }
3934         return insn->n;
3935 }
3936
3937 static int ni_8255_callback(struct comedi_device *dev,
3938                             int dir, int port, int data, unsigned long iobase)
3939 {
3940         if (dir) {
3941                 ni_writeb(dev, data, iobase + 2 * port);
3942                 return 0;
3943         }
3944
3945         return ni_readb(dev, iobase + 2 * port);
3946 }
3947
3948 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
3949 {
3950         struct ni_private *devpriv = dev->private;
3951
3952         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
3953         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
3954         return 3;
3955 }
3956
3957 static int ni_m_series_pwm_config(struct comedi_device *dev,
3958                                   struct comedi_subdevice *s,
3959                                   struct comedi_insn *insn,
3960                                   unsigned int *data)
3961 {
3962         struct ni_private *devpriv = dev->private;
3963         unsigned up_count, down_count;
3964
3965         switch (data[0]) {
3966         case INSN_CONFIG_PWM_OUTPUT:
3967                 switch (data[1]) {
3968                 case CMDF_ROUND_NEAREST:
3969                         up_count =
3970                             (data[2] +
3971                              devpriv->clock_ns / 2) / devpriv->clock_ns;
3972                         break;
3973                 case CMDF_ROUND_DOWN:
3974                         up_count = data[2] / devpriv->clock_ns;
3975                         break;
3976                 case CMDF_ROUND_UP:
3977                         up_count =
3978                             (data[2] + devpriv->clock_ns -
3979                              1) / devpriv->clock_ns;
3980                         break;
3981                 default:
3982                         return -EINVAL;
3983                 }
3984                 switch (data[3]) {
3985                 case CMDF_ROUND_NEAREST:
3986                         down_count =
3987                             (data[4] +
3988                              devpriv->clock_ns / 2) / devpriv->clock_ns;
3989                         break;
3990                 case CMDF_ROUND_DOWN:
3991                         down_count = data[4] / devpriv->clock_ns;
3992                         break;
3993                 case CMDF_ROUND_UP:
3994                         down_count =
3995                             (data[4] + devpriv->clock_ns -
3996                              1) / devpriv->clock_ns;
3997                         break;
3998                 default:
3999                         return -EINVAL;
4000                 }
4001                 if (up_count * devpriv->clock_ns != data[2] ||
4002                     down_count * devpriv->clock_ns != data[4]) {
4003                         data[2] = up_count * devpriv->clock_ns;
4004                         data[4] = down_count * devpriv->clock_ns;
4005                         return -EAGAIN;
4006                 }
4007                 ni_writel(dev, NI_M_CAL_PWM_HIGH_TIME(up_count) |
4008                                NI_M_CAL_PWM_LOW_TIME(down_count),
4009                           NI_M_CAL_PWM_REG);
4010                 devpriv->pwm_up_count = up_count;
4011                 devpriv->pwm_down_count = down_count;
4012                 return 5;
4013         case INSN_CONFIG_GET_PWM_OUTPUT:
4014                 return ni_get_pwm_config(dev, data);
4015         default:
4016                 return -EINVAL;
4017         }
4018         return 0;
4019 }
4020
4021 static int ni_6143_pwm_config(struct comedi_device *dev,
4022                               struct comedi_subdevice *s,
4023                               struct comedi_insn *insn,
4024                               unsigned int *data)
4025 {
4026         struct ni_private *devpriv = dev->private;
4027         unsigned up_count, down_count;
4028
4029         switch (data[0]) {
4030         case INSN_CONFIG_PWM_OUTPUT:
4031                 switch (data[1]) {
4032                 case CMDF_ROUND_NEAREST:
4033                         up_count =
4034                             (data[2] +
4035                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4036                         break;
4037                 case CMDF_ROUND_DOWN:
4038                         up_count = data[2] / devpriv->clock_ns;
4039                         break;
4040                 case CMDF_ROUND_UP:
4041                         up_count =
4042                             (data[2] + devpriv->clock_ns -
4043                              1) / devpriv->clock_ns;
4044                         break;
4045                 default:
4046                         return -EINVAL;
4047                 }
4048                 switch (data[3]) {
4049                 case CMDF_ROUND_NEAREST:
4050                         down_count =
4051                             (data[4] +
4052                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4053                         break;
4054                 case CMDF_ROUND_DOWN:
4055                         down_count = data[4] / devpriv->clock_ns;
4056                         break;
4057                 case CMDF_ROUND_UP:
4058                         down_count =
4059                             (data[4] + devpriv->clock_ns -
4060                              1) / devpriv->clock_ns;
4061                         break;
4062                 default:
4063                         return -EINVAL;
4064                 }
4065                 if (up_count * devpriv->clock_ns != data[2] ||
4066                     down_count * devpriv->clock_ns != data[4]) {
4067                         data[2] = up_count * devpriv->clock_ns;
4068                         data[4] = down_count * devpriv->clock_ns;
4069                         return -EAGAIN;
4070                 }
4071                 ni_writel(dev, up_count, NI6143_CALIB_HI_TIME_REG);
4072                 devpriv->pwm_up_count = up_count;
4073                 ni_writel(dev, down_count, NI6143_CALIB_LO_TIME_REG);
4074                 devpriv->pwm_down_count = down_count;
4075                 return 5;
4076         case INSN_CONFIG_GET_PWM_OUTPUT:
4077                 return ni_get_pwm_config(dev, data);
4078         default:
4079                 return -EINVAL;
4080         }
4081         return 0;
4082 }
4083
4084 static int pack_mb88341(int addr, int val, int *bitstring)
4085 {
4086         /*
4087            Fujitsu MB 88341
4088            Note that address bits are reversed.  Thanks to
4089            Ingo Keen for noticing this.
4090
4091            Note also that the 88341 expects address values from
4092            1-12, whereas we use channel numbers 0-11.  The NI
4093            docs use 1-12, also, so be careful here.
4094          */
4095         addr++;
4096         *bitstring = ((addr & 0x1) << 11) |
4097             ((addr & 0x2) << 9) |
4098             ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4099         return 12;
4100 }
4101
4102 static int pack_dac8800(int addr, int val, int *bitstring)
4103 {
4104         *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4105         return 11;
4106 }
4107
4108 static int pack_dac8043(int addr, int val, int *bitstring)
4109 {
4110         *bitstring = val & 0xfff;
4111         return 12;
4112 }
4113
4114 static int pack_ad8522(int addr, int val, int *bitstring)
4115 {
4116         *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4117         return 16;
4118 }
4119
4120 static int pack_ad8804(int addr, int val, int *bitstring)
4121 {
4122         *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4123         return 12;
4124 }
4125
4126 static int pack_ad8842(int addr, int val, int *bitstring)
4127 {
4128         *bitstring = ((addr + 1) << 8) | (val & 0xff);
4129         return 12;
4130 }
4131
4132 struct caldac_struct {
4133         int n_chans;
4134         int n_bits;
4135         int (*packbits)(int, int, int *);
4136 };
4137
4138 static struct caldac_struct caldacs[] = {
4139         [mb88341] = {12, 8, pack_mb88341},
4140         [dac8800] = {8, 8, pack_dac8800},
4141         [dac8043] = {1, 12, pack_dac8043},
4142         [ad8522] = {2, 12, pack_ad8522},
4143         [ad8804] = {12, 8, pack_ad8804},
4144         [ad8842] = {8, 8, pack_ad8842},
4145         [ad8804_debug] = {16, 8, pack_ad8804},
4146 };
4147
4148 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4149 {
4150         const struct ni_board_struct *board = dev->board_ptr;
4151         struct ni_private *devpriv = dev->private;
4152         unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4153         unsigned int cmd;
4154         int i;
4155         int type;
4156
4157         if (devpriv->caldacs[addr] == val)
4158                 return;
4159         devpriv->caldacs[addr] = val;
4160
4161         for (i = 0; i < 3; i++) {
4162                 type = board->caldac[i];
4163                 if (type == caldac_none)
4164                         break;
4165                 if (addr < caldacs[type].n_chans) {
4166                         bits = caldacs[type].packbits(addr, val, &bitstring);
4167                         loadbit = NI_E_SERIAL_CMD_DAC_LD(i);
4168                         break;
4169                 }
4170                 addr -= caldacs[type].n_chans;
4171         }
4172
4173         /* bits will be 0 if there is no caldac for the given addr */
4174         if (bits == 0)
4175                 return;
4176
4177         for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4178                 cmd = (bit & bitstring) ? NI_E_SERIAL_CMD_SDATA : 0;
4179                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4180                 udelay(1);
4181                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4182                 udelay(1);
4183         }
4184         ni_writeb(dev, loadbit, NI_E_SERIAL_CMD_REG);
4185         udelay(1);
4186         ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4187 }
4188
4189 static int ni_calib_insn_write(struct comedi_device *dev,
4190                                struct comedi_subdevice *s,
4191                                struct comedi_insn *insn,
4192                                unsigned int *data)
4193 {
4194         ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4195
4196         return 1;
4197 }
4198
4199 static int ni_calib_insn_read(struct comedi_device *dev,
4200                               struct comedi_subdevice *s,
4201                               struct comedi_insn *insn,
4202                               unsigned int *data)
4203 {
4204         struct ni_private *devpriv = dev->private;
4205
4206         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4207
4208         return 1;
4209 }
4210
4211 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4212 {
4213         const struct ni_board_struct *board = dev->board_ptr;
4214         struct ni_private *devpriv = dev->private;
4215         int i, j;
4216         int n_dacs;
4217         int n_chans = 0;
4218         int n_bits;
4219         int diffbits = 0;
4220         int type;
4221         int chan;
4222
4223         type = board->caldac[0];
4224         if (type == caldac_none)
4225                 return;
4226         n_bits = caldacs[type].n_bits;
4227         for (i = 0; i < 3; i++) {
4228                 type = board->caldac[i];
4229                 if (type == caldac_none)
4230                         break;
4231                 if (caldacs[type].n_bits != n_bits)
4232                         diffbits = 1;
4233                 n_chans += caldacs[type].n_chans;
4234         }
4235         n_dacs = i;
4236         s->n_chan = n_chans;
4237
4238         if (diffbits) {
4239                 unsigned int *maxdata_list;
4240
4241                 if (n_chans > MAX_N_CALDACS)
4242                         dev_err(dev->class_dev,
4243                                 "BUG! MAX_N_CALDACS too small\n");
4244                 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4245                 chan = 0;
4246                 for (i = 0; i < n_dacs; i++) {
4247                         type = board->caldac[i];
4248                         for (j = 0; j < caldacs[type].n_chans; j++) {
4249                                 maxdata_list[chan] =
4250                                     (1 << caldacs[type].n_bits) - 1;
4251                                 chan++;
4252                         }
4253                 }
4254
4255                 for (chan = 0; chan < s->n_chan; chan++)
4256                         ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4257         } else {
4258                 type = board->caldac[0];
4259                 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4260
4261                 for (chan = 0; chan < s->n_chan; chan++)
4262                         ni_write_caldac(dev, i, s->maxdata / 2);
4263         }
4264 }
4265
4266 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4267 {
4268         unsigned int cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4269         int bit;
4270         int bitstring;
4271
4272         bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4273         ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4274         for (bit = 0x8000; bit; bit >>= 1) {
4275                 if (bit & bitstring)
4276                         cmd |= NI_E_SERIAL_CMD_SDATA;
4277                 else
4278                         cmd &= ~NI_E_SERIAL_CMD_SDATA;
4279
4280                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4281                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4282         }
4283         cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4284         bitstring = 0;
4285         for (bit = 0x80; bit; bit >>= 1) {
4286                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4287                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4288                 if (ni_readb(dev, NI_E_STATUS_REG) & NI_E_STATUS_PROMOUT)
4289                         bitstring |= bit;
4290         }
4291         ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4292
4293         return bitstring;
4294 }
4295
4296 static int ni_eeprom_insn_read(struct comedi_device *dev,
4297                                struct comedi_subdevice *s,
4298                                struct comedi_insn *insn,
4299                                unsigned int *data)
4300 {
4301         data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4302
4303         return 1;
4304 }
4305
4306 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4307                                         struct comedi_subdevice *s,
4308                                         struct comedi_insn *insn,
4309                                         unsigned int *data)
4310 {
4311         struct ni_private *devpriv = dev->private;
4312
4313         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4314
4315         return 1;
4316 }
4317
4318 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
4319                                        unsigned chan)
4320 {
4321         /*  pre-m-series boards have fixed signals on pfi pins */
4322         switch (chan) {
4323         case 0:
4324                 return NI_PFI_OUTPUT_AI_START1;
4325         case 1:
4326                 return NI_PFI_OUTPUT_AI_START2;
4327         case 2:
4328                 return NI_PFI_OUTPUT_AI_CONVERT;
4329         case 3:
4330                 return NI_PFI_OUTPUT_G_SRC1;
4331         case 4:
4332                 return NI_PFI_OUTPUT_G_GATE1;
4333         case 5:
4334                 return NI_PFI_OUTPUT_AO_UPDATE_N;
4335         case 6:
4336                 return NI_PFI_OUTPUT_AO_START1;
4337         case 7:
4338                 return NI_PFI_OUTPUT_AI_START_PULSE;
4339         case 8:
4340                 return NI_PFI_OUTPUT_G_SRC0;
4341         case 9:
4342                 return NI_PFI_OUTPUT_G_GATE0;
4343         default:
4344                 dev_err(dev->class_dev, "bug, unhandled case in switch.\n");
4345                 break;
4346         }
4347         return 0;
4348 }
4349
4350 static int ni_old_set_pfi_routing(struct comedi_device *dev,
4351                                   unsigned chan, unsigned source)
4352 {
4353         /*  pre-m-series boards have fixed signals on pfi pins */
4354         if (source != ni_old_get_pfi_routing(dev, chan))
4355                 return -EINVAL;
4356         return 2;
4357 }
4358
4359 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
4360                                             unsigned chan)
4361 {
4362         struct ni_private *devpriv = dev->private;
4363         const unsigned array_offset = chan / 3;
4364
4365         return NI_M_PFI_OUT_SEL_TO_SRC(chan,
4366                                 devpriv->pfi_output_select_reg[array_offset]);
4367 }
4368
4369 static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4370                                        unsigned chan, unsigned source)
4371 {
4372         struct ni_private *devpriv = dev->private;
4373         unsigned index = chan / 3;
4374         unsigned short val = devpriv->pfi_output_select_reg[index];
4375
4376         if ((source & 0x1f) != source)
4377                 return -EINVAL;
4378
4379         val &= ~NI_M_PFI_OUT_SEL_MASK(chan);
4380         val |= NI_M_PFI_OUT_SEL(chan, source);
4381         ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index));
4382         devpriv->pfi_output_select_reg[index] = val;
4383
4384         return 2;
4385 }
4386
4387 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
4388 {
4389         struct ni_private *devpriv = dev->private;
4390
4391         return (devpriv->is_m_series)
4392                         ? ni_m_series_get_pfi_routing(dev, chan)
4393                         : ni_old_get_pfi_routing(dev, chan);
4394 }
4395
4396 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
4397                               unsigned source)
4398 {
4399         struct ni_private *devpriv = dev->private;
4400
4401         return (devpriv->is_m_series)
4402                         ? ni_m_series_set_pfi_routing(dev, chan, source)
4403                         : ni_old_set_pfi_routing(dev, chan, source);
4404 }
4405
4406 static int ni_config_filter(struct comedi_device *dev,
4407                             unsigned pfi_channel,
4408                             enum ni_pfi_filter_select filter)
4409 {
4410         struct ni_private *devpriv = dev->private;
4411         unsigned bits;
4412
4413         if (!devpriv->is_m_series)
4414                 return -ENOTSUPP;
4415
4416         bits = ni_readl(dev, NI_M_PFI_FILTER_REG);
4417         bits &= ~NI_M_PFI_FILTER_SEL_MASK(pfi_channel);
4418         bits |= NI_M_PFI_FILTER_SEL(pfi_channel, filter);
4419         ni_writel(dev, bits, NI_M_PFI_FILTER_REG);
4420         return 0;
4421 }
4422
4423 static int ni_pfi_insn_config(struct comedi_device *dev,
4424                               struct comedi_subdevice *s,
4425                               struct comedi_insn *insn,
4426                               unsigned int *data)
4427 {
4428         struct ni_private *devpriv = dev->private;
4429         unsigned int chan;
4430
4431         if (insn->n < 1)
4432                 return -EINVAL;
4433
4434         chan = CR_CHAN(insn->chanspec);
4435
4436         switch (data[0]) {
4437         case COMEDI_OUTPUT:
4438                 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 1);
4439                 break;
4440         case COMEDI_INPUT:
4441                 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 0);
4442                 break;
4443         case INSN_CONFIG_DIO_QUERY:
4444                 data[1] =
4445                     (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
4446                     COMEDI_OUTPUT : COMEDI_INPUT;
4447                 return 0;
4448         case INSN_CONFIG_SET_ROUTING:
4449                 return ni_set_pfi_routing(dev, chan, data[1]);
4450         case INSN_CONFIG_GET_ROUTING:
4451                 data[1] = ni_get_pfi_routing(dev, chan);
4452                 break;
4453         case INSN_CONFIG_FILTER:
4454                 return ni_config_filter(dev, chan, data[1]);
4455         default:
4456                 return -EINVAL;
4457         }
4458         return 0;
4459 }
4460
4461 static int ni_pfi_insn_bits(struct comedi_device *dev,
4462                             struct comedi_subdevice *s,
4463                             struct comedi_insn *insn,
4464                             unsigned int *data)
4465 {
4466         struct ni_private *devpriv = dev->private;
4467
4468         if (!devpriv->is_m_series)
4469                 return -ENOTSUPP;
4470
4471         if (comedi_dio_update_state(s, data))
4472                 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
4473
4474         data[1] = ni_readw(dev, NI_M_PFI_DI_REG);
4475
4476         return insn->n;
4477 }
4478
4479 static int cs5529_wait_for_idle(struct comedi_device *dev)
4480 {
4481         unsigned short status;
4482         const int timeout = HZ;
4483         int i;
4484
4485         for (i = 0; i < timeout; i++) {
4486                 status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4487                 if ((status & NI67XX_CAL_STATUS_BUSY) == 0)
4488                         break;
4489                 set_current_state(TASK_INTERRUPTIBLE);
4490                 if (schedule_timeout(1))
4491                         return -EIO;
4492         }
4493         if (i == timeout) {
4494                 dev_err(dev->class_dev, "timeout\n");
4495                 return -ETIME;
4496         }
4497         return 0;
4498 }
4499
4500 static void cs5529_command(struct comedi_device *dev, unsigned short value)
4501 {
4502         static const int timeout = 100;
4503         int i;
4504
4505         ni_ao_win_outw(dev, value, NI67XX_CAL_CMD_REG);
4506         /* give time for command to start being serially clocked into cs5529.
4507          * this insures that the NI67XX_CAL_STATUS_BUSY bit will get properly
4508          * set before we exit this function.
4509          */
4510         for (i = 0; i < timeout; i++) {
4511                 if (ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG) &
4512                     NI67XX_CAL_STATUS_BUSY)
4513                         break;
4514                 udelay(1);
4515         }
4516         if (i == timeout)
4517                 dev_err(dev->class_dev,
4518                         "possible problem - never saw adc go busy?\n");
4519 }
4520
4521 static int cs5529_do_conversion(struct comedi_device *dev,
4522                                 unsigned short *data)
4523 {
4524         int retval;
4525         unsigned short status;
4526
4527         cs5529_command(dev, CS5529_CMD_CB | CS5529_CMD_SINGLE_CONV);
4528         retval = cs5529_wait_for_idle(dev);
4529         if (retval) {
4530                 dev_err(dev->class_dev,
4531                         "timeout or signal in cs5529_do_conversion()\n");
4532                 return -ETIME;
4533         }
4534         status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4535         if (status & NI67XX_CAL_STATUS_OSC_DETECT) {
4536                 dev_err(dev->class_dev,
4537                         "cs5529 conversion error, status CSS_OSC_DETECT\n");
4538                 return -EIO;
4539         }
4540         if (status & NI67XX_CAL_STATUS_OVERRANGE) {
4541                 dev_err(dev->class_dev,
4542                         "cs5529 conversion error, overrange (ignoring)\n");
4543         }
4544         if (data) {
4545                 *data = ni_ao_win_inw(dev, NI67XX_CAL_DATA_REG);
4546                 /* cs5529 returns 16 bit signed data in bipolar mode */
4547                 *data ^= (1 << 15);
4548         }
4549         return 0;
4550 }
4551
4552 static int cs5529_ai_insn_read(struct comedi_device *dev,
4553                                struct comedi_subdevice *s,
4554                                struct comedi_insn *insn,
4555                                unsigned int *data)
4556 {
4557         int n, retval;
4558         unsigned short sample;
4559         unsigned int channel_select;
4560         const unsigned int INTERNAL_REF = 0x1000;
4561
4562         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
4563          * do nothing. bit 12 seems to chooses internal reference voltage, bit
4564          * 13 causes the adc input to go overrange (maybe reads external reference?) */
4565         if (insn->chanspec & CR_ALT_SOURCE)
4566                 channel_select = INTERNAL_REF;
4567         else
4568                 channel_select = CR_CHAN(insn->chanspec);
4569         ni_ao_win_outw(dev, channel_select, NI67XX_AO_CAL_CHAN_SEL_REG);
4570
4571         for (n = 0; n < insn->n; n++) {
4572                 retval = cs5529_do_conversion(dev, &sample);
4573                 if (retval < 0)
4574                         return retval;
4575                 data[n] = sample;
4576         }
4577         return insn->n;
4578 }
4579
4580 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
4581                                 unsigned int reg_select_bits)
4582 {
4583         ni_ao_win_outw(dev, (value >> 16) & 0xff, NI67XX_CAL_CFG_HI_REG);
4584         ni_ao_win_outw(dev, value & 0xffff, NI67XX_CAL_CFG_LO_REG);
4585         reg_select_bits &= CS5529_CMD_REG_MASK;
4586         cs5529_command(dev, CS5529_CMD_CB | reg_select_bits);
4587         if (cs5529_wait_for_idle(dev))
4588                 dev_err(dev->class_dev,
4589                         "timeout or signal in %s\n", __func__);
4590 }
4591
4592 static int init_cs5529(struct comedi_device *dev)
4593 {
4594         unsigned int config_bits = CS5529_CFG_PORT_FLAG |
4595                                    CS5529_CFG_WORD_RATE_2180;
4596
4597 #if 1
4598         /* do self-calibration */
4599         cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_BOTH_SELF,
4600                             CS5529_CFG_REG);
4601         /* need to force a conversion for calibration to run */
4602         cs5529_do_conversion(dev, NULL);
4603 #else
4604         /* force gain calibration to 1 */
4605         cs5529_config_write(dev, 0x400000, CS5529_GAIN_REG);
4606         cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_OFFSET_SELF,
4607                             CS5529_CFG_REG);
4608         if (cs5529_wait_for_idle(dev))
4609                 dev_err(dev->class_dev,
4610                         "timeout or signal in %s\n", __func__);
4611 #endif
4612         return 0;
4613 }
4614
4615 /*
4616  * Find best multiplier/divider to try and get the PLL running at 80 MHz
4617  * given an arbitrary frequency input clock.
4618  */
4619 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
4620                                          unsigned *freq_divider,
4621                                          unsigned *freq_multiplier,
4622                                          unsigned *actual_period_ns)
4623 {
4624         unsigned div;
4625         unsigned best_div = 1;
4626         unsigned mult;
4627         unsigned best_mult = 1;
4628         static const unsigned pico_per_nano = 1000;
4629
4630         const unsigned reference_picosec = reference_period_ns * pico_per_nano;
4631         /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
4632          * 20 MHz for most timing clocks */
4633         static const unsigned target_picosec = 12500;
4634         static const unsigned fudge_factor_80_to_20Mhz = 4;
4635         int best_period_picosec = 0;
4636
4637         for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) {
4638                 for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) {
4639                         unsigned new_period_ps =
4640                             (reference_picosec * div) / mult;
4641                         if (abs(new_period_ps - target_picosec) <
4642                             abs(best_period_picosec - target_picosec)) {
4643                                 best_period_picosec = new_period_ps;
4644                                 best_div = div;
4645                                 best_mult = mult;
4646                         }
4647                 }
4648         }
4649         if (best_period_picosec == 0)
4650                 return -EIO;
4651
4652         *freq_divider = best_div;
4653         *freq_multiplier = best_mult;
4654         *actual_period_ns =
4655             (best_period_picosec * fudge_factor_80_to_20Mhz +
4656              (pico_per_nano / 2)) / pico_per_nano;
4657         return 0;
4658 }
4659
4660 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4661                                            unsigned source, unsigned period_ns)
4662 {
4663         struct ni_private *devpriv = dev->private;
4664         static const unsigned min_period_ns = 50;
4665         static const unsigned max_period_ns = 1000;
4666         static const unsigned timeout = 1000;
4667         unsigned pll_control_bits;
4668         unsigned freq_divider;
4669         unsigned freq_multiplier;
4670         unsigned rtsi;
4671         unsigned i;
4672         int retval;
4673
4674         if (source == NI_MIO_PLL_PXI10_CLOCK)
4675                 period_ns = 100;
4676         /*  these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
4677         if (period_ns < min_period_ns || period_ns > max_period_ns) {
4678                 dev_err(dev->class_dev,
4679                         "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n",
4680                         __func__, min_period_ns, max_period_ns);
4681                 return -EINVAL;
4682         }
4683         devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4684         ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4685                       NISTC_RTSI_TRIG_DIR_REG);
4686         pll_control_bits = NI_M_PLL_CTRL_ENA | NI_M_PLL_CTRL_VCO_MODE_75_150MHZ;
4687         devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4688                                     NI_M_CLK_FOUT2_TIMEBASE3_PLL;
4689         devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK;
4690         switch (source) {
4691         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4692                 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR;
4693                 break;
4694         case NI_MIO_PLL_PXI10_CLOCK:
4695                 /* pxi clock is 10MHz */
4696                 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10;
4697                 break;
4698         default:
4699                 for (rtsi = 0; rtsi <= NI_M_MAX_RTSI_CHAN; ++rtsi) {
4700                         if (source == NI_MIO_PLL_RTSI_CLOCK(rtsi)) {
4701                                 devpriv->clock_and_fout2 |=
4702                                         NI_M_CLK_FOUT2_PLL_SRC_RTSI(rtsi);
4703                                 break;
4704                         }
4705                 }
4706                 if (rtsi > NI_M_MAX_RTSI_CHAN)
4707                         return -EINVAL;
4708                 break;
4709         }
4710         retval = ni_mseries_get_pll_parameters(period_ns,
4711                                                &freq_divider,
4712                                                &freq_multiplier,
4713                                                &devpriv->clock_ns);
4714         if (retval < 0) {
4715                 dev_err(dev->class_dev,
4716                         "bug, failed to find pll parameters\n");
4717                 return retval;
4718         }
4719
4720         ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG);
4721         pll_control_bits |= NI_M_PLL_CTRL_DIVISOR(freq_divider) |
4722                             NI_M_PLL_CTRL_MULTIPLIER(freq_multiplier);
4723
4724         ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG);
4725         devpriv->clock_source = source;
4726         /* it seems to typically take a few hundred microseconds for PLL to lock */
4727         for (i = 0; i < timeout; ++i) {
4728                 if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED)
4729                         break;
4730                 udelay(1);
4731         }
4732         if (i == timeout) {
4733                 dev_err(dev->class_dev,
4734                         "%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n",
4735                         __func__, source, period_ns);
4736                 return -ETIMEDOUT;
4737         }
4738         return 3;
4739 }
4740
4741 static int ni_set_master_clock(struct comedi_device *dev,
4742                                unsigned source, unsigned period_ns)
4743 {
4744         struct ni_private *devpriv = dev->private;
4745
4746         if (source == NI_MIO_INTERNAL_CLOCK) {
4747                 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4748                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4749                               NISTC_RTSI_TRIG_DIR_REG);
4750                 devpriv->clock_ns = TIMEBASE_1_NS;
4751                 if (devpriv->is_m_series) {
4752                         devpriv->clock_and_fout2 &=
4753                             ~(NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4754                               NI_M_CLK_FOUT2_TIMEBASE3_PLL);
4755                         ni_writew(dev, devpriv->clock_and_fout2,
4756                                   NI_M_CLK_FOUT2_REG);
4757                         ni_writew(dev, 0, NI_M_PLL_CTRL_REG);
4758                 }
4759                 devpriv->clock_source = source;
4760         } else {
4761                 if (devpriv->is_m_series) {
4762                         return ni_mseries_set_pll_master_clock(dev, source,
4763                                                                period_ns);
4764                 } else {
4765                         if (source == NI_MIO_RTSI_CLOCK) {
4766                                 devpriv->rtsi_trig_direction_reg |=
4767                                     NISTC_RTSI_TRIG_USE_CLK;
4768                                 ni_stc_writew(dev,
4769                                               devpriv->rtsi_trig_direction_reg,
4770                                               NISTC_RTSI_TRIG_DIR_REG);
4771                                 if (period_ns == 0) {
4772                                         dev_err(dev->class_dev,
4773                                                 "we don't handle an unspecified clock period correctly yet, returning error\n");
4774                                         return -EINVAL;
4775                                 }
4776                                 devpriv->clock_ns = period_ns;
4777                                 devpriv->clock_source = source;
4778                         } else {
4779                                 return -EINVAL;
4780                         }
4781                 }
4782         }
4783         return 3;
4784 }
4785
4786 static int ni_valid_rtsi_output_source(struct comedi_device *dev,
4787                                        unsigned chan, unsigned source)
4788 {
4789         struct ni_private *devpriv = dev->private;
4790
4791         if (chan >= NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
4792                 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4793                         if (source == NI_RTSI_OUTPUT_RTSI_OSC)
4794                                 return 1;
4795
4796                         dev_err(dev->class_dev,
4797                                 "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n",
4798                                 __func__, chan, NISTC_RTSI_TRIG_OLD_CLK_CHAN);
4799                         return 0;
4800                 }
4801                 return 0;
4802         }
4803         switch (source) {
4804         case NI_RTSI_OUTPUT_ADR_START1:
4805         case NI_RTSI_OUTPUT_ADR_START2:
4806         case NI_RTSI_OUTPUT_SCLKG:
4807         case NI_RTSI_OUTPUT_DACUPDN:
4808         case NI_RTSI_OUTPUT_DA_START1:
4809         case NI_RTSI_OUTPUT_G_SRC0:
4810         case NI_RTSI_OUTPUT_G_GATE0:
4811         case NI_RTSI_OUTPUT_RGOUT0:
4812         case NI_RTSI_OUTPUT_RTSI_BRD(0):
4813         case NI_RTSI_OUTPUT_RTSI_BRD(1):
4814         case NI_RTSI_OUTPUT_RTSI_BRD(2):
4815         case NI_RTSI_OUTPUT_RTSI_BRD(3):
4816                 return 1;
4817         case NI_RTSI_OUTPUT_RTSI_OSC:
4818                 return (devpriv->is_m_series) ? 1 : 0;
4819         default:
4820                 return 0;
4821         }
4822 }
4823
4824 static int ni_set_rtsi_routing(struct comedi_device *dev,
4825                                unsigned chan, unsigned src)
4826 {
4827         struct ni_private *devpriv = dev->private;
4828
4829         if (ni_valid_rtsi_output_source(dev, chan, src) == 0)
4830                 return -EINVAL;
4831         if (chan < 4) {
4832                 devpriv->rtsi_trig_a_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
4833                 devpriv->rtsi_trig_a_output_reg |= NISTC_RTSI_TRIG(chan, src);
4834                 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4835                               NISTC_RTSI_TRIGA_OUT_REG);
4836         } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
4837                 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
4838                 devpriv->rtsi_trig_b_output_reg |= NISTC_RTSI_TRIG(chan, src);
4839                 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4840                               NISTC_RTSI_TRIGB_OUT_REG);
4841         } else if (chan != NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4842                 /* probably should never reach this, since the
4843                  * ni_valid_rtsi_output_source above errors out if chan is too
4844                  * high
4845                  */
4846                 dev_err(dev->class_dev, "%s: unknown rtsi channel\n", __func__);
4847                 return -EINVAL;
4848         }
4849         return 2;
4850 }
4851
4852 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
4853 {
4854         struct ni_private *devpriv = dev->private;
4855
4856         if (chan < 4) {
4857                 return NISTC_RTSI_TRIG_TO_SRC(chan,
4858                                               devpriv->rtsi_trig_a_output_reg);
4859         } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
4860                 return NISTC_RTSI_TRIG_TO_SRC(chan,
4861                                               devpriv->rtsi_trig_b_output_reg);
4862         } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4863                 return NI_RTSI_OUTPUT_RTSI_OSC;
4864         }
4865
4866         dev_err(dev->class_dev, "%s: unknown rtsi channel\n", __func__);
4867         return -EINVAL;
4868 }
4869
4870 static int ni_rtsi_insn_config(struct comedi_device *dev,
4871                                struct comedi_subdevice *s,
4872                                struct comedi_insn *insn,
4873                                unsigned int *data)
4874 {
4875         struct ni_private *devpriv = dev->private;
4876         unsigned int chan = CR_CHAN(insn->chanspec);
4877         unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series);
4878
4879         switch (data[0]) {
4880         case INSN_CONFIG_DIO_OUTPUT:
4881                 if (chan < max_chan) {
4882                         devpriv->rtsi_trig_direction_reg |=
4883                             NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
4884                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4885                         devpriv->rtsi_trig_direction_reg |=
4886                             NISTC_RTSI_TRIG_DRV_CLK;
4887                 }
4888                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4889                               NISTC_RTSI_TRIG_DIR_REG);
4890                 break;
4891         case INSN_CONFIG_DIO_INPUT:
4892                 if (chan < max_chan) {
4893                         devpriv->rtsi_trig_direction_reg &=
4894                             ~NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
4895                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4896                         devpriv->rtsi_trig_direction_reg &=
4897                             ~NISTC_RTSI_TRIG_DRV_CLK;
4898                 }
4899                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4900                               NISTC_RTSI_TRIG_DIR_REG);
4901                 break;
4902         case INSN_CONFIG_DIO_QUERY:
4903                 if (chan < max_chan) {
4904                         data[1] =
4905                             (devpriv->rtsi_trig_direction_reg &
4906                              NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series))
4907                                 ? INSN_CONFIG_DIO_OUTPUT
4908                                 : INSN_CONFIG_DIO_INPUT;
4909                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4910                         data[1] = (devpriv->rtsi_trig_direction_reg &
4911                                    NISTC_RTSI_TRIG_DRV_CLK)
4912                                   ? INSN_CONFIG_DIO_OUTPUT
4913                                   : INSN_CONFIG_DIO_INPUT;
4914                 }
4915                 return 2;
4916         case INSN_CONFIG_SET_CLOCK_SRC:
4917                 return ni_set_master_clock(dev, data[1], data[2]);
4918         case INSN_CONFIG_GET_CLOCK_SRC:
4919                 data[1] = devpriv->clock_source;
4920                 data[2] = devpriv->clock_ns;
4921                 return 3;
4922         case INSN_CONFIG_SET_ROUTING:
4923                 return ni_set_rtsi_routing(dev, chan, data[1]);
4924         case INSN_CONFIG_GET_ROUTING:
4925                 data[1] = ni_get_rtsi_routing(dev, chan);
4926                 return 2;
4927         default:
4928                 return -EINVAL;
4929         }
4930         return 1;
4931 }
4932
4933 static int ni_rtsi_insn_bits(struct comedi_device *dev,
4934                              struct comedi_subdevice *s,
4935                              struct comedi_insn *insn,
4936                              unsigned int *data)
4937 {
4938         data[1] = 0;
4939
4940         return insn->n;
4941 }
4942
4943 static void ni_rtsi_init(struct comedi_device *dev)
4944 {
4945         struct ni_private *devpriv = dev->private;
4946
4947         /*  Initialises the RTSI bus signal switch to a default state */
4948
4949         /*
4950          * Use 10MHz instead of 20MHz for RTSI clock frequency. Appears
4951          * to have no effect, at least on pxi-6281, which always uses
4952          * 20MHz rtsi clock frequency
4953          */
4954         devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ;
4955         /*  Set clock mode to internal */
4956         if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
4957                 dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n");
4958         /*  default internal lines routing to RTSI bus lines */
4959         devpriv->rtsi_trig_a_output_reg =
4960             NISTC_RTSI_TRIG(0, NI_RTSI_OUTPUT_ADR_START1) |
4961             NISTC_RTSI_TRIG(1, NI_RTSI_OUTPUT_ADR_START2) |
4962             NISTC_RTSI_TRIG(2, NI_RTSI_OUTPUT_SCLKG) |
4963             NISTC_RTSI_TRIG(3, NI_RTSI_OUTPUT_DACUPDN);
4964         ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4965                       NISTC_RTSI_TRIGA_OUT_REG);
4966         devpriv->rtsi_trig_b_output_reg =
4967             NISTC_RTSI_TRIG(4, NI_RTSI_OUTPUT_DA_START1) |
4968             NISTC_RTSI_TRIG(5, NI_RTSI_OUTPUT_G_SRC0) |
4969             NISTC_RTSI_TRIG(6, NI_RTSI_OUTPUT_G_GATE0);
4970         if (devpriv->is_m_series)
4971                 devpriv->rtsi_trig_b_output_reg |=
4972                     NISTC_RTSI_TRIG(7, NI_RTSI_OUTPUT_RTSI_OSC);
4973         ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4974                       NISTC_RTSI_TRIGB_OUT_REG);
4975
4976         /*
4977          * Sets the source and direction of the 4 on board lines
4978          * ni_stc_writew(dev, 0, NISTC_RTSI_BOARD_REG);
4979          */
4980 }
4981
4982 #ifdef PCIDMA
4983 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
4984 {
4985         struct ni_gpct *counter = s->private;
4986         int retval;
4987
4988         retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
4989                                               COMEDI_INPUT);
4990         if (retval) {
4991                 dev_err(dev->class_dev,
4992                         "no dma channel available for use by counter\n");
4993                 return retval;
4994         }
4995         ni_tio_acknowledge(counter);
4996         ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
4997
4998         return ni_tio_cmd(dev, s);
4999 }
5000
5001 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5002 {
5003         struct ni_gpct *counter = s->private;
5004         int retval;
5005
5006         retval = ni_tio_cancel(counter);
5007         ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5008         ni_release_gpct_mite_channel(dev, counter->counter_index);
5009         return retval;
5010 }
5011 #endif
5012
5013 static irqreturn_t ni_E_interrupt(int irq, void *d)
5014 {
5015         struct comedi_device *dev = d;
5016         unsigned short a_status;
5017         unsigned short b_status;
5018         unsigned int ai_mite_status = 0;
5019         unsigned int ao_mite_status = 0;
5020         unsigned long flags;
5021 #ifdef PCIDMA
5022         struct ni_private *devpriv = dev->private;
5023         struct mite_struct *mite = devpriv->mite;
5024 #endif
5025
5026         if (!dev->attached)
5027                 return IRQ_NONE;
5028         smp_mb();               /*  make sure dev->attached is checked before handler does anything else. */
5029
5030         /*  lock to avoid race with comedi_poll */
5031         spin_lock_irqsave(&dev->spinlock, flags);
5032         a_status = ni_stc_readw(dev, NISTC_AI_STATUS1_REG);
5033         b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
5034 #ifdef PCIDMA
5035         if (mite) {
5036                 struct ni_private *devpriv = dev->private;
5037                 unsigned long flags_too;
5038
5039                 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
5040                 if (devpriv->ai_mite_chan) {
5041                         ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
5042                         if (ai_mite_status & CHSR_LINKC)
5043                                 writel(CHOR_CLRLC,
5044                                        devpriv->mite->mite_io_addr +
5045                                        MITE_CHOR(devpriv->
5046                                                  ai_mite_chan->channel));
5047                 }
5048                 if (devpriv->ao_mite_chan) {
5049                         ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
5050                         if (ao_mite_status & CHSR_LINKC)
5051                                 writel(CHOR_CLRLC,
5052                                        mite->mite_io_addr +
5053                                        MITE_CHOR(devpriv->
5054                                                  ao_mite_chan->channel));
5055                 }
5056                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
5057         }
5058 #endif
5059         ack_a_interrupt(dev, a_status);
5060         ack_b_interrupt(dev, b_status);
5061         if ((a_status & NISTC_AI_STATUS1_INTA) || (ai_mite_status & CHSR_INT))
5062                 handle_a_interrupt(dev, a_status, ai_mite_status);
5063         if ((b_status & NISTC_AO_STATUS1_INTB) || (ao_mite_status & CHSR_INT))
5064                 handle_b_interrupt(dev, b_status, ao_mite_status);
5065         handle_gpct_interrupt(dev, 0);
5066         handle_gpct_interrupt(dev, 1);
5067         handle_cdio_interrupt(dev);
5068
5069         spin_unlock_irqrestore(&dev->spinlock, flags);
5070         return IRQ_HANDLED;
5071 }
5072
5073 static int ni_alloc_private(struct comedi_device *dev)
5074 {
5075         struct ni_private *devpriv;
5076
5077         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
5078         if (!devpriv)
5079                 return -ENOMEM;
5080
5081         spin_lock_init(&devpriv->window_lock);
5082         spin_lock_init(&devpriv->soft_reg_copy_lock);
5083         spin_lock_init(&devpriv->mite_channel_lock);
5084
5085         return 0;
5086 }
5087
5088 static int ni_E_init(struct comedi_device *dev,
5089                      unsigned interrupt_pin, unsigned irq_polarity)
5090 {
5091         const struct ni_board_struct *board = dev->board_ptr;
5092         struct ni_private *devpriv = dev->private;
5093         struct comedi_subdevice *s;
5094         int ret;
5095         int i;
5096
5097         if (board->n_aochan > MAX_N_AO_CHAN) {
5098                 dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n");
5099                 return -EINVAL;
5100         }
5101
5102         /* initialize clock dividers */
5103         devpriv->clock_and_fout = NISTC_CLK_FOUT_SLOW_DIV2 |
5104                                   NISTC_CLK_FOUT_SLOW_TIMEBASE |
5105                                   NISTC_CLK_FOUT_TO_BOARD_DIV2 |
5106                                   NISTC_CLK_FOUT_TO_BOARD;
5107         if (!devpriv->is_6xxx) {
5108                 /* BEAM is this needed for PCI-6143 ?? */
5109                 devpriv->clock_and_fout |= (NISTC_CLK_FOUT_AI_OUT_DIV2 |
5110                                             NISTC_CLK_FOUT_AO_OUT_DIV2);
5111         }
5112         ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
5113
5114         ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
5115         if (ret)
5116                 return ret;
5117
5118         /* Analog Input subdevice */
5119         s = &dev->subdevices[NI_AI_SUBDEV];
5120         if (board->n_adchan) {
5121                 s->type         = COMEDI_SUBD_AI;
5122                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER;
5123                 if (!devpriv->is_611x)
5124                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
5125                 if (board->ai_maxdata > 0xffff)
5126                         s->subdev_flags |= SDF_LSAMPL;
5127                 if (devpriv->is_m_series)
5128                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
5129                 s->n_chan       = board->n_adchan;
5130                 s->maxdata      = board->ai_maxdata;
5131                 s->range_table  = ni_range_lkup[board->gainlkup];
5132                 s->insn_read    = ni_ai_insn_read;
5133                 s->insn_config  = ni_ai_insn_config;
5134                 if (dev->irq) {
5135                         dev->read_subdev = s;
5136                         s->subdev_flags |= SDF_CMD_READ;
5137                         s->len_chanlist = 512;
5138                         s->do_cmdtest   = ni_ai_cmdtest;
5139                         s->do_cmd       = ni_ai_cmd;
5140                         s->cancel       = ni_ai_reset;
5141                         s->poll         = ni_ai_poll;
5142                         s->munge        = ni_ai_munge;
5143
5144                         if (devpriv->mite)
5145                                 s->async_dma_dir = DMA_FROM_DEVICE;
5146                 }
5147
5148                 /* reset the analog input configuration */
5149                 ni_ai_reset(dev, s);
5150         } else {
5151                 s->type         = COMEDI_SUBD_UNUSED;
5152         }
5153
5154         /* Analog Output subdevice */
5155         s = &dev->subdevices[NI_AO_SUBDEV];
5156         if (board->n_aochan) {
5157                 s->type         = COMEDI_SUBD_AO;
5158                 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
5159                 if (devpriv->is_m_series)
5160                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
5161                 s->n_chan       = board->n_aochan;
5162                 s->maxdata      = board->ao_maxdata;
5163                 s->range_table  = board->ao_range_table;
5164                 s->insn_config  = ni_ao_insn_config;
5165                 s->insn_write   = ni_ao_insn_write;
5166
5167                 ret = comedi_alloc_subdev_readback(s);
5168                 if (ret)
5169                         return ret;
5170
5171                 /*
5172                  * Along with the IRQ we need either a FIFO or DMA for
5173                  * async command support.
5174                  */
5175                 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) {
5176                         dev->write_subdev = s;
5177                         s->subdev_flags |= SDF_CMD_WRITE;
5178                         s->len_chanlist = s->n_chan;
5179                         s->do_cmdtest   = ni_ao_cmdtest;
5180                         s->do_cmd       = ni_ao_cmd;
5181                         s->cancel       = ni_ao_reset;
5182                         if (!devpriv->is_m_series)
5183                                 s->munge        = ni_ao_munge;
5184
5185                         if (devpriv->mite)
5186                                 s->async_dma_dir = DMA_TO_DEVICE;
5187                 }
5188
5189                 if (devpriv->is_67xx)
5190                         init_ao_67xx(dev, s);
5191
5192                 /* reset the analog output configuration */
5193                 ni_ao_reset(dev, s);
5194         } else {
5195                 s->type         = COMEDI_SUBD_UNUSED;
5196         }
5197
5198         /* Digital I/O subdevice */
5199         s = &dev->subdevices[NI_DIO_SUBDEV];
5200         s->type         = COMEDI_SUBD_DIO;
5201         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
5202         s->n_chan       = board->has_32dio_chan ? 32 : 8;
5203         s->maxdata      = 1;
5204         s->range_table  = &range_digital;
5205         if (devpriv->is_m_series) {
5206                 s->subdev_flags |= SDF_LSAMPL;
5207                 s->insn_bits    = ni_m_series_dio_insn_bits;
5208                 s->insn_config  = ni_m_series_dio_insn_config;
5209                 if (dev->irq) {
5210                         s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */;
5211                         s->len_chanlist = s->n_chan;
5212                         s->do_cmdtest   = ni_cdio_cmdtest;
5213                         s->do_cmd       = ni_cdio_cmd;
5214                         s->cancel       = ni_cdio_cancel;
5215
5216                         /* M-series boards use DMA */
5217                         s->async_dma_dir = DMA_BIDIRECTIONAL;
5218                 }
5219
5220                 /* reset DIO and set all channels to inputs */
5221                 ni_writel(dev, NI_M_CDO_CMD_RESET |
5222                                NI_M_CDI_CMD_RESET,
5223                           NI_M_CDIO_CMD_REG);
5224                 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
5225         } else {
5226                 s->insn_bits    = ni_dio_insn_bits;
5227                 s->insn_config  = ni_dio_insn_config;
5228
5229                 /* set all channels to inputs */
5230                 devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits);
5231                 ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
5232         }
5233
5234         /* 8255 device */
5235         s = &dev->subdevices[NI_8255_DIO_SUBDEV];
5236         if (board->has_8255) {
5237                 ret = subdev_8255_init(dev, s, ni_8255_callback,
5238                                        NI_E_8255_BASE);
5239                 if (ret)
5240                         return ret;
5241         } else {
5242                 s->type = COMEDI_SUBD_UNUSED;
5243         }
5244
5245         /* formerly general purpose counter/timer device, but no longer used */
5246         s = &dev->subdevices[NI_UNUSED_SUBDEV];
5247         s->type = COMEDI_SUBD_UNUSED;
5248
5249         /* Calibration subdevice */
5250         s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
5251         s->type         = COMEDI_SUBD_CALIB;
5252         s->subdev_flags = SDF_INTERNAL;
5253         s->n_chan       = 1;
5254         s->maxdata      = 0;
5255         if (devpriv->is_m_series) {
5256                 /* internal PWM output used for AI nonlinearity calibration */
5257                 s->insn_config  = ni_m_series_pwm_config;
5258
5259                 ni_writel(dev, 0x0, NI_M_CAL_PWM_REG);
5260         } else if (devpriv->is_6143) {
5261                 /* internal PWM output used for AI nonlinearity calibration */
5262                 s->insn_config  = ni_6143_pwm_config;
5263         } else {
5264                 s->subdev_flags |= SDF_WRITABLE;
5265                 s->insn_read    = ni_calib_insn_read;
5266                 s->insn_write   = ni_calib_insn_write;
5267
5268                 /* setup the caldacs and find the real n_chan and maxdata */
5269                 caldac_setup(dev, s);
5270         }
5271
5272         /* EEPROM subdevice */
5273         s = &dev->subdevices[NI_EEPROM_SUBDEV];
5274         s->type         = COMEDI_SUBD_MEMORY;
5275         s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
5276         s->maxdata      = 0xff;
5277         if (devpriv->is_m_series) {
5278                 s->n_chan       = M_SERIES_EEPROM_SIZE;
5279                 s->insn_read    = ni_m_series_eeprom_insn_read;
5280         } else {
5281                 s->n_chan       = 512;
5282                 s->insn_read    = ni_eeprom_insn_read;
5283         }
5284
5285         /* Digital I/O (PFI) subdevice */
5286         s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
5287         s->type         = COMEDI_SUBD_DIO;
5288         s->maxdata      = 1;
5289         if (devpriv->is_m_series) {
5290                 s->n_chan       = 16;
5291                 s->insn_bits    = ni_pfi_insn_bits;
5292                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5293
5294                 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
5295                 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
5296                         ni_writew(dev, devpriv->pfi_output_select_reg[i],
5297                                   NI_M_PFI_OUT_SEL_REG(i));
5298                 }
5299         } else {
5300                 s->n_chan       = 10;
5301                 s->subdev_flags = SDF_INTERNAL;
5302         }
5303         s->insn_config  = ni_pfi_insn_config;
5304
5305         ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, ~0, 0);
5306
5307         /* cs5529 calibration adc */
5308         s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
5309         if (devpriv->is_67xx) {
5310                 s->type = COMEDI_SUBD_AI;
5311                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
5312                 /*  one channel for each analog output channel */
5313                 s->n_chan = board->n_aochan;
5314                 s->maxdata = (1 << 16) - 1;
5315                 s->range_table = &range_unknown;        /* XXX */
5316                 s->insn_read = cs5529_ai_insn_read;
5317                 s->insn_config = NULL;
5318                 init_cs5529(dev);
5319         } else {
5320                 s->type = COMEDI_SUBD_UNUSED;
5321         }
5322
5323         /* Serial */
5324         s = &dev->subdevices[NI_SERIAL_SUBDEV];
5325         s->type = COMEDI_SUBD_SERIAL;
5326         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5327         s->n_chan = 1;
5328         s->maxdata = 0xff;
5329         s->insn_config = ni_serial_insn_config;
5330         devpriv->serial_interval_ns = 0;
5331         devpriv->serial_hw_mode = 0;
5332
5333         /* RTSI */
5334         s = &dev->subdevices[NI_RTSI_SUBDEV];
5335         s->type = COMEDI_SUBD_DIO;
5336         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5337         s->n_chan = 8;
5338         s->maxdata = 1;
5339         s->insn_bits = ni_rtsi_insn_bits;
5340         s->insn_config = ni_rtsi_insn_config;
5341         ni_rtsi_init(dev);
5342
5343         /* allocate and initialize the gpct counter device */
5344         devpriv->counter_dev = ni_gpct_device_construct(dev,
5345                                         ni_gpct_write_register,
5346                                         ni_gpct_read_register,
5347                                         (devpriv->is_m_series)
5348                                                 ? ni_gpct_variant_m_series
5349                                                 : ni_gpct_variant_e_series,
5350                                         NUM_GPCT);
5351         if (!devpriv->counter_dev)
5352                 return -ENOMEM;
5353
5354         /* Counter (gpct) subdevices */
5355         for (i = 0; i < NUM_GPCT; ++i) {
5356                 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i];
5357
5358                 /* setup and initialize the counter */
5359                 gpct->chip_index = 0;
5360                 gpct->counter_index = i;
5361                 ni_tio_init_counter(gpct);
5362
5363                 s = &dev->subdevices[NI_GPCT_SUBDEV(i)];
5364                 s->type         = COMEDI_SUBD_COUNTER;
5365                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
5366                 s->n_chan       = 3;
5367                 s->maxdata      = (devpriv->is_m_series) ? 0xffffffff
5368                                                          : 0x00ffffff;
5369                 s->insn_read    = ni_tio_insn_read;
5370                 s->insn_write   = ni_tio_insn_write;
5371                 s->insn_config  = ni_tio_insn_config;
5372 #ifdef PCIDMA
5373                 if (dev->irq && devpriv->mite) {
5374                         s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
5375                         s->len_chanlist = 1;
5376                         s->do_cmdtest   = ni_tio_cmdtest;
5377                         s->do_cmd       = ni_gpct_cmd;
5378                         s->cancel       = ni_gpct_cancel;
5379
5380                         s->async_dma_dir = DMA_BIDIRECTIONAL;
5381                 }
5382 #endif
5383                 s->private      = gpct;
5384         }
5385
5386         /* Frequency output subdevice */
5387         s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
5388         s->type         = COMEDI_SUBD_COUNTER;
5389         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
5390         s->n_chan       = 1;
5391         s->maxdata      = 0xf;
5392         s->insn_read    = ni_freq_out_insn_read;
5393         s->insn_write   = ni_freq_out_insn_write;
5394         s->insn_config  = ni_freq_out_insn_config;
5395
5396         if (dev->irq) {
5397                 ni_stc_writew(dev,
5398                               (irq_polarity ? NISTC_INT_CTRL_INT_POL : 0) |
5399                               (NISTC_INT_CTRL_3PIN_INT & 0) |
5400                               NISTC_INT_CTRL_INTA_ENA |
5401                               NISTC_INT_CTRL_INTB_ENA |
5402                               NISTC_INT_CTRL_INTA_SEL(interrupt_pin) |
5403                               NISTC_INT_CTRL_INTB_SEL(interrupt_pin),
5404                               NISTC_INT_CTRL_REG);
5405         }
5406
5407         /* DMA setup */
5408         ni_writeb(dev, devpriv->ai_ao_select_reg, NI_E_DMA_AI_AO_SEL_REG);
5409         ni_writeb(dev, devpriv->g0_g1_select_reg, NI_E_DMA_G0_G1_SEL_REG);
5410
5411         if (devpriv->is_6xxx) {
5412                 ni_writeb(dev, 0, NI611X_MAGIC_REG);
5413         } else if (devpriv->is_m_series) {
5414                 int channel;
5415
5416                 for (channel = 0; channel < board->n_aochan; ++channel) {
5417                         ni_writeb(dev, 0xf,
5418                                   NI_M_AO_WAVEFORM_ORDER_REG(channel));
5419                         ni_writeb(dev, 0x0,
5420                                   NI_M_AO_REF_ATTENUATION_REG(channel));
5421                 }
5422                 ni_writeb(dev, 0x0, NI_M_AO_CALIB_REG);
5423         }
5424
5425         return 0;
5426 }
5427
5428 static void mio_common_detach(struct comedi_device *dev)
5429 {
5430         struct ni_private *devpriv = dev->private;
5431
5432         if (devpriv) {
5433                 if (devpriv->counter_dev)
5434                         ni_gpct_device_destroy(devpriv->counter_dev);
5435         }
5436 }