drivers/staging/comedi/drivers/ni_mio_common.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Hardware driver for DAQ-STC based boards
   4  *
   5  * COMEDI - Linux Control and Measurement Device Interface
   6  * Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7  * Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   8  */
   9
  10 /*
  11  * This file is meant to be included by another file, e.g.,
  12  * ni_atmio.c or ni_pcimio.c.
  13  *
  14  * Interrupt support originally added by Truxton Fulton <trux@truxton.com>
  15  *
  16  * References (ftp://ftp.natinst.com/support/manuals):
  17  *   340747b.pdf  AT-MIO E series Register Level Programmer Manual
  18  *   341079b.pdf  PCI E Series RLPM
  19  *   340934b.pdf  DAQ-STC reference manual
  20  *
  21  * 67xx and 611x registers (ftp://ftp.ni.com/support/daq/mhddk/documentation/)
  22  *   release_ni611x.pdf
  23  *   release_ni67xx.pdf
  24  *
  25  * Other possibly relevant info:
  26  *   320517c.pdf  User manual (obsolete)
  27  *   320517f.pdf  User manual (new)
  28  *   320889a.pdf  delete
  29  *   320906c.pdf  maximum signal ratings
  30  *   321066a.pdf  about 16x
  31  *   321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  32  *   321808a.pdf  about at-mio-16e-10 rev P
  33  *   321837a.pdf  discontinuation of at-mio-16de-10 rev d
  34  *   321838a.pdf  about at-mio-16de-10 rev N
  35  *
  36  * ISSUES:
  37  *   - the interrupt routine needs to be cleaned up
  38  *
  39  * 2006-02-07: S-Series PCI-6143: Support has been added but is not
  40  * fully tested as yet. Terry Barnaby, BEAM Ltd.
  41  */
  42
  43 #include <linux/interrupt.h>
  44 #include <linux/sched.h>
  45 #include <linux/delay.h>
  46 #include "8255.h"
  47 #include "mite.h"
  48
  49 /* A timeout count */
  50 #define NI_TIMEOUT 1000
  51
  52 /* Note: this table must match the ai_gain_* definitions */
  53 static const short ni_gainlkup[][16] = {
  54         [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
  55                         0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  56         [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
  57         [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
  58                         0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  59         [ai_gain_4] = {0, 1, 4, 7},
  60         [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
  61                           0x003, 0x004, 0x005, 0x006},
  62         [ai_gain_622x] = {0, 1, 4, 5},
  63         [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
  64         [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  65 };
  66
  67 static const struct comedi_lrange range_ni_E_ai = {
  68         16, {
  69                 BIP_RANGE(10),
  70                 BIP_RANGE(5),
  71                 BIP_RANGE(2.5),
  72                 BIP_RANGE(1),
  73                 BIP_RANGE(0.5),
  74                 BIP_RANGE(0.25),
  75                 BIP_RANGE(0.1),
  76                 BIP_RANGE(0.05),
  77                 UNI_RANGE(20),
  78                 UNI_RANGE(10),
  79                 UNI_RANGE(5),
  80                 UNI_RANGE(2),
  81                 UNI_RANGE(1),
  82                 UNI_RANGE(0.5),
  83                 UNI_RANGE(0.2),
  84                 UNI_RANGE(0.1)
  85         }
  86 };
  87
  88 static const struct comedi_lrange range_ni_E_ai_limited = {
  89         8, {
  90                 BIP_RANGE(10),
  91                 BIP_RANGE(5),
  92                 BIP_RANGE(1),
  93                 BIP_RANGE(0.1),
  94                 UNI_RANGE(10),
  95                 UNI_RANGE(5),
  96                 UNI_RANGE(1),
  97                 UNI_RANGE(0.1)
  98         }
  99 };
 100
 101 static const struct comedi_lrange range_ni_E_ai_limited14 = {
 102         14, {
 103                 BIP_RANGE(10),
 104                 BIP_RANGE(5),
 105                 BIP_RANGE(2),
 106                 BIP_RANGE(1),
 107                 BIP_RANGE(0.5),
 108                 BIP_RANGE(0.2),
 109                 BIP_RANGE(0.1),
 110                 UNI_RANGE(10),
 111                 UNI_RANGE(5),
 112                 UNI_RANGE(2),
 113                 UNI_RANGE(1),
 114                 UNI_RANGE(0.5),
 115                 UNI_RANGE(0.2),
 116                 UNI_RANGE(0.1)
 117         }
 118 };
 119
 120 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
 121         4, {
 122                 BIP_RANGE(10),
 123                 BIP_RANGE(5),
 124                 BIP_RANGE(0.5),
 125                 BIP_RANGE(0.05)
 126         }
 127 };
 128
 129 static const struct comedi_lrange range_ni_E_ai_611x = {
 130         8, {
 131                 BIP_RANGE(50),
 132                 BIP_RANGE(20),
 133                 BIP_RANGE(10),
 134                 BIP_RANGE(5),
 135                 BIP_RANGE(2),
 136                 BIP_RANGE(1),
 137                 BIP_RANGE(0.5),
 138                 BIP_RANGE(0.2)
 139         }
 140 };
 141
 142 static const struct comedi_lrange range_ni_M_ai_622x = {
 143         4, {
 144                 BIP_RANGE(10),
 145                 BIP_RANGE(5),
 146                 BIP_RANGE(1),
 147                 BIP_RANGE(0.2)
 148         }
 149 };
 150
 151 static const struct comedi_lrange range_ni_M_ai_628x = {
 152         7, {
 153                 BIP_RANGE(10),
 154                 BIP_RANGE(5),
 155                 BIP_RANGE(2),
 156                 BIP_RANGE(1),
 157                 BIP_RANGE(0.5),
 158                 BIP_RANGE(0.2),
 159                 BIP_RANGE(0.1)
 160         }
 161 };
 162
 163 static const struct comedi_lrange range_ni_E_ao_ext = {
 164         4, {
 165                 BIP_RANGE(10),
 166                 UNI_RANGE(10),
 167                 RANGE_ext(-1, 1),
 168                 RANGE_ext(0, 1)
 169         }
 170 };
 171
 172 static const struct comedi_lrange *const ni_range_lkup[] = {
 173         [ai_gain_16] = &range_ni_E_ai,
 174         [ai_gain_8] = &range_ni_E_ai_limited,
 175         [ai_gain_14] = &range_ni_E_ai_limited14,
 176         [ai_gain_4] = &range_ni_E_ai_bipolar4,
 177         [ai_gain_611x] = &range_ni_E_ai_611x,
 178         [ai_gain_622x] = &range_ni_M_ai_622x,
 179         [ai_gain_628x] = &range_ni_M_ai_628x,
 180         [ai_gain_6143] = &range_bipolar5
 181 };
 182
 183 enum aimodes {
 184         AIMODE_NONE = 0,
 185         AIMODE_HALF_FULL = 1,
 186         AIMODE_SCAN = 2,
 187         AIMODE_SAMPLE = 3,
 188 };
 189
 190 enum ni_common_subdevices {
 191         NI_AI_SUBDEV,
 192         NI_AO_SUBDEV,
 193         NI_DIO_SUBDEV,
 194         NI_8255_DIO_SUBDEV,
 195         NI_UNUSED_SUBDEV,
 196         NI_CALIBRATION_SUBDEV,
 197         NI_EEPROM_SUBDEV,
 198         NI_PFI_DIO_SUBDEV,
 199         NI_CS5529_CALIBRATION_SUBDEV,
 200         NI_SERIAL_SUBDEV,
 201         NI_RTSI_SUBDEV,
 202         NI_GPCT0_SUBDEV,
 203         NI_GPCT1_SUBDEV,
 204         NI_FREQ_OUT_SUBDEV,
 205         NI_NUM_SUBDEVICES
 206 };
 207
 208 #define NI_GPCT_SUBDEV(x)       (NI_GPCT0_SUBDEV + (x))
 209
 210 enum timebase_nanoseconds {
 211         TIMEBASE_1_NS = 50,
 212         TIMEBASE_2_NS = 10000
 213 };
 214
 215 #define SERIAL_DISABLED         0
 216 #define SERIAL_600NS            600
 217 #define SERIAL_1_2US            1200
 218 #define SERIAL_10US                     10000
 219
 220 static const int num_adc_stages_611x = 3;
 221
 222 static void ni_writel(struct comedi_device *dev, unsigned int data, int reg)
 223 {
 224         if (dev->mmio)
 225                 writel(data, dev->mmio + reg);
 226         else
 227                 outl(data, dev->iobase + reg);
 228 }
 229
 230 static void ni_writew(struct comedi_device *dev, unsigned int data, int reg)
 231 {
 232         if (dev->mmio)
 233                 writew(data, dev->mmio + reg);
 234         else
 235                 outw(data, dev->iobase + reg);
 236 }
 237
 238 static void ni_writeb(struct comedi_device *dev, unsigned int data, int reg)
 239 {
 240         if (dev->mmio)
 241                 writeb(data, dev->mmio + reg);
 242         else
 243                 outb(data, dev->iobase + reg);
 244 }
 245
 246 static unsigned int ni_readl(struct comedi_device *dev, int reg)
 247 {
 248         if (dev->mmio)
 249                 return readl(dev->mmio + reg);
 250
 251         return inl(dev->iobase + reg);
 252 }
 253
 254 static unsigned int ni_readw(struct comedi_device *dev, int reg)
 255 {
 256         if (dev->mmio)
 257                 return readw(dev->mmio + reg);
 258
 259         return inw(dev->iobase + reg);
 260 }
 261
 262 static unsigned int ni_readb(struct comedi_device *dev, int reg)
 263 {
 264         if (dev->mmio)
 265                 return readb(dev->mmio + reg);
 266
 267         return inb(dev->iobase + reg);
 268 }
 269
 270 /*
 271  * We automatically take advantage of STC registers that can be
 272  * read/written directly in the I/O space of the board.
 273  *
 274  * The AT-MIO and DAQCard devices map the low 8 STC registers to
 275  * iobase+reg*2.
 276  *
 277  * Most PCIMIO devices also map the low 8 STC registers but the
 278  * 611x devices map the read registers to iobase+(addr-1)*2.
 279  * For now non-windowed STC access is disabled if a PCIMIO device
 280  * is detected (devpriv->mite has been initialized).
 281  *
 282  * The M series devices do not used windowed registers for the
 283  * STC registers. The functions below handle the mapping of the
 284  * windowed STC registers to the m series register offsets.
 285  */
 286
 287 struct mio_regmap {
 288         unsigned int mio_reg;
 289         int size;
 290 };
 291
 292 static const struct mio_regmap m_series_stc_write_regmap[] = {
 293         [NISTC_INTA_ACK_REG]            = { 0x104, 2 },
 294         [NISTC_INTB_ACK_REG]            = { 0x106, 2 },
 295         [NISTC_AI_CMD2_REG]             = { 0x108, 2 },
 296         [NISTC_AO_CMD2_REG]             = { 0x10a, 2 },
 297         [NISTC_G0_CMD_REG]              = { 0x10c, 2 },
 298         [NISTC_G1_CMD_REG]              = { 0x10e, 2 },
 299         [NISTC_AI_CMD1_REG]             = { 0x110, 2 },
 300         [NISTC_AO_CMD1_REG]             = { 0x112, 2 },
 301         /*
 302          * NISTC_DIO_OUT_REG maps to:
 303          * { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 }
 304          */
 305         [NISTC_DIO_OUT_REG]             = { 0, 0 }, /* DOES NOT MAP CLEANLY */
 306         [NISTC_DIO_CTRL_REG]            = { 0, 0 }, /* DOES NOT MAP CLEANLY */
 307         [NISTC_AI_MODE1_REG]            = { 0x118, 2 },
 308         [NISTC_AI_MODE2_REG]            = { 0x11a, 2 },
 309         [NISTC_AI_SI_LOADA_REG]         = { 0x11c, 4 },
 310         [NISTC_AI_SI_LOADB_REG]         = { 0x120, 4 },
 311         [NISTC_AI_SC_LOADA_REG]         = { 0x124, 4 },
 312         [NISTC_AI_SC_LOADB_REG]         = { 0x128, 4 },
 313         [NISTC_AI_SI2_LOADA_REG]        = { 0x12c, 4 },
 314         [NISTC_AI_SI2_LOADB_REG]        = { 0x130, 4 },
 315         [NISTC_G0_MODE_REG]             = { 0x134, 2 },
 316         [NISTC_G1_MODE_REG]             = { 0x136, 2 },
 317         [NISTC_G0_LOADA_REG]            = { 0x138, 4 },
 318         [NISTC_G0_LOADB_REG]            = { 0x13c, 4 },
 319         [NISTC_G1_LOADA_REG]            = { 0x140, 4 },
 320         [NISTC_G1_LOADB_REG]            = { 0x144, 4 },
 321         [NISTC_G0_INPUT_SEL_REG]        = { 0x148, 2 },
 322         [NISTC_G1_INPUT_SEL_REG]        = { 0x14a, 2 },
 323         [NISTC_AO_MODE1_REG]            = { 0x14c, 2 },
 324         [NISTC_AO_MODE2_REG]            = { 0x14e, 2 },
 325         [NISTC_AO_UI_LOADA_REG]         = { 0x150, 4 },
 326         [NISTC_AO_UI_LOADB_REG]         = { 0x154, 4 },
 327         [NISTC_AO_BC_LOADA_REG]         = { 0x158, 4 },
 328         [NISTC_AO_BC_LOADB_REG]         = { 0x15c, 4 },
 329         [NISTC_AO_UC_LOADA_REG]         = { 0x160, 4 },
 330         [NISTC_AO_UC_LOADB_REG]         = { 0x164, 4 },
 331         [NISTC_CLK_FOUT_REG]            = { 0x170, 2 },
 332         [NISTC_IO_BIDIR_PIN_REG]        = { 0x172, 2 },
 333         [NISTC_RTSI_TRIG_DIR_REG]       = { 0x174, 2 },
 334         [NISTC_INT_CTRL_REG]            = { 0x176, 2 },
 335         [NISTC_AI_OUT_CTRL_REG]         = { 0x178, 2 },
 336         [NISTC_ATRIG_ETC_REG]           = { 0x17a, 2 },
 337         [NISTC_AI_START_STOP_REG]       = { 0x17c, 2 },
 338         [NISTC_AI_TRIG_SEL_REG]         = { 0x17e, 2 },
 339         [NISTC_AI_DIV_LOADA_REG]        = { 0x180, 4 },
 340         [NISTC_AO_START_SEL_REG]        = { 0x184, 2 },
 341         [NISTC_AO_TRIG_SEL_REG]         = { 0x186, 2 },
 342         [NISTC_G0_AUTOINC_REG]          = { 0x188, 2 },
 343         [NISTC_G1_AUTOINC_REG]          = { 0x18a, 2 },
 344         [NISTC_AO_MODE3_REG]            = { 0x18c, 2 },
 345         [NISTC_RESET_REG]               = { 0x190, 2 },
 346         [NISTC_INTA_ENA_REG]            = { 0x192, 2 },
 347         [NISTC_INTA2_ENA_REG]           = { 0, 0 }, /* E-Series only */
 348         [NISTC_INTB_ENA_REG]            = { 0x196, 2 },
 349         [NISTC_INTB2_ENA_REG]           = { 0, 0 }, /* E-Series only */
 350         [NISTC_AI_PERSONAL_REG]         = { 0x19a, 2 },
 351         [NISTC_AO_PERSONAL_REG]         = { 0x19c, 2 },
 352         [NISTC_RTSI_TRIGA_OUT_REG]      = { 0x19e, 2 },
 353         [NISTC_RTSI_TRIGB_OUT_REG]      = { 0x1a0, 2 },
 354         /* doc for following line: mhddk/nimseries/ChipObjects/tMSeries.h */
 355         [NISTC_RTSI_BOARD_REG]          = { 0x1a2, 2 },
 356         [NISTC_CFG_MEM_CLR_REG]         = { 0x1a4, 2 },
 357         [NISTC_ADC_FIFO_CLR_REG]        = { 0x1a6, 2 },
 358         [NISTC_DAC_FIFO_CLR_REG]        = { 0x1a8, 2 },
 359         [NISTC_AO_OUT_CTRL_REG]         = { 0x1ac, 2 },
 360         [NISTC_AI_MODE3_REG]            = { 0x1ae, 2 },
 361 };
 362
 363 static void m_series_stc_write(struct comedi_device *dev,
 364                                unsigned int data, unsigned int reg)
 365 {
 366         const struct mio_regmap *regmap;
 367
 368         if (reg < ARRAY_SIZE(m_series_stc_write_regmap)) {
 369                 regmap = &m_series_stc_write_regmap[reg];
 370         } else {
 371                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
 372                          __func__, reg);
 373                 return;
 374         }
 375
 376         switch (regmap->size) {
 377         case 4:
 378                 ni_writel(dev, data, regmap->mio_reg);
 379                 break;
 380         case 2:
 381                 ni_writew(dev, data, regmap->mio_reg);
 382                 break;
 383         default:
 384                 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
 385                          __func__, reg);
 386                 break;
 387         }
 388 }
 389
 390 static const struct mio_regmap m_series_stc_read_regmap[] = {
 391         [NISTC_AI_STATUS1_REG]          = { 0x104, 2 },
 392         [NISTC_AO_STATUS1_REG]          = { 0x106, 2 },
 393         [NISTC_G01_STATUS_REG]          = { 0x108, 2 },
 394         [NISTC_AI_STATUS2_REG]          = { 0, 0 }, /* Unknown */
 395         [NISTC_AO_STATUS2_REG]          = { 0x10c, 2 },
 396         [NISTC_DIO_IN_REG]              = { 0, 0 }, /* Unknown */
 397         [NISTC_G0_HW_SAVE_REG]          = { 0x110, 4 },
 398         [NISTC_G1_HW_SAVE_REG]          = { 0x114, 4 },
 399         [NISTC_G0_SAVE_REG]             = { 0x118, 4 },
 400         [NISTC_G1_SAVE_REG]             = { 0x11c, 4 },
 401         [NISTC_AO_UI_SAVE_REG]          = { 0x120, 4 },
 402         [NISTC_AO_BC_SAVE_REG]          = { 0x124, 4 },
 403         [NISTC_AO_UC_SAVE_REG]          = { 0x128, 4 },
 404         [NISTC_STATUS1_REG]             = { 0x136, 2 },
 405         [NISTC_DIO_SERIAL_IN_REG]       = { 0x009, 1 },
 406         [NISTC_STATUS2_REG]             = { 0x13a, 2 },
 407         [NISTC_AI_SI_SAVE_REG]          = { 0x180, 4 },
 408         [NISTC_AI_SC_SAVE_REG]          = { 0x184, 4 },
 409 };
 410
 411 static unsigned int m_series_stc_read(struct comedi_device *dev,
 412                                       unsigned int reg)
 413 {
 414         const struct mio_regmap *regmap;
 415
 416         if (reg < ARRAY_SIZE(m_series_stc_read_regmap)) {
 417                 regmap = &m_series_stc_read_regmap[reg];
 418         } else {
 419                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
 420                          __func__, reg);
 421                 return 0;
 422         }
 423
 424         switch (regmap->size) {
 425         case 4:
 426                 return ni_readl(dev, regmap->mio_reg);
 427         case 2:
 428                 return ni_readw(dev, regmap->mio_reg);
 429         case 1:
 430                 return ni_readb(dev, regmap->mio_reg);
 431         default:
 432                 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
 433                          __func__, reg);
 434                 return 0;
 435         }
 436 }
 437
 438 static void ni_stc_writew(struct comedi_device *dev,
 439                           unsigned int data, int reg)
 440 {
 441         struct ni_private *devpriv = dev->private;
 442         unsigned long flags;
 443
 444         if (devpriv->is_m_series) {
 445                 m_series_stc_write(dev, data, reg);
 446         } else {
 447                 spin_lock_irqsave(&devpriv->window_lock, flags);
 448                 if (!devpriv->mite && reg < 8) {
 449                         ni_writew(dev, data, reg * 2);
 450                 } else {
 451                         ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
 452                         ni_writew(dev, data, NI_E_STC_WINDOW_DATA_REG);
 453                 }
 454                 spin_unlock_irqrestore(&devpriv->window_lock, flags);
 455         }
 456 }
 457
 458 static void ni_stc_writel(struct comedi_device *dev,
 459                           unsigned int data, int reg)
 460 {
 461         struct ni_private *devpriv = dev->private;
 462
 463         if (devpriv->is_m_series) {
 464                 m_series_stc_write(dev, data, reg);
 465         } else {
 466                 ni_stc_writew(dev, data >> 16, reg);
 467                 ni_stc_writew(dev, data & 0xffff, reg + 1);
 468         }
 469 }
 470
 471 static unsigned int ni_stc_readw(struct comedi_device *dev, int reg)
 472 {
 473         struct ni_private *devpriv = dev->private;
 474         unsigned long flags;
 475         unsigned int val;
 476
 477         if (devpriv->is_m_series) {
 478                 val = m_series_stc_read(dev, reg);
 479         } else {
 480                 spin_lock_irqsave(&devpriv->window_lock, flags);
 481                 if (!devpriv->mite && reg < 8) {
 482                         val = ni_readw(dev, reg * 2);
 483                 } else {
 484                         ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
 485                         val = ni_readw(dev, NI_E_STC_WINDOW_DATA_REG);
 486                 }
 487                 spin_unlock_irqrestore(&devpriv->window_lock, flags);
 488         }
 489         return val;
 490 }
 491
 492 static unsigned int ni_stc_readl(struct comedi_device *dev, int reg)
 493 {
 494         struct ni_private *devpriv = dev->private;
 495         unsigned int val;
 496
 497         if (devpriv->is_m_series) {
 498                 val = m_series_stc_read(dev, reg);
 499         } else {
 500                 val = ni_stc_readw(dev, reg) << 16;
 501                 val |= ni_stc_readw(dev, reg + 1);
 502         }
 503         return val;
 504 }
 505
 506 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
 507                                    unsigned int bit_mask,
 508                                    unsigned int bit_values)
 509 {
 510         struct ni_private *devpriv = dev->private;
 511         unsigned long flags;
 512
 513         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 514         switch (reg) {
 515         case NISTC_INTA_ENA_REG:
 516                 devpriv->int_a_enable_reg &= ~bit_mask;
 517                 devpriv->int_a_enable_reg |= bit_values & bit_mask;
 518                 ni_stc_writew(dev, devpriv->int_a_enable_reg, reg);
 519                 break;
 520         case NISTC_INTB_ENA_REG:
 521                 devpriv->int_b_enable_reg &= ~bit_mask;
 522                 devpriv->int_b_enable_reg |= bit_values & bit_mask;
 523                 ni_stc_writew(dev, devpriv->int_b_enable_reg, reg);
 524                 break;
 525         case NISTC_IO_BIDIR_PIN_REG:
 526                 devpriv->io_bidirection_pin_reg &= ~bit_mask;
 527                 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
 528                 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg);
 529                 break;
 530         case NI_E_DMA_AI_AO_SEL_REG:
 531                 devpriv->ai_ao_select_reg &= ~bit_mask;
 532                 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
 533                 ni_writeb(dev, devpriv->ai_ao_select_reg, reg);
 534                 break;
 535         case NI_E_DMA_G0_G1_SEL_REG:
 536                 devpriv->g0_g1_select_reg &= ~bit_mask;
 537                 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
 538                 ni_writeb(dev, devpriv->g0_g1_select_reg, reg);
 539                 break;
 540         case NI_M_CDIO_DMA_SEL_REG:
 541                 devpriv->cdio_dma_select_reg &= ~bit_mask;
 542                 devpriv->cdio_dma_select_reg |= bit_values & bit_mask;
 543                 ni_writeb(dev, devpriv->cdio_dma_select_reg, reg);
 544                 break;
 545         default:
 546                 dev_err(dev->class_dev, "called with invalid register %d\n",
 547                         reg);
 548                 break;
 549         }
 550         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 551 }
 552
 553 #ifdef PCIDMA
 554
 555 /* selects the MITE channel to use for DMA */
 556 #define NI_STC_DMA_CHAN_SEL(x)  (((x) < 4) ? BIT(x) :   \
 557                                  ((x) == 4) ? 0x3 :     \
 558                                  ((x) == 5) ? 0x5 : 0x0)
 559
 560 /* DMA channel setup */
 561 static int ni_request_ai_mite_channel(struct comedi_device *dev)
 562 {
 563         struct ni_private *devpriv = dev->private;
 564         struct mite_channel *mite_chan;
 565         unsigned long flags;
 566         unsigned int bits;
 567
 568         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 569         mite_chan = mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
 570         if (!mite_chan) {
 571                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 572                 dev_err(dev->class_dev,
 573                         "failed to reserve mite dma channel for analog input\n");
 574                 return -EBUSY;
 575         }
 576         mite_chan->dir = COMEDI_INPUT;
 577         devpriv->ai_mite_chan = mite_chan;
 578
 579         bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
 580         ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 581                         NI_E_DMA_AI_SEL_MASK, NI_E_DMA_AI_SEL(bits));
 582
 583         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 584         return 0;
 585 }
 586
 587 static int ni_request_ao_mite_channel(struct comedi_device *dev)
 588 {
 589         struct ni_private *devpriv = dev->private;
 590         struct mite_channel *mite_chan;
 591         unsigned long flags;
 592         unsigned int bits;
 593
 594         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 595         mite_chan = mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
 596         if (!mite_chan) {
 597                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 598                 dev_err(dev->class_dev,
 599                         "failed to reserve mite dma channel for analog output\n");
 600                 return -EBUSY;
 601         }
 602         mite_chan->dir = COMEDI_OUTPUT;
 603         devpriv->ao_mite_chan = mite_chan;
 604
 605         bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
 606         ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 607                         NI_E_DMA_AO_SEL_MASK, NI_E_DMA_AO_SEL(bits));
 608
 609         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 610         return 0;
 611 }
 612
 613 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
 614                                         unsigned int gpct_index,
 615                                         enum comedi_io_direction direction)
 616 {
 617         struct ni_private *devpriv = dev->private;
 618         struct ni_gpct *counter = &devpriv->counter_dev->counters[gpct_index];
 619         struct mite_channel *mite_chan;
 620         unsigned long flags;
 621         unsigned int bits;
 622
 623         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 624         mite_chan = mite_request_channel(devpriv->mite,
 625                                          devpriv->gpct_mite_ring[gpct_index]);
 626         if (!mite_chan) {
 627                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 628                 dev_err(dev->class_dev,
 629                         "failed to reserve mite dma channel for counter\n");
 630                 return -EBUSY;
 631         }
 632         mite_chan->dir = direction;
 633         ni_tio_set_mite_channel(counter, mite_chan);
 634
 635         bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
 636         ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
 637                         NI_E_DMA_G0_G1_SEL_MASK(gpct_index),
 638                         NI_E_DMA_G0_G1_SEL(gpct_index, bits));
 639
 640         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 641         return 0;
 642 }
 643
 644 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
 645 {
 646         struct ni_private *devpriv = dev->private;
 647         struct mite_channel *mite_chan;
 648         unsigned long flags;
 649         unsigned int bits;
 650
 651         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 652         mite_chan = mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
 653         if (!mite_chan) {
 654                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 655                 dev_err(dev->class_dev,
 656                         "failed to reserve mite dma channel for correlated digital output\n");
 657                 return -EBUSY;
 658         }
 659         mite_chan->dir = COMEDI_OUTPUT;
 660         devpriv->cdo_mite_chan = mite_chan;
 661
 662         /*
 663          * XXX just guessing NI_STC_DMA_CHAN_SEL()
 664          * returns the right bits, under the assumption the cdio dma
 665          * selection works just like ai/ao/gpct.
 666          * Definitely works for dma channels 0 and 1.
 667          */
 668         bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
 669         ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG,
 670                         NI_M_CDIO_DMA_SEL_CDO_MASK,
 671                         NI_M_CDIO_DMA_SEL_CDO(bits));
 672
 673         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 674         return 0;
 675 }
 676 #endif /*  PCIDMA */
 677
 678 static void ni_release_ai_mite_channel(struct comedi_device *dev)
 679 {
 680 #ifdef PCIDMA
 681         struct ni_private *devpriv = dev->private;
 682         unsigned long flags;
 683
 684         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 685         if (devpriv->ai_mite_chan) {
 686                 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 687                                 NI_E_DMA_AI_SEL_MASK, 0);
 688                 mite_release_channel(devpriv->ai_mite_chan);
 689                 devpriv->ai_mite_chan = NULL;
 690         }
 691         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 692 #endif /*  PCIDMA */
 693 }
 694
 695 static void ni_release_ao_mite_channel(struct comedi_device *dev)
 696 {
 697 #ifdef PCIDMA
 698         struct ni_private *devpriv = dev->private;
 699         unsigned long flags;
 700
 701         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 702         if (devpriv->ao_mite_chan) {
 703                 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 704                                 NI_E_DMA_AO_SEL_MASK, 0);
 705                 mite_release_channel(devpriv->ao_mite_chan);
 706                 devpriv->ao_mite_chan = NULL;
 707         }
 708         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 709 #endif /*  PCIDMA */
 710 }
 711
 712 #ifdef PCIDMA
 713 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
 714                                          unsigned int gpct_index)
 715 {
 716         struct ni_private *devpriv = dev->private;
 717         unsigned long flags;
 718
 719         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 720         if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
 721                 struct mite_channel *mite_chan =
 722                     devpriv->counter_dev->counters[gpct_index].mite_chan;
 723
 724                 ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
 725                                 NI_E_DMA_G0_G1_SEL_MASK(gpct_index), 0);
 726                 ni_tio_set_mite_channel(&devpriv->
 727                                         counter_dev->counters[gpct_index],
 728                                         NULL);
 729                 mite_release_channel(mite_chan);
 730         }
 731         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 732 }
 733
 734 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
 735 {
 736         struct ni_private *devpriv = dev->private;
 737         unsigned long flags;
 738
 739         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 740         if (devpriv->cdo_mite_chan) {
 741                 ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG,
 742                                 NI_M_CDIO_DMA_SEL_CDO_MASK, 0);
 743                 mite_release_channel(devpriv->cdo_mite_chan);
 744                 devpriv->cdo_mite_chan = NULL;
 745         }
 746         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 747 }
 748
 749 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
 750                                           unsigned int gpct_index, short enable)
 751 {
 752         struct ni_private *devpriv = dev->private;
 753         unsigned int val = 0;
 754         int reg;
 755
 756         if (devpriv->is_m_series || gpct_index > 1)
 757                 return;
 758
 759         /*
 760          * e-series boards use the second irq signals to generate
 761          * dma requests for their counters
 762          */
 763         if (gpct_index == 0) {
 764                 reg = NISTC_INTA2_ENA_REG;
 765                 if (enable)
 766                         val = NISTC_INTA_ENA_G0_GATE;
 767         } else {
 768                 reg = NISTC_INTB2_ENA_REG;
 769                 if (enable)
 770                         val = NISTC_INTB_ENA_G1_GATE;
 771         }
 772         ni_stc_writew(dev, val, reg);
 773 }
 774 #endif /*  PCIDMA */
 775
 776 static void ni_clear_ai_fifo(struct comedi_device *dev)
 777 {
 778         struct ni_private *devpriv = dev->private;
 779         static const int timeout = 10000;
 780         int i;
 781
 782         if (devpriv->is_6143) {
 783                 /*  Flush the 6143 data FIFO */
 784                 ni_writel(dev, 0x10, NI6143_AI_FIFO_CTRL_REG);
 785                 ni_writel(dev, 0x00, NI6143_AI_FIFO_CTRL_REG);
 786                 /*  Wait for complete */
 787                 for (i = 0; i < timeout; i++) {
 788                         if (!(ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x10))
 789                                 break;
 790                         udelay(1);
 791                 }
 792                 if (i == timeout)
 793                         dev_err(dev->class_dev, "FIFO flush timeout\n");
 794         } else {
 795                 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
 796                 if (devpriv->is_625x) {
 797                         ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0));
 798                         ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0));
 799 #if 0
 800                         /*
 801                          * The NI example code does 3 convert pulses for 625x
 802                          * boards, But that appears to be wrong in practice.
 803                          */
 804                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 805                                       NISTC_AI_CMD1_REG);
 806                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 807                                       NISTC_AI_CMD1_REG);
 808                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 809                                       NISTC_AI_CMD1_REG);
 810 #endif
 811                 }
 812         }
 813 }
 814
 815 static inline void ni_ao_win_outw(struct comedi_device *dev,
 816                                   unsigned int data, int addr)
 817 {
 818         struct ni_private *devpriv = dev->private;
 819         unsigned long flags;
 820
 821         spin_lock_irqsave(&devpriv->window_lock, flags);
 822         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 823         ni_writew(dev, data, NI611X_AO_WINDOW_DATA_REG);
 824         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 825 }
 826
 827 static inline void ni_ao_win_outl(struct comedi_device *dev,
 828                                   unsigned int data, int addr)
 829 {
 830         struct ni_private *devpriv = dev->private;
 831         unsigned long flags;
 832
 833         spin_lock_irqsave(&devpriv->window_lock, flags);
 834         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 835         ni_writel(dev, data, NI611X_AO_WINDOW_DATA_REG);
 836         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 837 }
 838
 839 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
 840 {
 841         struct ni_private *devpriv = dev->private;
 842         unsigned long flags;
 843         unsigned short data;
 844
 845         spin_lock_irqsave(&devpriv->window_lock, flags);
 846         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 847         data = ni_readw(dev, NI611X_AO_WINDOW_DATA_REG);
 848         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 849         return data;
 850 }
 851
 852 /*
 853  * ni_set_bits( ) allows different parts of the ni_mio_common driver to
 854  * share registers (such as Interrupt_A_Register) without interfering with
 855  * each other.
 856  *
 857  * NOTE: the switch/case statements are optimized out for a constant argument
 858  * so this is actually quite fast---  If you must wrap another function around
 859  * this make it inline to avoid a large speed penalty.
 860  *
 861  * value should only be 1 or 0.
 862  */
 863 static inline void ni_set_bits(struct comedi_device *dev, int reg,
 864                                unsigned int bits, unsigned int value)
 865 {
 866         unsigned int bit_values;
 867
 868         if (value)
 869                 bit_values = bits;
 870         else
 871                 bit_values = 0;
 872         ni_set_bitfield(dev, reg, bits, bit_values);
 873 }
 874
 875 #ifdef PCIDMA
 876 static void ni_sync_ai_dma(struct comedi_device *dev)
 877 {
 878         struct ni_private *devpriv = dev->private;
 879         struct comedi_subdevice *s = dev->read_subdev;
 880         unsigned long flags;
 881
 882         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 883         if (devpriv->ai_mite_chan)
 884                 mite_sync_dma(devpriv->ai_mite_chan, s);
 885         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 886 }
 887
 888 static int ni_ai_drain_dma(struct comedi_device *dev)
 889 {
 890         struct ni_private *devpriv = dev->private;
 891         int i;
 892         static const int timeout = 10000;
 893         unsigned long flags;
 894         int retval = 0;
 895
 896         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 897         if (devpriv->ai_mite_chan) {
 898                 for (i = 0; i < timeout; i++) {
 899                         if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
 900                              NISTC_AI_STATUS1_FIFO_E) &&
 901                             mite_bytes_in_transit(devpriv->ai_mite_chan) == 0)
 902                                 break;
 903                         udelay(5);
 904                 }
 905                 if (i == timeout) {
 906                         dev_err(dev->class_dev, "timed out\n");
 907                         dev_err(dev->class_dev,
 908                                 "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
 909                                 mite_bytes_in_transit(devpriv->ai_mite_chan),
 910                                 ni_stc_readw(dev, NISTC_AI_STATUS1_REG));
 911                         retval = -1;
 912                 }
 913         }
 914         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 915
 916         ni_sync_ai_dma(dev);
 917
 918         return retval;
 919 }
 920
 921 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
 922 {
 923         static const int timeout = 10000;
 924         int i;
 925
 926         for (i = 0; i < timeout; i++) {
 927                 unsigned short b_status;
 928
 929                 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
 930                 if (b_status & NISTC_AO_STATUS1_FIFO_HF)
 931                         break;
 932                 /*
 933                  * If we poll too often, the pci bus activity seems
 934                  * to slow the dma transfer down.
 935                  */
 936                 usleep_range(10, 100);
 937         }
 938         if (i == timeout) {
 939                 dev_err(dev->class_dev, "timed out waiting for dma load\n");
 940                 return -EPIPE;
 941         }
 942         return 0;
 943 }
 944 #endif /* PCIDMA */
 945
 946 #ifndef PCIDMA
 947
 948 static void ni_ao_fifo_load(struct comedi_device *dev,
 949                             struct comedi_subdevice *s, int n)
 950 {
 951         struct ni_private *devpriv = dev->private;
 952         int i;
 953         unsigned short d;
 954         unsigned int packed_data;
 955
 956         for (i = 0; i < n; i++) {
 957                 comedi_buf_read_samples(s, &d, 1);
 958
 959                 if (devpriv->is_6xxx) {
 960                         packed_data = d & 0xffff;
 961                         /* 6711 only has 16 bit wide ao fifo */
 962                         if (!devpriv->is_6711) {
 963                                 comedi_buf_read_samples(s, &d, 1);
 964                                 i++;
 965                                 packed_data |= (d << 16) & 0xffff0000;
 966                         }
 967                         ni_writel(dev, packed_data, NI611X_AO_FIFO_DATA_REG);
 968                 } else {
 969                         ni_writew(dev, d, NI_E_AO_FIFO_DATA_REG);
 970                 }
 971         }
 972 }
 973
 974 /*
 975  *  There's a small problem if the FIFO gets really low and we
 976  *  don't have the data to fill it.  Basically, if after we fill
 977  *  the FIFO with all the data available, the FIFO is _still_
 978  *  less than half full, we never clear the interrupt.  If the
 979  *  IRQ is in edge mode, we never get another interrupt, because
 980  *  this one wasn't cleared.  If in level mode, we get flooded
 981  *  with interrupts that we can't fulfill, because nothing ever
 982  *  gets put into the buffer.
 983  *
 984  *  This kind of situation is recoverable, but it is easier to
 985  *  just pretend we had a FIFO underrun, since there is a good
 986  *  chance it will happen anyway.  This is _not_ the case for
 987  *  RT code, as RT code might purposely be running close to the
 988  *  metal.  Needs to be fixed eventually.
 989  */
 990 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
 991                                  struct comedi_subdevice *s)
 992 {
 993         const struct ni_board_struct *board = dev->board_ptr;
 994         unsigned int nbytes;
 995         unsigned int nsamples;
 996
 997         nbytes = comedi_buf_read_n_available(s);
 998         if (nbytes == 0) {
 999                 s->async->events |= COMEDI_CB_OVERFLOW;
1000                 return 0;
1001         }
1002
1003         nsamples = comedi_bytes_to_samples(s, nbytes);
1004         if (nsamples > board->ao_fifo_depth / 2)
1005                 nsamples = board->ao_fifo_depth / 2;
1006
1007         ni_ao_fifo_load(dev, s, nsamples);
1008
1009         return 1;
1010 }
1011
1012 static int ni_ao_prep_fifo(struct comedi_device *dev,
1013                            struct comedi_subdevice *s)
1014 {
1015         const struct ni_board_struct *board = dev->board_ptr;
1016         struct ni_private *devpriv = dev->private;
1017         unsigned int nbytes;
1018         unsigned int nsamples;
1019
1020         /* reset fifo */
1021         ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
1022         if (devpriv->is_6xxx)
1023                 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
1024
1025         /* load some data */
1026         nbytes = comedi_buf_read_n_available(s);
1027         if (nbytes == 0)
1028                 return 0;
1029
1030         nsamples = comedi_bytes_to_samples(s, nbytes);
1031         if (nsamples > board->ao_fifo_depth)
1032                 nsamples = board->ao_fifo_depth;
1033
1034         ni_ao_fifo_load(dev, s, nsamples);
1035
1036         return nsamples;
1037 }
1038
1039 static void ni_ai_fifo_read(struct comedi_device *dev,
1040                             struct comedi_subdevice *s, int n)
1041 {
1042         struct ni_private *devpriv = dev->private;
1043         struct comedi_async *async = s->async;
1044         unsigned int dl;
1045         unsigned short data;
1046         int i;
1047
1048         if (devpriv->is_611x) {
1049                 for (i = 0; i < n / 2; i++) {
1050                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1051                         /* This may get the hi/lo data in the wrong order */
1052                         data = (dl >> 16) & 0xffff;
1053                         comedi_buf_write_samples(s, &data, 1);
1054                         data = dl & 0xffff;
1055                         comedi_buf_write_samples(s, &data, 1);
1056                 }
1057                 /* Check if there's a single sample stuck in the FIFO */
1058                 if (n % 2) {
1059                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1060                         data = dl & 0xffff;
1061                         comedi_buf_write_samples(s, &data, 1);
1062                 }
1063         } else if (devpriv->is_6143) {
1064                 /*
1065                  * This just reads the FIFO assuming the data is present,
1066                  * no checks on the FIFO status are performed.
1067                  */
1068                 for (i = 0; i < n / 2; i++) {
1069                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1070
1071                         data = (dl >> 16) & 0xffff;
1072                         comedi_buf_write_samples(s, &data, 1);
1073                         data = dl & 0xffff;
1074                         comedi_buf_write_samples(s, &data, 1);
1075                 }
1076                 if (n % 2) {
1077                         /* Assume there is a single sample stuck in the FIFO */
1078                         /* Get stranded sample into FIFO */
1079                         ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1080                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1081                         data = (dl >> 16) & 0xffff;
1082                         comedi_buf_write_samples(s, &data, 1);
1083                 }
1084         } else {
1085                 if (n > ARRAY_SIZE(devpriv->ai_fifo_buffer)) {
1086                         dev_err(dev->class_dev,
1087                                 "bug! ai_fifo_buffer too small\n");
1088                         async->events |= COMEDI_CB_ERROR;
1089                         return;
1090                 }
1091                 for (i = 0; i < n; i++) {
1092                         devpriv->ai_fifo_buffer[i] =
1093                             ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1094                 }
1095                 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n);
1096         }
1097 }
1098
1099 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1100 {
1101         const struct ni_board_struct *board = dev->board_ptr;
1102         struct comedi_subdevice *s = dev->read_subdev;
1103         int n;
1104
1105         n = board->ai_fifo_depth / 2;
1106
1107         ni_ai_fifo_read(dev, s, n);
1108 }
1109 #endif
1110
1111 /* Empties the AI fifo */
1112 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1113 {
1114         struct ni_private *devpriv = dev->private;
1115         struct comedi_subdevice *s = dev->read_subdev;
1116         unsigned int dl;
1117         unsigned short data;
1118         int i;
1119
1120         if (devpriv->is_611x) {
1121                 while ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1122                         NISTC_AI_STATUS1_FIFO_E) == 0) {
1123                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1124
1125                         /* This may get the hi/lo data in the wrong order */
1126                         data = dl >> 16;
1127                         comedi_buf_write_samples(s, &data, 1);
1128                         data = dl & 0xffff;
1129                         comedi_buf_write_samples(s, &data, 1);
1130                 }
1131         } else if (devpriv->is_6143) {
1132                 i = 0;
1133                 while (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x04) {
1134                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1135
1136                         /* This may get the hi/lo data in the wrong order */
1137                         data = dl >> 16;
1138                         comedi_buf_write_samples(s, &data, 1);
1139                         data = dl & 0xffff;
1140                         comedi_buf_write_samples(s, &data, 1);
1141                         i += 2;
1142                 }
1143                 /*  Check if stranded sample is present */
1144                 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1145                         /* Get stranded sample into FIFO */
1146                         ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1147                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1148                         data = (dl >> 16) & 0xffff;
1149                         comedi_buf_write_samples(s, &data, 1);
1150                 }
1151
1152         } else {
1153                 unsigned short fe;      /* fifo empty */
1154
1155                 fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1156                      NISTC_AI_STATUS1_FIFO_E;
1157                 while (fe == 0) {
1158                         for (i = 0;
1159                              i < ARRAY_SIZE(devpriv->ai_fifo_buffer); i++) {
1160                                 fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1161                                      NISTC_AI_STATUS1_FIFO_E;
1162                                 if (fe)
1163                                         break;
1164                                 devpriv->ai_fifo_buffer[i] =
1165                                     ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1166                         }
1167                         comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i);
1168                 }
1169         }
1170 }
1171
1172 static void get_last_sample_611x(struct comedi_device *dev)
1173 {
1174         struct ni_private *devpriv = dev->private;
1175         struct comedi_subdevice *s = dev->read_subdev;
1176         unsigned short data;
1177         unsigned int dl;
1178
1179         if (!devpriv->is_611x)
1180                 return;
1181
1182         /* Check if there's a single sample stuck in the FIFO */
1183         if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1184                 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1185                 data = dl & 0xffff;
1186                 comedi_buf_write_samples(s, &data, 1);
1187         }
1188 }
1189
1190 static void get_last_sample_6143(struct comedi_device *dev)
1191 {
1192         struct ni_private *devpriv = dev->private;
1193         struct comedi_subdevice *s = dev->read_subdev;
1194         unsigned short data;
1195         unsigned int dl;
1196
1197         if (!devpriv->is_6143)
1198                 return;
1199
1200         /* Check if there's a single sample stuck in the FIFO */
1201         if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1202                 /* Get stranded sample into FIFO */
1203                 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1204                 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1205
1206                 /* This may get the hi/lo data in the wrong order */
1207                 data = (dl >> 16) & 0xffff;
1208                 comedi_buf_write_samples(s, &data, 1);
1209         }
1210 }
1211
1212 static void shutdown_ai_command(struct comedi_device *dev)
1213 {
1214         struct comedi_subdevice *s = dev->read_subdev;
1215
1216 #ifdef PCIDMA
1217         ni_ai_drain_dma(dev);
1218 #endif
1219         ni_handle_fifo_dregs(dev);
1220         get_last_sample_611x(dev);
1221         get_last_sample_6143(dev);
1222
1223         s->async->events |= COMEDI_CB_EOA;
1224 }
1225
1226 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
1227 {
1228         struct ni_private *devpriv = dev->private;
1229
1230         if (devpriv->aimode == AIMODE_SCAN) {
1231 #ifdef PCIDMA
1232                 static const int timeout = 10;
1233                 int i;
1234
1235                 for (i = 0; i < timeout; i++) {
1236                         ni_sync_ai_dma(dev);
1237                         if ((s->async->events & COMEDI_CB_EOS))
1238                                 break;
1239                         udelay(1);
1240                 }
1241 #else
1242                 ni_handle_fifo_dregs(dev);
1243                 s->async->events |= COMEDI_CB_EOS;
1244 #endif
1245         }
1246         /* handle special case of single scan */
1247         if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)
1248                 shutdown_ai_command(dev);
1249 }
1250
1251 static void handle_gpct_interrupt(struct comedi_device *dev,
1252                                   unsigned short counter_index)
1253 {
1254 #ifdef PCIDMA
1255         struct ni_private *devpriv = dev->private;
1256         struct comedi_subdevice *s;
1257
1258         s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1259
1260         ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1261                                 s);
1262         comedi_handle_events(dev, s);
1263 #endif
1264 }
1265
1266 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1267 {
1268         unsigned short ack = 0;
1269
1270         if (a_status & NISTC_AI_STATUS1_SC_TC)
1271                 ack |= NISTC_INTA_ACK_AI_SC_TC;
1272         if (a_status & NISTC_AI_STATUS1_START1)
1273                 ack |= NISTC_INTA_ACK_AI_START1;
1274         if (a_status & NISTC_AI_STATUS1_START)
1275                 ack |= NISTC_INTA_ACK_AI_START;
1276         if (a_status & NISTC_AI_STATUS1_STOP)
1277                 ack |= NISTC_INTA_ACK_AI_STOP;
1278         if (a_status & NISTC_AI_STATUS1_OVER)
1279                 ack |= NISTC_INTA_ACK_AI_ERR;
1280         if (ack)
1281                 ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG);
1282 }
1283
1284 static void handle_a_interrupt(struct comedi_device *dev,
1285                                struct comedi_subdevice *s,
1286                                unsigned short status)
1287 {
1288         struct comedi_cmd *cmd = &s->async->cmd;
1289
1290         /* test for all uncommon interrupt events at the same time */
1291         if (status & (NISTC_AI_STATUS1_ERR |
1292                       NISTC_AI_STATUS1_SC_TC | NISTC_AI_STATUS1_START1)) {
1293                 if (status == 0xffff) {
1294                         dev_err(dev->class_dev, "Card removed?\n");
1295                         /*
1296                          * We probably aren't even running a command now,
1297                          * so it's a good idea to be careful.
1298                          */
1299                         if (comedi_is_subdevice_running(s))
1300                                 s->async->events |= COMEDI_CB_ERROR;
1301                         return;
1302                 }
1303                 if (status & NISTC_AI_STATUS1_ERR) {
1304                         dev_err(dev->class_dev, "ai error a_status=%04x\n",
1305                                 status);
1306
1307                         shutdown_ai_command(dev);
1308
1309                         s->async->events |= COMEDI_CB_ERROR;
1310                         if (status & NISTC_AI_STATUS1_OVER)
1311                                 s->async->events |= COMEDI_CB_OVERFLOW;
1312                         return;
1313                 }
1314                 if (status & NISTC_AI_STATUS1_SC_TC) {
1315                         if (cmd->stop_src == TRIG_COUNT)
1316                                 shutdown_ai_command(dev);
1317                 }
1318         }
1319 #ifndef PCIDMA
1320         if (status & NISTC_AI_STATUS1_FIFO_HF) {
1321                 int i;
1322                 static const int timeout = 10;
1323                 /*
1324                  * PCMCIA cards (at least 6036) seem to stop producing
1325                  * interrupts if we fail to get the fifo less than half
1326                  * full, so loop to be sure.
1327                  */
1328                 for (i = 0; i < timeout; ++i) {
1329                         ni_handle_fifo_half_full(dev);
1330                         if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1331                              NISTC_AI_STATUS1_FIFO_HF) == 0)
1332                                 break;
1333                 }
1334         }
1335 #endif /*  !PCIDMA */
1336
1337         if (status & NISTC_AI_STATUS1_STOP)
1338                 ni_handle_eos(dev, s);
1339 }
1340
1341 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1342 {
1343         unsigned short ack = 0;
1344
1345         if (b_status & NISTC_AO_STATUS1_BC_TC)
1346                 ack |= NISTC_INTB_ACK_AO_BC_TC;
1347         if (b_status & NISTC_AO_STATUS1_OVERRUN)
1348                 ack |= NISTC_INTB_ACK_AO_ERR;
1349         if (b_status & NISTC_AO_STATUS1_START)
1350                 ack |= NISTC_INTB_ACK_AO_START;
1351         if (b_status & NISTC_AO_STATUS1_START1)
1352                 ack |= NISTC_INTB_ACK_AO_START1;
1353         if (b_status & NISTC_AO_STATUS1_UC_TC)
1354                 ack |= NISTC_INTB_ACK_AO_UC_TC;
1355         if (b_status & NISTC_AO_STATUS1_UI2_TC)
1356                 ack |= NISTC_INTB_ACK_AO_UI2_TC;
1357         if (b_status & NISTC_AO_STATUS1_UPDATE)
1358                 ack |= NISTC_INTB_ACK_AO_UPDATE;
1359         if (ack)
1360                 ni_stc_writew(dev, ack, NISTC_INTB_ACK_REG);
1361 }
1362
1363 static void handle_b_interrupt(struct comedi_device *dev,
1364                                struct comedi_subdevice *s,
1365                                unsigned short b_status)
1366 {
1367         if (b_status == 0xffff)
1368                 return;
1369         if (b_status & NISTC_AO_STATUS1_OVERRUN) {
1370                 dev_err(dev->class_dev,
1371                         "AO FIFO underrun status=0x%04x status2=0x%04x\n",
1372                         b_status, ni_stc_readw(dev, NISTC_AO_STATUS2_REG));
1373                 s->async->events |= COMEDI_CB_OVERFLOW;
1374         }
1375
1376         if (s->async->cmd.stop_src != TRIG_NONE &&
1377             b_status & NISTC_AO_STATUS1_BC_TC)
1378                 s->async->events |= COMEDI_CB_EOA;
1379
1380 #ifndef PCIDMA
1381         if (b_status & NISTC_AO_STATUS1_FIFO_REQ) {
1382                 int ret;
1383
1384                 ret = ni_ao_fifo_half_empty(dev, s);
1385                 if (!ret) {
1386                         dev_err(dev->class_dev, "AO buffer underrun\n");
1387                         ni_set_bits(dev, NISTC_INTB_ENA_REG,
1388                                     NISTC_INTB_ENA_AO_FIFO |
1389                                     NISTC_INTB_ENA_AO_ERR, 0);
1390                         s->async->events |= COMEDI_CB_OVERFLOW;
1391                 }
1392         }
1393 #endif
1394 }
1395
1396 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1397                         void *data, unsigned int num_bytes,
1398                         unsigned int chan_index)
1399 {
1400         struct ni_private *devpriv = dev->private;
1401         struct comedi_async *async = s->async;
1402         struct comedi_cmd *cmd = &async->cmd;
1403         unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
1404         unsigned short *array = data;
1405         unsigned int *larray = data;
1406         unsigned int i;
1407 #ifdef PCIDMA
1408         __le16 *barray = data;
1409         __le32 *blarray = data;
1410 #endif
1411
1412         for (i = 0; i < nsamples; i++) {
1413 #ifdef PCIDMA
1414                 if (s->subdev_flags & SDF_LSAMPL)
1415                         larray[i] = le32_to_cpu(blarray[i]);
1416                 else
1417                         array[i] = le16_to_cpu(barray[i]);
1418 #endif
1419                 if (s->subdev_flags & SDF_LSAMPL)
1420                         larray[i] += devpriv->ai_offset[chan_index];
1421                 else
1422                         array[i] += devpriv->ai_offset[chan_index];
1423                 chan_index++;
1424                 chan_index %= cmd->chanlist_len;
1425         }
1426 }
1427
1428 #ifdef PCIDMA
1429
1430 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1431 {
1432         struct ni_private *devpriv = dev->private;
1433         struct comedi_subdevice *s = dev->read_subdev;
1434         int retval;
1435         unsigned long flags;
1436
1437         retval = ni_request_ai_mite_channel(dev);
1438         if (retval)
1439                 return retval;
1440
1441         /* write alloc the entire buffer */
1442         comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
1443
1444         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1445         if (!devpriv->ai_mite_chan) {
1446                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1447                 return -EIO;
1448         }
1449
1450         if (devpriv->is_611x || devpriv->is_6143)
1451                 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1452         else if (devpriv->is_628x)
1453                 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1454         else
1455                 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1456
1457         /*start the MITE */
1458         mite_dma_arm(devpriv->ai_mite_chan);
1459         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1460
1461         return 0;
1462 }
1463
1464 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1465 {
1466         struct ni_private *devpriv = dev->private;
1467         struct comedi_subdevice *s = dev->write_subdev;
1468         int retval;
1469         unsigned long flags;
1470
1471         retval = ni_request_ao_mite_channel(dev);
1472         if (retval)
1473                 return retval;
1474
1475         /* read alloc the entire buffer */
1476         comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
1477
1478         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1479         if (devpriv->ao_mite_chan) {
1480                 if (devpriv->is_611x || devpriv->is_6713) {
1481                         mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1482                 } else {
1483                         /*
1484                          * Doing 32 instead of 16 bit wide transfers from
1485                          * memory makes the mite do 32 bit pci transfers,
1486                          * doubling pci bandwidth.
1487                          */
1488                         mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1489                 }
1490                 mite_dma_arm(devpriv->ao_mite_chan);
1491         } else {
1492                 retval = -EIO;
1493         }
1494         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1495
1496         return retval;
1497 }
1498
1499 #endif /*  PCIDMA */
1500
1501 /*
1502  * used for both cancel ioctl and board initialization
1503  *
1504  * this is pretty harsh for a cancel, but it works...
1505  */
1506 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1507 {
1508         struct ni_private *devpriv = dev->private;
1509         unsigned int ai_personal;
1510         unsigned int ai_out_ctrl;
1511
1512         ni_release_ai_mite_channel(dev);
1513         /* ai configuration */
1514         ni_stc_writew(dev, NISTC_RESET_AI_CFG_START | NISTC_RESET_AI,
1515                       NISTC_RESET_REG);
1516
1517         ni_set_bits(dev, NISTC_INTA_ENA_REG, NISTC_INTA_ENA_AI_MASK, 0);
1518
1519         ni_clear_ai_fifo(dev);
1520
1521         if (!devpriv->is_6143)
1522                 ni_writeb(dev, NI_E_MISC_CMD_EXT_ATRIG, NI_E_MISC_CMD_REG);
1523
1524         ni_stc_writew(dev, NISTC_AI_CMD1_DISARM, NISTC_AI_CMD1_REG);
1525         ni_stc_writew(dev, NISTC_AI_MODE1_START_STOP |
1526                            NISTC_AI_MODE1_RSVD
1527                             /*| NISTC_AI_MODE1_TRIGGER_ONCE */,
1528                       NISTC_AI_MODE1_REG);
1529         ni_stc_writew(dev, 0, NISTC_AI_MODE2_REG);
1530         /* generate FIFO interrupts on non-empty */
1531         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
1532                       NISTC_AI_MODE3_REG);
1533
1534         ai_personal = NISTC_AI_PERSONAL_SHIFTIN_PW |
1535                       NISTC_AI_PERSONAL_SOC_POLARITY |
1536                       NISTC_AI_PERSONAL_LOCALMUX_CLK_PW;
1537         ai_out_ctrl = NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(3) |
1538                       NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(0) |
1539                       NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(2) |
1540                       NISTC_AI_OUT_CTRL_SC_TC_SEL(3);
1541         if (devpriv->is_611x) {
1542                 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1543         } else if (devpriv->is_6143) {
1544                 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1545         } else {
1546                 ai_personal |= NISTC_AI_PERSONAL_CONVERT_PW;
1547                 if (devpriv->is_622x)
1548                         ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1549                 else
1550                         ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1551         }
1552         ni_stc_writew(dev, ai_personal, NISTC_AI_PERSONAL_REG);
1553         ni_stc_writew(dev, ai_out_ctrl, NISTC_AI_OUT_CTRL_REG);
1554
1555         /* the following registers should not be changed, because there
1556          * are no backup registers in devpriv.  If you want to change
1557          * any of these, add a backup register and other appropriate code:
1558          *      NISTC_AI_MODE1_REG
1559          *      NISTC_AI_MODE3_REG
1560          *      NISTC_AI_PERSONAL_REG
1561          *      NISTC_AI_OUT_CTRL_REG
1562          */
1563
1564         /* clear interrupts */
1565         ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
1566
1567         ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
1568
1569         return 0;
1570 }
1571
1572 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1573 {
1574         unsigned long flags;
1575         int count;
1576
1577         /*  lock to avoid race with interrupt handler */
1578         spin_lock_irqsave(&dev->spinlock, flags);
1579 #ifndef PCIDMA
1580         ni_handle_fifo_dregs(dev);
1581 #else
1582         ni_sync_ai_dma(dev);
1583 #endif
1584         count = comedi_buf_n_bytes_ready(s);
1585         spin_unlock_irqrestore(&dev->spinlock, flags);
1586
1587         return count;
1588 }
1589
1590 static void ni_prime_channelgain_list(struct comedi_device *dev)
1591 {
1592         int i;
1593
1594         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG);
1595         for (i = 0; i < NI_TIMEOUT; ++i) {
1596                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1597                       NISTC_AI_STATUS1_FIFO_E)) {
1598                         ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
1599                         return;
1600                 }
1601                 udelay(1);
1602         }
1603         dev_err(dev->class_dev, "timeout loading channel/gain list\n");
1604 }
1605
1606 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1607                                               unsigned int n_chan,
1608                                               unsigned int *list)
1609 {
1610         const struct ni_board_struct *board = dev->board_ptr;
1611         struct ni_private *devpriv = dev->private;
1612         unsigned int chan, range, aref;
1613         unsigned int i;
1614         unsigned int dither;
1615         unsigned int range_code;
1616
1617         ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1618
1619         if ((list[0] & CR_ALT_SOURCE)) {
1620                 unsigned int bypass_bits;
1621
1622                 chan = CR_CHAN(list[0]);
1623                 range = CR_RANGE(list[0]);
1624                 range_code = ni_gainlkup[board->gainlkup][range];
1625                 dither = (list[0] & CR_ALT_FILTER) != 0;
1626                 bypass_bits = NI_M_CFG_BYPASS_FIFO |
1627                               NI_M_CFG_BYPASS_AI_CHAN(chan) |
1628                               NI_M_CFG_BYPASS_AI_GAIN(range_code) |
1629                               devpriv->ai_calib_source;
1630                 if (dither)
1631                         bypass_bits |= NI_M_CFG_BYPASS_AI_DITHER;
1632                 /*  don't use 2's complement encoding */
1633                 bypass_bits |= NI_M_CFG_BYPASS_AI_POLARITY;
1634                 ni_writel(dev, bypass_bits, NI_M_CFG_BYPASS_FIFO_REG);
1635         } else {
1636                 ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG);
1637         }
1638         for (i = 0; i < n_chan; i++) {
1639                 unsigned int config_bits = 0;
1640
1641                 chan = CR_CHAN(list[i]);
1642                 aref = CR_AREF(list[i]);
1643                 range = CR_RANGE(list[i]);
1644                 dither = (list[i] & CR_ALT_FILTER) != 0;
1645
1646                 range_code = ni_gainlkup[board->gainlkup][range];
1647                 devpriv->ai_offset[i] = 0;
1648                 switch (aref) {
1649                 case AREF_DIFF:
1650                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_DIFF;
1651                         break;
1652                 case AREF_COMMON:
1653                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_COMMON;
1654                         break;
1655                 case AREF_GROUND:
1656                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_GROUND;
1657                         break;
1658                 case AREF_OTHER:
1659                         break;
1660                 }
1661                 config_bits |= NI_M_AI_CFG_CHAN_SEL(chan);
1662                 config_bits |= NI_M_AI_CFG_BANK_SEL(chan);
1663                 config_bits |= NI_M_AI_CFG_GAIN(range_code);
1664                 if (i == n_chan - 1)
1665                         config_bits |= NI_M_AI_CFG_LAST_CHAN;
1666                 if (dither)
1667                         config_bits |= NI_M_AI_CFG_DITHER;
1668                 /*  don't use 2's complement encoding */
1669                 config_bits |= NI_M_AI_CFG_POLARITY;
1670                 ni_writew(dev, config_bits, NI_M_AI_CFG_FIFO_DATA_REG);
1671         }
1672         ni_prime_channelgain_list(dev);
1673 }
1674
1675 /*
1676  * Notes on the 6110 and 6111:
1677  * These boards a slightly different than the rest of the series, since
1678  * they have multiple A/D converters.
1679  * From the driver side, the configuration memory is a
1680  * little different.
1681  * Configuration Memory Low:
1682  *   bits 15-9: same
1683  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1684  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1685  *       1001 gain=0.1 (+/- 50)
1686  *       1010 0.2
1687  *       1011 0.1
1688  *       0001 1
1689  *       0010 2
1690  *       0011 5
1691  *       0100 10
1692  *       0101 20
1693  *       0110 50
1694  * Configuration Memory High:
1695  *   bits 12-14: Channel Type
1696  *       001 for differential
1697  *       000 for calibration
1698  *   bit 11: coupling  (this is not currently handled)
1699  *       1 AC coupling
1700  *       0 DC coupling
1701  *   bits 0-2: channel
1702  *       valid channels are 0-3
1703  */
1704 static void ni_load_channelgain_list(struct comedi_device *dev,
1705                                      struct comedi_subdevice *s,
1706                                      unsigned int n_chan, unsigned int *list)
1707 {
1708         const struct ni_board_struct *board = dev->board_ptr;
1709         struct ni_private *devpriv = dev->private;
1710         unsigned int offset = (s->maxdata + 1) >> 1;
1711         unsigned int chan, range, aref;
1712         unsigned int i;
1713         unsigned int hi, lo;
1714         unsigned int dither;
1715
1716         if (devpriv->is_m_series) {
1717                 ni_m_series_load_channelgain_list(dev, n_chan, list);
1718                 return;
1719         }
1720         if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) {
1721                 if (devpriv->changain_state &&
1722                     devpriv->changain_spec == list[0]) {
1723                         /*  ready to go. */
1724                         return;
1725                 }
1726                 devpriv->changain_state = 1;
1727                 devpriv->changain_spec = list[0];
1728         } else {
1729                 devpriv->changain_state = 0;
1730         }
1731
1732         ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1733
1734         /*  Set up Calibration mode if required */
1735         if (devpriv->is_6143) {
1736                 if ((list[0] & CR_ALT_SOURCE) &&
1737                     !devpriv->ai_calib_source_enabled) {
1738                         /*  Strobe Relay enable bit */
1739                         ni_writew(dev, devpriv->ai_calib_source |
1740                                        NI6143_CALIB_CHAN_RELAY_ON,
1741                                   NI6143_CALIB_CHAN_REG);
1742                         ni_writew(dev, devpriv->ai_calib_source,
1743                                   NI6143_CALIB_CHAN_REG);
1744                         devpriv->ai_calib_source_enabled = 1;
1745                         /* Allow relays to change */
1746                         msleep_interruptible(100);
1747                 } else if (!(list[0] & CR_ALT_SOURCE) &&
1748                            devpriv->ai_calib_source_enabled) {
1749                         /*  Strobe Relay disable bit */
1750                         ni_writew(dev, devpriv->ai_calib_source |
1751                                        NI6143_CALIB_CHAN_RELAY_OFF,
1752                                   NI6143_CALIB_CHAN_REG);
1753                         ni_writew(dev, devpriv->ai_calib_source,
1754                                   NI6143_CALIB_CHAN_REG);
1755                         devpriv->ai_calib_source_enabled = 0;
1756                         /* Allow relays to change */
1757                         msleep_interruptible(100);
1758                 }
1759         }
1760
1761         for (i = 0; i < n_chan; i++) {
1762                 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE))
1763                         chan = devpriv->ai_calib_source;
1764                 else
1765                         chan = CR_CHAN(list[i]);
1766                 aref = CR_AREF(list[i]);
1767                 range = CR_RANGE(list[i]);
1768                 dither = (list[i] & CR_ALT_FILTER) != 0;
1769
1770                 /* fix the external/internal range differences */
1771                 range = ni_gainlkup[board->gainlkup][range];
1772                 if (devpriv->is_611x)
1773                         devpriv->ai_offset[i] = offset;
1774                 else
1775                         devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
1776
1777                 hi = 0;
1778                 if ((list[i] & CR_ALT_SOURCE)) {
1779                         if (devpriv->is_611x)
1780                                 ni_writew(dev, CR_CHAN(list[i]) & 0x0003,
1781                                           NI611X_CALIB_CHAN_SEL_REG);
1782                 } else {
1783                         if (devpriv->is_611x)
1784                                 aref = AREF_DIFF;
1785                         else if (devpriv->is_6143)
1786                                 aref = AREF_OTHER;
1787                         switch (aref) {
1788                         case AREF_DIFF:
1789                                 hi |= NI_E_AI_CFG_HI_TYPE_DIFF;
1790                                 break;
1791                         case AREF_COMMON:
1792                                 hi |= NI_E_AI_CFG_HI_TYPE_COMMON;
1793                                 break;
1794                         case AREF_GROUND:
1795                                 hi |= NI_E_AI_CFG_HI_TYPE_GROUND;
1796                                 break;
1797                         case AREF_OTHER:
1798                                 break;
1799                         }
1800                 }
1801                 hi |= NI_E_AI_CFG_HI_CHAN(chan);
1802
1803                 ni_writew(dev, hi, NI_E_AI_CFG_HI_REG);
1804
1805                 if (!devpriv->is_6143) {
1806                         lo = NI_E_AI_CFG_LO_GAIN(range);
1807
1808                         if (i == n_chan - 1)
1809                                 lo |= NI_E_AI_CFG_LO_LAST_CHAN;
1810                         if (dither)
1811                                 lo |= NI_E_AI_CFG_LO_DITHER;
1812
1813                         ni_writew(dev, lo, NI_E_AI_CFG_LO_REG);
1814                 }
1815         }
1816
1817         /* prime the channel/gain list */
1818         if (!devpriv->is_611x && !devpriv->is_6143)
1819                 ni_prime_channelgain_list(dev);
1820 }
1821
1822 static int ni_ai_insn_read(struct comedi_device *dev,
1823                            struct comedi_subdevice *s,
1824                            struct comedi_insn *insn,
1825                            unsigned int *data)
1826 {
1827         struct ni_private *devpriv = dev->private;
1828         unsigned int mask = s->maxdata;
1829         int i, n;
1830         unsigned int signbits;
1831         unsigned int d;
1832
1833         ni_load_channelgain_list(dev, s, 1, &insn->chanspec);
1834
1835         ni_clear_ai_fifo(dev);
1836
1837         signbits = devpriv->ai_offset[0];
1838         if (devpriv->is_611x) {
1839                 for (n = 0; n < num_adc_stages_611x; n++) {
1840                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1841                                       NISTC_AI_CMD1_REG);
1842                         udelay(1);
1843                 }
1844                 for (n = 0; n < insn->n; n++) {
1845                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1846                                       NISTC_AI_CMD1_REG);
1847                         /* The 611x has screwy 32-bit FIFOs. */
1848                         d = 0;
1849                         for (i = 0; i < NI_TIMEOUT; i++) {
1850                                 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1851                                         d = ni_readl(dev,
1852                                                      NI611X_AI_FIFO_DATA_REG);
1853                                         d >>= 16;
1854                                         d &= 0xffff;
1855                                         break;
1856                                 }
1857                                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1858                                       NISTC_AI_STATUS1_FIFO_E)) {
1859                                         d = ni_readl(dev,
1860                                                      NI611X_AI_FIFO_DATA_REG);
1861                                         d &= 0xffff;
1862                                         break;
1863                                 }
1864                         }
1865                         if (i == NI_TIMEOUT) {
1866                                 dev_err(dev->class_dev, "timeout\n");
1867                                 return -ETIME;
1868                         }
1869                         d += signbits;
1870                         data[n] = d & 0xffff;
1871                 }
1872         } else if (devpriv->is_6143) {
1873                 for (n = 0; n < insn->n; n++) {
1874                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1875                                       NISTC_AI_CMD1_REG);
1876
1877                         /*
1878                          * The 6143 has 32-bit FIFOs. You need to strobe a
1879                          * bit to move a single 16bit stranded sample into
1880                          * the FIFO.
1881                          */
1882                         d = 0;
1883                         for (i = 0; i < NI_TIMEOUT; i++) {
1884                                 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) &
1885                                     0x01) {
1886                                         /* Get stranded sample into FIFO */
1887                                         ni_writel(dev, 0x01,
1888                                                   NI6143_AI_FIFO_CTRL_REG);
1889                                         d = ni_readl(dev,
1890                                                      NI6143_AI_FIFO_DATA_REG);
1891                                         break;
1892                                 }
1893                         }
1894                         if (i == NI_TIMEOUT) {
1895                                 dev_err(dev->class_dev, "timeout\n");
1896                                 return -ETIME;
1897                         }
1898                         data[n] = (((d >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1899                 }
1900         } else {
1901                 for (n = 0; n < insn->n; n++) {
1902                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1903                                       NISTC_AI_CMD1_REG);
1904                         for (i = 0; i < NI_TIMEOUT; i++) {
1905                                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1906                                       NISTC_AI_STATUS1_FIFO_E))
1907                                         break;
1908                         }
1909                         if (i == NI_TIMEOUT) {
1910                                 dev_err(dev->class_dev, "timeout\n");
1911                                 return -ETIME;
1912                         }
1913                         if (devpriv->is_m_series) {
1914                                 d = ni_readl(dev, NI_M_AI_FIFO_DATA_REG);
1915                                 d &= mask;
1916                                 data[n] = d;
1917                         } else {
1918                                 d = ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1919                                 d += signbits;
1920                                 data[n] = d & 0xffff;
1921                         }
1922                 }
1923         }
1924         return insn->n;
1925 }
1926
1927 static int ni_ns_to_timer(const struct comedi_device *dev,
1928                           unsigned int nanosec, unsigned int flags)
1929 {
1930         struct ni_private *devpriv = dev->private;
1931         int divider;
1932
1933         switch (flags & CMDF_ROUND_MASK) {
1934         case CMDF_ROUND_NEAREST:
1935         default:
1936                 divider = DIV_ROUND_CLOSEST(nanosec, devpriv->clock_ns);
1937                 break;
1938         case CMDF_ROUND_DOWN:
1939                 divider = (nanosec) / devpriv->clock_ns;
1940                 break;
1941         case CMDF_ROUND_UP:
1942                 divider = DIV_ROUND_UP(nanosec, devpriv->clock_ns);
1943                 break;
1944         }
1945         return divider - 1;
1946 }
1947
1948 static unsigned int ni_timer_to_ns(const struct comedi_device *dev, int timer)
1949 {
1950         struct ni_private *devpriv = dev->private;
1951
1952         return devpriv->clock_ns * (timer + 1);
1953 }
1954
1955 static void ni_cmd_set_mite_transfer(struct mite_ring *ring,
1956                                      struct comedi_subdevice *sdev,
1957                                      const struct comedi_cmd *cmd,
1958                                      unsigned int max_count)
1959 {
1960 #ifdef PCIDMA
1961         unsigned int nbytes = max_count;
1962
1963         if (cmd->stop_arg > 0 && cmd->stop_arg < max_count)
1964                 nbytes = cmd->stop_arg;
1965         nbytes *= comedi_bytes_per_scan(sdev);
1966
1967         if (nbytes > sdev->async->prealloc_bufsz) {
1968                 if (cmd->stop_arg > 0)
1969                         dev_err(sdev->device->class_dev,
1970                                 "%s: tried exact data transfer limits greater than buffer size\n",
1971                                 __func__);
1972
1973                 /*
1974                  * we can only transfer up to the size of the buffer.  In this
1975                  * case, the user is expected to continue to write into the
1976                  * comedi buffer (already implemented as a ring buffer).
1977                  */
1978                 nbytes = sdev->async->prealloc_bufsz;
1979         }
1980
1981         mite_init_ring_descriptors(ring, sdev, nbytes);
1982 #else
1983         dev_err(sdev->device->class_dev,
1984                 "%s: exact data transfer limits not implemented yet without DMA\n",
1985                 __func__);
1986 #endif
1987 }
1988
1989 static unsigned int ni_min_ai_scan_period_ns(struct comedi_device *dev,
1990                                              unsigned int num_channels)
1991 {
1992         const struct ni_board_struct *board = dev->board_ptr;
1993         struct ni_private *devpriv = dev->private;
1994
1995         /* simultaneously-sampled inputs */
1996         if (devpriv->is_611x || devpriv->is_6143)
1997                 return board->ai_speed;
1998
1999         /* multiplexed inputs */
2000         return board->ai_speed * num_channels;
2001 }
2002
2003 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2004                          struct comedi_cmd *cmd)
2005 {
2006         const struct ni_board_struct *board = dev->board_ptr;
2007         struct ni_private *devpriv = dev->private;
2008         int err = 0;
2009         unsigned int sources;
2010
2011         /* Step 1 : check if triggers are trivially valid */
2012
2013         err |= comedi_check_trigger_src(&cmd->start_src,
2014                                         TRIG_NOW | TRIG_INT | TRIG_EXT);
2015         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
2016                                         TRIG_TIMER | TRIG_EXT);
2017
2018         sources = TRIG_TIMER | TRIG_EXT;
2019         if (devpriv->is_611x || devpriv->is_6143)
2020                 sources |= TRIG_NOW;
2021         err |= comedi_check_trigger_src(&cmd->convert_src, sources);
2022
2023         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2024         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2025
2026         if (err)
2027                 return 1;
2028
2029         /* Step 2a : make sure trigger sources are unique */
2030
2031         err |= comedi_check_trigger_is_unique(cmd->start_src);
2032         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2033         err |= comedi_check_trigger_is_unique(cmd->convert_src);
2034         err |= comedi_check_trigger_is_unique(cmd->stop_src);
2035
2036         /* Step 2b : and mutually compatible */
2037
2038         if (err)
2039                 return 2;
2040
2041         /* Step 3: check if arguments are trivially valid */
2042
2043         switch (cmd->start_src) {
2044         case TRIG_NOW:
2045         case TRIG_INT:
2046                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2047                 break;
2048         case TRIG_EXT:
2049                 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->start_arg),
2050                                                   NI_AI_StartTrigger,
2051                                                   &devpriv->routing_tables, 1);
2052                 break;
2053         }
2054
2055         if (cmd->scan_begin_src == TRIG_TIMER) {
2056                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
2057                         ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2058                 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
2059                                                     devpriv->clock_ns *
2060                                                     0xffffff);
2061         } else if (cmd->scan_begin_src == TRIG_EXT) {
2062                 /* external trigger */
2063                 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->scan_begin_arg),
2064                                                   NI_AI_SampleClock,
2065                                                   &devpriv->routing_tables, 1);
2066         } else {                /* TRIG_OTHER */
2067                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2068         }
2069
2070         if (cmd->convert_src == TRIG_TIMER) {
2071                 if (devpriv->is_611x || devpriv->is_6143) {
2072                         err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2073                                                            0);
2074                 } else {
2075                         err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2076                                                             board->ai_speed);
2077                         err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
2078                                                             devpriv->clock_ns *
2079                                                             0xffff);
2080                 }
2081         } else if (cmd->convert_src == TRIG_EXT) {
2082                 /* external trigger */
2083                 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->convert_arg),
2084                                                   NI_AI_ConvertClock,
2085                                                   &devpriv->routing_tables, 1);
2086         } else if (cmd->convert_src == TRIG_NOW) {
2087                 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
2088         }
2089
2090         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2091                                            cmd->chanlist_len);
2092
2093         if (cmd->stop_src == TRIG_COUNT) {
2094                 unsigned int max_count = 0x01000000;
2095
2096                 if (devpriv->is_611x)
2097                         max_count -= num_adc_stages_611x;
2098                 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count);
2099                 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2100         } else {
2101                 /* TRIG_NONE */
2102                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2103         }
2104
2105         if (err)
2106                 return 3;
2107
2108         /* step 4: fix up any arguments */
2109
2110         if (cmd->scan_begin_src == TRIG_TIMER) {
2111                 unsigned int tmp = cmd->scan_begin_arg;
2112
2113                 cmd->scan_begin_arg =
2114                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2115                                                        cmd->scan_begin_arg,
2116                                                        cmd->flags));
2117                 if (tmp != cmd->scan_begin_arg)
2118                         err++;
2119         }
2120         if (cmd->convert_src == TRIG_TIMER) {
2121                 if (!devpriv->is_611x && !devpriv->is_6143) {
2122                         unsigned int tmp = cmd->convert_arg;
2123
2124                         cmd->convert_arg =
2125                             ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2126                                                                cmd->convert_arg,
2127                                                                cmd->flags));
2128                         if (tmp != cmd->convert_arg)
2129                                 err++;
2130                         if (cmd->scan_begin_src == TRIG_TIMER &&
2131                             cmd->scan_begin_arg <
2132                             cmd->convert_arg * cmd->scan_end_arg) {
2133                                 cmd->scan_begin_arg =
2134                                     cmd->convert_arg * cmd->scan_end_arg;
2135                                 err++;
2136                         }
2137                 }
2138         }
2139
2140         if (err)
2141                 return 4;
2142
2143         return 0;
2144 }
2145
2146 static int ni_ai_inttrig(struct comedi_device *dev,
2147                          struct comedi_subdevice *s,
2148                          unsigned int trig_num)
2149 {
2150         struct ni_private *devpriv = dev->private;
2151         struct comedi_cmd *cmd = &s->async->cmd;
2152
2153         if (trig_num != cmd->start_arg)
2154                 return -EINVAL;
2155
2156         ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2,
2157                       NISTC_AI_CMD2_REG);
2158         s->async->inttrig = NULL;
2159
2160         return 1;
2161 }
2162
2163 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2164 {
2165         struct ni_private *devpriv = dev->private;
2166         const struct comedi_cmd *cmd = &s->async->cmd;
2167         int timer;
2168         int mode1 = 0;          /* mode1 is needed for both stop and convert */
2169         int mode2 = 0;
2170         int start_stop_select = 0;
2171         unsigned int stop_count;
2172         int interrupt_a_enable = 0;
2173         unsigned int ai_trig;
2174
2175         if (dev->irq == 0) {
2176                 dev_err(dev->class_dev, "cannot run command without an irq\n");
2177                 return -EIO;
2178         }
2179         ni_clear_ai_fifo(dev);
2180
2181         ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist);
2182
2183         /* start configuration */
2184         ni_stc_writew(dev, NISTC_RESET_AI_CFG_START, NISTC_RESET_REG);
2185
2186         /*
2187          * Disable analog triggering for now, since it interferes
2188          * with the use of pfi0.
2189          */
2190         devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA;
2191         ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
2192
2193         ai_trig = NISTC_AI_TRIG_START2_SEL(0) | NISTC_AI_TRIG_START1_SYNC;
2194         switch (cmd->start_src) {
2195         case TRIG_INT:
2196         case TRIG_NOW:
2197                 ai_trig |= NISTC_AI_TRIG_START1_EDGE |
2198                            NISTC_AI_TRIG_START1_SEL(0);
2199                 break;
2200         case TRIG_EXT:
2201                 ai_trig |= NISTC_AI_TRIG_START1_SEL(
2202                                 ni_get_reg_value_roffs(
2203                                         CR_CHAN(cmd->start_arg),
2204                                         NI_AI_StartTrigger,
2205                                         &devpriv->routing_tables, 1));
2206
2207                 if (cmd->start_arg & CR_INVERT)
2208                         ai_trig |= NISTC_AI_TRIG_START1_POLARITY;
2209                 if (cmd->start_arg & CR_EDGE)
2210                         ai_trig |= NISTC_AI_TRIG_START1_EDGE;
2211                 break;
2212         }
2213         ni_stc_writew(dev, ai_trig, NISTC_AI_TRIG_SEL_REG);
2214
2215         mode2 &= ~NISTC_AI_MODE2_PRE_TRIGGER;
2216         mode2 &= ~NISTC_AI_MODE2_SC_INIT_LOAD_SRC;
2217         mode2 &= ~NISTC_AI_MODE2_SC_RELOAD_MODE;
2218         ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2219
2220         if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) {
2221                 /* logic low */
2222                 start_stop_select |= NISTC_AI_STOP_POLARITY |
2223                                      NISTC_AI_STOP_SEL(31) |
2224                                      NISTC_AI_STOP_SYNC;
2225         } else {
2226                 /*  ai configuration memory */
2227                 start_stop_select |= NISTC_AI_STOP_SEL(19);
2228         }
2229         ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2230
2231         devpriv->ai_cmd2 = 0;
2232         switch (cmd->stop_src) {
2233         case TRIG_COUNT:
2234                 stop_count = cmd->stop_arg - 1;
2235
2236                 if (devpriv->is_611x) {
2237                         /*  have to take 3 stage adc pipeline into account */
2238                         stop_count += num_adc_stages_611x;
2239                 }
2240                 /* stage number of scans */
2241                 ni_stc_writel(dev, stop_count, NISTC_AI_SC_LOADA_REG);
2242
2243                 mode1 |= NISTC_AI_MODE1_START_STOP |
2244                          NISTC_AI_MODE1_RSVD |
2245                          NISTC_AI_MODE1_TRIGGER_ONCE;
2246                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2247                 /* load SC (Scan Count) */
2248                 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2249
2250                 if (stop_count == 0) {
2251                         devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS;
2252                         interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2253                         /*
2254                          * This is required to get the last sample for
2255                          * chanlist_len > 1, not sure why.
2256                          */
2257                         if (cmd->chanlist_len > 1)
2258                                 start_stop_select |= NISTC_AI_STOP_POLARITY |
2259                                                      NISTC_AI_STOP_EDGE;
2260                 }
2261                 break;
2262         case TRIG_NONE:
2263                 /* stage number of scans */
2264                 ni_stc_writel(dev, 0, NISTC_AI_SC_LOADA_REG);
2265
2266                 mode1 |= NISTC_AI_MODE1_START_STOP |
2267                          NISTC_AI_MODE1_RSVD |
2268                          NISTC_AI_MODE1_CONTINUOUS;
2269                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2270
2271                 /* load SC (Scan Count) */
2272                 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2273                 break;
2274         }
2275
2276         switch (cmd->scan_begin_src) {
2277         case TRIG_TIMER:
2278                 /*
2279                  * stop bits for non 611x boards
2280                  * NISTC_AI_MODE3_SI_TRIG_DELAY=0
2281                  * NISTC_AI_MODE2_PRE_TRIGGER=0
2282                  * NISTC_AI_START_STOP_REG:
2283                  * NISTC_AI_START_POLARITY=0    (?) rising edge
2284                  * NISTC_AI_START_EDGE=1        edge triggered
2285                  * NISTC_AI_START_SYNC=1        (?)
2286                  * NISTC_AI_START_SEL=0         SI_TC
2287                  * NISTC_AI_STOP_POLARITY=0     rising edge
2288                  * NISTC_AI_STOP_EDGE=0         level
2289                  * NISTC_AI_STOP_SYNC=1
2290                  * NISTC_AI_STOP_SEL=19         external pin (configuration mem)
2291                  */
2292                 start_stop_select |= NISTC_AI_START_EDGE | NISTC_AI_START_SYNC;
2293                 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2294
2295                 mode2 &= ~NISTC_AI_MODE2_SI_INIT_LOAD_SRC;      /* A */
2296                 mode2 |= NISTC_AI_MODE2_SI_RELOAD_MODE(0);
2297                 /* mode2 |= NISTC_AI_MODE2_SC_RELOAD_MODE; */
2298                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2299
2300                 /* load SI */
2301                 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2302                                        CMDF_ROUND_NEAREST);
2303                 ni_stc_writel(dev, timer, NISTC_AI_SI_LOADA_REG);
2304                 ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG);
2305                 break;
2306         case TRIG_EXT:
2307                 if (cmd->scan_begin_arg & CR_EDGE)
2308                         start_stop_select |= NISTC_AI_START_EDGE;
2309                 if (cmd->scan_begin_arg & CR_INVERT)    /* falling edge */
2310                         start_stop_select |= NISTC_AI_START_POLARITY;
2311                 if (cmd->scan_begin_src != cmd->convert_src ||
2312                     (cmd->scan_begin_arg & ~CR_EDGE) !=
2313                     (cmd->convert_arg & ~CR_EDGE))
2314                         start_stop_select |= NISTC_AI_START_SYNC;
2315
2316                 start_stop_select |= NISTC_AI_START_SEL(
2317                                         ni_get_reg_value_roffs(
2318                                                 CR_CHAN(cmd->scan_begin_arg),
2319                                                 NI_AI_SampleClock,
2320                                                 &devpriv->routing_tables, 1));
2321                 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2322                 break;
2323         }
2324
2325         switch (cmd->convert_src) {
2326         case TRIG_TIMER:
2327         case TRIG_NOW:
2328                 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2329                         timer = 1;
2330                 else
2331                         timer = ni_ns_to_timer(dev, cmd->convert_arg,
2332                                                CMDF_ROUND_NEAREST);
2333                 /* 0,0 does not work */
2334                 ni_stc_writew(dev, 1, NISTC_AI_SI2_LOADA_REG);
2335                 ni_stc_writew(dev, timer, NISTC_AI_SI2_LOADB_REG);
2336
2337                 mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC;     /* A */
2338                 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE;        /* alternate */
2339                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2340
2341                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_LOAD, NISTC_AI_CMD1_REG);
2342
2343                 mode2 |= NISTC_AI_MODE2_SI2_INIT_LOAD_SRC;      /* B */
2344                 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE;        /* alternate */
2345                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2346                 break;
2347         case TRIG_EXT:
2348                 mode1 |= NISTC_AI_MODE1_CONVERT_SRC(
2349                                 ni_get_reg_value_roffs(
2350                                                 CR_CHAN(cmd->convert_arg),
2351                                                 NI_AI_ConvertClock,
2352                                                 &devpriv->routing_tables, 1));
2353                 if ((cmd->convert_arg & CR_INVERT) == 0)
2354                         mode1 |= NISTC_AI_MODE1_CONVERT_POLARITY;
2355                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2356
2357                 mode2 |= NISTC_AI_MODE2_SC_GATE_ENA |
2358                          NISTC_AI_MODE2_START_STOP_GATE_ENA;
2359                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2360
2361                 break;
2362         }
2363
2364         if (dev->irq) {
2365                 /* interrupt on FIFO, errors, SC_TC */
2366                 interrupt_a_enable |= NISTC_INTA_ENA_AI_ERR |
2367                                       NISTC_INTA_ENA_AI_SC_TC;
2368
2369 #ifndef PCIDMA
2370                 interrupt_a_enable |= NISTC_INTA_ENA_AI_FIFO;
2371 #endif
2372
2373                 if ((cmd->flags & CMDF_WAKE_EOS) ||
2374                     (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) {
2375                         /* wake on end-of-scan */
2376                         devpriv->aimode = AIMODE_SCAN;
2377                 } else {
2378                         devpriv->aimode = AIMODE_HALF_FULL;
2379                 }
2380
2381                 switch (devpriv->aimode) {
2382                 case AIMODE_HALF_FULL:
2383                         /* FIFO interrupts and DMA requests on half-full */
2384 #ifdef PCIDMA
2385                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF_E,
2386                                       NISTC_AI_MODE3_REG);
2387 #else
2388                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2389                                       NISTC_AI_MODE3_REG);
2390 #endif
2391                         break;
2392                 case AIMODE_SAMPLE:
2393                         /* generate FIFO interrupts on non-empty */
2394                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2395                                       NISTC_AI_MODE3_REG);
2396                         break;
2397                 case AIMODE_SCAN:
2398 #ifdef PCIDMA
2399                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2400                                       NISTC_AI_MODE3_REG);
2401 #else
2402                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2403                                       NISTC_AI_MODE3_REG);
2404 #endif
2405                         interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2406                         break;
2407                 default:
2408                         break;
2409                 }
2410
2411                 /* clear interrupts */
2412                 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
2413
2414                 ni_set_bits(dev, NISTC_INTA_ENA_REG, interrupt_a_enable, 1);
2415         } else {
2416                 /* interrupt on nothing */
2417                 ni_set_bits(dev, NISTC_INTA_ENA_REG, ~0, 0);
2418
2419                 /* XXX start polling if necessary */
2420         }
2421
2422         /* end configuration */
2423         ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
2424
2425         switch (cmd->scan_begin_src) {
2426         case TRIG_TIMER:
2427                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2428                                    NISTC_AI_CMD1_SI_ARM |
2429                                    NISTC_AI_CMD1_DIV_ARM |
2430                                    NISTC_AI_CMD1_SC_ARM,
2431                               NISTC_AI_CMD1_REG);
2432                 break;
2433         case TRIG_EXT:
2434                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2435                                    NISTC_AI_CMD1_SI_ARM |       /* XXX ? */
2436                                    NISTC_AI_CMD1_DIV_ARM |
2437                                    NISTC_AI_CMD1_SC_ARM,
2438                               NISTC_AI_CMD1_REG);
2439                 break;
2440         }
2441
2442 #ifdef PCIDMA
2443         {
2444                 int retval = ni_ai_setup_MITE_dma(dev);
2445
2446                 if (retval)
2447                         return retval;
2448         }
2449 #endif
2450
2451         if (cmd->start_src == TRIG_NOW) {
2452                 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE |
2453                                    devpriv->ai_cmd2,
2454                               NISTC_AI_CMD2_REG);
2455                 s->async->inttrig = NULL;
2456         } else if (cmd->start_src == TRIG_EXT) {
2457                 s->async->inttrig = NULL;
2458         } else {        /* TRIG_INT */
2459                 s->async->inttrig = ni_ai_inttrig;
2460         }
2461
2462         return 0;
2463 }
2464
2465 static int ni_ai_insn_config(struct comedi_device *dev,
2466                              struct comedi_subdevice *s,
2467                              struct comedi_insn *insn, unsigned int *data)
2468 {
2469         const struct ni_board_struct *board = dev->board_ptr;
2470         struct ni_private *devpriv = dev->private;
2471
2472         if (insn->n < 1)
2473                 return -EINVAL;
2474
2475         switch (data[0]) {
2476         case INSN_CONFIG_ALT_SOURCE:
2477                 if (devpriv->is_m_series) {
2478                         if (data[1] & ~NI_M_CFG_BYPASS_AI_CAL_MASK)
2479                                 return -EINVAL;
2480                         devpriv->ai_calib_source = data[1];
2481                 } else if (devpriv->is_6143) {
2482                         unsigned int calib_source;
2483
2484                         calib_source = data[1] & 0xf;
2485
2486                         devpriv->ai_calib_source = calib_source;
2487                         ni_writew(dev, calib_source, NI6143_CALIB_CHAN_REG);
2488                 } else {
2489                         unsigned int calib_source;
2490                         unsigned int calib_source_adjust;
2491
2492                         calib_source = data[1] & 0xf;
2493                         calib_source_adjust = (data[1] >> 4) & 0xff;
2494
2495                         if (calib_source >= 8)
2496                                 return -EINVAL;
2497                         devpriv->ai_calib_source = calib_source;
2498                         if (devpriv->is_611x) {
2499                                 ni_writeb(dev, calib_source_adjust,
2500                                           NI611X_CAL_GAIN_SEL_REG);
2501                         }
2502                 }
2503                 return 2;
2504         case INSN_CONFIG_GET_CMD_TIMING_CONSTRAINTS:
2505                 /* we don't care about actual channels */
2506                 /* data[3] : chanlist_len */
2507                 data[1] = ni_min_ai_scan_period_ns(dev, data[3]);
2508                 if (devpriv->is_611x || devpriv->is_6143)
2509                         data[2] = 0; /* simultaneous output */
2510                 else
2511                         data[2] = board->ai_speed;
2512                 return 0;
2513         default:
2514                 break;
2515         }
2516
2517         return -EINVAL;
2518 }
2519
2520 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2521                         void *data, unsigned int num_bytes,
2522                         unsigned int chan_index)
2523 {
2524         struct comedi_cmd *cmd = &s->async->cmd;
2525         unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
2526         unsigned short *array = data;
2527         unsigned int i;
2528 #ifdef PCIDMA
2529         __le16 buf, *barray = data;
2530 #endif
2531
2532         for (i = 0; i < nsamples; i++) {
2533                 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]);
2534                 unsigned short val = array[i];
2535
2536                 /*
2537                  * Munge data from unsigned to two's complement for
2538                  * bipolar ranges.
2539                  */
2540                 if (comedi_range_is_bipolar(s, range))
2541                         val = comedi_offset_munge(s, val);
2542 #ifdef PCIDMA
2543                 buf = cpu_to_le16(val);
2544                 barray[i] = buf;
2545 #else
2546                 array[i] = val;
2547 #endif
2548                 chan_index++;
2549                 chan_index %= cmd->chanlist_len;
2550         }
2551 }
2552
2553 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2554                                           struct comedi_subdevice *s,
2555                                           unsigned int chanspec[],
2556                                           unsigned int n_chans, int timed)
2557 {
2558         struct ni_private *devpriv = dev->private;
2559         unsigned int range;
2560         unsigned int chan;
2561         unsigned int conf;
2562         int i;
2563         int invert = 0;
2564
2565         if (timed) {
2566                 for (i = 0; i < s->n_chan; ++i) {
2567                         devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED;
2568                         ni_writeb(dev, devpriv->ao_conf[i],
2569                                   NI_M_AO_CFG_BANK_REG(i));
2570                         ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i));
2571                 }
2572         }
2573         for (i = 0; i < n_chans; i++) {
2574                 const struct comedi_krange *krange;
2575
2576                 chan = CR_CHAN(chanspec[i]);
2577                 range = CR_RANGE(chanspec[i]);
2578                 krange = s->range_table->range + range;
2579                 invert = 0;
2580                 conf = 0;
2581                 switch (krange->max - krange->min) {
2582                 case 20000000:
2583                         conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2584                         ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2585                         break;
2586                 case 10000000:
2587                         conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2588                         ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2589                         break;
2590                 case 4000000:
2591                         conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2592                         ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2593                                   NI_M_AO_REF_ATTENUATION_REG(chan));
2594                         break;
2595                 case 2000000:
2596                         conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2597                         ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2598                                   NI_M_AO_REF_ATTENUATION_REG(chan));
2599                         break;
2600                 default:
2601                         dev_err(dev->class_dev,
2602                                 "bug! unhandled ao reference voltage\n");
2603                         break;
2604                 }
2605                 switch (krange->max + krange->min) {
2606                 case 0:
2607                         conf |= NI_M_AO_CFG_BANK_OFFSET_0V;
2608                         break;
2609                 case 10000000:
2610                         conf |= NI_M_AO_CFG_BANK_OFFSET_5V;
2611                         break;
2612                 default:
2613                         dev_err(dev->class_dev,
2614                                 "bug! unhandled ao offset voltage\n");
2615                         break;
2616                 }
2617                 if (timed)
2618                         conf |= NI_M_AO_CFG_BANK_UPDATE_TIMED;
2619                 ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan));
2620                 devpriv->ao_conf[chan] = conf;
2621                 ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan));
2622         }
2623         return invert;
2624 }
2625
2626 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2627                                      struct comedi_subdevice *s,
2628                                      unsigned int chanspec[],
2629                                      unsigned int n_chans)
2630 {
2631         struct ni_private *devpriv = dev->private;
2632         unsigned int range;
2633         unsigned int chan;
2634         unsigned int conf;
2635         int i;
2636         int invert = 0;
2637
2638         for (i = 0; i < n_chans; i++) {
2639                 chan = CR_CHAN(chanspec[i]);
2640                 range = CR_RANGE(chanspec[i]);
2641                 conf = NI_E_AO_DACSEL(chan);
2642
2643                 if (comedi_range_is_bipolar(s, range)) {
2644                         conf |= NI_E_AO_CFG_BIP;
2645                         invert = (s->maxdata + 1) >> 1;
2646                 } else {
2647                         invert = 0;
2648                 }
2649                 if (comedi_range_is_external(s, range))
2650                         conf |= NI_E_AO_EXT_REF;
2651
2652                 /* not all boards can deglitch, but this shouldn't hurt */
2653                 if (chanspec[i] & CR_DEGLITCH)
2654                         conf |= NI_E_AO_DEGLITCH;
2655
2656                 /* analog reference */
2657                 /* AREF_OTHER connects AO ground to AI ground, i think */
2658                 if (CR_AREF(chanspec[i]) == AREF_OTHER)
2659                         conf |= NI_E_AO_GROUND_REF;
2660
2661                 ni_writew(dev, conf, NI_E_AO_CFG_REG);
2662                 devpriv->ao_conf[chan] = conf;
2663         }
2664         return invert;
2665 }
2666
2667 static int ni_ao_config_chanlist(struct comedi_device *dev,
2668                                  struct comedi_subdevice *s,
2669                                  unsigned int chanspec[], unsigned int n_chans,
2670                                  int timed)
2671 {
2672         struct ni_private *devpriv = dev->private;
2673
2674         if (devpriv->is_m_series)
2675                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2676                                                       timed);
2677         else
2678                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2679 }
2680
2681 static int ni_ao_insn_write(struct comedi_device *dev,
2682                             struct comedi_subdevice *s,
2683                             struct comedi_insn *insn,
2684                             unsigned int *data)
2685 {
2686         struct ni_private *devpriv = dev->private;
2687         unsigned int chan = CR_CHAN(insn->chanspec);
2688         unsigned int range = CR_RANGE(insn->chanspec);
2689         int reg;
2690         int i;
2691
2692         if (devpriv->is_6xxx) {
2693                 ni_ao_win_outw(dev, 1 << chan, NI671X_AO_IMMEDIATE_REG);
2694
2695                 reg = NI671X_DAC_DIRECT_DATA_REG(chan);
2696         } else if (devpriv->is_m_series) {
2697                 reg = NI_M_DAC_DIRECT_DATA_REG(chan);
2698         } else {
2699                 reg = NI_E_DAC_DIRECT_DATA_REG(chan);
2700         }
2701
2702         ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2703
2704         for (i = 0; i < insn->n; i++) {
2705                 unsigned int val = data[i];
2706
2707                 s->readback[chan] = val;
2708
2709                 if (devpriv->is_6xxx) {
2710                         /*
2711                          * 6xxx boards have bipolar outputs, munge the
2712                          * unsigned comedi values to 2's complement
2713                          */
2714                         val = comedi_offset_munge(s, val);
2715
2716                         ni_ao_win_outw(dev, val, reg);
2717                 } else if (devpriv->is_m_series) {
2718                         /*
2719                          * M-series boards use offset binary values for
2720                          * bipolar and uinpolar outputs
2721                          */
2722                         ni_writew(dev, val, reg);
2723                 } else {
2724                         /*
2725                          * Non-M series boards need two's complement values
2726                          * for bipolar ranges.
2727                          */
2728                         if (comedi_range_is_bipolar(s, range))
2729                                 val = comedi_offset_munge(s, val);
2730
2731                         ni_writew(dev, val, reg);
2732                 }
2733         }
2734
2735         return insn->n;
2736 }
2737
2738 /*
2739  * Arms the AO device in preparation for a trigger event.
2740  * This function also allocates and prepares a DMA channel (or FIFO if DMA is
2741  * not used).  As a part of this preparation, this function preloads the DAC
2742  * registers with the first values of the output stream.  This ensures that the
2743  * first clock cycle after the trigger can be used for output.
2744  *
2745  * Note that this function _must_ happen after a user has written data to the
2746  * output buffers via either mmap or write(fileno,...).
2747  */
2748 static int ni_ao_arm(struct comedi_device *dev,
2749                      struct comedi_subdevice *s)
2750 {
2751         struct ni_private *devpriv = dev->private;
2752         int ret;
2753         int interrupt_b_bits;
2754         int i;
2755         static const int timeout = 1000;
2756
2757         /*
2758          * Prevent ao from doing things like trying to allocate the ao dma
2759          * channel multiple times.
2760          */
2761         if (!devpriv->ao_needs_arming) {
2762                 dev_dbg(dev->class_dev, "%s: device does not need arming!\n",
2763                         __func__);
2764                 return -EINVAL;
2765         }
2766
2767         devpriv->ao_needs_arming = 0;
2768
2769         ni_set_bits(dev, NISTC_INTB_ENA_REG,
2770                     NISTC_INTB_ENA_AO_FIFO | NISTC_INTB_ENA_AO_ERR, 0);
2771         interrupt_b_bits = NISTC_INTB_ENA_AO_ERR;
2772 #ifdef PCIDMA
2773         ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
2774         if (devpriv->is_6xxx)
2775                 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
2776         ret = ni_ao_setup_MITE_dma(dev);
2777         if (ret)
2778                 return ret;
2779         ret = ni_ao_wait_for_dma_load(dev);
2780         if (ret < 0)
2781                 return ret;
2782 #else
2783         ret = ni_ao_prep_fifo(dev, s);
2784         if (ret == 0)
2785                 return -EPIPE;
2786
2787         interrupt_b_bits |= NISTC_INTB_ENA_AO_FIFO;
2788 #endif
2789
2790         ni_stc_writew(dev, devpriv->ao_mode3 | NISTC_AO_MODE3_NOT_AN_UPDATE,
2791                       NISTC_AO_MODE3_REG);
2792         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2793         /* wait for DACs to be loaded */
2794         for (i = 0; i < timeout; i++) {
2795                 udelay(1);
2796                 if ((ni_stc_readw(dev, NISTC_STATUS2_REG) &
2797                      NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS) == 0)
2798                         break;
2799         }
2800         if (i == timeout) {
2801                 dev_err(dev->class_dev,
2802                         "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n");
2803                 return -EIO;
2804         }
2805         /*
2806          * stc manual says we are need to clear error interrupt after
2807          * AO_TMRDACWRs_In_Progress_St clears
2808          */
2809         ni_stc_writew(dev, NISTC_INTB_ACK_AO_ERR, NISTC_INTB_ACK_REG);
2810
2811         ni_set_bits(dev, NISTC_INTB_ENA_REG, interrupt_b_bits, 1);
2812
2813         ni_stc_writew(dev, NISTC_AO_CMD1_UI_ARM |
2814                            NISTC_AO_CMD1_UC_ARM |
2815                            NISTC_AO_CMD1_BC_ARM |
2816                            devpriv->ao_cmd1,
2817                       NISTC_AO_CMD1_REG);
2818
2819         return 0;
2820 }
2821
2822 static int ni_ao_insn_config(struct comedi_device *dev,
2823                              struct comedi_subdevice *s,
2824                              struct comedi_insn *insn, unsigned int *data)
2825 {
2826         const struct ni_board_struct *board = dev->board_ptr;
2827         struct ni_private *devpriv = dev->private;
2828         unsigned int nbytes;
2829
2830         switch (data[0]) {
2831         case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2832                 switch (data[1]) {
2833                 case COMEDI_OUTPUT:
2834                         nbytes = comedi_samples_to_bytes(s,
2835                                                          board->ao_fifo_depth);
2836                         data[2] = 1 + nbytes;
2837                         if (devpriv->mite)
2838                                 data[2] += devpriv->mite->fifo_size;
2839                         break;
2840                 case COMEDI_INPUT:
2841                         data[2] = 0;
2842                         break;
2843                 default:
2844                         return -EINVAL;
2845                 }
2846                 return 0;
2847         case INSN_CONFIG_ARM:
2848                 return ni_ao_arm(dev, s);
2849         case INSN_CONFIG_GET_CMD_TIMING_CONSTRAINTS:
2850                 /* we don't care about actual channels */
2851                 /* data[3] : chanlist_len */
2852                 data[1] = board->ao_speed * data[3];
2853                 data[2] = 0;
2854                 return 0;
2855         default:
2856                 break;
2857         }
2858
2859         return -EINVAL;
2860 }
2861
2862 static int ni_ao_inttrig(struct comedi_device *dev,
2863                          struct comedi_subdevice *s,
2864                          unsigned int trig_num)
2865 {
2866         struct ni_private *devpriv = dev->private;
2867         struct comedi_cmd *cmd = &s->async->cmd;
2868         int ret;
2869
2870         /*
2871          * Require trig_num == cmd->start_arg when cmd->start_src == TRIG_INT.
2872          * For backwards compatibility, also allow trig_num == 0 when
2873          * cmd->start_src != TRIG_INT (i.e. when cmd->start_src == TRIG_EXT);
2874          * in that case, the internal trigger is being used as a pre-trigger
2875          * before the external trigger.
2876          */
2877         if (!(trig_num == cmd->start_arg ||
2878               (trig_num == 0 && cmd->start_src != TRIG_INT)))
2879                 return -EINVAL;
2880
2881         /*
2882          * Null trig at beginning prevent ao start trigger from executing more
2883          * than once per command.
2884          */
2885         s->async->inttrig = NULL;
2886
2887         if (devpriv->ao_needs_arming) {
2888                 /* only arm this device if it still needs arming */
2889                 ret = ni_ao_arm(dev, s);
2890                 if (ret)
2891                         return ret;
2892         }
2893
2894         ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2,
2895                       NISTC_AO_CMD2_REG);
2896
2897         return 0;
2898 }
2899
2900 /*
2901  * begin ni_ao_cmd.
2902  * Organized similar to NI-STC and MHDDK examples.
2903  * ni_ao_cmd is broken out into configuration sub-routines for clarity.
2904  */
2905
2906 static void ni_ao_cmd_personalize(struct comedi_device *dev,
2907                                   const struct comedi_cmd *cmd)
2908 {
2909         const struct ni_board_struct *board = dev->board_ptr;
2910         unsigned int bits;
2911
2912         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2913
2914         bits =
2915           /* fast CPU interface--only eseries */
2916           /* ((slow CPU interface) ? 0 : AO_Fast_CPU) | */
2917           NISTC_AO_PERSONAL_BC_SRC_SEL  |
2918           0 /* (use_original_pulse ? 0 : NISTC_AO_PERSONAL_UPDATE_TIMEBASE) */ |
2919           /*
2920            * FIXME:  start setting following bit when appropriate.  Need to
2921            * determine whether board is E4 or E1.
2922            * FROM MHHDK:
2923            * if board is E4 or E1
2924            *   Set bit "NISTC_AO_PERSONAL_UPDATE_PW" to 0
2925            * else
2926            *   set it to 1
2927            */
2928           NISTC_AO_PERSONAL_UPDATE_PW   |
2929           /* FIXME:  when should we set following bit to zero? */
2930           NISTC_AO_PERSONAL_TMRDACWR_PW |
2931           (board->ao_fifo_depth ?
2932             NISTC_AO_PERSONAL_FIFO_ENA : NISTC_AO_PERSONAL_DMA_PIO_CTRL)
2933           ;
2934 #if 0
2935         /*
2936          * FIXME:
2937          * add something like ".has_individual_dacs = 0" to ni_board_struct
2938          * since, as F Hess pointed out, not all in m series have singles.  not
2939          * sure if e-series all have duals...
2940          */
2941
2942         /*
2943          * F Hess: windows driver does not set NISTC_AO_PERSONAL_NUM_DAC bit for
2944          * 6281, verified with bus analyzer.
2945          */
2946         if (devpriv->is_m_series)
2947                 bits |= NISTC_AO_PERSONAL_NUM_DAC;
2948 #endif
2949         ni_stc_writew(dev, bits, NISTC_AO_PERSONAL_REG);
2950
2951         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
2952 }
2953
2954 static void ni_ao_cmd_set_trigger(struct comedi_device *dev,
2955                                   const struct comedi_cmd *cmd)
2956 {
2957         struct ni_private *devpriv = dev->private;
2958         unsigned int trigsel;
2959
2960         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2961
2962         /* sync */
2963         if (cmd->stop_src == TRIG_NONE) {
2964                 devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS;
2965                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE;
2966         } else {
2967                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS;
2968                 devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE;
2969         }
2970         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2971
2972         if (cmd->start_src == TRIG_INT) {
2973                 trigsel = NISTC_AO_TRIG_START1_EDGE |
2974                           NISTC_AO_TRIG_START1_SYNC;
2975         } else { /* TRIG_EXT */
2976                 trigsel = NISTC_AO_TRIG_START1_SEL(
2977                                 ni_get_reg_value_roffs(
2978                                                 CR_CHAN(cmd->start_arg),
2979                                                 NI_AO_StartTrigger,
2980                                                 &devpriv->routing_tables, 1));
2981
2982                 /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
2983                 if (cmd->start_arg & CR_INVERT)
2984                         trigsel |= NISTC_AO_TRIG_START1_POLARITY;
2985                 /* 0=edge detection disabled, 1=enabled */
2986                 if (cmd->start_arg & CR_EDGE)
2987                         trigsel |= NISTC_AO_TRIG_START1_EDGE;
2988         }
2989         ni_stc_writew(dev, trigsel, NISTC_AO_TRIG_SEL_REG);
2990
2991         /* AO_Delayed_START1 = 0, we do not support delayed start...yet */
2992
2993         /* sync */
2994         /* select DA_START1 as PFI6/AO_START1 when configured as an output */
2995         devpriv->ao_mode3 &= ~NISTC_AO_MODE3_TRIG_LEN;
2996         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2997
2998         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
2999 }
3000
3001 static void ni_ao_cmd_set_counters(struct comedi_device *dev,
3002                                    const struct comedi_cmd *cmd)
3003 {
3004         struct ni_private *devpriv = dev->private;
3005         /* Not supporting 'waveform staging' or 'local buffer with pauses' */
3006
3007         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3008         /*
3009          * This relies on ao_mode1/(Trigger_Once | Continuous) being set in
3010          * set_trigger above.  It is unclear whether we really need to re-write
3011          * this register with these values.  The mhddk examples for e-series
3012          * show writing this in both places, but the examples for m-series show
3013          * a single write in the set_counters function (here).
3014          */
3015         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3016
3017         /* sync (upload number of buffer iterations -1) */
3018         /* indicate that we want to use BC_Load_A_Register as the source */
3019         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC;
3020         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3021
3022         /*
3023          * if the BC_TC interrupt is still issued in spite of UC, BC, UI
3024          * ignoring BC_TC, then we will need to find a way to ignore that
3025          * interrupt in continuous mode.
3026          */
3027         ni_stc_writel(dev, 0, NISTC_AO_BC_LOADA_REG); /* iter once */
3028
3029         /* sync (issue command to load number of buffer iterations -1) */
3030         ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG);
3031
3032         /* sync (upload number of updates in buffer) */
3033         /* indicate that we want to use UC_Load_A_Register as the source */
3034         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC;
3035         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3036
3037         /*
3038          * if a user specifies '0', this automatically assumes the entire 24bit
3039          * address space is available for the (multiple iterations of single
3040          * buffer) MISB.  Otherwise, stop_arg specifies the MISB length that
3041          * will be used, regardless of whether we are in continuous mode or not.
3042          * In continuous mode, the output will just iterate indefinitely over
3043          * the MISB.
3044          */
3045         {
3046                 unsigned int stop_arg = cmd->stop_arg > 0 ?
3047                         (cmd->stop_arg & 0xffffff) : 0xffffff;
3048
3049                 if (devpriv->is_m_series) {
3050                         /*
3051                          * this is how the NI example code does it for m-series
3052                          * boards, verified correct with 6259
3053                          */
3054                         ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
3055
3056                         /* sync (issue cmd to load number of updates in MISB) */
3057                         ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3058                                       NISTC_AO_CMD1_REG);
3059                 } else {
3060                         ni_stc_writel(dev, stop_arg, NISTC_AO_UC_LOADA_REG);
3061
3062                         /* sync (issue cmd to load number of updates in MISB) */
3063                         ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3064                                       NISTC_AO_CMD1_REG);
3065
3066                         /*
3067                          * sync (upload number of updates-1 in MISB)
3068                          * --eseries only?
3069                          */
3070                         ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
3071                 }
3072         }
3073
3074         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3075 }
3076
3077 static void ni_ao_cmd_set_update(struct comedi_device *dev,
3078                                  const struct comedi_cmd *cmd)
3079 {
3080         struct ni_private *devpriv = dev->private;
3081
3082         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3083
3084         /*
3085          * zero out these bit fields to be set below. Does an ao-reset do this
3086          * automatically?
3087          */
3088         devpriv->ao_mode1 &=  ~(NISTC_AO_MODE1_UI_SRC_MASK         |
3089                                 NISTC_AO_MODE1_UI_SRC_POLARITY     |
3090                                 NISTC_AO_MODE1_UPDATE_SRC_MASK     |
3091                                 NISTC_AO_MODE1_UPDATE_SRC_POLARITY);
3092
3093         if (cmd->scan_begin_src == TRIG_TIMER) {
3094                 unsigned int trigvar;
3095
3096                 devpriv->ao_cmd2  &= ~NISTC_AO_CMD2_BC_GATE_ENA;
3097
3098                 /*
3099                  * NOTE: there are several other ways of configuring internal
3100                  * updates, but we'll only support one for now:  using
3101                  * AO_IN_TIMEBASE, w/o waveform staging, w/o a delay between
3102                  * START1 and first update, and also w/o local buffer mode w/
3103                  * pauses.
3104                  */
3105
3106                 /*
3107                  * This is already done above:
3108                  * devpriv->ao_mode1 &= ~(
3109                  *   // set UPDATE_Source to UI_TC:
3110                  *   NISTC_AO_MODE1_UPDATE_SRC_MASK |
3111                  *   // set UPDATE_Source_Polarity to rising (required?)
3112                  *   NISTC_AO_MODE1_UPDATE_SRC_POLARITY |
3113                  *   // set UI_Source to AO_IN_TIMEBASE1:
3114                  *   NISTC_AO_MODE1_UI_SRC_MASK     |
3115                  *   // set UI_Source_Polarity to rising (required?)
3116                  *   NISTC_AO_MODE1_UI_SRC_POLARITY
3117                  * );
3118                  */
3119
3120                 /*
3121                  * TODO:  use ao_ui_clock_source to allow all possible signals
3122                  * to be routed to UI_Source_Select.  See tSTC.h for
3123                  * eseries/ni67xx and tMSeries.h for mseries.
3124                  */
3125
3126                 trigvar = ni_ns_to_timer(dev, cmd->scan_begin_arg,
3127                                          CMDF_ROUND_NEAREST);
3128
3129                 /*
3130                  * Wait N TB3 ticks after the start trigger before
3131                  * clocking (N must be >=2).
3132                  */
3133                 /* following line: 2-1 per STC */
3134                 ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG);
3135                 ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, NISTC_AO_CMD1_REG);
3136                 ni_stc_writel(dev, trigvar, NISTC_AO_UI_LOADA_REG);
3137         } else { /* TRIG_EXT */
3138                 /* FIXME:  assert scan_begin_arg != 0, ret failure otherwise */
3139                 devpriv->ao_cmd2  |= NISTC_AO_CMD2_BC_GATE_ENA;
3140                 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC(
3141                                         ni_get_reg_value(
3142                                                 CR_CHAN(cmd->scan_begin_arg),
3143                                                 NI_AO_SampleClock,
3144                                                 &devpriv->routing_tables));
3145                 if (cmd->scan_begin_arg & CR_INVERT)
3146                         devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY;
3147         }
3148
3149         ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3150         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3151         devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) |
3152                                NISTC_AO_MODE2_UI_INIT_LOAD_SRC);
3153         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3154
3155         /* Configure DAQ-STC for Timed update mode */
3156         devpriv->ao_cmd1 |= NISTC_AO_CMD1_DAC1_UPDATE_MODE |
3157                             NISTC_AO_CMD1_DAC0_UPDATE_MODE;
3158         /* We are not using UPDATE2-->don't have to set DACx_Source_Select */
3159         ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG);
3160
3161         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3162 }
3163
3164 static void ni_ao_cmd_set_channels(struct comedi_device *dev,
3165                                    struct comedi_subdevice *s)
3166 {
3167         struct ni_private *devpriv = dev->private;
3168         const struct comedi_cmd *cmd = &s->async->cmd;
3169         unsigned int bits = 0;
3170
3171         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3172
3173         if (devpriv->is_6xxx) {
3174                 unsigned int i;
3175
3176                 bits = 0;
3177                 for (i = 0; i < cmd->chanlist_len; ++i) {
3178                         int chan = CR_CHAN(cmd->chanlist[i]);
3179
3180                         bits |= 1 << chan;
3181                         ni_ao_win_outw(dev, chan, NI611X_AO_WAVEFORM_GEN_REG);
3182                 }
3183                 ni_ao_win_outw(dev, bits, NI611X_AO_TIMED_REG);
3184         }
3185
3186         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3187
3188         if (cmd->scan_end_arg > 1) {
3189                 devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN;
3190                 bits = NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1)
3191                                  | NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3192
3193         } else {
3194                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN;
3195                 bits = NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3196                 if (devpriv->is_m_series | devpriv->is_6xxx)
3197                         bits |= NISTC_AO_OUT_CTRL_CHANS(0);
3198                 else
3199                         bits |= NISTC_AO_OUT_CTRL_CHANS(
3200                                         CR_CHAN(cmd->chanlist[0]));
3201         }
3202
3203         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3204         ni_stc_writew(dev, bits,              NISTC_AO_OUT_CTRL_REG);
3205
3206         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3207 }
3208
3209 static void ni_ao_cmd_set_stop_conditions(struct comedi_device *dev,
3210                                           const struct comedi_cmd *cmd)
3211 {
3212         struct ni_private *devpriv = dev->private;
3213
3214         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3215
3216         devpriv->ao_mode3 |= NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR;
3217         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3218
3219         /*
3220          * Since we are not supporting waveform staging, we ignore these errors:
3221          * NISTC_AO_MODE3_STOP_ON_BC_TC_ERR,
3222          * NISTC_AO_MODE3_STOP_ON_BC_TC_TRIG_ERR
3223          */
3224
3225         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3226 }
3227
3228 static void ni_ao_cmd_set_fifo_mode(struct comedi_device *dev)
3229 {
3230         struct ni_private *devpriv = dev->private;
3231
3232         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3233
3234         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK;
3235 #ifdef PCIDMA
3236         devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F;
3237 #else
3238         devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF;
3239 #endif
3240         /* NOTE:  this is where use_onboard_memory=True would be implemented */
3241         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA;
3242         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3243
3244         /* enable sending of ao fifo requests (dma request) */
3245         ni_stc_writew(dev, NISTC_AO_START_AOFREQ_ENA, NISTC_AO_START_SEL_REG);
3246
3247         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3248
3249         /* we are not supporting boards with virtual fifos */
3250 }
3251
3252 static void ni_ao_cmd_set_interrupts(struct comedi_device *dev,
3253                                      struct comedi_subdevice *s)
3254 {
3255         if (s->async->cmd.stop_src == TRIG_COUNT)
3256                 ni_set_bits(dev, NISTC_INTB_ENA_REG,
3257                             NISTC_INTB_ENA_AO_BC_TC, 1);
3258
3259         s->async->inttrig = ni_ao_inttrig;
3260 }
3261
3262 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3263 {
3264         struct ni_private *devpriv = dev->private;
3265         const struct comedi_cmd *cmd = &s->async->cmd;
3266
3267         if (dev->irq == 0) {
3268                 dev_err(dev->class_dev, "cannot run command without an irq");
3269                 return -EIO;
3270         }
3271
3272         /* ni_ao_reset should have already been done */
3273         ni_ao_cmd_personalize(dev, cmd);
3274         /* clearing fifo and preload happens elsewhere */
3275
3276         ni_ao_cmd_set_trigger(dev, cmd);
3277         ni_ao_cmd_set_counters(dev, cmd);
3278         ni_ao_cmd_set_update(dev, cmd);
3279         ni_ao_cmd_set_channels(dev, s);
3280         ni_ao_cmd_set_stop_conditions(dev, cmd);
3281         ni_ao_cmd_set_fifo_mode(dev);
3282         ni_cmd_set_mite_transfer(devpriv->ao_mite_ring, s, cmd, 0x00ffffff);
3283         ni_ao_cmd_set_interrupts(dev, s);
3284
3285         /*
3286          * arm(ing) must happen later so that DMA can be setup and DACs
3287          * preloaded with the actual output buffer before starting.
3288          *
3289          * start(ing) must happen _after_ arming is completed.  Starting can be
3290          * done either via ni_ao_inttrig, or via an external trigger.
3291          *
3292          * **Currently, ni_ao_inttrig will automatically attempt a call to
3293          * ni_ao_arm if the device still needs arming at that point.  This
3294          * allows backwards compatibility.
3295          */
3296         devpriv->ao_needs_arming = 1;
3297         return 0;
3298 }
3299
3300 /* end ni_ao_cmd */
3301
3302 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3303                          struct comedi_cmd *cmd)
3304 {
3305         const struct ni_board_struct *board = dev->board_ptr;
3306         struct ni_private *devpriv = dev->private;
3307         int err = 0;
3308         unsigned int tmp;
3309
3310         /* Step 1 : check if triggers are trivially valid */
3311
3312         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3313         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3314                                         TRIG_TIMER | TRIG_EXT);
3315         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3316         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3317         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3318
3319         if (err)
3320                 return 1;
3321
3322         /* Step 2a : make sure trigger sources are unique */
3323
3324         err |= comedi_check_trigger_is_unique(cmd->start_src);
3325         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3326         err |= comedi_check_trigger_is_unique(cmd->stop_src);
3327
3328         /* Step 2b : and mutually compatible */
3329
3330         if (err)
3331                 return 2;
3332
3333         /* Step 3: check if arguments are trivially valid */
3334
3335         switch (cmd->start_src) {
3336         case TRIG_INT:
3337                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3338                 break;
3339         case TRIG_EXT:
3340                 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->start_arg),
3341                                                   NI_AO_StartTrigger,
3342                                                   &devpriv->routing_tables, 1);
3343                 break;
3344         }
3345
3346         if (cmd->scan_begin_src == TRIG_TIMER) {
3347                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3348                                                     board->ao_speed);
3349                 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
3350                                                     devpriv->clock_ns *
3351                                                     0xffffff);
3352         } else {                /* TRIG_EXT */
3353                 err |= ni_check_trigger_arg(CR_CHAN(cmd->scan_begin_arg),
3354                                             NI_AO_SampleClock,
3355                                             &devpriv->routing_tables);
3356         }
3357
3358         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3359         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3360                                            cmd->chanlist_len);
3361         err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3362
3363         if (err)
3364                 return 3;
3365
3366         /* step 4: fix up any arguments */
3367         if (cmd->scan_begin_src == TRIG_TIMER) {
3368                 tmp = cmd->scan_begin_arg;
3369                 cmd->scan_begin_arg =
3370                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3371                                                        cmd->scan_begin_arg,
3372                                                        cmd->flags));
3373                 if (tmp != cmd->scan_begin_arg)
3374                         err++;
3375         }
3376         if (err)
3377                 return 4;
3378
3379         return 0;
3380 }
3381
3382 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3383 {
3384         /* See 3.6.1.2 "Resetting", of DAQ-STC Technical Reference Manual */
3385
3386         /*
3387          * In the following, the "--sync" comments are meant to denote
3388          * asynchronous boundaries for setting the registers as described in the
3389          * DAQ-STC mostly in the order also described in the DAQ-STC.
3390          */
3391
3392         struct ni_private *devpriv = dev->private;
3393
3394         ni_release_ao_mite_channel(dev);
3395
3396         /* --sync (reset AO) */
3397         if (devpriv->is_m_series)
3398                 /* following example in mhddk for m-series */
3399                 ni_stc_writew(dev, NISTC_RESET_AO, NISTC_RESET_REG);
3400
3401         /*--sync (start config) */
3402         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3403
3404         /*--sync (Disarm) */
3405         ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
3406
3407         /*
3408          * --sync
3409          * (clear bunch of registers--mseries mhddk examples do not include
3410          * this)
3411          */
3412         devpriv->ao_cmd1  = 0;
3413         devpriv->ao_cmd2  = 0;
3414         devpriv->ao_mode1 = 0;
3415         devpriv->ao_mode2 = 0;
3416         if (devpriv->is_m_series)
3417                 devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE;
3418         else
3419                 devpriv->ao_mode3 = 0;
3420
3421         ni_stc_writew(dev, 0, NISTC_AO_PERSONAL_REG);
3422         ni_stc_writew(dev, 0, NISTC_AO_CMD1_REG);
3423         ni_stc_writew(dev, 0, NISTC_AO_CMD2_REG);
3424         ni_stc_writew(dev, 0, NISTC_AO_MODE1_REG);
3425         ni_stc_writew(dev, 0, NISTC_AO_MODE2_REG);
3426         ni_stc_writew(dev, 0, NISTC_AO_OUT_CTRL_REG);
3427         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3428         ni_stc_writew(dev, 0, NISTC_AO_START_SEL_REG);
3429         ni_stc_writew(dev, 0, NISTC_AO_TRIG_SEL_REG);
3430
3431         /*--sync (disable interrupts) */
3432         ni_set_bits(dev, NISTC_INTB_ENA_REG, ~0, 0);
3433
3434         /*--sync (ack) */
3435         ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL, NISTC_AO_PERSONAL_REG);
3436         ni_stc_writew(dev, NISTC_INTB_ACK_AO_ALL, NISTC_INTB_ACK_REG);
3437
3438         /*--not in DAQ-STC.  which doc? */
3439         if (devpriv->is_6xxx) {
3440                 ni_ao_win_outw(dev, (1u << s->n_chan) - 1u,
3441                                NI671X_AO_IMMEDIATE_REG);
3442                 ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG,
3443                                NI611X_AO_MISC_REG);
3444         }
3445         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3446         /*--end */
3447
3448         return 0;
3449 }
3450
3451 /* digital io */
3452
3453 static int ni_dio_insn_config(struct comedi_device *dev,
3454                               struct comedi_subdevice *s,
3455                               struct comedi_insn *insn,
3456                               unsigned int *data)
3457 {
3458         struct ni_private *devpriv = dev->private;
3459         int ret;
3460
3461         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3462         if (ret)
3463                 return ret;
3464
3465         devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK;
3466         devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits);
3467         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3468
3469         return insn->n;
3470 }
3471
3472 static int ni_dio_insn_bits(struct comedi_device *dev,
3473                             struct comedi_subdevice *s,
3474                             struct comedi_insn *insn,
3475                             unsigned int *data)
3476 {
3477         struct ni_private *devpriv = dev->private;
3478
3479         /* Make sure we're not using the serial part of the dio */
3480         if ((data[0] & (NISTC_DIO_SDIN | NISTC_DIO_SDOUT)) &&
3481             devpriv->serial_interval_ns)
3482                 return -EBUSY;
3483
3484         if (comedi_dio_update_state(s, data)) {
3485                 devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK;
3486                 devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state);
3487                 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3488         }
3489
3490         data[1] = ni_stc_readw(dev, NISTC_DIO_IN_REG);
3491
3492         return insn->n;
3493 }
3494
3495 #ifdef PCIDMA
3496 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3497                                        struct comedi_subdevice *s,
3498                                        struct comedi_insn *insn,
3499                                        unsigned int *data)
3500 {
3501         int ret;
3502
3503         if (data[0] == INSN_CONFIG_GET_CMD_TIMING_CONSTRAINTS) {
3504                 const struct ni_board_struct *board = dev->board_ptr;
3505
3506                 /* we don't care about actual channels */
3507                 data[1] = board->dio_speed;
3508                 data[2] = 0;
3509                 return 0;
3510         }
3511
3512         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3513         if (ret)
3514                 return ret;
3515
3516         ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
3517
3518         return insn->n;
3519 }
3520
3521 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3522                                      struct comedi_subdevice *s,
3523                                      struct comedi_insn *insn,
3524                                      unsigned int *data)
3525 {
3526         if (comedi_dio_update_state(s, data))
3527                 ni_writel(dev, s->state, NI_M_DIO_REG);
3528
3529         data[1] = ni_readl(dev, NI_M_DIO_REG);
3530
3531         return insn->n;
3532 }
3533
3534 static int ni_cdio_check_chanlist(struct comedi_device *dev,
3535                                   struct comedi_subdevice *s,
3536                                   struct comedi_cmd *cmd)
3537 {
3538         int i;
3539
3540         for (i = 0; i < cmd->chanlist_len; ++i) {
3541                 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3542
3543                 if (chan != i)
3544                         return -EINVAL;
3545         }
3546
3547         return 0;
3548 }
3549
3550 static int ni_cdio_cmdtest(struct comedi_device *dev,
3551                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
3552 {
3553         struct ni_private *devpriv = dev->private;
3554         unsigned int bytes_per_scan;
3555         int err = 0;
3556
3557         /* Step 1 : check if triggers are trivially valid */
3558
3559         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT);
3560         err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3561         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3562         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3563         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3564
3565         if (err)
3566                 return 1;
3567
3568         /* Step 2a : make sure trigger sources are unique */
3569         /* Step 2b : and mutually compatible */
3570
3571         /* Step 3: check if arguments are trivially valid */
3572
3573         err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3574
3575         /*
3576          * Although NI_D[IO]_SampleClock are the same, perhaps we should still,
3577          * for completeness, test whether the cmd is output or input?
3578          */
3579         err |= ni_check_trigger_arg(CR_CHAN(cmd->scan_begin_arg),
3580                                     NI_DO_SampleClock,
3581                                     &devpriv->routing_tables);
3582         if (CR_RANGE(cmd->scan_begin_arg) != 0 ||
3583             CR_AREF(cmd->scan_begin_arg) != 0)
3584                 err |= -EINVAL;
3585
3586         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3587         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3588                                            cmd->chanlist_len);
3589         bytes_per_scan = comedi_bytes_per_scan_cmd(s, cmd);
3590         if (bytes_per_scan) {
3591                 err |= comedi_check_trigger_arg_max(&cmd->stop_arg,
3592                                                     s->async->prealloc_bufsz /
3593                                                     bytes_per_scan);
3594         }
3595
3596         if (err)
3597                 return 3;
3598
3599         /* Step 4: fix up any arguments */
3600
3601         /* Step 5: check channel list if it exists */
3602
3603         if (cmd->chanlist && cmd->chanlist_len > 0)
3604                 err |= ni_cdio_check_chanlist(dev, s, cmd);
3605
3606         if (err)
3607                 return 5;
3608
3609         return 0;
3610 }
3611
3612 static int ni_cdo_inttrig(struct comedi_device *dev,
3613                           struct comedi_subdevice *s,
3614                           unsigned int trig_num)
3615 {
3616         struct comedi_cmd *cmd = &s->async->cmd;
3617         const unsigned int timeout = 1000;
3618         int retval = 0;
3619         unsigned int i;
3620         struct ni_private *devpriv = dev->private;
3621         unsigned long flags;
3622
3623         if (trig_num != cmd->start_arg)
3624                 return -EINVAL;
3625
3626         s->async->inttrig = NULL;
3627
3628         /* read alloc the entire buffer */
3629         comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
3630
3631         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3632         if (devpriv->cdo_mite_chan) {
3633                 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3634                 mite_dma_arm(devpriv->cdo_mite_chan);
3635         } else {
3636                 dev_err(dev->class_dev, "BUG: no cdo mite channel?\n");
3637                 retval = -EIO;
3638         }
3639         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3640         if (retval < 0)
3641                 return retval;
3642
3643         /*
3644          * XXX not sure what interrupt C group does
3645          * wait for dma to fill output fifo
3646          * ni_writeb(dev, NI_M_INTC_ENA, NI_M_INTC_ENA_REG);
3647          */
3648         for (i = 0; i < timeout; ++i) {
3649                 if (ni_readl(dev, NI_M_CDIO_STATUS_REG) &
3650                     NI_M_CDIO_STATUS_CDO_FIFO_FULL)
3651                         break;
3652                 usleep_range(10, 100);
3653         }
3654         if (i == timeout) {
3655                 dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n");
3656                 s->cancel(dev, s);
3657                 return -EIO;
3658         }
3659         ni_writel(dev, NI_M_CDO_CMD_ARM |
3660                        NI_M_CDO_CMD_ERR_INT_ENA_SET |
3661                        NI_M_CDO_CMD_F_E_INT_ENA_SET,
3662                   NI_M_CDIO_CMD_REG);
3663         return retval;
3664 }
3665
3666 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3667 {
3668         struct ni_private *devpriv = dev->private;
3669         const struct comedi_cmd *cmd = &s->async->cmd;
3670         unsigned int cdo_mode_bits;
3671         int retval;
3672
3673         ni_writel(dev, NI_M_CDO_CMD_RESET, NI_M_CDIO_CMD_REG);
3674         /*
3675          * Although NI_D[IO]_SampleClock are the same, perhaps we should still,
3676          * for completeness, test whether the cmd is output or input(?)
3677          */
3678         cdo_mode_bits = NI_M_CDO_MODE_FIFO_MODE |
3679                         NI_M_CDO_MODE_HALT_ON_ERROR |
3680                         NI_M_CDO_MODE_SAMPLE_SRC(
3681                                 ni_get_reg_value(
3682                                         CR_CHAN(cmd->scan_begin_arg),
3683                                         NI_DO_SampleClock,
3684                                         &devpriv->routing_tables));
3685         if (cmd->scan_begin_arg & CR_INVERT)
3686                 cdo_mode_bits |= NI_M_CDO_MODE_POLARITY;
3687         ni_writel(dev, cdo_mode_bits, NI_M_CDO_MODE_REG);
3688         if (s->io_bits) {
3689                 ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG);
3690                 ni_writel(dev, NI_M_CDO_CMD_SW_UPDATE, NI_M_CDIO_CMD_REG);
3691                 ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG);
3692         } else {
3693                 dev_err(dev->class_dev,
3694                         "attempted to run digital output command with no lines configured as outputs\n");
3695                 return -EIO;
3696         }
3697         retval = ni_request_cdo_mite_channel(dev);
3698         if (retval < 0)
3699                 return retval;
3700
3701         ni_cmd_set_mite_transfer(devpriv->cdo_mite_ring, s, cmd,
3702                                  s->async->prealloc_bufsz /
3703                                  comedi_bytes_per_scan(s));
3704
3705         s->async->inttrig = ni_cdo_inttrig;
3706
3707         return 0;
3708 }
3709
3710 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3711 {
3712         ni_writel(dev, NI_M_CDO_CMD_DISARM |
3713                        NI_M_CDO_CMD_ERR_INT_ENA_CLR |
3714                        NI_M_CDO_CMD_F_E_INT_ENA_CLR |
3715                        NI_M_CDO_CMD_F_REQ_INT_ENA_CLR,
3716                   NI_M_CDIO_CMD_REG);
3717         /*
3718          * XXX not sure what interrupt C group does
3719          * ni_writeb(dev, 0, NI_M_INTC_ENA_REG);
3720          */
3721         ni_writel(dev, 0, NI_M_CDO_MASK_ENA_REG);
3722         ni_release_cdo_mite_channel(dev);
3723         return 0;
3724 }
3725
3726 static void handle_cdio_interrupt(struct comedi_device *dev)
3727 {
3728         struct ni_private *devpriv = dev->private;
3729         unsigned int cdio_status;
3730         struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3731         unsigned long flags;
3732
3733         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3734         if (devpriv->cdo_mite_chan)
3735                 mite_ack_linkc(devpriv->cdo_mite_chan, s, true);
3736         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3737
3738         cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG);
3739         if (cdio_status & NI_M_CDIO_STATUS_CDO_ERROR) {
3740                 /* XXX just guessing this is needed and does something useful */
3741                 ni_writel(dev, NI_M_CDO_CMD_ERR_INT_CONFIRM,
3742                           NI_M_CDIO_CMD_REG);
3743                 s->async->events |= COMEDI_CB_OVERFLOW;
3744         }
3745         if (cdio_status & NI_M_CDIO_STATUS_CDO_FIFO_EMPTY) {
3746                 ni_writel(dev, NI_M_CDO_CMD_F_E_INT_ENA_CLR,
3747                           NI_M_CDIO_CMD_REG);
3748                 /* s->async->events |= COMEDI_CB_EOA; */
3749         }
3750         comedi_handle_events(dev, s);
3751 }
3752 #endif /*  PCIDMA */
3753
3754 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3755                                    struct comedi_subdevice *s,
3756                                    unsigned char data_out,
3757                                    unsigned char *data_in)
3758 {
3759         struct ni_private *devpriv = dev->private;
3760         unsigned int status1;
3761         int err = 0, count = 20;
3762
3763         devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK;
3764         devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out);
3765         ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3766
3767         status1 = ni_stc_readw(dev, NISTC_STATUS1_REG);
3768         if (status1 & NISTC_STATUS1_SERIO_IN_PROG) {
3769                 err = -EBUSY;
3770                 goto error;
3771         }
3772
3773         devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START;
3774         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3775         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START;
3776
3777         /* Wait until STC says we're done, but don't loop infinitely. */
3778         while ((status1 = ni_stc_readw(dev, NISTC_STATUS1_REG)) &
3779                NISTC_STATUS1_SERIO_IN_PROG) {
3780                 /* Delay one bit per loop */
3781                 udelay((devpriv->serial_interval_ns + 999) / 1000);
3782                 if (--count < 0) {
3783                         dev_err(dev->class_dev,
3784                                 "SPI serial I/O didn't finish in time!\n");
3785                         err = -ETIME;
3786                         goto error;
3787                 }
3788         }
3789
3790         /*
3791          * Delay for last bit. This delay is absolutely necessary, because
3792          * NISTC_STATUS1_SERIO_IN_PROG goes high one bit too early.
3793          */
3794         udelay((devpriv->serial_interval_ns + 999) / 1000);
3795
3796         if (data_in)
3797                 *data_in = ni_stc_readw(dev, NISTC_DIO_SERIAL_IN_REG);
3798
3799 error:
3800         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3801
3802         return err;
3803 }
3804
3805 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3806                                    struct comedi_subdevice *s,
3807                                    unsigned char data_out,
3808                                    unsigned char *data_in)
3809 {
3810         struct ni_private *devpriv = dev->private;
3811         unsigned char mask, input = 0;
3812
3813         /* Wait for one bit before transfer */
3814         udelay((devpriv->serial_interval_ns + 999) / 1000);
3815
3816         for (mask = 0x80; mask; mask >>= 1) {
3817                 /*
3818                  * Output current bit; note that we cannot touch s->state
3819                  * because it is a per-subdevice field, and serial is
3820                  * a separate subdevice from DIO.
3821                  */
3822                 devpriv->dio_output &= ~NISTC_DIO_SDOUT;
3823                 if (data_out & mask)
3824                         devpriv->dio_output |= NISTC_DIO_SDOUT;
3825                 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3826
3827                 /*
3828                  * Assert SDCLK (active low, inverted), wait for half of
3829                  * the delay, deassert SDCLK, and wait for the other half.
3830                  */
3831                 devpriv->dio_control |= NISTC_DIO_SDCLK;
3832                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3833
3834                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3835
3836                 devpriv->dio_control &= ~NISTC_DIO_SDCLK;
3837                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3838
3839                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3840
3841                 /* Input current bit */
3842                 if (ni_stc_readw(dev, NISTC_DIO_IN_REG) & NISTC_DIO_SDIN)
3843                         input |= mask;
3844         }
3845
3846         if (data_in)
3847                 *data_in = input;
3848
3849         return 0;
3850 }
3851
3852 static int ni_serial_insn_config(struct comedi_device *dev,
3853                                  struct comedi_subdevice *s,
3854                                  struct comedi_insn *insn,
3855                                  unsigned int *data)
3856 {
3857         struct ni_private *devpriv = dev->private;
3858         unsigned int clk_fout = devpriv->clock_and_fout;
3859         int err = insn->n;
3860         unsigned char byte_out, byte_in = 0;
3861
3862         if (insn->n != 2)
3863                 return -EINVAL;
3864
3865         switch (data[0]) {
3866         case INSN_CONFIG_SERIAL_CLOCK:
3867                 devpriv->serial_hw_mode = 1;
3868                 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA;
3869
3870                 if (data[1] == SERIAL_DISABLED) {
3871                         devpriv->serial_hw_mode = 0;
3872                         devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3873                                                   NISTC_DIO_SDCLK);
3874                         data[1] = SERIAL_DISABLED;
3875                         devpriv->serial_interval_ns = data[1];
3876                 } else if (data[1] <= SERIAL_600NS) {
3877                         /*
3878                          * Warning: this clock speed is too fast to reliably
3879                          * control SCXI.
3880                          */
3881                         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3882                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE;
3883                         clk_fout &= ~NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3884                         data[1] = SERIAL_600NS;
3885                         devpriv->serial_interval_ns = data[1];
3886                 } else if (data[1] <= SERIAL_1_2US) {
3887                         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3888                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3889                                     NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3890                         data[1] = SERIAL_1_2US;
3891                         devpriv->serial_interval_ns = data[1];
3892                 } else if (data[1] <= SERIAL_10US) {
3893                         devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3894                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3895                                     NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3896                         /*
3897                          * Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects
3898                          * 600ns/1.2us. If you turn divide_by_2 off with the
3899                          * slow clock, you will still get 10us, except then
3900                          * all your delays are wrong.
3901                          */
3902                         data[1] = SERIAL_10US;
3903                         devpriv->serial_interval_ns = data[1];
3904                 } else {
3905                         devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3906                                                   NISTC_DIO_SDCLK);
3907                         devpriv->serial_hw_mode = 0;
3908                         data[1] = (data[1] / 1000) * 1000;
3909                         devpriv->serial_interval_ns = data[1];
3910                 }
3911                 devpriv->clock_and_fout = clk_fout;
3912
3913                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3914                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3915                 return 1;
3916
3917         case INSN_CONFIG_BIDIRECTIONAL_DATA:
3918
3919                 if (devpriv->serial_interval_ns == 0)
3920                         return -EINVAL;
3921
3922                 byte_out = data[1] & 0xFF;
3923
3924                 if (devpriv->serial_hw_mode) {
3925                         err = ni_serial_hw_readwrite8(dev, s, byte_out,
3926                                                       &byte_in);
3927                 } else if (devpriv->serial_interval_ns > 0) {
3928                         err = ni_serial_sw_readwrite8(dev, s, byte_out,
3929                                                       &byte_in);
3930                 } else {
3931                         dev_err(dev->class_dev, "serial disabled!\n");
3932                         return -EINVAL;
3933                 }
3934                 if (err < 0)
3935                         return err;
3936                 data[1] = byte_in & 0xFF;
3937                 return insn->n;
3938
3939                 break;
3940         default:
3941                 return -EINVAL;
3942         }
3943 }
3944
3945 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3946 {
3947         int i;
3948
3949         for (i = 0; i < s->n_chan; i++) {
3950                 ni_ao_win_outw(dev, NI_E_AO_DACSEL(i) | 0x0,
3951                                NI67XX_AO_CFG2_REG);
3952         }
3953         ni_ao_win_outw(dev, 0x0, NI67XX_AO_SP_UPDATES_REG);
3954 }
3955
3956 static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
3957         [NITIO_G0_AUTO_INC]     = { NISTC_G0_AUTOINC_REG, 2 },
3958         [NITIO_G1_AUTO_INC]     = { NISTC_G1_AUTOINC_REG, 2 },
3959         [NITIO_G0_CMD]          = { NISTC_G0_CMD_REG, 2 },
3960         [NITIO_G1_CMD]          = { NISTC_G1_CMD_REG, 2 },
3961         [NITIO_G0_HW_SAVE]      = { NISTC_G0_HW_SAVE_REG, 4 },
3962         [NITIO_G1_HW_SAVE]      = { NISTC_G1_HW_SAVE_REG, 4 },
3963         [NITIO_G0_SW_SAVE]      = { NISTC_G0_SAVE_REG, 4 },
3964         [NITIO_G1_SW_SAVE]      = { NISTC_G1_SAVE_REG, 4 },
3965         [NITIO_G0_MODE]         = { NISTC_G0_MODE_REG, 2 },
3966         [NITIO_G1_MODE]         = { NISTC_G1_MODE_REG, 2 },
3967         [NITIO_G0_LOADA]        = { NISTC_G0_LOADA_REG, 4 },
3968         [NITIO_G1_LOADA]        = { NISTC_G1_LOADA_REG, 4 },
3969         [NITIO_G0_LOADB]        = { NISTC_G0_LOADB_REG, 4 },
3970         [NITIO_G1_LOADB]        = { NISTC_G1_LOADB_REG, 4 },
3971         [NITIO_G0_INPUT_SEL]    = { NISTC_G0_INPUT_SEL_REG, 2 },
3972         [NITIO_G1_INPUT_SEL]    = { NISTC_G1_INPUT_SEL_REG, 2 },
3973         [NITIO_G0_CNT_MODE]     = { 0x1b0, 2 }, /* M-Series only */
3974         [NITIO_G1_CNT_MODE]     = { 0x1b2, 2 }, /* M-Series only */
3975         [NITIO_G0_GATE2]        = { 0x1b4, 2 }, /* M-Series only */
3976         [NITIO_G1_GATE2]        = { 0x1b6, 2 }, /* M-Series only */
3977         [NITIO_G01_STATUS]      = { NISTC_G01_STATUS_REG, 2 },
3978         [NITIO_G01_RESET]       = { NISTC_RESET_REG, 2 },
3979         [NITIO_G01_STATUS1]     = { NISTC_STATUS1_REG, 2 },
3980         [NITIO_G01_STATUS2]     = { NISTC_STATUS2_REG, 2 },
3981         [NITIO_G0_DMA_CFG]      = { 0x1b8, 2 }, /* M-Series only */
3982         [NITIO_G1_DMA_CFG]      = { 0x1ba, 2 }, /* M-Series only */
3983         [NITIO_G0_DMA_STATUS]   = { 0x1b8, 2 }, /* M-Series only */
3984         [NITIO_G1_DMA_STATUS]   = { 0x1ba, 2 }, /* M-Series only */
3985         [NITIO_G0_ABZ]          = { 0x1c0, 2 }, /* M-Series only */
3986         [NITIO_G1_ABZ]          = { 0x1c2, 2 }, /* M-Series only */
3987         [NITIO_G0_INT_ACK]      = { NISTC_INTA_ACK_REG, 2 },
3988         [NITIO_G1_INT_ACK]      = { NISTC_INTB_ACK_REG, 2 },
3989         [NITIO_G0_STATUS]       = { NISTC_AI_STATUS1_REG, 2 },
3990         [NITIO_G1_STATUS]       = { NISTC_AO_STATUS1_REG, 2 },
3991         [NITIO_G0_INT_ENA]      = { NISTC_INTA_ENA_REG, 2 },
3992         [NITIO_G1_INT_ENA]      = { NISTC_INTB_ENA_REG, 2 },
3993 };
3994
3995 static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev,
3996                                             enum ni_gpct_register reg)
3997 {
3998         const struct mio_regmap *regmap;
3999
4000         if (reg < ARRAY_SIZE(ni_gpct_to_stc_regmap)) {
4001                 regmap = &ni_gpct_to_stc_regmap[reg];
4002         } else {
4003                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
4004                          __func__, reg);
4005                 return 0;
4006         }
4007
4008         return regmap->mio_reg;
4009 }
4010
4011 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned int bits,
4012                                    enum ni_gpct_register reg)
4013 {
4014         struct comedi_device *dev = counter->counter_dev->dev;
4015         unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
4016
4017         if (stc_register == 0)
4018                 return;
4019
4020         switch (reg) {
4021                 /* m-series only registers */
4022         case NITIO_G0_CNT_MODE:
4023         case NITIO_G1_CNT_MODE:
4024         case NITIO_G0_GATE2:
4025         case NITIO_G1_GATE2:
4026         case NITIO_G0_DMA_CFG:
4027         case NITIO_G1_DMA_CFG:
4028         case NITIO_G0_ABZ:
4029         case NITIO_G1_ABZ:
4030                 ni_writew(dev, bits, stc_register);
4031                 break;
4032
4033                 /* 32 bit registers */
4034         case NITIO_G0_LOADA:
4035         case NITIO_G1_LOADA:
4036         case NITIO_G0_LOADB:
4037         case NITIO_G1_LOADB:
4038                 ni_stc_writel(dev, bits, stc_register);
4039                 break;
4040
4041                 /* 16 bit registers */
4042         case NITIO_G0_INT_ENA:
4043                 ni_set_bitfield(dev, stc_register,
4044                                 NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC,
4045                                 bits);
4046                 break;
4047         case NITIO_G1_INT_ENA:
4048                 ni_set_bitfield(dev, stc_register,
4049                                 NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC,
4050                                 bits);
4051                 break;
4052         default:
4053                 ni_stc_writew(dev, bits, stc_register);
4054         }
4055 }
4056
4057 static unsigned int ni_gpct_read_register(struct ni_gpct *counter,
4058                                           enum ni_gpct_register reg)
4059 {
4060         struct comedi_device *dev = counter->counter_dev->dev;
4061         unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
4062
4063         if (stc_register == 0)
4064                 return 0;
4065
4066         switch (reg) {
4067                 /* m-series only registers */
4068         case NITIO_G0_DMA_STATUS:
4069         case NITIO_G1_DMA_STATUS:
4070                 return ni_readw(dev, stc_register);
4071
4072                 /* 32 bit registers */
4073         case NITIO_G0_HW_SAVE:
4074         case NITIO_G1_HW_SAVE:
4075         case NITIO_G0_SW_SAVE:
4076         case NITIO_G1_SW_SAVE:
4077                 return ni_stc_readl(dev, stc_register);
4078
4079                 /* 16 bit registers */
4080         default:
4081                 return ni_stc_readw(dev, stc_register);
4082         }
4083 }
4084
4085 static int ni_freq_out_insn_read(struct comedi_device *dev,
4086                                  struct comedi_subdevice *s,
4087                                  struct comedi_insn *insn,
4088                                  unsigned int *data)
4089 {
4090         struct ni_private *devpriv = dev->private;
4091         unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout);
4092         int i;
4093
4094         for (i = 0; i < insn->n; i++)
4095                 data[i] = val;
4096
4097         return insn->n;
4098 }
4099
4100 static int ni_freq_out_insn_write(struct comedi_device *dev,
4101                                   struct comedi_subdevice *s,
4102                                   struct comedi_insn *insn,
4103                                   unsigned int *data)
4104 {
4105         struct ni_private *devpriv = dev->private;
4106
4107         if (insn->n) {
4108                 unsigned int val = data[insn->n - 1];
4109
4110                 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_ENA;
4111                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4112                 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_DIVIDER_MASK;
4113
4114                 /* use the last data value to set the fout divider */
4115                 devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val);
4116
4117                 devpriv->clock_and_fout |= NISTC_CLK_FOUT_ENA;
4118                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4119         }
4120         return insn->n;
4121 }
4122
4123 static int ni_freq_out_insn_config(struct comedi_device *dev,
4124                                    struct comedi_subdevice *s,
4125                                    struct comedi_insn *insn,
4126                                    unsigned int *data)
4127 {
4128         struct ni_private *devpriv = dev->private;
4129
4130         switch (data[0]) {
4131         case INSN_CONFIG_SET_CLOCK_SRC:
4132                 switch (data[1]) {
4133                 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4134                         devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_TIMEBASE_SEL;
4135                         break;
4136                 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4137                         devpriv->clock_and_fout |= NISTC_CLK_FOUT_TIMEBASE_SEL;
4138                         break;
4139                 default:
4140                         return -EINVAL;
4141                 }
4142                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4143                 break;
4144         case INSN_CONFIG_GET_CLOCK_SRC:
4145                 if (devpriv->clock_and_fout & NISTC_CLK_FOUT_TIMEBASE_SEL) {
4146                         data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4147                         data[2] = TIMEBASE_2_NS;
4148                 } else {
4149                         data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4150                         data[2] = TIMEBASE_1_NS * 2;
4151                 }
4152                 break;
4153         default:
4154                 return -EINVAL;
4155         }
4156         return insn->n;
4157 }
4158
4159 static int ni_8255_callback(struct comedi_device *dev,
4160                             int dir, int port, int data, unsigned long iobase)
4161 {
4162         if (dir) {
4163                 ni_writeb(dev, data, iobase + 2 * port);
4164                 return 0;
4165         }
4166
4167         return ni_readb(dev, iobase + 2 * port);
4168 }
4169
4170 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4171 {
4172         struct ni_private *devpriv = dev->private;
4173
4174         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4175         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4176         return 3;
4177 }
4178
4179 static int ni_m_series_pwm_config(struct comedi_device *dev,
4180                                   struct comedi_subdevice *s,
4181                                   struct comedi_insn *insn,
4182                                   unsigned int *data)
4183 {
4184         struct ni_private *devpriv = dev->private;
4185         unsigned int up_count, down_count;
4186
4187         switch (data[0]) {
4188         case INSN_CONFIG_PWM_OUTPUT:
4189                 switch (data[1]) {
4190                 case CMDF_ROUND_NEAREST:
4191                         up_count = DIV_ROUND_CLOSEST(data[2],
4192                                                      devpriv->clock_ns);
4193                         break;
4194                 case CMDF_ROUND_DOWN:
4195                         up_count = data[2] / devpriv->clock_ns;
4196                         break;
4197                 case CMDF_ROUND_UP:
4198                         up_count =
4199                             DIV_ROUND_UP(data[2], devpriv->clock_ns);
4200                         break;
4201                 default:
4202                         return -EINVAL;
4203                 }
4204                 switch (data[3]) {
4205                 case CMDF_ROUND_NEAREST:
4206                         down_count = DIV_ROUND_CLOSEST(data[4],
4207                                                        devpriv->clock_ns);
4208                         break;
4209                 case CMDF_ROUND_DOWN:
4210                         down_count = data[4] / devpriv->clock_ns;
4211                         break;
4212                 case CMDF_ROUND_UP:
4213                         down_count =
4214                             DIV_ROUND_UP(data[4], devpriv->clock_ns);
4215                         break;
4216                 default:
4217                         return -EINVAL;
4218                 }
4219                 if (up_count * devpriv->clock_ns != data[2] ||
4220                     down_count * devpriv->clock_ns != data[4]) {
4221                         data[2] = up_count * devpriv->clock_ns;
4222                         data[4] = down_count * devpriv->clock_ns;
4223                         return -EAGAIN;
4224                 }
4225                 ni_writel(dev, NI_M_CAL_PWM_HIGH_TIME(up_count) |
4226                                NI_M_CAL_PWM_LOW_TIME(down_count),
4227                           NI_M_CAL_PWM_REG);
4228                 devpriv->pwm_up_count = up_count;
4229                 devpriv->pwm_down_count = down_count;
4230                 return 5;
4231         case INSN_CONFIG_GET_PWM_OUTPUT:
4232                 return ni_get_pwm_config(dev, data);
4233         default:
4234                 return -EINVAL;
4235         }
4236         return 0;
4237 }
4238
4239 static int ni_6143_pwm_config(struct comedi_device *dev,
4240                               struct comedi_subdevice *s,
4241                               struct comedi_insn *insn,
4242                               unsigned int *data)
4243 {
4244         struct ni_private *devpriv = dev->private;
4245         unsigned int up_count, down_count;
4246
4247         switch (data[0]) {
4248         case INSN_CONFIG_PWM_OUTPUT:
4249                 switch (data[1]) {
4250                 case CMDF_ROUND_NEAREST:
4251                         up_count = DIV_ROUND_CLOSEST(data[2],
4252                                                      devpriv->clock_ns);
4253                         break;
4254                 case CMDF_ROUND_DOWN:
4255                         up_count = data[2] / devpriv->clock_ns;
4256                         break;
4257                 case CMDF_ROUND_UP:
4258                         up_count =
4259                             DIV_ROUND_UP(data[2], devpriv->clock_ns);
4260                         break;
4261                 default:
4262                         return -EINVAL;
4263                 }
4264                 switch (data[3]) {
4265                 case CMDF_ROUND_NEAREST:
4266                         down_count = DIV_ROUND_CLOSEST(data[4],
4267                                                        devpriv->clock_ns);
4268                         break;
4269                 case CMDF_ROUND_DOWN:
4270                         down_count = data[4] / devpriv->clock_ns;
4271                         break;
4272                 case CMDF_ROUND_UP:
4273                         down_count =
4274                             DIV_ROUND_UP(data[4], devpriv->clock_ns);
4275                         break;
4276                 default:
4277                         return -EINVAL;
4278                 }
4279                 if (up_count * devpriv->clock_ns != data[2] ||
4280                     down_count * devpriv->clock_ns != data[4]) {
4281                         data[2] = up_count * devpriv->clock_ns;
4282                         data[4] = down_count * devpriv->clock_ns;
4283                         return -EAGAIN;
4284                 }
4285                 ni_writel(dev, up_count, NI6143_CALIB_HI_TIME_REG);
4286                 devpriv->pwm_up_count = up_count;
4287                 ni_writel(dev, down_count, NI6143_CALIB_LO_TIME_REG);
4288                 devpriv->pwm_down_count = down_count;
4289                 return 5;
4290         case INSN_CONFIG_GET_PWM_OUTPUT:
4291                 return ni_get_pwm_config(dev, data);
4292         default:
4293                 return -EINVAL;
4294         }
4295         return 0;
4296 }
4297
4298 static int pack_mb88341(int addr, int val, int *bitstring)
4299 {
4300         /*
4301          * Fujitsu MB 88341
4302          * Note that address bits are reversed.  Thanks to
4303          * Ingo Keen for noticing this.
4304          *
4305          * Note also that the 88341 expects address values from
4306          * 1-12, whereas we use channel numbers 0-11.  The NI
4307          * docs use 1-12, also, so be careful here.
4308          */
4309         addr++;
4310         *bitstring = ((addr & 0x1) << 11) |
4311             ((addr & 0x2) << 9) |
4312             ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4313         return 12;
4314 }
4315
4316 static int pack_dac8800(int addr, int val, int *bitstring)
4317 {
4318         *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4319         return 11;
4320 }
4321
4322 static int pack_dac8043(int addr, int val, int *bitstring)
4323 {
4324         *bitstring = val & 0xfff;
4325         return 12;
4326 }
4327
4328 static int pack_ad8522(int addr, int val, int *bitstring)
4329 {
4330         *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4331         return 16;
4332 }
4333
4334 static int pack_ad8804(int addr, int val, int *bitstring)
4335 {
4336         *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4337         return 12;
4338 }
4339
4340 static int pack_ad8842(int addr, int val, int *bitstring)
4341 {
4342         *bitstring = ((addr + 1) << 8) | (val & 0xff);
4343         return 12;
4344 }
4345
4346 struct caldac_struct {
4347         int n_chans;
4348         int n_bits;
4349         int (*packbits)(int address, int value, int *bitstring);
4350 };
4351
4352 static struct caldac_struct caldacs[] = {
4353         [mb88341] = {12, 8, pack_mb88341},
4354         [dac8800] = {8, 8, pack_dac8800},
4355         [dac8043] = {1, 12, pack_dac8043},
4356         [ad8522] = {2, 12, pack_ad8522},
4357         [ad8804] = {12, 8, pack_ad8804},
4358         [ad8842] = {8, 8, pack_ad8842},
4359         [ad8804_debug] = {16, 8, pack_ad8804},
4360 };
4361
4362 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4363 {
4364         const struct ni_board_struct *board = dev->board_ptr;
4365         struct ni_private *devpriv = dev->private;
4366         unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4367         unsigned int cmd;
4368         int i;
4369         int type;
4370
4371         if (devpriv->caldacs[addr] == val)
4372                 return;
4373         devpriv->caldacs[addr] = val;
4374
4375         for (i = 0; i < 3; i++) {
4376                 type = board->caldac[i];
4377                 if (type == caldac_none)
4378                         break;
4379                 if (addr < caldacs[type].n_chans) {
4380                         bits = caldacs[type].packbits(addr, val, &bitstring);
4381                         loadbit = NI_E_SERIAL_CMD_DAC_LD(i);
4382                         break;
4383                 }
4384                 addr -= caldacs[type].n_chans;
4385         }
4386
4387         /* bits will be 0 if there is no caldac for the given addr */
4388         if (bits == 0)
4389                 return;
4390
4391         for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4392                 cmd = (bit & bitstring) ? NI_E_SERIAL_CMD_SDATA : 0;
4393                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4394                 udelay(1);
4395                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4396                 udelay(1);
4397         }
4398         ni_writeb(dev, loadbit, NI_E_SERIAL_CMD_REG);
4399         udelay(1);
4400         ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4401 }
4402
4403 static int ni_calib_insn_write(struct comedi_device *dev,
4404                                struct comedi_subdevice *s,
4405                                struct comedi_insn *insn,
4406                                unsigned int *data)
4407 {
4408         if (insn->n) {
4409                 /* only bother writing the last sample to the channel */
4410                 ni_write_caldac(dev, CR_CHAN(insn->chanspec),
4411                                 data[insn->n - 1]);
4412         }
4413
4414         return insn->n;
4415 }
4416
4417 static int ni_calib_insn_read(struct comedi_device *dev,
4418                               struct comedi_subdevice *s,
4419                               struct comedi_insn *insn,
4420                               unsigned int *data)
4421 {
4422         struct ni_private *devpriv = dev->private;
4423         unsigned int i;
4424
4425         for (i = 0; i < insn->n; i++)
4426                 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4427
4428         return insn->n;
4429 }
4430
4431 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4432 {
4433         const struct ni_board_struct *board = dev->board_ptr;
4434         struct ni_private *devpriv = dev->private;
4435         int i, j;
4436         int n_dacs;
4437         int n_chans = 0;
4438         int n_bits;
4439         int diffbits = 0;
4440         int type;
4441         int chan;
4442
4443         type = board->caldac[0];
4444         if (type == caldac_none)
4445                 return;
4446         n_bits = caldacs[type].n_bits;
4447         for (i = 0; i < 3; i++) {
4448                 type = board->caldac[i];
4449                 if (type == caldac_none)
4450                         break;
4451                 if (caldacs[type].n_bits != n_bits)
4452                         diffbits = 1;
4453                 n_chans += caldacs[type].n_chans;
4454         }
4455         n_dacs = i;
4456         s->n_chan = n_chans;
4457
4458         if (diffbits) {
4459                 unsigned int *maxdata_list = devpriv->caldac_maxdata_list;
4460
4461                 if (n_chans > MAX_N_CALDACS)
4462                         dev_err(dev->class_dev,
4463                                 "BUG! MAX_N_CALDACS too small\n");
4464                 s->maxdata_list = maxdata_list;
4465                 chan = 0;
4466                 for (i = 0; i < n_dacs; i++) {
4467                         type = board->caldac[i];
4468                         for (j = 0; j < caldacs[type].n_chans; j++) {
4469                                 maxdata_list[chan] =
4470                                     (1 << caldacs[type].n_bits) - 1;
4471                                 chan++;
4472                         }
4473                 }
4474
4475                 for (chan = 0; chan < s->n_chan; chan++)
4476                         ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4477         } else {
4478                 type = board->caldac[0];
4479                 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4480
4481                 for (chan = 0; chan < s->n_chan; chan++)
4482                         ni_write_caldac(dev, i, s->maxdata / 2);
4483         }
4484 }
4485
4486 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4487 {
4488         unsigned int cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4489         int bit;
4490         int bitstring;
4491
4492         bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4493         ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4494         for (bit = 0x8000; bit; bit >>= 1) {
4495                 if (bit & bitstring)
4496                         cmd |= NI_E_SERIAL_CMD_SDATA;
4497                 else
4498                         cmd &= ~NI_E_SERIAL_CMD_SDATA;
4499
4500                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4501                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4502         }
4503         cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4504         bitstring = 0;
4505         for (bit = 0x80; bit; bit >>= 1) {
4506                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4507                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4508                 if (ni_readb(dev, NI_E_STATUS_REG) & NI_E_STATUS_PROMOUT)
4509                         bitstring |= bit;
4510         }
4511         ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4512
4513         return bitstring;
4514 }
4515
4516 static int ni_eeprom_insn_read(struct comedi_device *dev,
4517                                struct comedi_subdevice *s,
4518                                struct comedi_insn *insn,
4519                                unsigned int *data)
4520 {
4521         unsigned int val;
4522         unsigned int i;
4523
4524         if (insn->n) {
4525                 val = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4526                 for (i = 0; i < insn->n; i++)
4527                         data[i] = val;
4528         }
4529         return insn->n;
4530 }
4531
4532 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4533                                         struct comedi_subdevice *s,
4534                                         struct comedi_insn *insn,
4535                                         unsigned int *data)
4536 {
4537         struct ni_private *devpriv = dev->private;
4538         unsigned int i;
4539
4540         for (i = 0; i < insn->n; i++)
4541                 data[i] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4542
4543         return insn->n;
4544 }
4545
4546 static unsigned int ni_old_get_pfi_routing(struct comedi_device *dev,
4547                                            unsigned int chan)
4548 {
4549         /*  pre-m-series boards have fixed signals on pfi pins */
4550         switch (chan) {
4551         case 0:
4552                 return NI_PFI_OUTPUT_AI_START1;
4553         case 1:
4554                 return NI_PFI_OUTPUT_AI_START2;
4555         case 2:
4556                 return NI_PFI_OUTPUT_AI_CONVERT;
4557         case 3:
4558                 return NI_PFI_OUTPUT_G_SRC1;
4559         case 4:
4560                 return NI_PFI_OUTPUT_G_GATE1;
4561         case 5:
4562                 return NI_PFI_OUTPUT_AO_UPDATE_N;
4563         case 6:
4564                 return NI_PFI_OUTPUT_AO_START1;
4565         case 7:
4566                 return NI_PFI_OUTPUT_AI_START_PULSE;
4567         case 8:
4568                 return NI_PFI_OUTPUT_G_SRC0;
4569         case 9:
4570                 return NI_PFI_OUTPUT_G_GATE0;
4571         default:
4572                 dev_err(dev->class_dev, "bug, unhandled case in switch.\n");
4573                 break;
4574         }
4575         return 0;
4576 }
4577
4578 static int ni_old_set_pfi_routing(struct comedi_device *dev,
4579                                   unsigned int chan, unsigned int source)
4580 {
4581         /*  pre-m-series boards have fixed signals on pfi pins */
4582         if (source != ni_old_get_pfi_routing(dev, chan))
4583                 return -EINVAL;
4584         return 2;
4585 }
4586
4587 static unsigned int ni_m_series_get_pfi_routing(struct comedi_device *dev,
4588                                                 unsigned int chan)
4589 {
4590         struct ni_private *devpriv = dev->private;
4591         const unsigned int array_offset = chan / 3;
4592
4593         return NI_M_PFI_OUT_SEL_TO_SRC(chan,
4594                                 devpriv->pfi_output_select_reg[array_offset]);
4595 }
4596
4597 static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4598                                        unsigned int chan, unsigned int source)
4599 {
4600         struct ni_private *devpriv = dev->private;
4601         unsigned int index = chan / 3;
4602         unsigned short val = devpriv->pfi_output_select_reg[index];
4603
4604         if ((source & 0x1f) != source)
4605                 return -EINVAL;
4606
4607         val &= ~NI_M_PFI_OUT_SEL_MASK(chan);
4608         val |= NI_M_PFI_OUT_SEL(chan, source);
4609         ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index));
4610         devpriv->pfi_output_select_reg[index] = val;
4611
4612         return 2;
4613 }
4614
4615 static unsigned int ni_get_pfi_routing(struct comedi_device *dev,
4616                                        unsigned int chan)
4617 {
4618         struct ni_private *devpriv = dev->private;
4619
4620         if (chan >= NI_PFI(0)) {
4621                 /* allow new and old names of pfi channels to work. */
4622                 chan -= NI_PFI(0);
4623         }
4624         return (devpriv->is_m_series)
4625                         ? ni_m_series_get_pfi_routing(dev, chan)
4626                         : ni_old_get_pfi_routing(dev, chan);
4627 }
4628
4629 /* Sets the output mux for the specified PFI channel. */
4630 static int ni_set_pfi_routing(struct comedi_device *dev,
4631                               unsigned int chan, unsigned int source)
4632 {
4633         struct ni_private *devpriv = dev->private;
4634
4635         if (chan >= NI_PFI(0)) {
4636                 /* allow new and old names of pfi channels to work. */
4637                 chan -= NI_PFI(0);
4638         }
4639         return (devpriv->is_m_series)
4640                         ? ni_m_series_set_pfi_routing(dev, chan, source)
4641                         : ni_old_set_pfi_routing(dev, chan, source);
4642 }
4643
4644 static int ni_config_pfi_filter(struct comedi_device *dev,
4645                                 unsigned int chan,
4646                                 enum ni_pfi_filter_select filter)
4647 {
4648         struct ni_private *devpriv = dev->private;
4649         unsigned int bits;
4650
4651         if (!devpriv->is_m_series)
4652                 return -ENOTSUPP;
4653
4654         if (chan >= NI_PFI(0)) {
4655                 /* allow new and old names of pfi channels to work. */
4656                 chan -= NI_PFI(0);
4657         }
4658
4659         bits = ni_readl(dev, NI_M_PFI_FILTER_REG);
4660         bits &= ~NI_M_PFI_FILTER_SEL_MASK(chan);
4661         bits |= NI_M_PFI_FILTER_SEL(chan, filter);
4662         ni_writel(dev, bits, NI_M_PFI_FILTER_REG);
4663         return 0;
4664 }
4665
4666 static void ni_set_pfi_direction(struct comedi_device *dev, int chan,
4667                                  unsigned int direction)
4668 {
4669         if (chan >= NI_PFI(0)) {
4670                 /* allow new and old names of pfi channels to work. */
4671                 chan -= NI_PFI(0);
4672         }
4673         direction = (direction == COMEDI_OUTPUT) ? 1u : 0u;
4674         ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, direction);
4675 }
4676
4677 static int ni_get_pfi_direction(struct comedi_device *dev, int chan)
4678 {
4679         struct ni_private *devpriv = dev->private;
4680
4681         if (chan >= NI_PFI(0)) {
4682                 /* allow new and old names of pfi channels to work. */
4683                 chan -= NI_PFI(0);
4684         }
4685         return devpriv->io_bidirection_pin_reg & (1 << chan) ?
4686                COMEDI_OUTPUT : COMEDI_INPUT;
4687 }
4688
4689 static int ni_pfi_insn_config(struct comedi_device *dev,
4690                               struct comedi_subdevice *s,
4691                               struct comedi_insn *insn,
4692                               unsigned int *data)
4693 {
4694         unsigned int chan;
4695
4696         if (insn->n < 1)
4697                 return -EINVAL;
4698
4699         chan = CR_CHAN(insn->chanspec);
4700
4701         switch (data[0]) {
4702         case COMEDI_OUTPUT:
4703         case COMEDI_INPUT:
4704                 ni_set_pfi_direction(dev, chan, data[0]);
4705                 break;
4706         case INSN_CONFIG_DIO_QUERY:
4707                 data[1] = ni_get_pfi_direction(dev, chan);
4708                 break;
4709         case INSN_CONFIG_SET_ROUTING:
4710                 return ni_set_pfi_routing(dev, chan, data[1]);
4711         case INSN_CONFIG_GET_ROUTING:
4712                 data[1] = ni_get_pfi_routing(dev, chan);
4713                 break;
4714         case INSN_CONFIG_FILTER:
4715                 return ni_config_pfi_filter(dev, chan, data[1]);
4716         default:
4717                 return -EINVAL;
4718         }
4719         return 0;
4720 }
4721
4722 static int ni_pfi_insn_bits(struct comedi_device *dev,
4723                             struct comedi_subdevice *s,
4724                             struct comedi_insn *insn,
4725                             unsigned int *data)
4726 {
4727         struct ni_private *devpriv = dev->private;
4728
4729         if (!devpriv->is_m_series)
4730                 return -ENOTSUPP;
4731
4732         if (comedi_dio_update_state(s, data))
4733                 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
4734
4735         data[1] = ni_readw(dev, NI_M_PFI_DI_REG);
4736
4737         return insn->n;
4738 }
4739
4740 static int cs5529_wait_for_idle(struct comedi_device *dev)
4741 {
4742         unsigned short status;
4743         const int timeout = HZ;
4744         int i;
4745
4746         for (i = 0; i < timeout; i++) {
4747                 status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4748                 if ((status & NI67XX_CAL_STATUS_BUSY) == 0)
4749                         break;
4750                 set_current_state(TASK_INTERRUPTIBLE);
4751                 if (schedule_timeout(1))
4752                         return -EIO;
4753         }
4754         if (i == timeout) {
4755                 dev_err(dev->class_dev, "timeout\n");
4756                 return -ETIME;
4757         }
4758         return 0;
4759 }
4760
4761 static void cs5529_command(struct comedi_device *dev, unsigned short value)
4762 {
4763         static const int timeout = 100;
4764         int i;
4765
4766         ni_ao_win_outw(dev, value, NI67XX_CAL_CMD_REG);
4767         /* give time for command to start being serially clocked into cs5529.
4768          * this insures that the NI67XX_CAL_STATUS_BUSY bit will get properly
4769          * set before we exit this function.
4770          */
4771         for (i = 0; i < timeout; i++) {
4772                 if (ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG) &
4773                     NI67XX_CAL_STATUS_BUSY)
4774                         break;
4775                 udelay(1);
4776         }
4777         if (i == timeout)
4778                 dev_err(dev->class_dev,
4779                         "possible problem - never saw adc go busy?\n");
4780 }
4781
4782 static int cs5529_do_conversion(struct comedi_device *dev,
4783                                 unsigned short *data)
4784 {
4785         int retval;
4786         unsigned short status;
4787
4788         cs5529_command(dev, CS5529_CMD_CB | CS5529_CMD_SINGLE_CONV);
4789         retval = cs5529_wait_for_idle(dev);
4790         if (retval) {
4791                 dev_err(dev->class_dev,
4792                         "timeout or signal in %s()\n", __func__);
4793                 return -ETIME;
4794         }
4795         status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4796         if (status & NI67XX_CAL_STATUS_OSC_DETECT) {
4797                 dev_err(dev->class_dev,
4798                         "cs5529 conversion error, status CSS_OSC_DETECT\n");
4799                 return -EIO;
4800         }
4801         if (status & NI67XX_CAL_STATUS_OVERRANGE) {
4802                 dev_err(dev->class_dev,
4803                         "cs5529 conversion error, overrange (ignoring)\n");
4804         }
4805         if (data) {
4806                 *data = ni_ao_win_inw(dev, NI67XX_CAL_DATA_REG);
4807                 /* cs5529 returns 16 bit signed data in bipolar mode */
4808                 *data ^= BIT(15);
4809         }
4810         return 0;
4811 }
4812
4813 static int cs5529_ai_insn_read(struct comedi_device *dev,
4814                                struct comedi_subdevice *s,
4815                                struct comedi_insn *insn,
4816                                unsigned int *data)
4817 {
4818         int n, retval;
4819         unsigned short sample;
4820         unsigned int channel_select;
4821         const unsigned int INTERNAL_REF = 0x1000;
4822
4823         /*
4824          * Set calibration adc source.  Docs lie, reference select bits 8 to 11
4825          * do nothing. bit 12 seems to chooses internal reference voltage, bit
4826          * 13 causes the adc input to go overrange (maybe reads external
4827          * reference?)
4828          */
4829         if (insn->chanspec & CR_ALT_SOURCE)
4830                 channel_select = INTERNAL_REF;
4831         else
4832                 channel_select = CR_CHAN(insn->chanspec);
4833         ni_ao_win_outw(dev, channel_select, NI67XX_AO_CAL_CHAN_SEL_REG);
4834
4835         for (n = 0; n < insn->n; n++) {
4836                 retval = cs5529_do_conversion(dev, &sample);
4837                 if (retval < 0)
4838                         return retval;
4839                 data[n] = sample;
4840         }
4841         return insn->n;
4842 }
4843
4844 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
4845                                 unsigned int reg_select_bits)
4846 {
4847         ni_ao_win_outw(dev, (value >> 16) & 0xff, NI67XX_CAL_CFG_HI_REG);
4848         ni_ao_win_outw(dev, value & 0xffff, NI67XX_CAL_CFG_LO_REG);
4849         reg_select_bits &= CS5529_CMD_REG_MASK;
4850         cs5529_command(dev, CS5529_CMD_CB | reg_select_bits);
4851         if (cs5529_wait_for_idle(dev))
4852                 dev_err(dev->class_dev,
4853                         "timeout or signal in %s\n", __func__);
4854 }
4855
4856 static int init_cs5529(struct comedi_device *dev)
4857 {
4858         unsigned int config_bits = CS5529_CFG_PORT_FLAG |
4859                                    CS5529_CFG_WORD_RATE_2180;
4860
4861 #if 1
4862         /* do self-calibration */
4863         cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_BOTH_SELF,
4864                             CS5529_CFG_REG);
4865         /* need to force a conversion for calibration to run */
4866         cs5529_do_conversion(dev, NULL);
4867 #else
4868         /* force gain calibration to 1 */
4869         cs5529_config_write(dev, 0x400000, CS5529_GAIN_REG);
4870         cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_OFFSET_SELF,
4871                             CS5529_CFG_REG);
4872         if (cs5529_wait_for_idle(dev))
4873                 dev_err(dev->class_dev,
4874                         "timeout or signal in %s\n", __func__);
4875 #endif
4876         return 0;
4877 }
4878
4879 /*
4880  * Find best multiplier/divider to try and get the PLL running at 80 MHz
4881  * given an arbitrary frequency input clock.
4882  */
4883 static int ni_mseries_get_pll_parameters(unsigned int reference_period_ns,
4884                                          unsigned int *freq_divider,
4885                                          unsigned int *freq_multiplier,
4886                                          unsigned int *actual_period_ns)
4887 {
4888         unsigned int div;
4889         unsigned int best_div = 1;
4890         unsigned int mult;
4891         unsigned int best_mult = 1;
4892         static const unsigned int pico_per_nano = 1000;
4893         const unsigned int reference_picosec = reference_period_ns *
4894                                                pico_per_nano;
4895         /*
4896          * m-series wants the phased-locked loop to output 80MHz, which is
4897          * divided by 4 to 20 MHz for most timing clocks
4898          */
4899         static const unsigned int target_picosec = 12500;
4900         int best_period_picosec = 0;
4901
4902         for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) {
4903                 for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) {
4904                         unsigned int new_period_ps =
4905                             (reference_picosec * div) / mult;
4906                         if (abs(new_period_ps - target_picosec) <
4907                             abs(best_period_picosec - target_picosec)) {
4908                                 best_period_picosec = new_period_ps;
4909                                 best_div = div;
4910                                 best_mult = mult;
4911                         }
4912                 }
4913         }
4914         if (best_period_picosec == 0)
4915                 return -EIO;
4916
4917         *freq_divider = best_div;
4918         *freq_multiplier = best_mult;
4919         /* return the actual period (* fudge factor for 80 to 20 MHz) */
4920         *actual_period_ns = DIV_ROUND_CLOSEST(best_period_picosec * 4,
4921                                               pico_per_nano);
4922         return 0;
4923 }
4924
4925 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4926                                            unsigned int source,
4927                                            unsigned int period_ns)
4928 {
4929         struct ni_private *devpriv = dev->private;
4930         static const unsigned int min_period_ns = 50;
4931         static const unsigned int max_period_ns = 1000;
4932         static const unsigned int timeout = 1000;
4933         unsigned int pll_control_bits;
4934         unsigned int freq_divider;
4935         unsigned int freq_multiplier;
4936         unsigned int rtsi;
4937         unsigned int i;
4938         int retval;
4939
4940         if (source == NI_MIO_PLL_PXI10_CLOCK)
4941                 period_ns = 100;
4942         /*
4943          * These limits are somewhat arbitrary, but NI advertises 1 to 20MHz
4944          * range so we'll use that.
4945          */
4946         if (period_ns < min_period_ns || period_ns > max_period_ns) {
4947                 dev_err(dev->class_dev,
4948                         "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n",
4949                         __func__, min_period_ns, max_period_ns);
4950                 return -EINVAL;
4951         }
4952         devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4953         ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4954                       NISTC_RTSI_TRIG_DIR_REG);
4955         pll_control_bits = NI_M_PLL_CTRL_ENA | NI_M_PLL_CTRL_VCO_MODE_75_150MHZ;
4956         devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4957                                     NI_M_CLK_FOUT2_TIMEBASE3_PLL;
4958         devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK;
4959         switch (source) {
4960         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4961                 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR;
4962                 break;
4963         case NI_MIO_PLL_PXI10_CLOCK:
4964                 /* pxi clock is 10MHz */
4965                 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10;
4966                 break;
4967         default:
4968                 for (rtsi = 0; rtsi <= NI_M_MAX_RTSI_CHAN; ++rtsi) {
4969                         if (source == NI_MIO_PLL_RTSI_CLOCK(rtsi)) {
4970                                 devpriv->clock_and_fout2 |=
4971                                         NI_M_CLK_FOUT2_PLL_SRC_RTSI(rtsi);
4972                                 break;
4973                         }
4974                 }
4975                 if (rtsi > NI_M_MAX_RTSI_CHAN)
4976                         return -EINVAL;
4977                 break;
4978         }
4979         retval = ni_mseries_get_pll_parameters(period_ns,
4980                                                &freq_divider,
4981                                                &freq_multiplier,
4982                                                &devpriv->clock_ns);
4983         if (retval < 0) {
4984                 dev_err(dev->class_dev,
4985                         "bug, failed to find pll parameters\n");
4986                 return retval;
4987         }
4988
4989         ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG);
4990         pll_control_bits |= NI_M_PLL_CTRL_DIVISOR(freq_divider) |
4991                             NI_M_PLL_CTRL_MULTIPLIER(freq_multiplier);
4992
4993         ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG);
4994         devpriv->clock_source = source;
4995         /* it takes a few hundred microseconds for PLL to lock */
4996         for (i = 0; i < timeout; ++i) {
4997                 if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED)
4998                         break;
4999                 udelay(1);
5000         }
5001         if (i == timeout) {
5002                 dev_err(dev->class_dev,
5003                         "%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n",
5004                         __func__, source, period_ns);
5005                 return -ETIMEDOUT;
5006         }
5007         return 3;
5008 }
5009
5010 static int ni_set_master_clock(struct comedi_device *dev,
5011                                unsigned int source, unsigned int period_ns)
5012 {
5013         struct ni_private *devpriv = dev->private;
5014
5015         if (source == NI_MIO_INTERNAL_CLOCK) {
5016                 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
5017                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5018                               NISTC_RTSI_TRIG_DIR_REG);
5019                 devpriv->clock_ns = TIMEBASE_1_NS;
5020                 if (devpriv->is_m_series) {
5021                         devpriv->clock_and_fout2 &=
5022                             ~(NI_M_CLK_FOUT2_TIMEBASE1_PLL |
5023                               NI_M_CLK_FOUT2_TIMEBASE3_PLL);
5024                         ni_writew(dev, devpriv->clock_and_fout2,
5025                                   NI_M_CLK_FOUT2_REG);
5026                         ni_writew(dev, 0, NI_M_PLL_CTRL_REG);
5027                 }
5028                 devpriv->clock_source = source;
5029         } else {
5030                 if (devpriv->is_m_series) {
5031                         return ni_mseries_set_pll_master_clock(dev, source,
5032                                                                period_ns);
5033                 } else {
5034                         if (source == NI_MIO_RTSI_CLOCK) {
5035                                 devpriv->rtsi_trig_direction_reg |=
5036                                     NISTC_RTSI_TRIG_USE_CLK;
5037                                 ni_stc_writew(dev,
5038                                               devpriv->rtsi_trig_direction_reg,
5039                                               NISTC_RTSI_TRIG_DIR_REG);
5040                                 if (period_ns == 0) {
5041                                         dev_err(dev->class_dev,
5042                                                 "we don't handle an unspecified clock period correctly yet, returning error\n");
5043                                         return -EINVAL;
5044                                 }
5045                                 devpriv->clock_ns = period_ns;
5046                                 devpriv->clock_source = source;
5047                         } else {
5048                                 return -EINVAL;
5049                         }
5050                 }
5051         }
5052         return 3;
5053 }
5054
5055 static int ni_valid_rtsi_output_source(struct comedi_device *dev,
5056                                        unsigned int chan, unsigned int source)
5057 {
5058         struct ni_private *devpriv = dev->private;
5059
5060         if (chan >= NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
5061                 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5062                         if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5063                                 return 1;
5064
5065                         dev_err(dev->class_dev,
5066                                 "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n",
5067                                 __func__, chan, NISTC_RTSI_TRIG_OLD_CLK_CHAN);
5068                         return 0;
5069                 }
5070                 return 0;
5071         }
5072         switch (source) {
5073         case NI_RTSI_OUTPUT_ADR_START1:
5074         case NI_RTSI_OUTPUT_ADR_START2:
5075         case NI_RTSI_OUTPUT_SCLKG:
5076         case NI_RTSI_OUTPUT_DACUPDN:
5077         case NI_RTSI_OUTPUT_DA_START1:
5078         case NI_RTSI_OUTPUT_G_SRC0:
5079         case NI_RTSI_OUTPUT_G_GATE0:
5080         case NI_RTSI_OUTPUT_RGOUT0:
5081         case NI_RTSI_OUTPUT_RTSI_BRD(0):
5082         case NI_RTSI_OUTPUT_RTSI_BRD(1):
5083         case NI_RTSI_OUTPUT_RTSI_BRD(2):
5084         case NI_RTSI_OUTPUT_RTSI_BRD(3):
5085                 return 1;
5086         case NI_RTSI_OUTPUT_RTSI_OSC:
5087                 return (devpriv->is_m_series) ? 1 : 0;
5088         default:
5089                 return 0;
5090         }
5091 }
5092
5093 static int ni_set_rtsi_routing(struct comedi_device *dev,
5094                                unsigned int chan, unsigned int src)
5095 {
5096         struct ni_private *devpriv = dev->private;
5097
5098         if (chan >= TRIGGER_LINE(0))
5099                 /* allow new and old names of rtsi channels to work. */
5100                 chan -= TRIGGER_LINE(0);
5101
5102         if (ni_valid_rtsi_output_source(dev, chan, src) == 0)
5103                 return -EINVAL;
5104         if (chan < 4) {
5105                 devpriv->rtsi_trig_a_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
5106                 devpriv->rtsi_trig_a_output_reg |= NISTC_RTSI_TRIG(chan, src);
5107                 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5108                               NISTC_RTSI_TRIGA_OUT_REG);
5109         } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
5110                 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
5111                 devpriv->rtsi_trig_b_output_reg |= NISTC_RTSI_TRIG(chan, src);
5112                 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5113                               NISTC_RTSI_TRIGB_OUT_REG);
5114         } else if (chan != NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5115                 /* probably should never reach this, since the
5116                  * ni_valid_rtsi_output_source above errors out if chan is too
5117                  * high
5118                  */
5119                 dev_err(dev->class_dev, "%s: unknown rtsi channel\n", __func__);
5120                 return -EINVAL;
5121         }
5122         return 2;
5123 }
5124
5125 static unsigned int ni_get_rtsi_routing(struct comedi_device *dev,
5126                                         unsigned int chan)
5127 {
5128         struct ni_private *devpriv = dev->private;
5129
5130         if (chan >= TRIGGER_LINE(0))
5131                 /* allow new and old names of rtsi channels to work. */
5132                 chan -= TRIGGER_LINE(0);
5133
5134         if (chan < 4) {
5135                 return NISTC_RTSI_TRIG_TO_SRC(chan,
5136                                               devpriv->rtsi_trig_a_output_reg);
5137         } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
5138                 return NISTC_RTSI_TRIG_TO_SRC(chan,
5139                                               devpriv->rtsi_trig_b_output_reg);
5140         } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5141                 return NI_RTSI_OUTPUT_RTSI_OSC;
5142         }
5143
5144         dev_err(dev->class_dev, "%s: unknown rtsi channel\n", __func__);
5145         return -EINVAL;
5146 }
5147
5148 static void ni_set_rtsi_direction(struct comedi_device *dev, int chan,
5149                                   unsigned int direction)
5150 {
5151         struct ni_private *devpriv = dev->private;
5152         unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series);
5153
5154         if (chan >= TRIGGER_LINE(0))
5155                 /* allow new and old names of rtsi channels to work. */
5156                 chan -= TRIGGER_LINE(0);
5157
5158         if (direction == COMEDI_OUTPUT) {
5159                 if (chan < max_chan) {
5160                         devpriv->rtsi_trig_direction_reg |=
5161                             NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
5162                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5163                         devpriv->rtsi_trig_direction_reg |=
5164                             NISTC_RTSI_TRIG_DRV_CLK;
5165                 }
5166         } else {
5167                 if (chan < max_chan) {
5168                         devpriv->rtsi_trig_direction_reg &=
5169                             ~NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
5170                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5171                         devpriv->rtsi_trig_direction_reg &=
5172                             ~NISTC_RTSI_TRIG_DRV_CLK;
5173                 }
5174         }
5175         ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5176                       NISTC_RTSI_TRIG_DIR_REG);
5177 }
5178
5179 static int ni_get_rtsi_direction(struct comedi_device *dev, int chan)
5180 {
5181         struct ni_private *devpriv = dev->private;
5182         unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series);
5183
5184         if (chan >= TRIGGER_LINE(0))
5185                 /* allow new and old names of rtsi channels to work. */
5186                 chan -= TRIGGER_LINE(0);
5187
5188         if (chan < max_chan) {
5189                 return (devpriv->rtsi_trig_direction_reg &
5190                         NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series))
5191                            ? COMEDI_OUTPUT : COMEDI_INPUT;
5192         } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5193                 return (devpriv->rtsi_trig_direction_reg &
5194                         NISTC_RTSI_TRIG_DRV_CLK)
5195                            ? COMEDI_OUTPUT : COMEDI_INPUT;
5196         }
5197         return -EINVAL;
5198 }
5199
5200 static int ni_rtsi_insn_config(struct comedi_device *dev,
5201                                struct comedi_subdevice *s,
5202                                struct comedi_insn *insn,
5203                                unsigned int *data)
5204 {
5205         struct ni_private *devpriv = dev->private;
5206         unsigned int chan = CR_CHAN(insn->chanspec);
5207
5208         switch (data[0]) {
5209         case COMEDI_OUTPUT:
5210         case COMEDI_INPUT:
5211                 ni_set_rtsi_direction(dev, chan, data[0]);
5212                 break;
5213         case INSN_CONFIG_DIO_QUERY: {
5214                 int ret = ni_get_rtsi_direction(dev, chan);
5215
5216                 if (ret < 0)
5217                         return ret;
5218                 data[1] = ret;
5219                 return 2;
5220         }
5221         case INSN_CONFIG_SET_CLOCK_SRC:
5222                 return ni_set_master_clock(dev, data[1], data[2]);
5223         case INSN_CONFIG_GET_CLOCK_SRC:
5224                 data[1] = devpriv->clock_source;
5225                 data[2] = devpriv->clock_ns;
5226                 return 3;
5227         case INSN_CONFIG_SET_ROUTING:
5228                 return ni_set_rtsi_routing(dev, chan, data[1]);
5229         case INSN_CONFIG_GET_ROUTING: {
5230                 int ret = ni_get_rtsi_routing(dev, chan);
5231
5232                 if (ret < 0)
5233                         return ret;
5234                 data[1] = ret;
5235                 return 2;
5236         }
5237         default:
5238                 return -EINVAL;
5239         }
5240         return 1;
5241 }
5242
5243 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5244                              struct comedi_subdevice *s,
5245                              struct comedi_insn *insn,
5246                              unsigned int *data)
5247 {
5248         data[1] = 0;
5249
5250         return insn->n;
5251 }
5252
5253 /*
5254  * Default routing for RTSI trigger lines.
5255  *
5256  * These values are used here in the init function, as well as in the
5257  * disconnect_route function, after a RTSI route has been disconnected.
5258  */
5259 static const int default_rtsi_routing[] = {
5260         [0] = NI_RTSI_OUTPUT_ADR_START1,
5261         [1] = NI_RTSI_OUTPUT_ADR_START2,
5262         [2] = NI_RTSI_OUTPUT_SCLKG,
5263         [3] = NI_RTSI_OUTPUT_DACUPDN,
5264         [4] = NI_RTSI_OUTPUT_DA_START1,
5265         [5] = NI_RTSI_OUTPUT_G_SRC0,
5266         [6] = NI_RTSI_OUTPUT_G_GATE0,
5267         [7] = NI_RTSI_OUTPUT_RTSI_OSC,
5268 };
5269
5270 /*
5271  * Route signals through RGOUT0 terminal.
5272  * @reg: raw register value of RGOUT0 bits (only bit0 is important).
5273  * @dev: comedi device handle.
5274  */
5275 static void set_rgout0_reg(int reg, struct comedi_device *dev)
5276 {
5277         struct ni_private *devpriv = dev->private;
5278
5279         if (devpriv->is_m_series) {
5280                 devpriv->rtsi_trig_direction_reg &=
5281                         ~NISTC_RTSI_TRIG_DIR_SUB_SEL1;
5282                 devpriv->rtsi_trig_direction_reg |=
5283                         (reg << NISTC_RTSI_TRIG_DIR_SUB_SEL1_SHIFT) &
5284                         NISTC_RTSI_TRIG_DIR_SUB_SEL1;
5285                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5286                               NISTC_RTSI_TRIG_DIR_REG);
5287         } else {
5288                 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIGB_SUB_SEL1;
5289                 devpriv->rtsi_trig_b_output_reg |=
5290                         (reg << NISTC_RTSI_TRIGB_SUB_SEL1_SHIFT) &
5291                         NISTC_RTSI_TRIGB_SUB_SEL1;
5292                 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5293                               NISTC_RTSI_TRIGB_OUT_REG);
5294         }
5295 }
5296
5297 static int get_rgout0_reg(struct comedi_device *dev)
5298 {
5299         struct ni_private *devpriv = dev->private;
5300         int reg;
5301
5302         if (devpriv->is_m_series)
5303                 reg = (devpriv->rtsi_trig_direction_reg &
5304                        NISTC_RTSI_TRIG_DIR_SUB_SEL1)
5305                     >> NISTC_RTSI_TRIG_DIR_SUB_SEL1_SHIFT;
5306         else
5307                 reg = (devpriv->rtsi_trig_b_output_reg &
5308                        NISTC_RTSI_TRIGB_SUB_SEL1)
5309                     >> NISTC_RTSI_TRIGB_SUB_SEL1_SHIFT;
5310         return reg;
5311 }
5312
5313 static inline int get_rgout0_src(struct comedi_device *dev)
5314 {
5315         struct ni_private *devpriv = dev->private;
5316         int reg = get_rgout0_reg(dev);
5317
5318         return ni_find_route_source(reg, NI_RGOUT0, &devpriv->routing_tables);
5319 }
5320
5321 /*
5322  * Route signals through RGOUT0 terminal and increment the RGOUT0 use for this
5323  * particular route.
5324  * @src: device-global signal name
5325  * @dev: comedi device handle
5326  *
5327  * Return: -EINVAL if the source is not valid to route to RGOUT0;
5328  *         -EBUSY if the RGOUT0 is already used;
5329  *         0 if successful.
5330  */
5331 static int incr_rgout0_src_use(int src, struct comedi_device *dev)
5332 {
5333         struct ni_private *devpriv = dev->private;
5334         s8 reg = ni_lookup_route_register(CR_CHAN(src), NI_RGOUT0,
5335                                           &devpriv->routing_tables);
5336
5337         if (reg < 0)
5338                 return -EINVAL;
5339
5340         if (devpriv->rgout0_usage > 0 && get_rgout0_reg(dev) != reg)
5341                 return -EBUSY;
5342
5343         ++devpriv->rgout0_usage;
5344         set_rgout0_reg(reg, dev);
5345         return 0;
5346 }
5347
5348 /*
5349  * Unroute signals through RGOUT0 terminal and deccrement the RGOUT0 use for
5350  * this particular source.  This function does not actually unroute anything
5351  * with respect to RGOUT0.  It does, on the other hand, decrement the usage
5352  * counter for the current src->RGOUT0 mapping.
5353  *
5354  * Return: -EINVAL if the source is not already routed to RGOUT0 (or usage is
5355  *      already at zero); 0 if successful.
5356  */
5357 static int decr_rgout0_src_use(int src, struct comedi_device *dev)
5358 {
5359         struct ni_private *devpriv = dev->private;
5360         s8 reg = ni_lookup_route_register(CR_CHAN(src), NI_RGOUT0,
5361                                           &devpriv->routing_tables);
5362
5363         if (devpriv->rgout0_usage > 0 && get_rgout0_reg(dev) == reg) {
5364                 --devpriv->rgout0_usage;
5365                 if (!devpriv->rgout0_usage)
5366                         set_rgout0_reg(0, dev); /* ok default? */
5367                 return 0;
5368         }
5369         return -EINVAL;
5370 }
5371
5372 /*
5373  * Route signals through given NI_RTSI_BRD mux.
5374  * @i: index of mux to route
5375  * @reg: raw register value of RTSI_BRD bits
5376  * @dev: comedi device handle
5377  */
5378 static void set_ith_rtsi_brd_reg(int i, int reg, struct comedi_device *dev)
5379 {
5380         struct ni_private *devpriv = dev->private;
5381         int reg_i_sz = 3; /* value for e-series */
5382         int reg_i_mask;
5383         int reg_i_shift;
5384
5385         if (devpriv->is_m_series)
5386                 reg_i_sz = 4;
5387         reg_i_mask = ~((~0) << reg_i_sz);
5388         reg_i_shift = i * reg_i_sz;
5389
5390         /* clear out the current reg_i for ith brd */
5391         devpriv->rtsi_shared_mux_reg &= ~(reg_i_mask       << reg_i_shift);
5392         /* (softcopy) write the new reg_i for ith brd */
5393         devpriv->rtsi_shared_mux_reg |= (reg & reg_i_mask) << reg_i_shift;
5394         /* (hardcopy) write the new reg_i for ith brd */
5395         ni_stc_writew(dev, devpriv->rtsi_shared_mux_reg, NISTC_RTSI_BOARD_REG);
5396 }
5397
5398 static int get_ith_rtsi_brd_reg(int i, struct comedi_device *dev)
5399 {
5400         struct ni_private *devpriv = dev->private;
5401         int reg_i_sz = 3; /* value for e-series */
5402         int reg_i_mask;
5403         int reg_i_shift;
5404
5405         if (devpriv->is_m_series)
5406                 reg_i_sz = 4;
5407         reg_i_mask = ~((~0) << reg_i_sz);
5408         reg_i_shift = i * reg_i_sz;
5409
5410         return (devpriv->rtsi_shared_mux_reg >> reg_i_shift) & reg_i_mask;
5411 }
5412
5413 static inline int get_rtsi_brd_src(int brd, struct comedi_device *dev)
5414 {
5415         struct ni_private *devpriv = dev->private;
5416         int brd_index = brd;
5417         int reg;
5418
5419         if (brd >= NI_RTSI_BRD(0))
5420                 brd_index = brd - NI_RTSI_BRD(0);
5421         else
5422                 brd = NI_RTSI_BRD(brd);
5423         /*
5424          * And now:
5425          * brd : device-global name
5426          * brd_index : index number of RTSI_BRD mux
5427          */
5428
5429         reg = get_ith_rtsi_brd_reg(brd_index, dev);
5430
5431         return ni_find_route_source(reg, brd, &devpriv->routing_tables);
5432 }
5433
5434 /*
5435  * Route signals through NI_RTSI_BRD mux and increment the use counter for this
5436  * particular route.
5437  *
5438  * Return: -EINVAL if the source is not valid to route to NI_RTSI_BRD(i);
5439  *         -EBUSY if all NI_RTSI_BRD muxes are already used;
5440  *         NI_RTSI_BRD(i) of allocated ith mux if successful.
5441  */
5442 static int incr_rtsi_brd_src_use(int src, struct comedi_device *dev)
5443 {
5444         struct ni_private *devpriv = dev->private;
5445         int first_available = -1;
5446         int err = -EINVAL;
5447         s8 reg;
5448         int i;
5449
5450         /* first look for a mux that is already configured to provide src */
5451         for (i = 0; i < NUM_RTSI_SHARED_MUXS; ++i) {
5452                 reg = ni_lookup_route_register(CR_CHAN(src), NI_RTSI_BRD(i),
5453                                                &devpriv->routing_tables);
5454
5455                 if (reg < 0)
5456                         continue; /* invalid route */
5457
5458                 if (!devpriv->rtsi_shared_mux_usage[i]) {
5459                         if (first_available < 0)
5460                                 /* found the first unused, but usable mux */
5461                                 first_available = i;
5462                 } else {
5463                         /*
5464                          * we've seen at least one possible route, so change the
5465                          * final error to -EBUSY in case there are no muxes
5466                          * available.
5467                          */
5468                         err = -EBUSY;
5469
5470                         if (get_ith_rtsi_brd_reg(i, dev) == reg) {
5471                                 /*
5472                                  * we've found a mux that is already being used
5473                                  * to provide the requested signal.  Reuse it.
5474                                  */
5475                                 goto success;
5476                         }
5477                 }
5478         }
5479
5480         if (first_available < 0)
5481                 return err;
5482
5483         /* we did not find a mux to reuse, but there is at least one usable */
5484         i = first_available;
5485
5486 success:
5487         ++devpriv->rtsi_shared_mux_usage[i];
5488         set_ith_rtsi_brd_reg(i, reg, dev);
5489         return NI_RTSI_BRD(i);
5490 }
5491
5492 /*
5493  * Unroute signals through NI_RTSI_BRD mux and decrement the user counter for
5494  * this particular route.
5495  *
5496  * Return: -EINVAL if the source is not already routed to rtsi_brd(i) (or usage
5497  *      is already at zero); 0 if successful.
5498  */
5499 static int decr_rtsi_brd_src_use(int src, int rtsi_brd,
5500                                  struct comedi_device *dev)
5501 {
5502         struct ni_private *devpriv = dev->private;
5503         s8 reg = ni_lookup_route_register(CR_CHAN(src), rtsi_brd,
5504                                           &devpriv->routing_tables);
5505         const int i = rtsi_brd - NI_RTSI_BRD(0);
5506
5507         if (devpriv->rtsi_shared_mux_usage[i] > 0 &&
5508             get_ith_rtsi_brd_reg(i, dev) == reg) {
5509                 --devpriv->rtsi_shared_mux_usage[i];
5510                 if (!devpriv->rtsi_shared_mux_usage[i])
5511                         set_ith_rtsi_brd_reg(i, 0, dev); /* ok default? */
5512                 return 0;
5513         }
5514
5515         return -EINVAL;
5516 }
5517
5518 static void ni_rtsi_init(struct comedi_device *dev)
5519 {
5520         struct ni_private *devpriv = dev->private;
5521         int i;
5522
5523         /*  Initialises the RTSI bus signal switch to a default state */
5524
5525         /*
5526          * Use 10MHz instead of 20MHz for RTSI clock frequency. Appears
5527          * to have no effect, at least on pxi-6281, which always uses
5528          * 20MHz rtsi clock frequency
5529          */
5530         devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ;
5531         /*  Set clock mode to internal */
5532         if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
5533                 dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n");
5534
5535         /* default internal lines routing to RTSI bus lines */
5536         for (i = 0; i < 8; ++i) {
5537                 ni_set_rtsi_direction(dev, i, COMEDI_INPUT);
5538                 ni_set_rtsi_routing(dev, i, default_rtsi_routing[i]);
5539         }
5540
5541         /*
5542          * Sets the source and direction of the 4 on board lines.
5543          * This configures all board lines to be:
5544          * for e-series:
5545          *   1) inputs (not sure what "output" would mean)
5546          *   2) copying TRIGGER_LINE(0) (or RTSI0) output
5547          * for m-series:
5548          *   copying NI_PFI(0) output
5549          */
5550         devpriv->rtsi_shared_mux_reg = 0;
5551         for (i = 0; i < 4; ++i)
5552                 set_ith_rtsi_brd_reg(i, 0, dev);
5553         memset(devpriv->rtsi_shared_mux_usage, 0,
5554                sizeof(devpriv->rtsi_shared_mux_usage));
5555
5556         /* initialize rgout0 pin as unused. */
5557         devpriv->rgout0_usage = 0;
5558         set_rgout0_reg(0, dev);
5559 }
5560
5561 /* Get route of GPFO_i/CtrOut pins */
5562 static inline int ni_get_gout_routing(unsigned int dest,
5563                                       struct comedi_device *dev)
5564 {
5565         struct ni_private *devpriv = dev->private;
5566         unsigned int reg = devpriv->an_trig_etc_reg;
5567
5568         switch (dest) {
5569         case 0:
5570                 if (reg & NISTC_ATRIG_ETC_GPFO_0_ENA)
5571                         return NISTC_ATRIG_ETC_GPFO_0_SEL_TO_SRC(reg);
5572                 break;
5573         case 1:
5574                 if (reg & NISTC_ATRIG_ETC_GPFO_1_ENA)
5575                         return NISTC_ATRIG_ETC_GPFO_1_SEL_TO_SRC(reg);
5576                 break;
5577         }
5578
5579         return -EINVAL;
5580 }
5581
5582 /* Set route of GPFO_i/CtrOut pins */
5583 static inline int ni_disable_gout_routing(unsigned int dest,
5584                                           struct comedi_device *dev)
5585 {
5586         struct ni_private *devpriv = dev->private;
5587
5588         switch (dest) {
5589         case 0:
5590                 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_0_ENA;
5591                 break;
5592         case 1:
5593                 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_1_ENA;
5594                 break;
5595         default:
5596                 return -EINVAL;
5597         }
5598
5599         ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
5600         return 0;
5601 }
5602
5603 /* Set route of GPFO_i/CtrOut pins */
5604 static inline int ni_set_gout_routing(unsigned int src, unsigned int dest,
5605                                       struct comedi_device *dev)
5606 {
5607         struct ni_private *devpriv = dev->private;
5608
5609         switch (dest) {
5610         case 0:
5611                 /* clear reg */
5612                 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_0_SEL(-1);
5613                 /* set reg */
5614                 devpriv->an_trig_etc_reg |= NISTC_ATRIG_ETC_GPFO_0_ENA
5615                                          |  NISTC_ATRIG_ETC_GPFO_0_SEL(src);
5616                 break;
5617         case 1:
5618                 /* clear reg */
5619                 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_1_SEL;
5620                 src = src ? NISTC_ATRIG_ETC_GPFO_1_SEL : 0;
5621                 /* set reg */
5622                 devpriv->an_trig_etc_reg |= NISTC_ATRIG_ETC_GPFO_1_ENA | src;
5623                 break;
5624         default:
5625                 return -EINVAL;
5626         }
5627
5628         ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
5629         return 0;
5630 }
5631
5632 /*
5633  * Retrieves the current source of the output selector for the given
5634  * destination.  If the terminal for the destination is not already configured
5635  * as an output, this function returns -EINVAL as error.
5636  *
5637  * Return: the register value of the destination output selector;
5638  *         -EINVAL if terminal is not configured for output.
5639  */
5640 static int get_output_select_source(int dest, struct comedi_device *dev)
5641 {
5642         struct ni_private *devpriv = dev->private;
5643         int reg = -1;
5644
5645         if (channel_is_pfi(dest)) {
5646                 if (ni_get_pfi_direction(dev, dest) == COMEDI_OUTPUT)
5647                         reg = ni_get_pfi_routing(dev, dest);
5648         } else if (channel_is_rtsi(dest)) {
5649                 if (ni_get_rtsi_direction(dev, dest) == COMEDI_OUTPUT) {
5650                         reg = ni_get_rtsi_routing(dev, dest);
5651
5652                         if (reg == NI_RTSI_OUTPUT_RGOUT0) {
5653                                 dest = NI_RGOUT0; /* prepare for lookup below */
5654                                 reg = get_rgout0_reg(dev);
5655                         } else if (reg >= NI_RTSI_OUTPUT_RTSI_BRD(0) &&
5656                                    reg <= NI_RTSI_OUTPUT_RTSI_BRD(3)) {
5657                                 const int i = reg - NI_RTSI_OUTPUT_RTSI_BRD(0);
5658
5659                                 dest = NI_RTSI_BRD(i); /* prepare for lookup */
5660                                 reg = get_ith_rtsi_brd_reg(i, dev);
5661                         }
5662                 }
5663         } else if (dest >= NI_CtrOut(0) && dest <= NI_CtrOut(-1)) {
5664                 /*
5665                  * not handled by ni_tio.  Only available for GPFO registers in
5666                  * e/m series.
5667                  */
5668                 dest -= NI_CtrOut(0);
5669                 if (dest > 1)
5670                         /* there are only two g_out outputs. */
5671                         return -EINVAL;
5672                 reg = ni_get_gout_routing(dest, dev);
5673         } else if (channel_is_ctr(dest)) {
5674                 reg = ni_tio_get_routing(devpriv->counter_dev, dest);
5675         } else {
5676                 dev_dbg(dev->class_dev, "%s: unhandled destination (%d) queried\n",
5677                         __func__, dest);
5678         }
5679
5680         if (reg >= 0)
5681                 return ni_find_route_source(CR_CHAN(reg), dest,
5682                                             &devpriv->routing_tables);
5683         return -EINVAL;
5684 }
5685
5686 /*
5687  * Test a route:
5688  *
5689  * Return: -1 if not connectible;
5690  *          0 if connectible and not connected;
5691  *          1 if connectible and connected.
5692  */
5693 static int test_route(unsigned int src, unsigned int dest,
5694                       struct comedi_device *dev)
5695 {
5696         struct ni_private *devpriv = dev->private;
5697         s8 reg = ni_route_to_register(CR_CHAN(src), dest,
5698                                       &devpriv->routing_tables);
5699
5700         if (reg < 0)
5701                 return -1;
5702         if (get_output_select_source(dest, dev) != CR_CHAN(src))
5703                 return 0;
5704         return 1;
5705 }
5706
5707 /* Connect the actual route.  */
5708 static int connect_route(unsigned int src, unsigned int dest,
5709                          struct comedi_device *dev)
5710 {
5711         struct ni_private *devpriv = dev->private;
5712         s8 reg = ni_route_to_register(CR_CHAN(src), dest,
5713                                       &devpriv->routing_tables);
5714         s8 current_src;
5715
5716         if (reg < 0)
5717                 /* route is not valid */
5718                 return -EINVAL;
5719
5720         current_src = get_output_select_source(dest, dev);
5721         if (current_src == CR_CHAN(src))
5722                 return -EALREADY;
5723         if (current_src >= 0)
5724                 /* destination mux is already busy. complain, don't overwrite */
5725                 return -EBUSY;
5726
5727         /* The route is valid and available. Now connect... */
5728         if (channel_is_pfi(dest)) {
5729                 /* set routing source, then open output */
5730                 ni_set_pfi_routing(dev, dest, reg);
5731                 ni_set_pfi_direction(dev, dest, COMEDI_OUTPUT);
5732         } else if (channel_is_rtsi(dest)) {
5733                 if (reg == NI_RTSI_OUTPUT_RGOUT0) {
5734                         int ret = incr_rgout0_src_use(src, dev);
5735
5736                         if (ret < 0)
5737                                 return ret;
5738                 } else if (ni_rtsi_route_requires_mux(reg)) {
5739                         /* Attempt to allocate and  route (src->brd) */
5740                         int brd = incr_rtsi_brd_src_use(src, dev);
5741
5742                         if (brd < 0)
5743                                 return brd;
5744
5745                         /* Now lookup the register value for (brd->dest) */
5746                         reg = ni_lookup_route_register(
5747                                 brd, dest, &devpriv->routing_tables);
5748                 }
5749
5750                 ni_set_rtsi_direction(dev, dest, COMEDI_OUTPUT);
5751                 ni_set_rtsi_routing(dev, dest, reg);
5752         } else if (dest >= NI_CtrOut(0) && dest <= NI_CtrOut(-1)) {
5753                 /*
5754                  * not handled by ni_tio.  Only available for GPFO registers in
5755                  * e/m series.
5756                  */
5757                 dest -= NI_CtrOut(0);
5758                 if (dest > 1)
5759                         /* there are only two g_out outputs. */
5760                         return -EINVAL;
5761                 if (ni_set_gout_routing(src, dest, dev))
5762                         return -EINVAL;
5763         } else if (channel_is_ctr(dest)) {
5764                 /*
5765                  * we are adding back the channel modifier info to set
5766                  * invert/edge info passed by the user
5767                  */
5768                 ni_tio_set_routing(devpriv->counter_dev, dest,
5769                                    reg | (src & ~CR_CHAN(-1)));
5770         } else {
5771                 return -EINVAL;
5772         }
5773         return 0;
5774 }
5775
5776 static int disconnect_route(unsigned int src, unsigned int dest,
5777                             struct comedi_device *dev)
5778 {
5779         struct ni_private *devpriv = dev->private;
5780         s8 reg = ni_route_to_register(CR_CHAN(src), dest,
5781                                       &devpriv->routing_tables);
5782
5783         if (reg < 0)
5784                 /* route is not valid */
5785                 return -EINVAL;
5786         if (get_output_select_source(dest, dev) != src)
5787                 /* cannot disconnect something not connected */
5788                 return -EINVAL;
5789
5790         /* The route is valid and is connected.  Now disconnect... */
5791         if (channel_is_pfi(dest)) {
5792                 /* set the pfi to high impedance, and disconnect */
5793                 ni_set_pfi_direction(dev, dest, COMEDI_INPUT);
5794                 ni_set_pfi_routing(dev, dest, NI_PFI_OUTPUT_PFI_DEFAULT);
5795         } else if (channel_is_rtsi(dest)) {
5796                 if (reg == NI_RTSI_OUTPUT_RGOUT0) {
5797                         int ret = decr_rgout0_src_use(src, dev);
5798
5799                         if (ret < 0)
5800                                 return ret;
5801                 } else if (ni_rtsi_route_requires_mux(reg)) {
5802                         /* find which RTSI_BRD line is source for rtsi pin */
5803                         int brd = ni_find_route_source(
5804                                 ni_get_rtsi_routing(dev, dest), dest,
5805                                 &devpriv->routing_tables);
5806
5807                         if (brd < 0)
5808                                 return brd;
5809
5810                         /* decrement/disconnect RTSI_BRD line from source */
5811                         decr_rtsi_brd_src_use(src, brd, dev);
5812                 }
5813
5814                 /* set rtsi output selector to default state */
5815                 reg = default_rtsi_routing[dest - TRIGGER_LINE(0)];
5816                 ni_set_rtsi_direction(dev, dest, COMEDI_INPUT);
5817                 ni_set_rtsi_routing(dev, dest, reg);
5818         } else if (dest >= NI_CtrOut(0) && dest <= NI_CtrOut(-1)) {
5819                 /*
5820                  * not handled by ni_tio.  Only available for GPFO registers in
5821                  * e/m series.
5822                  */
5823                 dest -= NI_CtrOut(0);
5824                 if (dest > 1)
5825                         /* there are only two g_out outputs. */
5826                         return -EINVAL;
5827                 reg = ni_disable_gout_routing(dest, dev);
5828         } else if (channel_is_ctr(dest)) {
5829                 ni_tio_unset_routing(devpriv->counter_dev, dest);
5830         } else {
5831                 return -EINVAL;
5832         }
5833         return 0;
5834 }
5835
5836 static int ni_global_insn_config(struct comedi_device *dev,
5837                                  struct comedi_insn *insn,
5838                                  unsigned int *data)
5839 {
5840         switch (data[0]) {
5841         case INSN_DEVICE_CONFIG_TEST_ROUTE:
5842                 data[0] = test_route(data[1], data[2], dev);
5843                 return 2;
5844         case INSN_DEVICE_CONFIG_CONNECT_ROUTE:
5845                 return connect_route(data[1], data[2], dev);
5846         case INSN_DEVICE_CONFIG_DISCONNECT_ROUTE:
5847                 return disconnect_route(data[1], data[2], dev);
5848         /*
5849          * This case is already handled one level up.
5850          * case INSN_DEVICE_CONFIG_GET_ROUTES:
5851          */
5852         default:
5853                 return -EINVAL;
5854         }
5855         return 1;
5856 }
5857
5858 #ifdef PCIDMA
5859 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5860 {
5861         struct ni_gpct *counter = s->private;
5862         int retval;
5863
5864         retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5865                                               COMEDI_INPUT);
5866         if (retval) {
5867                 dev_err(dev->class_dev,
5868                         "no dma channel available for use by counter\n");
5869                 return retval;
5870         }
5871         ni_tio_acknowledge(counter);
5872         ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5873
5874         return ni_tio_cmd(dev, s);
5875 }
5876
5877 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5878 {
5879         struct ni_gpct *counter = s->private;
5880         int retval;
5881
5882         retval = ni_tio_cancel(counter);
5883         ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5884         ni_release_gpct_mite_channel(dev, counter->counter_index);
5885         return retval;
5886 }
5887 #endif
5888
5889 static irqreturn_t ni_E_interrupt(int irq, void *d)
5890 {
5891         struct comedi_device *dev = d;
5892         struct comedi_subdevice *s_ai = dev->read_subdev;
5893         struct comedi_subdevice *s_ao = dev->write_subdev;
5894         unsigned short a_status;
5895         unsigned short b_status;
5896         unsigned long flags;
5897 #ifdef PCIDMA
5898         struct ni_private *devpriv = dev->private;
5899 #endif
5900
5901         if (!dev->attached)
5902                 return IRQ_NONE;
5903         smp_mb();               /* make sure dev->attached is checked */
5904
5905         /*  lock to avoid race with comedi_poll */
5906         spin_lock_irqsave(&dev->spinlock, flags);
5907         a_status = ni_stc_readw(dev, NISTC_AI_STATUS1_REG);
5908         b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
5909 #ifdef PCIDMA
5910         if (devpriv->mite) {
5911                 unsigned long flags_too;
5912
5913                 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
5914                 if (s_ai && devpriv->ai_mite_chan)
5915                         mite_ack_linkc(devpriv->ai_mite_chan, s_ai, false);
5916                 if (s_ao && devpriv->ao_mite_chan)
5917                         mite_ack_linkc(devpriv->ao_mite_chan, s_ao, false);
5918                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
5919         }
5920 #endif
5921         ack_a_interrupt(dev, a_status);
5922         ack_b_interrupt(dev, b_status);
5923         if (s_ai) {
5924                 if (a_status & NISTC_AI_STATUS1_INTA)
5925                         handle_a_interrupt(dev, s_ai, a_status);
5926                 /* handle any interrupt or dma events */
5927                 comedi_handle_events(dev, s_ai);
5928         }
5929         if (s_ao) {
5930                 if (b_status & NISTC_AO_STATUS1_INTB)
5931                         handle_b_interrupt(dev, s_ao, b_status);
5932                 /* handle any interrupt or dma events */
5933                 comedi_handle_events(dev, s_ao);
5934         }
5935         handle_gpct_interrupt(dev, 0);
5936         handle_gpct_interrupt(dev, 1);
5937 #ifdef PCIDMA
5938         if (devpriv->is_m_series)
5939                 handle_cdio_interrupt(dev);
5940 #endif
5941
5942         spin_unlock_irqrestore(&dev->spinlock, flags);
5943         return IRQ_HANDLED;
5944 }
5945
5946 static int ni_alloc_private(struct comedi_device *dev)
5947 {
5948         struct ni_private *devpriv;
5949
5950         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
5951         if (!devpriv)
5952                 return -ENOMEM;
5953
5954         spin_lock_init(&devpriv->window_lock);
5955         spin_lock_init(&devpriv->soft_reg_copy_lock);
5956         spin_lock_init(&devpriv->mite_channel_lock);
5957
5958         return 0;
5959 }
5960
5961 static unsigned int _ni_get_valid_routes(struct comedi_device *dev,
5962                                          unsigned int n_pairs,
5963                                          unsigned int *pair_data)
5964 {
5965         struct ni_private *devpriv = dev->private;
5966
5967         return ni_get_valid_routes(&devpriv->routing_tables, n_pairs,
5968                                    pair_data);
5969 }
5970
5971 static int ni_E_init(struct comedi_device *dev,
5972                      unsigned int interrupt_pin, unsigned int irq_polarity)
5973 {
5974         const struct ni_board_struct *board = dev->board_ptr;
5975         struct ni_private *devpriv = dev->private;
5976         struct comedi_subdevice *s;
5977         int ret;
5978         int i;
5979         const char *dev_family = devpriv->is_m_series ? "ni_mseries"
5980                                                       : "ni_eseries";
5981
5982         /* prepare the device for globally-named routes. */
5983         if (ni_assign_device_routes(dev_family, board->name,
5984                                     board->alt_route_name,
5985                                     &devpriv->routing_tables) < 0) {
5986                 dev_warn(dev->class_dev, "%s: %s device has no signal routing table.\n",
5987                          __func__, board->name);
5988                 dev_warn(dev->class_dev, "%s: High level NI signal names will not be available for this %s board.\n",
5989                          __func__, board->name);
5990         } else {
5991                 /*
5992                  * only(?) assign insn_device_config if we have global names for
5993                  * this device.
5994                  */
5995                 dev->insn_device_config = ni_global_insn_config;
5996                 dev->get_valid_routes = _ni_get_valid_routes;
5997         }
5998
5999         if (board->n_aochan > MAX_N_AO_CHAN) {
6000                 dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n");
6001                 return -EINVAL;
6002         }
6003
6004         /* initialize clock dividers */
6005         devpriv->clock_and_fout = NISTC_CLK_FOUT_SLOW_DIV2 |
6006                                   NISTC_CLK_FOUT_SLOW_TIMEBASE |
6007                                   NISTC_CLK_FOUT_TO_BOARD_DIV2 |
6008                                   NISTC_CLK_FOUT_TO_BOARD;
6009         if (!devpriv->is_6xxx) {
6010                 /* BEAM is this needed for PCI-6143 ?? */
6011                 devpriv->clock_and_fout |= (NISTC_CLK_FOUT_AI_OUT_DIV2 |
6012                                             NISTC_CLK_FOUT_AO_OUT_DIV2);
6013         }
6014         ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
6015
6016         ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
6017         if (ret)
6018                 return ret;
6019
6020         /* Analog Input subdevice */
6021         s = &dev->subdevices[NI_AI_SUBDEV];
6022         if (board->n_adchan) {
6023                 s->type         = COMEDI_SUBD_AI;
6024                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER;
6025                 if (!devpriv->is_611x)
6026                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
6027                 if (board->ai_maxdata > 0xffff)
6028                         s->subdev_flags |= SDF_LSAMPL;
6029                 if (devpriv->is_m_series)
6030                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
6031                 s->n_chan       = board->n_adchan;
6032                 s->maxdata      = board->ai_maxdata;
6033                 s->range_table  = ni_range_lkup[board->gainlkup];
6034                 s->insn_read    = ni_ai_insn_read;
6035                 s->insn_config  = ni_ai_insn_config;
6036                 if (dev->irq) {
6037                         dev->read_subdev = s;
6038                         s->subdev_flags |= SDF_CMD_READ;
6039                         s->len_chanlist = 512;
6040                         s->do_cmdtest   = ni_ai_cmdtest;
6041                         s->do_cmd       = ni_ai_cmd;
6042                         s->cancel       = ni_ai_reset;
6043                         s->poll         = ni_ai_poll;
6044                         s->munge        = ni_ai_munge;
6045
6046                         if (devpriv->mite)
6047                                 s->async_dma_dir = DMA_FROM_DEVICE;
6048                 }
6049
6050                 /* reset the analog input configuration */
6051                 ni_ai_reset(dev, s);
6052         } else {
6053                 s->type         = COMEDI_SUBD_UNUSED;
6054         }
6055
6056         /* Analog Output subdevice */
6057         s = &dev->subdevices[NI_AO_SUBDEV];
6058         if (board->n_aochan) {
6059                 s->type         = COMEDI_SUBD_AO;
6060                 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
6061                 if (devpriv->is_m_series)
6062                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
6063                 s->n_chan       = board->n_aochan;
6064                 s->maxdata      = board->ao_maxdata;
6065                 s->range_table  = board->ao_range_table;
6066                 s->insn_config  = ni_ao_insn_config;
6067                 s->insn_write   = ni_ao_insn_write;
6068
6069                 ret = comedi_alloc_subdev_readback(s);
6070                 if (ret)
6071                         return ret;
6072
6073                 /*
6074                  * Along with the IRQ we need either a FIFO or DMA for
6075                  * async command support.
6076                  */
6077                 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) {
6078                         dev->write_subdev = s;
6079                         s->subdev_flags |= SDF_CMD_WRITE;
6080                         s->len_chanlist = s->n_chan;
6081                         s->do_cmdtest   = ni_ao_cmdtest;
6082                         s->do_cmd       = ni_ao_cmd;
6083                         s->cancel       = ni_ao_reset;
6084                         if (!devpriv->is_m_series)
6085                                 s->munge        = ni_ao_munge;
6086
6087                         if (devpriv->mite)
6088                                 s->async_dma_dir = DMA_TO_DEVICE;
6089                 }
6090
6091                 if (devpriv->is_67xx)
6092                         init_ao_67xx(dev, s);
6093
6094                 /* reset the analog output configuration */
6095                 ni_ao_reset(dev, s);
6096         } else {
6097                 s->type         = COMEDI_SUBD_UNUSED;
6098         }
6099
6100         /* Digital I/O subdevice */
6101         s = &dev->subdevices[NI_DIO_SUBDEV];
6102         s->type         = COMEDI_SUBD_DIO;
6103         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
6104         s->n_chan       = board->has_32dio_chan ? 32 : 8;
6105         s->maxdata      = 1;
6106         s->range_table  = &range_digital;
6107         if (devpriv->is_m_series) {
6108 #ifdef PCIDMA
6109                 s->subdev_flags |= SDF_LSAMPL;
6110                 s->insn_bits    = ni_m_series_dio_insn_bits;
6111                 s->insn_config  = ni_m_series_dio_insn_config;
6112                 if (dev->irq) {
6113                         s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */;
6114                         s->len_chanlist = s->n_chan;
6115                         s->do_cmdtest   = ni_cdio_cmdtest;
6116                         s->do_cmd       = ni_cdio_cmd;
6117                         s->cancel       = ni_cdio_cancel;
6118
6119                         /* M-series boards use DMA */
6120                         s->async_dma_dir = DMA_BIDIRECTIONAL;
6121                 }
6122
6123                 /* reset DIO and set all channels to inputs */
6124                 ni_writel(dev, NI_M_CDO_CMD_RESET |
6125                                NI_M_CDI_CMD_RESET,
6126                           NI_M_CDIO_CMD_REG);
6127                 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
6128 #endif /* PCIDMA */
6129         } else {
6130                 s->insn_bits    = ni_dio_insn_bits;
6131                 s->insn_config  = ni_dio_insn_config;
6132
6133                 /* set all channels to inputs */
6134                 devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits);
6135                 ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
6136         }
6137
6138         /* 8255 device */
6139         s = &dev->subdevices[NI_8255_DIO_SUBDEV];
6140         if (board->has_8255) {
6141                 ret = subdev_8255_init(dev, s, ni_8255_callback,
6142                                        NI_E_8255_BASE);
6143                 if (ret)
6144                         return ret;
6145         } else {
6146                 s->type = COMEDI_SUBD_UNUSED;
6147         }
6148
6149         /* formerly general purpose counter/timer device, but no longer used */
6150         s = &dev->subdevices[NI_UNUSED_SUBDEV];
6151         s->type = COMEDI_SUBD_UNUSED;
6152
6153         /* Calibration subdevice */
6154         s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
6155         s->type         = COMEDI_SUBD_CALIB;
6156         s->subdev_flags = SDF_INTERNAL;
6157         s->n_chan       = 1;
6158         s->maxdata      = 0;
6159         if (devpriv->is_m_series) {
6160                 /* internal PWM output used for AI nonlinearity calibration */
6161                 s->insn_config  = ni_m_series_pwm_config;
6162
6163                 ni_writel(dev, 0x0, NI_M_CAL_PWM_REG);
6164         } else if (devpriv->is_6143) {
6165                 /* internal PWM output used for AI nonlinearity calibration */
6166                 s->insn_config  = ni_6143_pwm_config;
6167         } else {
6168                 s->subdev_flags |= SDF_WRITABLE;
6169                 s->insn_read    = ni_calib_insn_read;
6170                 s->insn_write   = ni_calib_insn_write;
6171
6172                 /* setup the caldacs and find the real n_chan and maxdata */
6173                 caldac_setup(dev, s);
6174         }
6175
6176         /* EEPROM subdevice */
6177         s = &dev->subdevices[NI_EEPROM_SUBDEV];
6178         s->type         = COMEDI_SUBD_MEMORY;
6179         s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
6180         s->maxdata      = 0xff;
6181         if (devpriv->is_m_series) {
6182                 s->n_chan       = M_SERIES_EEPROM_SIZE;
6183                 s->insn_read    = ni_m_series_eeprom_insn_read;
6184         } else {
6185                 s->n_chan       = 512;
6186                 s->insn_read    = ni_eeprom_insn_read;
6187         }
6188
6189         /* Digital I/O (PFI) subdevice */
6190         s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
6191         s->type         = COMEDI_SUBD_DIO;
6192         s->maxdata      = 1;
6193         if (devpriv->is_m_series) {
6194                 s->n_chan       = 16;
6195                 s->insn_bits    = ni_pfi_insn_bits;
6196                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
6197
6198                 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
6199                 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
6200                         ni_writew(dev, devpriv->pfi_output_select_reg[i],
6201                                   NI_M_PFI_OUT_SEL_REG(i));
6202                 }
6203         } else {
6204                 s->n_chan       = 10;
6205                 s->subdev_flags = SDF_INTERNAL;
6206         }
6207         s->insn_config  = ni_pfi_insn_config;
6208
6209         ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, ~0, 0);
6210
6211         /* cs5529 calibration adc */
6212         s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
6213         if (devpriv->is_67xx) {
6214                 s->type = COMEDI_SUBD_AI;
6215                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
6216                 /*  one channel for each analog output channel */
6217                 s->n_chan = board->n_aochan;
6218                 s->maxdata = BIT(16) - 1;
6219                 s->range_table = &range_unknown;        /* XXX */
6220                 s->insn_read = cs5529_ai_insn_read;
6221                 s->insn_config = NULL;
6222                 init_cs5529(dev);
6223         } else {
6224                 s->type = COMEDI_SUBD_UNUSED;
6225         }
6226
6227         /* Serial */
6228         s = &dev->subdevices[NI_SERIAL_SUBDEV];
6229         s->type = COMEDI_SUBD_SERIAL;
6230         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
6231         s->n_chan = 1;
6232         s->maxdata = 0xff;
6233         s->insn_config = ni_serial_insn_config;
6234         devpriv->serial_interval_ns = 0;
6235         devpriv->serial_hw_mode = 0;
6236
6237         /* RTSI */
6238         s = &dev->subdevices[NI_RTSI_SUBDEV];
6239         s->type = COMEDI_SUBD_DIO;
6240         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
6241         s->n_chan = 8;
6242         s->maxdata = 1;
6243         s->insn_bits = ni_rtsi_insn_bits;
6244         s->insn_config = ni_rtsi_insn_config;
6245         ni_rtsi_init(dev);
6246
6247         /* allocate and initialize the gpct counter device */
6248         devpriv->counter_dev = ni_gpct_device_construct(dev,
6249                                         ni_gpct_write_register,
6250                                         ni_gpct_read_register,
6251                                         (devpriv->is_m_series)
6252                                                 ? ni_gpct_variant_m_series
6253                                                 : ni_gpct_variant_e_series,
6254                                         NUM_GPCT,
6255                                         NUM_GPCT,
6256                                         &devpriv->routing_tables);
6257         if (!devpriv->counter_dev)
6258                 return -ENOMEM;
6259
6260         /* Counter (gpct) subdevices */
6261         for (i = 0; i < NUM_GPCT; ++i) {
6262                 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i];
6263
6264                 /* setup and initialize the counter */
6265                 ni_tio_init_counter(gpct);
6266
6267                 s = &dev->subdevices[NI_GPCT_SUBDEV(i)];
6268                 s->type         = COMEDI_SUBD_COUNTER;
6269                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
6270                 s->n_chan       = 3;
6271                 s->maxdata      = (devpriv->is_m_series) ? 0xffffffff
6272                                                          : 0x00ffffff;
6273                 s->insn_read    = ni_tio_insn_read;
6274                 s->insn_write   = ni_tio_insn_write;
6275                 s->insn_config  = ni_tio_insn_config;
6276 #ifdef PCIDMA
6277                 if (dev->irq && devpriv->mite) {
6278                         s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
6279                         s->len_chanlist = 1;
6280                         s->do_cmdtest   = ni_tio_cmdtest;
6281                         s->do_cmd       = ni_gpct_cmd;
6282                         s->cancel       = ni_gpct_cancel;
6283
6284                         s->async_dma_dir = DMA_BIDIRECTIONAL;
6285                 }
6286 #endif
6287                 s->private      = gpct;
6288         }
6289
6290         /* Initialize GPFO_{0,1} to produce output of counters */
6291         ni_set_gout_routing(0, 0, dev); /* output of counter 0; DAQ STC, p338 */
6292         ni_set_gout_routing(0, 1, dev); /* output of counter 1; DAQ STC, p338 */
6293
6294         /* Frequency output subdevice */
6295         s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
6296         s->type         = COMEDI_SUBD_COUNTER;
6297         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
6298         s->n_chan       = 1;
6299         s->maxdata      = 0xf;
6300         s->insn_read    = ni_freq_out_insn_read;
6301         s->insn_write   = ni_freq_out_insn_write;
6302         s->insn_config  = ni_freq_out_insn_config;
6303
6304         if (dev->irq) {
6305                 ni_stc_writew(dev,
6306                               (irq_polarity ? NISTC_INT_CTRL_INT_POL : 0) |
6307                               (NISTC_INT_CTRL_3PIN_INT & 0) |
6308                               NISTC_INT_CTRL_INTA_ENA |
6309                               NISTC_INT_CTRL_INTB_ENA |
6310                               NISTC_INT_CTRL_INTA_SEL(interrupt_pin) |
6311                               NISTC_INT_CTRL_INTB_SEL(interrupt_pin),
6312                               NISTC_INT_CTRL_REG);
6313         }
6314
6315         /* DMA setup */
6316         ni_writeb(dev, devpriv->ai_ao_select_reg, NI_E_DMA_AI_AO_SEL_REG);
6317         ni_writeb(dev, devpriv->g0_g1_select_reg, NI_E_DMA_G0_G1_SEL_REG);
6318
6319         if (devpriv->is_6xxx) {
6320                 ni_writeb(dev, 0, NI611X_MAGIC_REG);
6321         } else if (devpriv->is_m_series) {
6322                 int channel;
6323
6324                 for (channel = 0; channel < board->n_aochan; ++channel) {
6325                         ni_writeb(dev, 0xf,
6326                                   NI_M_AO_WAVEFORM_ORDER_REG(channel));
6327                         ni_writeb(dev, 0x0,
6328                                   NI_M_AO_REF_ATTENUATION_REG(channel));
6329                 }
6330                 ni_writeb(dev, 0x0, NI_M_AO_CALIB_REG);
6331         }
6332
6333         return 0;
6334 }
6335
6336 static void mio_common_detach(struct comedi_device *dev)
6337 {
6338         struct ni_private *devpriv = dev->private;
6339
6340         if (devpriv)
6341                 ni_gpct_device_destroy(devpriv->counter_dev);
6342 }