drivers/staging/comedi/drivers/ni_mio_common.c

   1 /*
   2  * Hardware driver for DAQ-STC based boards
   3  *
   4  * COMEDI - Linux Control and Measurement Device Interface
   5  * Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   6  * Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 /*
  20  * This file is meant to be included by another file, e.g.,
  21  * ni_atmio.c or ni_pcimio.c.
  22  *
  23  * Interrupt support originally added by Truxton Fulton <trux@truxton.com>
  24  *
  25  * References (ftp://ftp.natinst.com/support/manuals):
  26  *   340747b.pdf  AT-MIO E series Register Level Programmer Manual
  27  *   341079b.pdf  PCI E Series RLPM
  28  *   340934b.pdf  DAQ-STC reference manual
  29  *
  30  * 67xx and 611x registers (ftp://ftp.ni.com/support/daq/mhddk/documentation/)
  31  *   release_ni611x.pdf
  32  *   release_ni67xx.pdf
  33  *
  34  * Other possibly relevant info:
  35  *   320517c.pdf  User manual (obsolete)
  36  *   320517f.pdf  User manual (new)
  37  *   320889a.pdf  delete
  38  *   320906c.pdf  maximum signal ratings
  39  *   321066a.pdf  about 16x
  40  *   321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  41  *   321808a.pdf  about at-mio-16e-10 rev P
  42  *   321837a.pdf  discontinuation of at-mio-16de-10 rev d
  43  *   321838a.pdf  about at-mio-16de-10 rev N
  44  *
  45  * ISSUES:
  46  *   - the interrupt routine needs to be cleaned up
  47  *
  48  * 2006-02-07: S-Series PCI-6143: Support has been added but is not
  49  * fully tested as yet. Terry Barnaby, BEAM Ltd.
  50  */
  51
  52 #include <linux/interrupt.h>
  53 #include <linux/sched.h>
  54 #include <linux/delay.h>
  55 #include "8255.h"
  56 #include "mite.h"
  57
  58 /* A timeout count */
  59 #define NI_TIMEOUT 1000
  60
  61 /* Note: this table must match the ai_gain_* definitions */
  62 static const short ni_gainlkup[][16] = {
  63         [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
  64                         0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  65         [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
  66         [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
  67                         0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  68         [ai_gain_4] = {0, 1, 4, 7},
  69         [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
  70                           0x003, 0x004, 0x005, 0x006},
  71         [ai_gain_622x] = {0, 1, 4, 5},
  72         [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
  73         [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  74 };
  75
  76 static const struct comedi_lrange range_ni_E_ai = {
  77         16, {
  78                 BIP_RANGE(10),
  79                 BIP_RANGE(5),
  80                 BIP_RANGE(2.5),
  81                 BIP_RANGE(1),
  82                 BIP_RANGE(0.5),
  83                 BIP_RANGE(0.25),
  84                 BIP_RANGE(0.1),
  85                 BIP_RANGE(0.05),
  86                 UNI_RANGE(20),
  87                 UNI_RANGE(10),
  88                 UNI_RANGE(5),
  89                 UNI_RANGE(2),
  90                 UNI_RANGE(1),
  91                 UNI_RANGE(0.5),
  92                 UNI_RANGE(0.2),
  93                 UNI_RANGE(0.1)
  94         }
  95 };
  96
  97 static const struct comedi_lrange range_ni_E_ai_limited = {
  98         8, {
  99                 BIP_RANGE(10),
 100                 BIP_RANGE(5),
 101                 BIP_RANGE(1),
 102                 BIP_RANGE(0.1),
 103                 UNI_RANGE(10),
 104                 UNI_RANGE(5),
 105                 UNI_RANGE(1),
 106                 UNI_RANGE(0.1)
 107         }
 108 };
 109
 110 static const struct comedi_lrange range_ni_E_ai_limited14 = {
 111         14, {
 112                 BIP_RANGE(10),
 113                 BIP_RANGE(5),
 114                 BIP_RANGE(2),
 115                 BIP_RANGE(1),
 116                 BIP_RANGE(0.5),
 117                 BIP_RANGE(0.2),
 118                 BIP_RANGE(0.1),
 119                 UNI_RANGE(10),
 120                 UNI_RANGE(5),
 121                 UNI_RANGE(2),
 122                 UNI_RANGE(1),
 123                 UNI_RANGE(0.5),
 124                 UNI_RANGE(0.2),
 125                 UNI_RANGE(0.1)
 126         }
 127 };
 128
 129 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
 130         4, {
 131                 BIP_RANGE(10),
 132                 BIP_RANGE(5),
 133                 BIP_RANGE(0.5),
 134                 BIP_RANGE(0.05)
 135         }
 136 };
 137
 138 static const struct comedi_lrange range_ni_E_ai_611x = {
 139         8, {
 140                 BIP_RANGE(50),
 141                 BIP_RANGE(20),
 142                 BIP_RANGE(10),
 143                 BIP_RANGE(5),
 144                 BIP_RANGE(2),
 145                 BIP_RANGE(1),
 146                 BIP_RANGE(0.5),
 147                 BIP_RANGE(0.2)
 148         }
 149 };
 150
 151 static const struct comedi_lrange range_ni_M_ai_622x = {
 152         4, {
 153                 BIP_RANGE(10),
 154                 BIP_RANGE(5),
 155                 BIP_RANGE(1),
 156                 BIP_RANGE(0.2)
 157         }
 158 };
 159
 160 static const struct comedi_lrange range_ni_M_ai_628x = {
 161         7, {
 162                 BIP_RANGE(10),
 163                 BIP_RANGE(5),
 164                 BIP_RANGE(2),
 165                 BIP_RANGE(1),
 166                 BIP_RANGE(0.5),
 167                 BIP_RANGE(0.2),
 168                 BIP_RANGE(0.1)
 169         }
 170 };
 171
 172 static const struct comedi_lrange range_ni_E_ao_ext = {
 173         4, {
 174                 BIP_RANGE(10),
 175                 UNI_RANGE(10),
 176                 RANGE_ext(-1, 1),
 177                 RANGE_ext(0, 1)
 178         }
 179 };
 180
 181 static const struct comedi_lrange *const ni_range_lkup[] = {
 182         [ai_gain_16] = &range_ni_E_ai,
 183         [ai_gain_8] = &range_ni_E_ai_limited,
 184         [ai_gain_14] = &range_ni_E_ai_limited14,
 185         [ai_gain_4] = &range_ni_E_ai_bipolar4,
 186         [ai_gain_611x] = &range_ni_E_ai_611x,
 187         [ai_gain_622x] = &range_ni_M_ai_622x,
 188         [ai_gain_628x] = &range_ni_M_ai_628x,
 189         [ai_gain_6143] = &range_bipolar5
 190 };
 191
 192 enum aimodes {
 193         AIMODE_NONE = 0,
 194         AIMODE_HALF_FULL = 1,
 195         AIMODE_SCAN = 2,
 196         AIMODE_SAMPLE = 3,
 197 };
 198
 199 enum ni_common_subdevices {
 200         NI_AI_SUBDEV,
 201         NI_AO_SUBDEV,
 202         NI_DIO_SUBDEV,
 203         NI_8255_DIO_SUBDEV,
 204         NI_UNUSED_SUBDEV,
 205         NI_CALIBRATION_SUBDEV,
 206         NI_EEPROM_SUBDEV,
 207         NI_PFI_DIO_SUBDEV,
 208         NI_CS5529_CALIBRATION_SUBDEV,
 209         NI_SERIAL_SUBDEV,
 210         NI_RTSI_SUBDEV,
 211         NI_GPCT0_SUBDEV,
 212         NI_GPCT1_SUBDEV,
 213         NI_FREQ_OUT_SUBDEV,
 214         NI_NUM_SUBDEVICES
 215 };
 216
 217 #define NI_GPCT_SUBDEV(x)       (NI_GPCT0_SUBDEV + (x))
 218
 219 enum timebase_nanoseconds {
 220         TIMEBASE_1_NS = 50,
 221         TIMEBASE_2_NS = 10000
 222 };
 223
 224 #define SERIAL_DISABLED         0
 225 #define SERIAL_600NS            600
 226 #define SERIAL_1_2US            1200
 227 #define SERIAL_10US                     10000
 228
 229 static const int num_adc_stages_611x = 3;
 230
 231 static void ni_writel(struct comedi_device *dev, unsigned int data, int reg)
 232 {
 233         if (dev->mmio)
 234                 writel(data, dev->mmio + reg);
 235         else
 236                 outl(data, dev->iobase + reg);
 237 }
 238
 239 static void ni_writew(struct comedi_device *dev, unsigned int data, int reg)
 240 {
 241         if (dev->mmio)
 242                 writew(data, dev->mmio + reg);
 243         else
 244                 outw(data, dev->iobase + reg);
 245 }
 246
 247 static void ni_writeb(struct comedi_device *dev, unsigned int data, int reg)
 248 {
 249         if (dev->mmio)
 250                 writeb(data, dev->mmio + reg);
 251         else
 252                 outb(data, dev->iobase + reg);
 253 }
 254
 255 static unsigned int ni_readl(struct comedi_device *dev, int reg)
 256 {
 257         if (dev->mmio)
 258                 return readl(dev->mmio + reg);
 259
 260         return inl(dev->iobase + reg);
 261 }
 262
 263 static unsigned int ni_readw(struct comedi_device *dev, int reg)
 264 {
 265         if (dev->mmio)
 266                 return readw(dev->mmio + reg);
 267
 268         return inw(dev->iobase + reg);
 269 }
 270
 271 static unsigned int ni_readb(struct comedi_device *dev, int reg)
 272 {
 273         if (dev->mmio)
 274                 return readb(dev->mmio + reg);
 275
 276         return inb(dev->iobase + reg);
 277 }
 278
 279 /*
 280  * We automatically take advantage of STC registers that can be
 281  * read/written directly in the I/O space of the board.
 282  *
 283  * The AT-MIO and DAQCard devices map the low 8 STC registers to
 284  * iobase+reg*2.
 285  *
 286  * Most PCIMIO devices also map the low 8 STC registers but the
 287  * 611x devices map the read registers to iobase+(addr-1)*2.
 288  * For now non-windowed STC access is disabled if a PCIMIO device
 289  * is detected (devpriv->mite has been initialized).
 290  *
 291  * The M series devices do not used windowed registers for the
 292  * STC registers. The functions below handle the mapping of the
 293  * windowed STC registers to the m series register offsets.
 294  */
 295
 296 struct mio_regmap {
 297         unsigned int mio_reg;
 298         int size;
 299 };
 300
 301 static const struct mio_regmap m_series_stc_write_regmap[] = {
 302         [NISTC_INTA_ACK_REG]            = { 0x104, 2 },
 303         [NISTC_INTB_ACK_REG]            = { 0x106, 2 },
 304         [NISTC_AI_CMD2_REG]             = { 0x108, 2 },
 305         [NISTC_AO_CMD2_REG]             = { 0x10a, 2 },
 306         [NISTC_G0_CMD_REG]              = { 0x10c, 2 },
 307         [NISTC_G1_CMD_REG]              = { 0x10e, 2 },
 308         [NISTC_AI_CMD1_REG]             = { 0x110, 2 },
 309         [NISTC_AO_CMD1_REG]             = { 0x112, 2 },
 310         /*
 311          * NISTC_DIO_OUT_REG maps to:
 312          * { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 }
 313          */
 314         [NISTC_DIO_OUT_REG]             = { 0, 0 }, /* DOES NOT MAP CLEANLY */
 315         [NISTC_DIO_CTRL_REG]            = { 0, 0 }, /* DOES NOT MAP CLEANLY */
 316         [NISTC_AI_MODE1_REG]            = { 0x118, 2 },
 317         [NISTC_AI_MODE2_REG]            = { 0x11a, 2 },
 318         [NISTC_AI_SI_LOADA_REG]         = { 0x11c, 4 },
 319         [NISTC_AI_SI_LOADB_REG]         = { 0x120, 4 },
 320         [NISTC_AI_SC_LOADA_REG]         = { 0x124, 4 },
 321         [NISTC_AI_SC_LOADB_REG]         = { 0x128, 4 },
 322         [NISTC_AI_SI2_LOADA_REG]        = { 0x12c, 4 },
 323         [NISTC_AI_SI2_LOADB_REG]        = { 0x130, 4 },
 324         [NISTC_G0_MODE_REG]             = { 0x134, 2 },
 325         [NISTC_G1_MODE_REG]             = { 0x136, 2 },
 326         [NISTC_G0_LOADA_REG]            = { 0x138, 4 },
 327         [NISTC_G0_LOADB_REG]            = { 0x13c, 4 },
 328         [NISTC_G1_LOADA_REG]            = { 0x140, 4 },
 329         [NISTC_G1_LOADB_REG]            = { 0x144, 4 },
 330         [NISTC_G0_INPUT_SEL_REG]        = { 0x148, 2 },
 331         [NISTC_G1_INPUT_SEL_REG]        = { 0x14a, 2 },
 332         [NISTC_AO_MODE1_REG]            = { 0x14c, 2 },
 333         [NISTC_AO_MODE2_REG]            = { 0x14e, 2 },
 334         [NISTC_AO_UI_LOADA_REG]         = { 0x150, 4 },
 335         [NISTC_AO_UI_LOADB_REG]         = { 0x154, 4 },
 336         [NISTC_AO_BC_LOADA_REG]         = { 0x158, 4 },
 337         [NISTC_AO_BC_LOADB_REG]         = { 0x15c, 4 },
 338         [NISTC_AO_UC_LOADA_REG]         = { 0x160, 4 },
 339         [NISTC_AO_UC_LOADB_REG]         = { 0x164, 4 },
 340         [NISTC_CLK_FOUT_REG]            = { 0x170, 2 },
 341         [NISTC_IO_BIDIR_PIN_REG]        = { 0x172, 2 },
 342         [NISTC_RTSI_TRIG_DIR_REG]       = { 0x174, 2 },
 343         [NISTC_INT_CTRL_REG]            = { 0x176, 2 },
 344         [NISTC_AI_OUT_CTRL_REG]         = { 0x178, 2 },
 345         [NISTC_ATRIG_ETC_REG]           = { 0x17a, 2 },
 346         [NISTC_AI_START_STOP_REG]       = { 0x17c, 2 },
 347         [NISTC_AI_TRIG_SEL_REG]         = { 0x17e, 2 },
 348         [NISTC_AI_DIV_LOADA_REG]        = { 0x180, 4 },
 349         [NISTC_AO_START_SEL_REG]        = { 0x184, 2 },
 350         [NISTC_AO_TRIG_SEL_REG]         = { 0x186, 2 },
 351         [NISTC_G0_AUTOINC_REG]          = { 0x188, 2 },
 352         [NISTC_G1_AUTOINC_REG]          = { 0x18a, 2 },
 353         [NISTC_AO_MODE3_REG]            = { 0x18c, 2 },
 354         [NISTC_RESET_REG]               = { 0x190, 2 },
 355         [NISTC_INTA_ENA_REG]            = { 0x192, 2 },
 356         [NISTC_INTA2_ENA_REG]           = { 0, 0 }, /* E-Series only */
 357         [NISTC_INTB_ENA_REG]            = { 0x196, 2 },
 358         [NISTC_INTB2_ENA_REG]           = { 0, 0 }, /* E-Series only */
 359         [NISTC_AI_PERSONAL_REG]         = { 0x19a, 2 },
 360         [NISTC_AO_PERSONAL_REG]         = { 0x19c, 2 },
 361         [NISTC_RTSI_TRIGA_OUT_REG]      = { 0x19e, 2 },
 362         [NISTC_RTSI_TRIGB_OUT_REG]      = { 0x1a0, 2 },
 363         [NISTC_RTSI_BOARD_REG]          = { 0, 0 }, /* Unknown */
 364         [NISTC_CFG_MEM_CLR_REG]         = { 0x1a4, 2 },
 365         [NISTC_ADC_FIFO_CLR_REG]        = { 0x1a6, 2 },
 366         [NISTC_DAC_FIFO_CLR_REG]        = { 0x1a8, 2 },
 367         [NISTC_AO_OUT_CTRL_REG]         = { 0x1ac, 2 },
 368         [NISTC_AI_MODE3_REG]            = { 0x1ae, 2 },
 369 };
 370
 371 static void m_series_stc_write(struct comedi_device *dev,
 372                                unsigned int data, unsigned int reg)
 373 {
 374         const struct mio_regmap *regmap;
 375
 376         if (reg < ARRAY_SIZE(m_series_stc_write_regmap)) {
 377                 regmap = &m_series_stc_write_regmap[reg];
 378         } else {
 379                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
 380                          __func__, reg);
 381                 return;
 382         }
 383
 384         switch (regmap->size) {
 385         case 4:
 386                 ni_writel(dev, data, regmap->mio_reg);
 387                 break;
 388         case 2:
 389                 ni_writew(dev, data, regmap->mio_reg);
 390                 break;
 391         default:
 392                 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
 393                          __func__, reg);
 394                 break;
 395         }
 396 }
 397
 398 static const struct mio_regmap m_series_stc_read_regmap[] = {
 399         [NISTC_AI_STATUS1_REG]          = { 0x104, 2 },
 400         [NISTC_AO_STATUS1_REG]          = { 0x106, 2 },
 401         [NISTC_G01_STATUS_REG]          = { 0x108, 2 },
 402         [NISTC_AI_STATUS2_REG]          = { 0, 0 }, /* Unknown */
 403         [NISTC_AO_STATUS2_REG]          = { 0x10c, 2 },
 404         [NISTC_DIO_IN_REG]              = { 0, 0 }, /* Unknown */
 405         [NISTC_G0_HW_SAVE_REG]          = { 0x110, 4 },
 406         [NISTC_G1_HW_SAVE_REG]          = { 0x114, 4 },
 407         [NISTC_G0_SAVE_REG]             = { 0x118, 4 },
 408         [NISTC_G1_SAVE_REG]             = { 0x11c, 4 },
 409         [NISTC_AO_UI_SAVE_REG]          = { 0x120, 4 },
 410         [NISTC_AO_BC_SAVE_REG]          = { 0x124, 4 },
 411         [NISTC_AO_UC_SAVE_REG]          = { 0x128, 4 },
 412         [NISTC_STATUS1_REG]             = { 0x136, 2 },
 413         [NISTC_DIO_SERIAL_IN_REG]       = { 0x009, 1 },
 414         [NISTC_STATUS2_REG]             = { 0x13a, 2 },
 415         [NISTC_AI_SI_SAVE_REG]          = { 0x180, 4 },
 416         [NISTC_AI_SC_SAVE_REG]          = { 0x184, 4 },
 417 };
 418
 419 static unsigned int m_series_stc_read(struct comedi_device *dev,
 420                                       unsigned int reg)
 421 {
 422         const struct mio_regmap *regmap;
 423
 424         if (reg < ARRAY_SIZE(m_series_stc_read_regmap)) {
 425                 regmap = &m_series_stc_read_regmap[reg];
 426         } else {
 427                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
 428                          __func__, reg);
 429                 return 0;
 430         }
 431
 432         switch (regmap->size) {
 433         case 4:
 434                 return ni_readl(dev, regmap->mio_reg);
 435         case 2:
 436                 return ni_readw(dev, regmap->mio_reg);
 437         case 1:
 438                 return ni_readb(dev, regmap->mio_reg);
 439         default:
 440                 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
 441                          __func__, reg);
 442                 return 0;
 443         }
 444 }
 445
 446 static void ni_stc_writew(struct comedi_device *dev,
 447                           unsigned int data, int reg)
 448 {
 449         struct ni_private *devpriv = dev->private;
 450         unsigned long flags;
 451
 452         if (devpriv->is_m_series) {
 453                 m_series_stc_write(dev, data, reg);
 454         } else {
 455                 spin_lock_irqsave(&devpriv->window_lock, flags);
 456                 if (!devpriv->mite && reg < 8) {
 457                         ni_writew(dev, data, reg * 2);
 458                 } else {
 459                         ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
 460                         ni_writew(dev, data, NI_E_STC_WINDOW_DATA_REG);
 461                 }
 462                 spin_unlock_irqrestore(&devpriv->window_lock, flags);
 463         }
 464 }
 465
 466 static void ni_stc_writel(struct comedi_device *dev,
 467                           unsigned int data, int reg)
 468 {
 469         struct ni_private *devpriv = dev->private;
 470
 471         if (devpriv->is_m_series) {
 472                 m_series_stc_write(dev, data, reg);
 473         } else {
 474                 ni_stc_writew(dev, data >> 16, reg);
 475                 ni_stc_writew(dev, data & 0xffff, reg + 1);
 476         }
 477 }
 478
 479 static unsigned int ni_stc_readw(struct comedi_device *dev, int reg)
 480 {
 481         struct ni_private *devpriv = dev->private;
 482         unsigned long flags;
 483         unsigned int val;
 484
 485         if (devpriv->is_m_series) {
 486                 val = m_series_stc_read(dev, reg);
 487         } else {
 488                 spin_lock_irqsave(&devpriv->window_lock, flags);
 489                 if (!devpriv->mite && reg < 8) {
 490                         val = ni_readw(dev, reg * 2);
 491                 } else {
 492                         ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
 493                         val = ni_readw(dev, NI_E_STC_WINDOW_DATA_REG);
 494                 }
 495                 spin_unlock_irqrestore(&devpriv->window_lock, flags);
 496         }
 497         return val;
 498 }
 499
 500 static unsigned int ni_stc_readl(struct comedi_device *dev, int reg)
 501 {
 502         struct ni_private *devpriv = dev->private;
 503         unsigned int val;
 504
 505         if (devpriv->is_m_series) {
 506                 val = m_series_stc_read(dev, reg);
 507         } else {
 508                 val = ni_stc_readw(dev, reg) << 16;
 509                 val |= ni_stc_readw(dev, reg + 1);
 510         }
 511         return val;
 512 }
 513
 514 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
 515                                    unsigned int bit_mask,
 516                                    unsigned int bit_values)
 517 {
 518         struct ni_private *devpriv = dev->private;
 519         unsigned long flags;
 520
 521         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 522         switch (reg) {
 523         case NISTC_INTA_ENA_REG:
 524                 devpriv->int_a_enable_reg &= ~bit_mask;
 525                 devpriv->int_a_enable_reg |= bit_values & bit_mask;
 526                 ni_stc_writew(dev, devpriv->int_a_enable_reg, reg);
 527                 break;
 528         case NISTC_INTB_ENA_REG:
 529                 devpriv->int_b_enable_reg &= ~bit_mask;
 530                 devpriv->int_b_enable_reg |= bit_values & bit_mask;
 531                 ni_stc_writew(dev, devpriv->int_b_enable_reg, reg);
 532                 break;
 533         case NISTC_IO_BIDIR_PIN_REG:
 534                 devpriv->io_bidirection_pin_reg &= ~bit_mask;
 535                 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
 536                 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg);
 537                 break;
 538         case NI_E_DMA_AI_AO_SEL_REG:
 539                 devpriv->ai_ao_select_reg &= ~bit_mask;
 540                 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
 541                 ni_writeb(dev, devpriv->ai_ao_select_reg, reg);
 542                 break;
 543         case NI_E_DMA_G0_G1_SEL_REG:
 544                 devpriv->g0_g1_select_reg &= ~bit_mask;
 545                 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
 546                 ni_writeb(dev, devpriv->g0_g1_select_reg, reg);
 547                 break;
 548         case NI_M_CDIO_DMA_SEL_REG:
 549                 devpriv->cdio_dma_select_reg &= ~bit_mask;
 550                 devpriv->cdio_dma_select_reg |= bit_values & bit_mask;
 551                 ni_writeb(dev, devpriv->cdio_dma_select_reg, reg);
 552                 break;
 553         default:
 554                 dev_err(dev->class_dev, "called with invalid register %d\n",
 555                         reg);
 556                 break;
 557         }
 558         mmiowb();
 559         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 560 }
 561
 562 #ifdef PCIDMA
 563
 564 /* selects the MITE channel to use for DMA */
 565 #define NI_STC_DMA_CHAN_SEL(x)  (((x) < 4) ? BIT(x) :   \
 566                                  ((x) == 4) ? 0x3 :     \
 567                                  ((x) == 5) ? 0x5 : 0x0)
 568
 569 /* DMA channel setup */
 570 static int ni_request_ai_mite_channel(struct comedi_device *dev)
 571 {
 572         struct ni_private *devpriv = dev->private;
 573         struct mite_channel *mite_chan;
 574         unsigned long flags;
 575         unsigned int bits;
 576
 577         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 578         mite_chan = mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
 579         if (!mite_chan) {
 580                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 581                 dev_err(dev->class_dev,
 582                         "failed to reserve mite dma channel for analog input\n");
 583                 return -EBUSY;
 584         }
 585         mite_chan->dir = COMEDI_INPUT;
 586         devpriv->ai_mite_chan = mite_chan;
 587
 588         bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
 589         ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 590                         NI_E_DMA_AI_SEL_MASK, NI_E_DMA_AI_SEL(bits));
 591
 592         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 593         return 0;
 594 }
 595
 596 static int ni_request_ao_mite_channel(struct comedi_device *dev)
 597 {
 598         struct ni_private *devpriv = dev->private;
 599         struct mite_channel *mite_chan;
 600         unsigned long flags;
 601         unsigned int bits;
 602
 603         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 604         mite_chan = mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
 605         if (!mite_chan) {
 606                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 607                 dev_err(dev->class_dev,
 608                         "failed to reserve mite dma channel for analog outut\n");
 609                 return -EBUSY;
 610         }
 611         mite_chan->dir = COMEDI_OUTPUT;
 612         devpriv->ao_mite_chan = mite_chan;
 613
 614         bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
 615         ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 616                         NI_E_DMA_AO_SEL_MASK, NI_E_DMA_AO_SEL(bits));
 617
 618         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 619         return 0;
 620 }
 621
 622 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
 623                                         unsigned int gpct_index,
 624                                         enum comedi_io_direction direction)
 625 {
 626         struct ni_private *devpriv = dev->private;
 627         struct ni_gpct *counter = &devpriv->counter_dev->counters[gpct_index];
 628         struct mite_channel *mite_chan;
 629         unsigned long flags;
 630         unsigned int bits;
 631
 632         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 633         mite_chan = mite_request_channel(devpriv->mite,
 634                                          devpriv->gpct_mite_ring[gpct_index]);
 635         if (!mite_chan) {
 636                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 637                 dev_err(dev->class_dev,
 638                         "failed to reserve mite dma channel for counter\n");
 639                 return -EBUSY;
 640         }
 641         mite_chan->dir = direction;
 642         ni_tio_set_mite_channel(counter, mite_chan);
 643
 644         bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
 645         ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
 646                         NI_E_DMA_G0_G1_SEL_MASK(gpct_index),
 647                         NI_E_DMA_G0_G1_SEL(gpct_index, bits));
 648
 649         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 650         return 0;
 651 }
 652
 653 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
 654 {
 655         struct ni_private *devpriv = dev->private;
 656         struct mite_channel *mite_chan;
 657         unsigned long flags;
 658         unsigned int bits;
 659
 660         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 661         mite_chan = mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
 662         if (!mite_chan) {
 663                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 664                 dev_err(dev->class_dev,
 665                         "failed to reserve mite dma channel for correlated digital output\n");
 666                 return -EBUSY;
 667         }
 668         mite_chan->dir = COMEDI_OUTPUT;
 669         devpriv->cdo_mite_chan = mite_chan;
 670
 671         /*
 672          * XXX just guessing NI_STC_DMA_CHAN_SEL()
 673          * returns the right bits, under the assumption the cdio dma
 674          * selection works just like ai/ao/gpct.
 675          * Definitely works for dma channels 0 and 1.
 676          */
 677         bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
 678         ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG,
 679                         NI_M_CDIO_DMA_SEL_CDO_MASK,
 680                         NI_M_CDIO_DMA_SEL_CDO(bits));
 681
 682         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 683         return 0;
 684 }
 685 #endif /*  PCIDMA */
 686
 687 static void ni_release_ai_mite_channel(struct comedi_device *dev)
 688 {
 689 #ifdef PCIDMA
 690         struct ni_private *devpriv = dev->private;
 691         unsigned long flags;
 692
 693         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 694         if (devpriv->ai_mite_chan) {
 695                 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 696                                 NI_E_DMA_AI_SEL_MASK, 0);
 697                 mite_release_channel(devpriv->ai_mite_chan);
 698                 devpriv->ai_mite_chan = NULL;
 699         }
 700         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 701 #endif /*  PCIDMA */
 702 }
 703
 704 static void ni_release_ao_mite_channel(struct comedi_device *dev)
 705 {
 706 #ifdef PCIDMA
 707         struct ni_private *devpriv = dev->private;
 708         unsigned long flags;
 709
 710         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 711         if (devpriv->ao_mite_chan) {
 712                 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 713                                 NI_E_DMA_AO_SEL_MASK, 0);
 714                 mite_release_channel(devpriv->ao_mite_chan);
 715                 devpriv->ao_mite_chan = NULL;
 716         }
 717         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 718 #endif /*  PCIDMA */
 719 }
 720
 721 #ifdef PCIDMA
 722 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
 723                                          unsigned int gpct_index)
 724 {
 725         struct ni_private *devpriv = dev->private;
 726         unsigned long flags;
 727
 728         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 729         if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
 730                 struct mite_channel *mite_chan =
 731                     devpriv->counter_dev->counters[gpct_index].mite_chan;
 732
 733                 ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
 734                                 NI_E_DMA_G0_G1_SEL_MASK(gpct_index), 0);
 735                 ni_tio_set_mite_channel(&devpriv->
 736                                         counter_dev->counters[gpct_index],
 737                                         NULL);
 738                 mite_release_channel(mite_chan);
 739         }
 740         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 741 }
 742
 743 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
 744 {
 745         struct ni_private *devpriv = dev->private;
 746         unsigned long flags;
 747
 748         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 749         if (devpriv->cdo_mite_chan) {
 750                 ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG,
 751                                 NI_M_CDIO_DMA_SEL_CDO_MASK, 0);
 752                 mite_release_channel(devpriv->cdo_mite_chan);
 753                 devpriv->cdo_mite_chan = NULL;
 754         }
 755         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 756 }
 757
 758 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
 759                                           unsigned int gpct_index, short enable)
 760 {
 761         struct ni_private *devpriv = dev->private;
 762         unsigned int val = 0;
 763         int reg;
 764
 765         if (devpriv->is_m_series || gpct_index > 1)
 766                 return;
 767
 768         /*
 769          * e-series boards use the second irq signals to generate
 770          * dma requests for their counters
 771          */
 772         if (gpct_index == 0) {
 773                 reg = NISTC_INTA2_ENA_REG;
 774                 if (enable)
 775                         val = NISTC_INTA_ENA_G0_GATE;
 776         } else {
 777                 reg = NISTC_INTB2_ENA_REG;
 778                 if (enable)
 779                         val = NISTC_INTB_ENA_G1_GATE;
 780         }
 781         ni_stc_writew(dev, val, reg);
 782 }
 783 #endif /*  PCIDMA */
 784
 785 static void ni_clear_ai_fifo(struct comedi_device *dev)
 786 {
 787         struct ni_private *devpriv = dev->private;
 788         static const int timeout = 10000;
 789         int i;
 790
 791         if (devpriv->is_6143) {
 792                 /*  Flush the 6143 data FIFO */
 793                 ni_writel(dev, 0x10, NI6143_AI_FIFO_CTRL_REG);
 794                 ni_writel(dev, 0x00, NI6143_AI_FIFO_CTRL_REG);
 795                 /*  Wait for complete */
 796                 for (i = 0; i < timeout; i++) {
 797                         if (!(ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x10))
 798                                 break;
 799                         udelay(1);
 800                 }
 801                 if (i == timeout)
 802                         dev_err(dev->class_dev, "FIFO flush timeout\n");
 803         } else {
 804                 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
 805                 if (devpriv->is_625x) {
 806                         ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0));
 807                         ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0));
 808 #if 0
 809                         /*
 810                          * The NI example code does 3 convert pulses for 625x
 811                          * boards, But that appears to be wrong in practice.
 812                          */
 813                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 814                                       NISTC_AI_CMD1_REG);
 815                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 816                                       NISTC_AI_CMD1_REG);
 817                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 818                                       NISTC_AI_CMD1_REG);
 819 #endif
 820                 }
 821         }
 822 }
 823
 824 static inline void ni_ao_win_outw(struct comedi_device *dev,
 825                                   unsigned int data, int addr)
 826 {
 827         struct ni_private *devpriv = dev->private;
 828         unsigned long flags;
 829
 830         spin_lock_irqsave(&devpriv->window_lock, flags);
 831         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 832         ni_writew(dev, data, NI611X_AO_WINDOW_DATA_REG);
 833         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 834 }
 835
 836 static inline void ni_ao_win_outl(struct comedi_device *dev,
 837                                   unsigned int data, int addr)
 838 {
 839         struct ni_private *devpriv = dev->private;
 840         unsigned long flags;
 841
 842         spin_lock_irqsave(&devpriv->window_lock, flags);
 843         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 844         ni_writel(dev, data, NI611X_AO_WINDOW_DATA_REG);
 845         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 846 }
 847
 848 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
 849 {
 850         struct ni_private *devpriv = dev->private;
 851         unsigned long flags;
 852         unsigned short data;
 853
 854         spin_lock_irqsave(&devpriv->window_lock, flags);
 855         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 856         data = ni_readw(dev, NI611X_AO_WINDOW_DATA_REG);
 857         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 858         return data;
 859 }
 860
 861 /*
 862  * ni_set_bits( ) allows different parts of the ni_mio_common driver to
 863  * share registers (such as Interrupt_A_Register) without interfering with
 864  * each other.
 865  *
 866  * NOTE: the switch/case statements are optimized out for a constant argument
 867  * so this is actually quite fast---  If you must wrap another function around
 868  * this make it inline to avoid a large speed penalty.
 869  *
 870  * value should only be 1 or 0.
 871  */
 872 static inline void ni_set_bits(struct comedi_device *dev, int reg,
 873                                unsigned int bits, unsigned int value)
 874 {
 875         unsigned int bit_values;
 876
 877         if (value)
 878                 bit_values = bits;
 879         else
 880                 bit_values = 0;
 881         ni_set_bitfield(dev, reg, bits, bit_values);
 882 }
 883
 884 #ifdef PCIDMA
 885 static void ni_sync_ai_dma(struct comedi_device *dev)
 886 {
 887         struct ni_private *devpriv = dev->private;
 888         struct comedi_subdevice *s = dev->read_subdev;
 889         unsigned long flags;
 890
 891         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 892         if (devpriv->ai_mite_chan)
 893                 mite_sync_dma(devpriv->ai_mite_chan, s);
 894         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 895 }
 896
 897 static int ni_ai_drain_dma(struct comedi_device *dev)
 898 {
 899         struct ni_private *devpriv = dev->private;
 900         int i;
 901         static const int timeout = 10000;
 902         unsigned long flags;
 903         int retval = 0;
 904
 905         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 906         if (devpriv->ai_mite_chan) {
 907                 for (i = 0; i < timeout; i++) {
 908                         if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
 909                              NISTC_AI_STATUS1_FIFO_E) &&
 910                             mite_bytes_in_transit(devpriv->ai_mite_chan) == 0)
 911                                 break;
 912                         udelay(5);
 913                 }
 914                 if (i == timeout) {
 915                         dev_err(dev->class_dev, "timed out\n");
 916                         dev_err(dev->class_dev,
 917                                 "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
 918                                 mite_bytes_in_transit(devpriv->ai_mite_chan),
 919                                 ni_stc_readw(dev, NISTC_AI_STATUS1_REG));
 920                         retval = -1;
 921                 }
 922         }
 923         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 924
 925         ni_sync_ai_dma(dev);
 926
 927         return retval;
 928 }
 929
 930 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
 931 {
 932         static const int timeout = 10000;
 933         int i;
 934
 935         for (i = 0; i < timeout; i++) {
 936                 unsigned short b_status;
 937
 938                 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
 939                 if (b_status & NISTC_AO_STATUS1_FIFO_HF)
 940                         break;
 941                 /*
 942                  * If we poll too often, the pci bus activity seems
 943                  * to slow the dma transfer down.
 944                  */
 945                 usleep_range(10, 100);
 946         }
 947         if (i == timeout) {
 948                 dev_err(dev->class_dev, "timed out waiting for dma load\n");
 949                 return -EPIPE;
 950         }
 951         return 0;
 952 }
 953 #endif /* PCIDMA */
 954
 955 #ifndef PCIDMA
 956
 957 static void ni_ao_fifo_load(struct comedi_device *dev,
 958                             struct comedi_subdevice *s, int n)
 959 {
 960         struct ni_private *devpriv = dev->private;
 961         int i;
 962         unsigned short d;
 963         unsigned int packed_data;
 964
 965         for (i = 0; i < n; i++) {
 966                 comedi_buf_read_samples(s, &d, 1);
 967
 968                 if (devpriv->is_6xxx) {
 969                         packed_data = d & 0xffff;
 970                         /* 6711 only has 16 bit wide ao fifo */
 971                         if (!devpriv->is_6711) {
 972                                 comedi_buf_read_samples(s, &d, 1);
 973                                 i++;
 974                                 packed_data |= (d << 16) & 0xffff0000;
 975                         }
 976                         ni_writel(dev, packed_data, NI611X_AO_FIFO_DATA_REG);
 977                 } else {
 978                         ni_writew(dev, d, NI_E_AO_FIFO_DATA_REG);
 979                 }
 980         }
 981 }
 982
 983 /*
 984  *  There's a small problem if the FIFO gets really low and we
 985  *  don't have the data to fill it.  Basically, if after we fill
 986  *  the FIFO with all the data available, the FIFO is _still_
 987  *  less than half full, we never clear the interrupt.  If the
 988  *  IRQ is in edge mode, we never get another interrupt, because
 989  *  this one wasn't cleared.  If in level mode, we get flooded
 990  *  with interrupts that we can't fulfill, because nothing ever
 991  *  gets put into the buffer.
 992  *
 993  *  This kind of situation is recoverable, but it is easier to
 994  *  just pretend we had a FIFO underrun, since there is a good
 995  *  chance it will happen anyway.  This is _not_ the case for
 996  *  RT code, as RT code might purposely be running close to the
 997  *  metal.  Needs to be fixed eventually.
 998  */
 999 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1000                                  struct comedi_subdevice *s)
1001 {
1002         const struct ni_board_struct *board = dev->board_ptr;
1003         unsigned int nbytes;
1004         unsigned int nsamples;
1005
1006         nbytes = comedi_buf_read_n_available(s);
1007         if (nbytes == 0) {
1008                 s->async->events |= COMEDI_CB_OVERFLOW;
1009                 return 0;
1010         }
1011
1012         nsamples = comedi_bytes_to_samples(s, nbytes);
1013         if (nsamples > board->ao_fifo_depth / 2)
1014                 nsamples = board->ao_fifo_depth / 2;
1015
1016         ni_ao_fifo_load(dev, s, nsamples);
1017
1018         return 1;
1019 }
1020
1021 static int ni_ao_prep_fifo(struct comedi_device *dev,
1022                            struct comedi_subdevice *s)
1023 {
1024         const struct ni_board_struct *board = dev->board_ptr;
1025         struct ni_private *devpriv = dev->private;
1026         unsigned int nbytes;
1027         unsigned int nsamples;
1028
1029         /* reset fifo */
1030         ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
1031         if (devpriv->is_6xxx)
1032                 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
1033
1034         /* load some data */
1035         nbytes = comedi_buf_read_n_available(s);
1036         if (nbytes == 0)
1037                 return 0;
1038
1039         nsamples = comedi_bytes_to_samples(s, nbytes);
1040         if (nsamples > board->ao_fifo_depth)
1041                 nsamples = board->ao_fifo_depth;
1042
1043         ni_ao_fifo_load(dev, s, nsamples);
1044
1045         return nsamples;
1046 }
1047
1048 static void ni_ai_fifo_read(struct comedi_device *dev,
1049                             struct comedi_subdevice *s, int n)
1050 {
1051         struct ni_private *devpriv = dev->private;
1052         struct comedi_async *async = s->async;
1053         unsigned int dl;
1054         unsigned short data;
1055         int i;
1056
1057         if (devpriv->is_611x) {
1058                 for (i = 0; i < n / 2; i++) {
1059                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1060                         /* This may get the hi/lo data in the wrong order */
1061                         data = (dl >> 16) & 0xffff;
1062                         comedi_buf_write_samples(s, &data, 1);
1063                         data = dl & 0xffff;
1064                         comedi_buf_write_samples(s, &data, 1);
1065                 }
1066                 /* Check if there's a single sample stuck in the FIFO */
1067                 if (n % 2) {
1068                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1069                         data = dl & 0xffff;
1070                         comedi_buf_write_samples(s, &data, 1);
1071                 }
1072         } else if (devpriv->is_6143) {
1073                 /*
1074                  * This just reads the FIFO assuming the data is present,
1075                  * no checks on the FIFO status are performed.
1076                  */
1077                 for (i = 0; i < n / 2; i++) {
1078                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1079
1080                         data = (dl >> 16) & 0xffff;
1081                         comedi_buf_write_samples(s, &data, 1);
1082                         data = dl & 0xffff;
1083                         comedi_buf_write_samples(s, &data, 1);
1084                 }
1085                 if (n % 2) {
1086                         /* Assume there is a single sample stuck in the FIFO */
1087                         /* Get stranded sample into FIFO */
1088                         ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1089                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1090                         data = (dl >> 16) & 0xffff;
1091                         comedi_buf_write_samples(s, &data, 1);
1092                 }
1093         } else {
1094                 if (n > ARRAY_SIZE(devpriv->ai_fifo_buffer)) {
1095                         dev_err(dev->class_dev,
1096                                 "bug! ai_fifo_buffer too small\n");
1097                         async->events |= COMEDI_CB_ERROR;
1098                         return;
1099                 }
1100                 for (i = 0; i < n; i++) {
1101                         devpriv->ai_fifo_buffer[i] =
1102                             ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1103                 }
1104                 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n);
1105         }
1106 }
1107
1108 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1109 {
1110         const struct ni_board_struct *board = dev->board_ptr;
1111         struct comedi_subdevice *s = dev->read_subdev;
1112         int n;
1113
1114         n = board->ai_fifo_depth / 2;
1115
1116         ni_ai_fifo_read(dev, s, n);
1117 }
1118 #endif
1119
1120 /* Empties the AI fifo */
1121 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1122 {
1123         struct ni_private *devpriv = dev->private;
1124         struct comedi_subdevice *s = dev->read_subdev;
1125         unsigned int dl;
1126         unsigned short data;
1127         int i;
1128
1129         if (devpriv->is_611x) {
1130                 while ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1131                         NISTC_AI_STATUS1_FIFO_E) == 0) {
1132                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1133
1134                         /* This may get the hi/lo data in the wrong order */
1135                         data = dl >> 16;
1136                         comedi_buf_write_samples(s, &data, 1);
1137                         data = dl & 0xffff;
1138                         comedi_buf_write_samples(s, &data, 1);
1139                 }
1140         } else if (devpriv->is_6143) {
1141                 i = 0;
1142                 while (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x04) {
1143                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1144
1145                         /* This may get the hi/lo data in the wrong order */
1146                         data = dl >> 16;
1147                         comedi_buf_write_samples(s, &data, 1);
1148                         data = dl & 0xffff;
1149                         comedi_buf_write_samples(s, &data, 1);
1150                         i += 2;
1151                 }
1152                 /*  Check if stranded sample is present */
1153                 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1154                         /* Get stranded sample into FIFO */
1155                         ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1156                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1157                         data = (dl >> 16) & 0xffff;
1158                         comedi_buf_write_samples(s, &data, 1);
1159                 }
1160
1161         } else {
1162                 unsigned short fe;      /* fifo empty */
1163
1164                 fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1165                      NISTC_AI_STATUS1_FIFO_E;
1166                 while (fe == 0) {
1167                         for (i = 0;
1168                              i < ARRAY_SIZE(devpriv->ai_fifo_buffer); i++) {
1169                                 fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1170                                      NISTC_AI_STATUS1_FIFO_E;
1171                                 if (fe)
1172                                         break;
1173                                 devpriv->ai_fifo_buffer[i] =
1174                                     ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1175                         }
1176                         comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i);
1177                 }
1178         }
1179 }
1180
1181 static void get_last_sample_611x(struct comedi_device *dev)
1182 {
1183         struct ni_private *devpriv = dev->private;
1184         struct comedi_subdevice *s = dev->read_subdev;
1185         unsigned short data;
1186         unsigned int dl;
1187
1188         if (!devpriv->is_611x)
1189                 return;
1190
1191         /* Check if there's a single sample stuck in the FIFO */
1192         if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1193                 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1194                 data = dl & 0xffff;
1195                 comedi_buf_write_samples(s, &data, 1);
1196         }
1197 }
1198
1199 static void get_last_sample_6143(struct comedi_device *dev)
1200 {
1201         struct ni_private *devpriv = dev->private;
1202         struct comedi_subdevice *s = dev->read_subdev;
1203         unsigned short data;
1204         unsigned int dl;
1205
1206         if (!devpriv->is_6143)
1207                 return;
1208
1209         /* Check if there's a single sample stuck in the FIFO */
1210         if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1211                 /* Get stranded sample into FIFO */
1212                 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1213                 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1214
1215                 /* This may get the hi/lo data in the wrong order */
1216                 data = (dl >> 16) & 0xffff;
1217                 comedi_buf_write_samples(s, &data, 1);
1218         }
1219 }
1220
1221 static void shutdown_ai_command(struct comedi_device *dev)
1222 {
1223         struct comedi_subdevice *s = dev->read_subdev;
1224
1225 #ifdef PCIDMA
1226         ni_ai_drain_dma(dev);
1227 #endif
1228         ni_handle_fifo_dregs(dev);
1229         get_last_sample_611x(dev);
1230         get_last_sample_6143(dev);
1231
1232         s->async->events |= COMEDI_CB_EOA;
1233 }
1234
1235 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
1236 {
1237         struct ni_private *devpriv = dev->private;
1238
1239         if (devpriv->aimode == AIMODE_SCAN) {
1240 #ifdef PCIDMA
1241                 static const int timeout = 10;
1242                 int i;
1243
1244                 for (i = 0; i < timeout; i++) {
1245                         ni_sync_ai_dma(dev);
1246                         if ((s->async->events & COMEDI_CB_EOS))
1247                                 break;
1248                         udelay(1);
1249                 }
1250 #else
1251                 ni_handle_fifo_dregs(dev);
1252                 s->async->events |= COMEDI_CB_EOS;
1253 #endif
1254         }
1255         /* handle special case of single scan */
1256         if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)
1257                 shutdown_ai_command(dev);
1258 }
1259
1260 static void handle_gpct_interrupt(struct comedi_device *dev,
1261                                   unsigned short counter_index)
1262 {
1263 #ifdef PCIDMA
1264         struct ni_private *devpriv = dev->private;
1265         struct comedi_subdevice *s;
1266
1267         s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1268
1269         ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1270                                 s);
1271         comedi_handle_events(dev, s);
1272 #endif
1273 }
1274
1275 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1276 {
1277         unsigned short ack = 0;
1278
1279         if (a_status & NISTC_AI_STATUS1_SC_TC)
1280                 ack |= NISTC_INTA_ACK_AI_SC_TC;
1281         if (a_status & NISTC_AI_STATUS1_START1)
1282                 ack |= NISTC_INTA_ACK_AI_START1;
1283         if (a_status & NISTC_AI_STATUS1_START)
1284                 ack |= NISTC_INTA_ACK_AI_START;
1285         if (a_status & NISTC_AI_STATUS1_STOP)
1286                 ack |= NISTC_INTA_ACK_AI_STOP;
1287         if (a_status & NISTC_AI_STATUS1_OVER)
1288                 ack |= NISTC_INTA_ACK_AI_ERR;
1289         if (ack)
1290                 ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG);
1291 }
1292
1293 static void handle_a_interrupt(struct comedi_device *dev,
1294                                struct comedi_subdevice *s,
1295                                unsigned short status)
1296 {
1297         struct comedi_cmd *cmd = &s->async->cmd;
1298
1299         /* test for all uncommon interrupt events at the same time */
1300         if (status & (NISTC_AI_STATUS1_ERR |
1301                       NISTC_AI_STATUS1_SC_TC | NISTC_AI_STATUS1_START1)) {
1302                 if (status == 0xffff) {
1303                         dev_err(dev->class_dev, "Card removed?\n");
1304                         /*
1305                          * We probably aren't even running a command now,
1306                          * so it's a good idea to be careful.
1307                          */
1308                         if (comedi_is_subdevice_running(s))
1309                                 s->async->events |= COMEDI_CB_ERROR;
1310                         return;
1311                 }
1312                 if (status & NISTC_AI_STATUS1_ERR) {
1313                         dev_err(dev->class_dev, "ai error a_status=%04x\n",
1314                                 status);
1315
1316                         shutdown_ai_command(dev);
1317
1318                         s->async->events |= COMEDI_CB_ERROR;
1319                         if (status & NISTC_AI_STATUS1_OVER)
1320                                 s->async->events |= COMEDI_CB_OVERFLOW;
1321                         return;
1322                 }
1323                 if (status & NISTC_AI_STATUS1_SC_TC) {
1324                         if (cmd->stop_src == TRIG_COUNT)
1325                                 shutdown_ai_command(dev);
1326                 }
1327         }
1328 #ifndef PCIDMA
1329         if (status & NISTC_AI_STATUS1_FIFO_HF) {
1330                 int i;
1331                 static const int timeout = 10;
1332                 /*
1333                  * PCMCIA cards (at least 6036) seem to stop producing
1334                  * interrupts if we fail to get the fifo less than half
1335                  * full, so loop to be sure.
1336                  */
1337                 for (i = 0; i < timeout; ++i) {
1338                         ni_handle_fifo_half_full(dev);
1339                         if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1340                              NISTC_AI_STATUS1_FIFO_HF) == 0)
1341                                 break;
1342                 }
1343         }
1344 #endif /*  !PCIDMA */
1345
1346         if (status & NISTC_AI_STATUS1_STOP)
1347                 ni_handle_eos(dev, s);
1348 }
1349
1350 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1351 {
1352         unsigned short ack = 0;
1353
1354         if (b_status & NISTC_AO_STATUS1_BC_TC)
1355                 ack |= NISTC_INTB_ACK_AO_BC_TC;
1356         if (b_status & NISTC_AO_STATUS1_OVERRUN)
1357                 ack |= NISTC_INTB_ACK_AO_ERR;
1358         if (b_status & NISTC_AO_STATUS1_START)
1359                 ack |= NISTC_INTB_ACK_AO_START;
1360         if (b_status & NISTC_AO_STATUS1_START1)
1361                 ack |= NISTC_INTB_ACK_AO_START1;
1362         if (b_status & NISTC_AO_STATUS1_UC_TC)
1363                 ack |= NISTC_INTB_ACK_AO_UC_TC;
1364         if (b_status & NISTC_AO_STATUS1_UI2_TC)
1365                 ack |= NISTC_INTB_ACK_AO_UI2_TC;
1366         if (b_status & NISTC_AO_STATUS1_UPDATE)
1367                 ack |= NISTC_INTB_ACK_AO_UPDATE;
1368         if (ack)
1369                 ni_stc_writew(dev, ack, NISTC_INTB_ACK_REG);
1370 }
1371
1372 static void handle_b_interrupt(struct comedi_device *dev,
1373                                struct comedi_subdevice *s,
1374                                unsigned short b_status)
1375 {
1376         if (b_status == 0xffff)
1377                 return;
1378         if (b_status & NISTC_AO_STATUS1_OVERRUN) {
1379                 dev_err(dev->class_dev,
1380                         "AO FIFO underrun status=0x%04x status2=0x%04x\n",
1381                         b_status, ni_stc_readw(dev, NISTC_AO_STATUS2_REG));
1382                 s->async->events |= COMEDI_CB_OVERFLOW;
1383         }
1384
1385         if (s->async->cmd.stop_src != TRIG_NONE &&
1386             b_status & NISTC_AO_STATUS1_BC_TC)
1387                 s->async->events |= COMEDI_CB_EOA;
1388
1389 #ifndef PCIDMA
1390         if (b_status & NISTC_AO_STATUS1_FIFO_REQ) {
1391                 int ret;
1392
1393                 ret = ni_ao_fifo_half_empty(dev, s);
1394                 if (!ret) {
1395                         dev_err(dev->class_dev, "AO buffer underrun\n");
1396                         ni_set_bits(dev, NISTC_INTB_ENA_REG,
1397                                     NISTC_INTB_ENA_AO_FIFO |
1398                                     NISTC_INTB_ENA_AO_ERR, 0);
1399                         s->async->events |= COMEDI_CB_OVERFLOW;
1400                 }
1401         }
1402 #endif
1403 }
1404
1405 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1406                         void *data, unsigned int num_bytes,
1407                         unsigned int chan_index)
1408 {
1409         struct ni_private *devpriv = dev->private;
1410         struct comedi_async *async = s->async;
1411         struct comedi_cmd *cmd = &async->cmd;
1412         unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
1413         unsigned short *array = data;
1414         unsigned int *larray = data;
1415         unsigned int i;
1416 #ifdef PCIDMA
1417         __le16 *barray = data;
1418         __le32 *blarray = data;
1419 #endif
1420
1421         for (i = 0; i < nsamples; i++) {
1422 #ifdef PCIDMA
1423                 if (s->subdev_flags & SDF_LSAMPL)
1424                         larray[i] = le32_to_cpu(blarray[i]);
1425                 else
1426                         array[i] = le16_to_cpu(barray[i]);
1427 #endif
1428                 if (s->subdev_flags & SDF_LSAMPL)
1429                         larray[i] += devpriv->ai_offset[chan_index];
1430                 else
1431                         array[i] += devpriv->ai_offset[chan_index];
1432                 chan_index++;
1433                 chan_index %= cmd->chanlist_len;
1434         }
1435 }
1436
1437 #ifdef PCIDMA
1438
1439 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1440 {
1441         struct ni_private *devpriv = dev->private;
1442         struct comedi_subdevice *s = dev->read_subdev;
1443         int retval;
1444         unsigned long flags;
1445
1446         retval = ni_request_ai_mite_channel(dev);
1447         if (retval)
1448                 return retval;
1449
1450         /* write alloc the entire buffer */
1451         comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
1452
1453         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1454         if (!devpriv->ai_mite_chan) {
1455                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1456                 return -EIO;
1457         }
1458
1459         if (devpriv->is_611x || devpriv->is_6143)
1460                 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1461         else if (devpriv->is_628x)
1462                 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1463         else
1464                 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1465
1466         /*start the MITE */
1467         mite_dma_arm(devpriv->ai_mite_chan);
1468         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1469
1470         return 0;
1471 }
1472
1473 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1474 {
1475         struct ni_private *devpriv = dev->private;
1476         struct comedi_subdevice *s = dev->write_subdev;
1477         int retval;
1478         unsigned long flags;
1479
1480         retval = ni_request_ao_mite_channel(dev);
1481         if (retval)
1482                 return retval;
1483
1484         /* read alloc the entire buffer */
1485         comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
1486
1487         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1488         if (devpriv->ao_mite_chan) {
1489                 if (devpriv->is_611x || devpriv->is_6713) {
1490                         mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1491                 } else {
1492                         /*
1493                          * Doing 32 instead of 16 bit wide transfers from
1494                          * memory makes the mite do 32 bit pci transfers,
1495                          * doubling pci bandwidth.
1496                          */
1497                         mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1498                 }
1499                 mite_dma_arm(devpriv->ao_mite_chan);
1500         } else {
1501                 retval = -EIO;
1502         }
1503         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1504
1505         return retval;
1506 }
1507
1508 #endif /*  PCIDMA */
1509
1510 /*
1511  * used for both cancel ioctl and board initialization
1512  *
1513  * this is pretty harsh for a cancel, but it works...
1514  */
1515 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1516 {
1517         struct ni_private *devpriv = dev->private;
1518         unsigned int ai_personal;
1519         unsigned int ai_out_ctrl;
1520
1521         ni_release_ai_mite_channel(dev);
1522         /* ai configuration */
1523         ni_stc_writew(dev, NISTC_RESET_AI_CFG_START | NISTC_RESET_AI,
1524                       NISTC_RESET_REG);
1525
1526         ni_set_bits(dev, NISTC_INTA_ENA_REG, NISTC_INTA_ENA_AI_MASK, 0);
1527
1528         ni_clear_ai_fifo(dev);
1529
1530         if (!devpriv->is_6143)
1531                 ni_writeb(dev, NI_E_MISC_CMD_EXT_ATRIG, NI_E_MISC_CMD_REG);
1532
1533         ni_stc_writew(dev, NISTC_AI_CMD1_DISARM, NISTC_AI_CMD1_REG);
1534         ni_stc_writew(dev, NISTC_AI_MODE1_START_STOP |
1535                            NISTC_AI_MODE1_RSVD
1536                             /*| NISTC_AI_MODE1_TRIGGER_ONCE */,
1537                       NISTC_AI_MODE1_REG);
1538         ni_stc_writew(dev, 0, NISTC_AI_MODE2_REG);
1539         /* generate FIFO interrupts on non-empty */
1540         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
1541                       NISTC_AI_MODE3_REG);
1542
1543         ai_personal = NISTC_AI_PERSONAL_SHIFTIN_PW |
1544                       NISTC_AI_PERSONAL_SOC_POLARITY |
1545                       NISTC_AI_PERSONAL_LOCALMUX_CLK_PW;
1546         ai_out_ctrl = NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(3) |
1547                       NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(0) |
1548                       NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(2) |
1549                       NISTC_AI_OUT_CTRL_SC_TC_SEL(3);
1550         if (devpriv->is_611x) {
1551                 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1552         } else if (devpriv->is_6143) {
1553                 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1554         } else {
1555                 ai_personal |= NISTC_AI_PERSONAL_CONVERT_PW;
1556                 if (devpriv->is_622x)
1557                         ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1558                 else
1559                         ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1560         }
1561         ni_stc_writew(dev, ai_personal, NISTC_AI_PERSONAL_REG);
1562         ni_stc_writew(dev, ai_out_ctrl, NISTC_AI_OUT_CTRL_REG);
1563
1564         /* the following registers should not be changed, because there
1565          * are no backup registers in devpriv.  If you want to change
1566          * any of these, add a backup register and other appropriate code:
1567          *      NISTC_AI_MODE1_REG
1568          *      NISTC_AI_MODE3_REG
1569          *      NISTC_AI_PERSONAL_REG
1570          *      NISTC_AI_OUT_CTRL_REG
1571          */
1572
1573         /* clear interrupts */
1574         ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
1575
1576         ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
1577
1578         return 0;
1579 }
1580
1581 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1582 {
1583         unsigned long flags;
1584         int count;
1585
1586         /*  lock to avoid race with interrupt handler */
1587         spin_lock_irqsave(&dev->spinlock, flags);
1588 #ifndef PCIDMA
1589         ni_handle_fifo_dregs(dev);
1590 #else
1591         ni_sync_ai_dma(dev);
1592 #endif
1593         count = comedi_buf_n_bytes_ready(s);
1594         spin_unlock_irqrestore(&dev->spinlock, flags);
1595
1596         return count;
1597 }
1598
1599 static void ni_prime_channelgain_list(struct comedi_device *dev)
1600 {
1601         int i;
1602
1603         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG);
1604         for (i = 0; i < NI_TIMEOUT; ++i) {
1605                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1606                       NISTC_AI_STATUS1_FIFO_E)) {
1607                         ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
1608                         return;
1609                 }
1610                 udelay(1);
1611         }
1612         dev_err(dev->class_dev, "timeout loading channel/gain list\n");
1613 }
1614
1615 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1616                                               unsigned int n_chan,
1617                                               unsigned int *list)
1618 {
1619         const struct ni_board_struct *board = dev->board_ptr;
1620         struct ni_private *devpriv = dev->private;
1621         unsigned int chan, range, aref;
1622         unsigned int i;
1623         unsigned int dither;
1624         unsigned int range_code;
1625
1626         ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1627
1628         if ((list[0] & CR_ALT_SOURCE)) {
1629                 unsigned int bypass_bits;
1630
1631                 chan = CR_CHAN(list[0]);
1632                 range = CR_RANGE(list[0]);
1633                 range_code = ni_gainlkup[board->gainlkup][range];
1634                 dither = (list[0] & CR_ALT_FILTER) != 0;
1635                 bypass_bits = NI_M_CFG_BYPASS_FIFO |
1636                               NI_M_CFG_BYPASS_AI_CHAN(chan) |
1637                               NI_M_CFG_BYPASS_AI_GAIN(range_code) |
1638                               devpriv->ai_calib_source;
1639                 if (dither)
1640                         bypass_bits |= NI_M_CFG_BYPASS_AI_DITHER;
1641                 /*  don't use 2's complement encoding */
1642                 bypass_bits |= NI_M_CFG_BYPASS_AI_POLARITY;
1643                 ni_writel(dev, bypass_bits, NI_M_CFG_BYPASS_FIFO_REG);
1644         } else {
1645                 ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG);
1646         }
1647         for (i = 0; i < n_chan; i++) {
1648                 unsigned int config_bits = 0;
1649
1650                 chan = CR_CHAN(list[i]);
1651                 aref = CR_AREF(list[i]);
1652                 range = CR_RANGE(list[i]);
1653                 dither = (list[i] & CR_ALT_FILTER) != 0;
1654
1655                 range_code = ni_gainlkup[board->gainlkup][range];
1656                 devpriv->ai_offset[i] = 0;
1657                 switch (aref) {
1658                 case AREF_DIFF:
1659                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_DIFF;
1660                         break;
1661                 case AREF_COMMON:
1662                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_COMMON;
1663                         break;
1664                 case AREF_GROUND:
1665                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_GROUND;
1666                         break;
1667                 case AREF_OTHER:
1668                         break;
1669                 }
1670                 config_bits |= NI_M_AI_CFG_CHAN_SEL(chan);
1671                 config_bits |= NI_M_AI_CFG_BANK_SEL(chan);
1672                 config_bits |= NI_M_AI_CFG_GAIN(range_code);
1673                 if (i == n_chan - 1)
1674                         config_bits |= NI_M_AI_CFG_LAST_CHAN;
1675                 if (dither)
1676                         config_bits |= NI_M_AI_CFG_DITHER;
1677                 /*  don't use 2's complement encoding */
1678                 config_bits |= NI_M_AI_CFG_POLARITY;
1679                 ni_writew(dev, config_bits, NI_M_AI_CFG_FIFO_DATA_REG);
1680         }
1681         ni_prime_channelgain_list(dev);
1682 }
1683
1684 /*
1685  * Notes on the 6110 and 6111:
1686  * These boards a slightly different than the rest of the series, since
1687  * they have multiple A/D converters.
1688  * From the driver side, the configuration memory is a
1689  * little different.
1690  * Configuration Memory Low:
1691  *   bits 15-9: same
1692  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1693  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1694  *       1001 gain=0.1 (+/- 50)
1695  *       1010 0.2
1696  *       1011 0.1
1697  *       0001 1
1698  *       0010 2
1699  *       0011 5
1700  *       0100 10
1701  *       0101 20
1702  *       0110 50
1703  * Configuration Memory High:
1704  *   bits 12-14: Channel Type
1705  *       001 for differential
1706  *       000 for calibration
1707  *   bit 11: coupling  (this is not currently handled)
1708  *       1 AC coupling
1709  *       0 DC coupling
1710  *   bits 0-2: channel
1711  *       valid channels are 0-3
1712  */
1713 static void ni_load_channelgain_list(struct comedi_device *dev,
1714                                      struct comedi_subdevice *s,
1715                                      unsigned int n_chan, unsigned int *list)
1716 {
1717         const struct ni_board_struct *board = dev->board_ptr;
1718         struct ni_private *devpriv = dev->private;
1719         unsigned int offset = (s->maxdata + 1) >> 1;
1720         unsigned int chan, range, aref;
1721         unsigned int i;
1722         unsigned int hi, lo;
1723         unsigned int dither;
1724
1725         if (devpriv->is_m_series) {
1726                 ni_m_series_load_channelgain_list(dev, n_chan, list);
1727                 return;
1728         }
1729         if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) {
1730                 if (devpriv->changain_state &&
1731                     devpriv->changain_spec == list[0]) {
1732                         /*  ready to go. */
1733                         return;
1734                 }
1735                 devpriv->changain_state = 1;
1736                 devpriv->changain_spec = list[0];
1737         } else {
1738                 devpriv->changain_state = 0;
1739         }
1740
1741         ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1742
1743         /*  Set up Calibration mode if required */
1744         if (devpriv->is_6143) {
1745                 if ((list[0] & CR_ALT_SOURCE) &&
1746                     !devpriv->ai_calib_source_enabled) {
1747                         /*  Strobe Relay enable bit */
1748                         ni_writew(dev, devpriv->ai_calib_source |
1749                                        NI6143_CALIB_CHAN_RELAY_ON,
1750                                   NI6143_CALIB_CHAN_REG);
1751                         ni_writew(dev, devpriv->ai_calib_source,
1752                                   NI6143_CALIB_CHAN_REG);
1753                         devpriv->ai_calib_source_enabled = 1;
1754                         /* Allow relays to change */
1755                         msleep_interruptible(100);
1756                 } else if (!(list[0] & CR_ALT_SOURCE) &&
1757                            devpriv->ai_calib_source_enabled) {
1758                         /*  Strobe Relay disable bit */
1759                         ni_writew(dev, devpriv->ai_calib_source |
1760                                        NI6143_CALIB_CHAN_RELAY_OFF,
1761                                   NI6143_CALIB_CHAN_REG);
1762                         ni_writew(dev, devpriv->ai_calib_source,
1763                                   NI6143_CALIB_CHAN_REG);
1764                         devpriv->ai_calib_source_enabled = 0;
1765                         /* Allow relays to change */
1766                         msleep_interruptible(100);
1767                 }
1768         }
1769
1770         for (i = 0; i < n_chan; i++) {
1771                 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE))
1772                         chan = devpriv->ai_calib_source;
1773                 else
1774                         chan = CR_CHAN(list[i]);
1775                 aref = CR_AREF(list[i]);
1776                 range = CR_RANGE(list[i]);
1777                 dither = (list[i] & CR_ALT_FILTER) != 0;
1778
1779                 /* fix the external/internal range differences */
1780                 range = ni_gainlkup[board->gainlkup][range];
1781                 if (devpriv->is_611x)
1782                         devpriv->ai_offset[i] = offset;
1783                 else
1784                         devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
1785
1786                 hi = 0;
1787                 if ((list[i] & CR_ALT_SOURCE)) {
1788                         if (devpriv->is_611x)
1789                                 ni_writew(dev, CR_CHAN(list[i]) & 0x0003,
1790                                           NI611X_CALIB_CHAN_SEL_REG);
1791                 } else {
1792                         if (devpriv->is_611x)
1793                                 aref = AREF_DIFF;
1794                         else if (devpriv->is_6143)
1795                                 aref = AREF_OTHER;
1796                         switch (aref) {
1797                         case AREF_DIFF:
1798                                 hi |= NI_E_AI_CFG_HI_TYPE_DIFF;
1799                                 break;
1800                         case AREF_COMMON:
1801                                 hi |= NI_E_AI_CFG_HI_TYPE_COMMON;
1802                                 break;
1803                         case AREF_GROUND:
1804                                 hi |= NI_E_AI_CFG_HI_TYPE_GROUND;
1805                                 break;
1806                         case AREF_OTHER:
1807                                 break;
1808                         }
1809                 }
1810                 hi |= NI_E_AI_CFG_HI_CHAN(chan);
1811
1812                 ni_writew(dev, hi, NI_E_AI_CFG_HI_REG);
1813
1814                 if (!devpriv->is_6143) {
1815                         lo = NI_E_AI_CFG_LO_GAIN(range);
1816
1817                         if (i == n_chan - 1)
1818                                 lo |= NI_E_AI_CFG_LO_LAST_CHAN;
1819                         if (dither)
1820                                 lo |= NI_E_AI_CFG_LO_DITHER;
1821
1822                         ni_writew(dev, lo, NI_E_AI_CFG_LO_REG);
1823                 }
1824         }
1825
1826         /* prime the channel/gain list */
1827         if (!devpriv->is_611x && !devpriv->is_6143)
1828                 ni_prime_channelgain_list(dev);
1829 }
1830
1831 static int ni_ai_insn_read(struct comedi_device *dev,
1832                            struct comedi_subdevice *s,
1833                            struct comedi_insn *insn,
1834                            unsigned int *data)
1835 {
1836         struct ni_private *devpriv = dev->private;
1837         unsigned int mask = s->maxdata;
1838         int i, n;
1839         unsigned int signbits;
1840         unsigned int d;
1841         unsigned long dl;
1842
1843         ni_load_channelgain_list(dev, s, 1, &insn->chanspec);
1844
1845         ni_clear_ai_fifo(dev);
1846
1847         signbits = devpriv->ai_offset[0];
1848         if (devpriv->is_611x) {
1849                 for (n = 0; n < num_adc_stages_611x; n++) {
1850                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1851                                       NISTC_AI_CMD1_REG);
1852                         udelay(1);
1853                 }
1854                 for (n = 0; n < insn->n; n++) {
1855                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1856                                       NISTC_AI_CMD1_REG);
1857                         /* The 611x has screwy 32-bit FIFOs. */
1858                         d = 0;
1859                         for (i = 0; i < NI_TIMEOUT; i++) {
1860                                 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1861                                         d = ni_readl(dev,
1862                                                      NI611X_AI_FIFO_DATA_REG);
1863                                         d >>= 16;
1864                                         d &= 0xffff;
1865                                         break;
1866                                 }
1867                                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1868                                       NISTC_AI_STATUS1_FIFO_E)) {
1869                                         d = ni_readl(dev,
1870                                                      NI611X_AI_FIFO_DATA_REG);
1871                                         d &= 0xffff;
1872                                         break;
1873                                 }
1874                         }
1875                         if (i == NI_TIMEOUT) {
1876                                 dev_err(dev->class_dev, "timeout\n");
1877                                 return -ETIME;
1878                         }
1879                         d += signbits;
1880                         data[n] = d & 0xffff;
1881                 }
1882         } else if (devpriv->is_6143) {
1883                 for (n = 0; n < insn->n; n++) {
1884                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1885                                       NISTC_AI_CMD1_REG);
1886
1887                         /*
1888                          * The 6143 has 32-bit FIFOs. You need to strobe a
1889                          * bit to move a single 16bit stranded sample into
1890                          * the FIFO.
1891                          */
1892                         dl = 0;
1893                         for (i = 0; i < NI_TIMEOUT; i++) {
1894                                 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) &
1895                                     0x01) {
1896                                         /* Get stranded sample into FIFO */
1897                                         ni_writel(dev, 0x01,
1898                                                   NI6143_AI_FIFO_CTRL_REG);
1899                                         dl = ni_readl(dev,
1900                                                       NI6143_AI_FIFO_DATA_REG);
1901                                         break;
1902                                 }
1903                         }
1904                         if (i == NI_TIMEOUT) {
1905                                 dev_err(dev->class_dev, "timeout\n");
1906                                 return -ETIME;
1907                         }
1908                         data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1909                 }
1910         } else {
1911                 for (n = 0; n < insn->n; n++) {
1912                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1913                                       NISTC_AI_CMD1_REG);
1914                         for (i = 0; i < NI_TIMEOUT; i++) {
1915                                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1916                                       NISTC_AI_STATUS1_FIFO_E))
1917                                         break;
1918                         }
1919                         if (i == NI_TIMEOUT) {
1920                                 dev_err(dev->class_dev, "timeout\n");
1921                                 return -ETIME;
1922                         }
1923                         if (devpriv->is_m_series) {
1924                                 dl = ni_readl(dev, NI_M_AI_FIFO_DATA_REG);
1925                                 dl &= mask;
1926                                 data[n] = dl;
1927                         } else {
1928                                 d = ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1929                                 d += signbits;
1930                                 data[n] = d & 0xffff;
1931                         }
1932                 }
1933         }
1934         return insn->n;
1935 }
1936
1937 static int ni_ns_to_timer(const struct comedi_device *dev,
1938                           unsigned int nanosec, unsigned int flags)
1939 {
1940         struct ni_private *devpriv = dev->private;
1941         int divider;
1942
1943         switch (flags & CMDF_ROUND_MASK) {
1944         case CMDF_ROUND_NEAREST:
1945         default:
1946                 divider = DIV_ROUND_CLOSEST(nanosec, devpriv->clock_ns);
1947                 break;
1948         case CMDF_ROUND_DOWN:
1949                 divider = (nanosec) / devpriv->clock_ns;
1950                 break;
1951         case CMDF_ROUND_UP:
1952                 divider = DIV_ROUND_UP(nanosec, devpriv->clock_ns);
1953                 break;
1954         }
1955         return divider - 1;
1956 }
1957
1958 static unsigned int ni_timer_to_ns(const struct comedi_device *dev, int timer)
1959 {
1960         struct ni_private *devpriv = dev->private;
1961
1962         return devpriv->clock_ns * (timer + 1);
1963 }
1964
1965 static void ni_cmd_set_mite_transfer(struct mite_ring *ring,
1966                                      struct comedi_subdevice *sdev,
1967                                      const struct comedi_cmd *cmd,
1968                                      unsigned int max_count) {
1969 #ifdef PCIDMA
1970         unsigned int nbytes = max_count;
1971
1972         if (cmd->stop_arg > 0 && cmd->stop_arg < max_count)
1973                 nbytes = cmd->stop_arg;
1974         nbytes *= comedi_bytes_per_scan(sdev);
1975
1976         if (nbytes > sdev->async->prealloc_bufsz) {
1977                 if (cmd->stop_arg > 0)
1978                         dev_err(sdev->device->class_dev,
1979                                 "ni_cmd_set_mite_transfer: tried exact data transfer limits greater than buffer size\n");
1980
1981                 /*
1982                  * we can only transfer up to the size of the buffer.  In this
1983                  * case, the user is expected to continue to write into the
1984                  * comedi buffer (already implemented as a ring buffer).
1985                  */
1986                 nbytes = sdev->async->prealloc_bufsz;
1987         }
1988
1989         mite_init_ring_descriptors(ring, sdev, nbytes);
1990 #else
1991         dev_err(sdev->device->class_dev,
1992                 "ni_cmd_set_mite_transfer: exact data transfer limits not implemented yet without DMA\n");
1993 #endif
1994 }
1995
1996 static unsigned int ni_min_ai_scan_period_ns(struct comedi_device *dev,
1997                                              unsigned int num_channels)
1998 {
1999         const struct ni_board_struct *board = dev->board_ptr;
2000         struct ni_private *devpriv = dev->private;
2001
2002         /* simultaneously-sampled inputs */
2003         if (devpriv->is_611x || devpriv->is_6143)
2004                 return board->ai_speed;
2005
2006         /* multiplexed inputs */
2007         return board->ai_speed * num_channels;
2008 }
2009
2010 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2011                          struct comedi_cmd *cmd)
2012 {
2013         const struct ni_board_struct *board = dev->board_ptr;
2014         struct ni_private *devpriv = dev->private;
2015         int err = 0;
2016         unsigned int tmp;
2017         unsigned int sources;
2018
2019         /* Step 1 : check if triggers are trivially valid */
2020
2021         err |= comedi_check_trigger_src(&cmd->start_src,
2022                                         TRIG_NOW | TRIG_INT | TRIG_EXT);
2023         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
2024                                         TRIG_TIMER | TRIG_EXT);
2025
2026         sources = TRIG_TIMER | TRIG_EXT;
2027         if (devpriv->is_611x || devpriv->is_6143)
2028                 sources |= TRIG_NOW;
2029         err |= comedi_check_trigger_src(&cmd->convert_src, sources);
2030
2031         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2032         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2033
2034         if (err)
2035                 return 1;
2036
2037         /* Step 2a : make sure trigger sources are unique */
2038
2039         err |= comedi_check_trigger_is_unique(cmd->start_src);
2040         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2041         err |= comedi_check_trigger_is_unique(cmd->convert_src);
2042         err |= comedi_check_trigger_is_unique(cmd->stop_src);
2043
2044         /* Step 2b : and mutually compatible */
2045
2046         if (err)
2047                 return 2;
2048
2049         /* Step 3: check if arguments are trivially valid */
2050
2051         switch (cmd->start_src) {
2052         case TRIG_NOW:
2053         case TRIG_INT:
2054                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2055                 break;
2056         case TRIG_EXT:
2057                 tmp = CR_CHAN(cmd->start_arg);
2058
2059                 if (tmp > 16)
2060                         tmp = 16;
2061                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2062                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
2063                 break;
2064         }
2065
2066         if (cmd->scan_begin_src == TRIG_TIMER) {
2067                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
2068                         ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2069                 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
2070                                                     devpriv->clock_ns *
2071                                                     0xffffff);
2072         } else if (cmd->scan_begin_src == TRIG_EXT) {
2073                 /* external trigger */
2074                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2075
2076                 if (tmp > 16)
2077                         tmp = 16;
2078                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2079                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2080         } else {                /* TRIG_OTHER */
2081                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2082         }
2083
2084         if (cmd->convert_src == TRIG_TIMER) {
2085                 if (devpriv->is_611x || devpriv->is_6143) {
2086                         err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2087                                                            0);
2088                 } else {
2089                         err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2090                                                             board->ai_speed);
2091                         err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
2092                                                             devpriv->clock_ns *
2093                                                             0xffff);
2094                 }
2095         } else if (cmd->convert_src == TRIG_EXT) {
2096                 /* external trigger */
2097                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2098
2099                 if (tmp > 16)
2100                         tmp = 16;
2101                 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2102                 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, tmp);
2103         } else if (cmd->convert_src == TRIG_NOW) {
2104                 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
2105         }
2106
2107         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2108                                            cmd->chanlist_len);
2109
2110         if (cmd->stop_src == TRIG_COUNT) {
2111                 unsigned int max_count = 0x01000000;
2112
2113                 if (devpriv->is_611x)
2114                         max_count -= num_adc_stages_611x;
2115                 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count);
2116                 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2117         } else {
2118                 /* TRIG_NONE */
2119                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2120         }
2121
2122         if (err)
2123                 return 3;
2124
2125         /* step 4: fix up any arguments */
2126
2127         if (cmd->scan_begin_src == TRIG_TIMER) {
2128                 tmp = cmd->scan_begin_arg;
2129                 cmd->scan_begin_arg =
2130                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2131                                                        cmd->scan_begin_arg,
2132                                                        cmd->flags));
2133                 if (tmp != cmd->scan_begin_arg)
2134                         err++;
2135         }
2136         if (cmd->convert_src == TRIG_TIMER) {
2137                 if (!devpriv->is_611x && !devpriv->is_6143) {
2138                         tmp = cmd->convert_arg;
2139                         cmd->convert_arg =
2140                             ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2141                                                                cmd->convert_arg,
2142                                                                cmd->flags));
2143                         if (tmp != cmd->convert_arg)
2144                                 err++;
2145                         if (cmd->scan_begin_src == TRIG_TIMER &&
2146                             cmd->scan_begin_arg <
2147                             cmd->convert_arg * cmd->scan_end_arg) {
2148                                 cmd->scan_begin_arg =
2149                                     cmd->convert_arg * cmd->scan_end_arg;
2150                                 err++;
2151                         }
2152                 }
2153         }
2154
2155         if (err)
2156                 return 4;
2157
2158         return 0;
2159 }
2160
2161 static int ni_ai_inttrig(struct comedi_device *dev,
2162                          struct comedi_subdevice *s,
2163                          unsigned int trig_num)
2164 {
2165         struct ni_private *devpriv = dev->private;
2166         struct comedi_cmd *cmd = &s->async->cmd;
2167
2168         if (trig_num != cmd->start_arg)
2169                 return -EINVAL;
2170
2171         ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2,
2172                       NISTC_AI_CMD2_REG);
2173         s->async->inttrig = NULL;
2174
2175         return 1;
2176 }
2177
2178 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2179 {
2180         struct ni_private *devpriv = dev->private;
2181         const struct comedi_cmd *cmd = &s->async->cmd;
2182         int timer;
2183         int mode1 = 0;          /* mode1 is needed for both stop and convert */
2184         int mode2 = 0;
2185         int start_stop_select = 0;
2186         unsigned int stop_count;
2187         int interrupt_a_enable = 0;
2188         unsigned int ai_trig;
2189
2190         if (dev->irq == 0) {
2191                 dev_err(dev->class_dev, "cannot run command without an irq\n");
2192                 return -EIO;
2193         }
2194         ni_clear_ai_fifo(dev);
2195
2196         ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist);
2197
2198         /* start configuration */
2199         ni_stc_writew(dev, NISTC_RESET_AI_CFG_START, NISTC_RESET_REG);
2200
2201         /*
2202          * Disable analog triggering for now, since it interferes
2203          * with the use of pfi0.
2204          */
2205         devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA;
2206         ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
2207
2208         ai_trig = NISTC_AI_TRIG_START2_SEL(0) | NISTC_AI_TRIG_START1_SYNC;
2209         switch (cmd->start_src) {
2210         case TRIG_INT:
2211         case TRIG_NOW:
2212                 ai_trig |= NISTC_AI_TRIG_START1_EDGE |
2213                            NISTC_AI_TRIG_START1_SEL(0);
2214                 break;
2215         case TRIG_EXT:
2216                 ai_trig |= NISTC_AI_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) +
2217                                                     1);
2218
2219                 if (cmd->start_arg & CR_INVERT)
2220                         ai_trig |= NISTC_AI_TRIG_START1_POLARITY;
2221                 if (cmd->start_arg & CR_EDGE)
2222                         ai_trig |= NISTC_AI_TRIG_START1_EDGE;
2223                 break;
2224         }
2225         ni_stc_writew(dev, ai_trig, NISTC_AI_TRIG_SEL_REG);
2226
2227         mode2 &= ~NISTC_AI_MODE2_PRE_TRIGGER;
2228         mode2 &= ~NISTC_AI_MODE2_SC_INIT_LOAD_SRC;
2229         mode2 &= ~NISTC_AI_MODE2_SC_RELOAD_MODE;
2230         ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2231
2232         if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) {
2233                 /* logic low */
2234                 start_stop_select |= NISTC_AI_STOP_POLARITY |
2235                                      NISTC_AI_STOP_SEL(31) |
2236                                      NISTC_AI_STOP_SYNC;
2237         } else {
2238                 /*  ai configuration memory */
2239                 start_stop_select |= NISTC_AI_STOP_SEL(19);
2240         }
2241         ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2242
2243         devpriv->ai_cmd2 = 0;
2244         switch (cmd->stop_src) {
2245         case TRIG_COUNT:
2246                 stop_count = cmd->stop_arg - 1;
2247
2248                 if (devpriv->is_611x) {
2249                         /*  have to take 3 stage adc pipeline into account */
2250                         stop_count += num_adc_stages_611x;
2251                 }
2252                 /* stage number of scans */
2253                 ni_stc_writel(dev, stop_count, NISTC_AI_SC_LOADA_REG);
2254
2255                 mode1 |= NISTC_AI_MODE1_START_STOP |
2256                          NISTC_AI_MODE1_RSVD |
2257                          NISTC_AI_MODE1_TRIGGER_ONCE;
2258                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2259                 /* load SC (Scan Count) */
2260                 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2261
2262                 if (stop_count == 0) {
2263                         devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS;
2264                         interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2265                         /*
2266                          * This is required to get the last sample for
2267                          * chanlist_len > 1, not sure why.
2268                          */
2269                         if (cmd->chanlist_len > 1)
2270                                 start_stop_select |= NISTC_AI_STOP_POLARITY |
2271                                                      NISTC_AI_STOP_EDGE;
2272                 }
2273                 break;
2274         case TRIG_NONE:
2275                 /* stage number of scans */
2276                 ni_stc_writel(dev, 0, NISTC_AI_SC_LOADA_REG);
2277
2278                 mode1 |= NISTC_AI_MODE1_START_STOP |
2279                          NISTC_AI_MODE1_RSVD |
2280                          NISTC_AI_MODE1_CONTINUOUS;
2281                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2282
2283                 /* load SC (Scan Count) */
2284                 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2285                 break;
2286         }
2287
2288         switch (cmd->scan_begin_src) {
2289         case TRIG_TIMER:
2290                 /*
2291                  * stop bits for non 611x boards
2292                  * NISTC_AI_MODE3_SI_TRIG_DELAY=0
2293                  * NISTC_AI_MODE2_PRE_TRIGGER=0
2294                  * NISTC_AI_START_STOP_REG:
2295                  * NISTC_AI_START_POLARITY=0    (?) rising edge
2296                  * NISTC_AI_START_EDGE=1        edge triggered
2297                  * NISTC_AI_START_SYNC=1        (?)
2298                  * NISTC_AI_START_SEL=0         SI_TC
2299                  * NISTC_AI_STOP_POLARITY=0     rising edge
2300                  * NISTC_AI_STOP_EDGE=0         level
2301                  * NISTC_AI_STOP_SYNC=1
2302                  * NISTC_AI_STOP_SEL=19         external pin (configuration mem)
2303                  */
2304                 start_stop_select |= NISTC_AI_START_EDGE | NISTC_AI_START_SYNC;
2305                 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2306
2307                 mode2 &= ~NISTC_AI_MODE2_SI_INIT_LOAD_SRC;      /* A */
2308                 mode2 |= NISTC_AI_MODE2_SI_RELOAD_MODE(0);
2309                 /* mode2 |= NISTC_AI_MODE2_SC_RELOAD_MODE; */
2310                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2311
2312                 /* load SI */
2313                 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2314                                        CMDF_ROUND_NEAREST);
2315                 ni_stc_writel(dev, timer, NISTC_AI_SI_LOADA_REG);
2316                 ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG);
2317                 break;
2318         case TRIG_EXT:
2319                 if (cmd->scan_begin_arg & CR_EDGE)
2320                         start_stop_select |= NISTC_AI_START_EDGE;
2321                 if (cmd->scan_begin_arg & CR_INVERT)    /* falling edge */
2322                         start_stop_select |= NISTC_AI_START_POLARITY;
2323                 if (cmd->scan_begin_src != cmd->convert_src ||
2324                     (cmd->scan_begin_arg & ~CR_EDGE) !=
2325                     (cmd->convert_arg & ~CR_EDGE))
2326                         start_stop_select |= NISTC_AI_START_SYNC;
2327                 start_stop_select |=
2328                     NISTC_AI_START_SEL(1 + CR_CHAN(cmd->scan_begin_arg));
2329                 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2330                 break;
2331         }
2332
2333         switch (cmd->convert_src) {
2334         case TRIG_TIMER:
2335         case TRIG_NOW:
2336                 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2337                         timer = 1;
2338                 else
2339                         timer = ni_ns_to_timer(dev, cmd->convert_arg,
2340                                                CMDF_ROUND_NEAREST);
2341                 /* 0,0 does not work */
2342                 ni_stc_writew(dev, 1, NISTC_AI_SI2_LOADA_REG);
2343                 ni_stc_writew(dev, timer, NISTC_AI_SI2_LOADB_REG);
2344
2345                 mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC;     /* A */
2346                 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE;        /* alternate */
2347                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2348
2349                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_LOAD, NISTC_AI_CMD1_REG);
2350
2351                 mode2 |= NISTC_AI_MODE2_SI2_INIT_LOAD_SRC;      /* B */
2352                 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE;        /* alternate */
2353                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2354                 break;
2355         case TRIG_EXT:
2356                 mode1 |= NISTC_AI_MODE1_CONVERT_SRC(1 +
2357                                                     CR_CHAN(cmd->convert_arg));
2358                 if ((cmd->convert_arg & CR_INVERT) == 0)
2359                         mode1 |= NISTC_AI_MODE1_CONVERT_POLARITY;
2360                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2361
2362                 mode2 |= NISTC_AI_MODE2_SC_GATE_ENA |
2363                          NISTC_AI_MODE2_START_STOP_GATE_ENA;
2364                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2365
2366                 break;
2367         }
2368
2369         if (dev->irq) {
2370                 /* interrupt on FIFO, errors, SC_TC */
2371                 interrupt_a_enable |= NISTC_INTA_ENA_AI_ERR |
2372                                       NISTC_INTA_ENA_AI_SC_TC;
2373
2374 #ifndef PCIDMA
2375                 interrupt_a_enable |= NISTC_INTA_ENA_AI_FIFO;
2376 #endif
2377
2378                 if ((cmd->flags & CMDF_WAKE_EOS) ||
2379                     (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) {
2380                         /* wake on end-of-scan */
2381                         devpriv->aimode = AIMODE_SCAN;
2382                 } else {
2383                         devpriv->aimode = AIMODE_HALF_FULL;
2384                 }
2385
2386                 switch (devpriv->aimode) {
2387                 case AIMODE_HALF_FULL:
2388                         /* FIFO interrupts and DMA requests on half-full */
2389 #ifdef PCIDMA
2390                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF_E,
2391                                       NISTC_AI_MODE3_REG);
2392 #else
2393                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2394                                       NISTC_AI_MODE3_REG);
2395 #endif
2396                         break;
2397                 case AIMODE_SAMPLE:
2398                         /*generate FIFO interrupts on non-empty */
2399                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2400                                       NISTC_AI_MODE3_REG);
2401                         break;
2402                 case AIMODE_SCAN:
2403 #ifdef PCIDMA
2404                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2405                                       NISTC_AI_MODE3_REG);
2406 #else
2407                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2408                                       NISTC_AI_MODE3_REG);
2409 #endif
2410                         interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2411                         break;
2412                 default:
2413                         break;
2414                 }
2415
2416                 /* clear interrupts */
2417                 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
2418
2419                 ni_set_bits(dev, NISTC_INTA_ENA_REG, interrupt_a_enable, 1);
2420         } else {
2421                 /* interrupt on nothing */
2422                 ni_set_bits(dev, NISTC_INTA_ENA_REG, ~0, 0);
2423
2424                 /* XXX start polling if necessary */
2425         }
2426
2427         /* end configuration */
2428         ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
2429
2430         switch (cmd->scan_begin_src) {
2431         case TRIG_TIMER:
2432                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2433                                    NISTC_AI_CMD1_SI_ARM |
2434                                    NISTC_AI_CMD1_DIV_ARM |
2435                                    NISTC_AI_CMD1_SC_ARM,
2436                               NISTC_AI_CMD1_REG);
2437                 break;
2438         case TRIG_EXT:
2439                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2440                                    NISTC_AI_CMD1_SI_ARM |       /* XXX ? */
2441                                    NISTC_AI_CMD1_DIV_ARM |
2442                                    NISTC_AI_CMD1_SC_ARM,
2443                               NISTC_AI_CMD1_REG);
2444                 break;
2445         }
2446
2447 #ifdef PCIDMA
2448         {
2449                 int retval = ni_ai_setup_MITE_dma(dev);
2450
2451                 if (retval)
2452                         return retval;
2453         }
2454 #endif
2455
2456         if (cmd->start_src == TRIG_NOW) {
2457                 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE |
2458                                    devpriv->ai_cmd2,
2459                               NISTC_AI_CMD2_REG);
2460                 s->async->inttrig = NULL;
2461         } else if (cmd->start_src == TRIG_EXT) {
2462                 s->async->inttrig = NULL;
2463         } else {        /* TRIG_INT */
2464                 s->async->inttrig = ni_ai_inttrig;
2465         }
2466
2467         return 0;
2468 }
2469
2470 static int ni_ai_insn_config(struct comedi_device *dev,
2471                              struct comedi_subdevice *s,
2472                              struct comedi_insn *insn, unsigned int *data)
2473 {
2474         struct ni_private *devpriv = dev->private;
2475
2476         if (insn->n < 1)
2477                 return -EINVAL;
2478
2479         switch (data[0]) {
2480         case INSN_CONFIG_ALT_SOURCE:
2481                 if (devpriv->is_m_series) {
2482                         if (data[1] & ~NI_M_CFG_BYPASS_AI_CAL_MASK)
2483                                 return -EINVAL;
2484                         devpriv->ai_calib_source = data[1];
2485                 } else if (devpriv->is_6143) {
2486                         unsigned int calib_source;
2487
2488                         calib_source = data[1] & 0xf;
2489
2490                         devpriv->ai_calib_source = calib_source;
2491                         ni_writew(dev, calib_source, NI6143_CALIB_CHAN_REG);
2492                 } else {
2493                         unsigned int calib_source;
2494                         unsigned int calib_source_adjust;
2495
2496                         calib_source = data[1] & 0xf;
2497                         calib_source_adjust = (data[1] >> 4) & 0xff;
2498
2499                         if (calib_source >= 8)
2500                                 return -EINVAL;
2501                         devpriv->ai_calib_source = calib_source;
2502                         if (devpriv->is_611x) {
2503                                 ni_writeb(dev, calib_source_adjust,
2504                                           NI611X_CAL_GAIN_SEL_REG);
2505                         }
2506                 }
2507                 return 2;
2508         default:
2509                 break;
2510         }
2511
2512         return -EINVAL;
2513 }
2514
2515 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2516                         void *data, unsigned int num_bytes,
2517                         unsigned int chan_index)
2518 {
2519         struct comedi_cmd *cmd = &s->async->cmd;
2520         unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
2521         unsigned short *array = data;
2522         unsigned int i;
2523 #ifdef PCIDMA
2524         __le16 buf, *barray = data;
2525 #endif
2526
2527         for (i = 0; i < nsamples; i++) {
2528                 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]);
2529                 unsigned short val = array[i];
2530
2531                 /*
2532                  * Munge data from unsigned to two's complement for
2533                  * bipolar ranges.
2534                  */
2535                 if (comedi_range_is_bipolar(s, range))
2536                         val = comedi_offset_munge(s, val);
2537 #ifdef PCIDMA
2538                 buf = cpu_to_le16(val);
2539                 barray[i] = buf;
2540 #else
2541                 array[i] = val;
2542 #endif
2543                 chan_index++;
2544                 chan_index %= cmd->chanlist_len;
2545         }
2546 }
2547
2548 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2549                                           struct comedi_subdevice *s,
2550                                           unsigned int chanspec[],
2551                                           unsigned int n_chans, int timed)
2552 {
2553         struct ni_private *devpriv = dev->private;
2554         unsigned int range;
2555         unsigned int chan;
2556         unsigned int conf;
2557         int i;
2558         int invert = 0;
2559
2560         if (timed) {
2561                 for (i = 0; i < s->n_chan; ++i) {
2562                         devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED;
2563                         ni_writeb(dev, devpriv->ao_conf[i],
2564                                   NI_M_AO_CFG_BANK_REG(i));
2565                         ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i));
2566                 }
2567         }
2568         for (i = 0; i < n_chans; i++) {
2569                 const struct comedi_krange *krange;
2570
2571                 chan = CR_CHAN(chanspec[i]);
2572                 range = CR_RANGE(chanspec[i]);
2573                 krange = s->range_table->range + range;
2574                 invert = 0;
2575                 conf = 0;
2576                 switch (krange->max - krange->min) {
2577                 case 20000000:
2578                         conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2579                         ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2580                         break;
2581                 case 10000000:
2582                         conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2583                         ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2584                         break;
2585                 case 4000000:
2586                         conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2587                         ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2588                                   NI_M_AO_REF_ATTENUATION_REG(chan));
2589                         break;
2590                 case 2000000:
2591                         conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2592                         ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2593                                   NI_M_AO_REF_ATTENUATION_REG(chan));
2594                         break;
2595                 default:
2596                         dev_err(dev->class_dev,
2597                                 "bug! unhandled ao reference voltage\n");
2598                         break;
2599                 }
2600                 switch (krange->max + krange->min) {
2601                 case 0:
2602                         conf |= NI_M_AO_CFG_BANK_OFFSET_0V;
2603                         break;
2604                 case 10000000:
2605                         conf |= NI_M_AO_CFG_BANK_OFFSET_5V;
2606                         break;
2607                 default:
2608                         dev_err(dev->class_dev,
2609                                 "bug! unhandled ao offset voltage\n");
2610                         break;
2611                 }
2612                 if (timed)
2613                         conf |= NI_M_AO_CFG_BANK_UPDATE_TIMED;
2614                 ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan));
2615                 devpriv->ao_conf[chan] = conf;
2616                 ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan));
2617         }
2618         return invert;
2619 }
2620
2621 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2622                                      struct comedi_subdevice *s,
2623                                      unsigned int chanspec[],
2624                                      unsigned int n_chans)
2625 {
2626         struct ni_private *devpriv = dev->private;
2627         unsigned int range;
2628         unsigned int chan;
2629         unsigned int conf;
2630         int i;
2631         int invert = 0;
2632
2633         for (i = 0; i < n_chans; i++) {
2634                 chan = CR_CHAN(chanspec[i]);
2635                 range = CR_RANGE(chanspec[i]);
2636                 conf = NI_E_AO_DACSEL(chan);
2637
2638                 if (comedi_range_is_bipolar(s, range)) {
2639                         conf |= NI_E_AO_CFG_BIP;
2640                         invert = (s->maxdata + 1) >> 1;
2641                 } else {
2642                         invert = 0;
2643                 }
2644                 if (comedi_range_is_external(s, range))
2645                         conf |= NI_E_AO_EXT_REF;
2646
2647                 /* not all boards can deglitch, but this shouldn't hurt */
2648                 if (chanspec[i] & CR_DEGLITCH)
2649                         conf |= NI_E_AO_DEGLITCH;
2650
2651                 /* analog reference */
2652                 /* AREF_OTHER connects AO ground to AI ground, i think */
2653                 if (CR_AREF(chanspec[i]) == AREF_OTHER)
2654                         conf |= NI_E_AO_GROUND_REF;
2655
2656                 ni_writew(dev, conf, NI_E_AO_CFG_REG);
2657                 devpriv->ao_conf[chan] = conf;
2658         }
2659         return invert;
2660 }
2661
2662 static int ni_ao_config_chanlist(struct comedi_device *dev,
2663                                  struct comedi_subdevice *s,
2664                                  unsigned int chanspec[], unsigned int n_chans,
2665                                  int timed)
2666 {
2667         struct ni_private *devpriv = dev->private;
2668
2669         if (devpriv->is_m_series)
2670                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2671                                                       timed);
2672         else
2673                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2674 }
2675
2676 static int ni_ao_insn_write(struct comedi_device *dev,
2677                             struct comedi_subdevice *s,
2678                             struct comedi_insn *insn,
2679                             unsigned int *data)
2680 {
2681         struct ni_private *devpriv = dev->private;
2682         unsigned int chan = CR_CHAN(insn->chanspec);
2683         unsigned int range = CR_RANGE(insn->chanspec);
2684         int reg;
2685         int i;
2686
2687         if (devpriv->is_6xxx) {
2688                 ni_ao_win_outw(dev, 1 << chan, NI671X_AO_IMMEDIATE_REG);
2689
2690                 reg = NI671X_DAC_DIRECT_DATA_REG(chan);
2691         } else if (devpriv->is_m_series) {
2692                 reg = NI_M_DAC_DIRECT_DATA_REG(chan);
2693         } else {
2694                 reg = NI_E_DAC_DIRECT_DATA_REG(chan);
2695         }
2696
2697         ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2698
2699         for (i = 0; i < insn->n; i++) {
2700                 unsigned int val = data[i];
2701
2702                 s->readback[chan] = val;
2703
2704                 if (devpriv->is_6xxx) {
2705                         /*
2706                          * 6xxx boards have bipolar outputs, munge the
2707                          * unsigned comedi values to 2's complement
2708                          */
2709                         val = comedi_offset_munge(s, val);
2710
2711                         ni_ao_win_outw(dev, val, reg);
2712                 } else if (devpriv->is_m_series) {
2713                         /*
2714                          * M-series boards use offset binary values for
2715                          * bipolar and uinpolar outputs
2716                          */
2717                         ni_writew(dev, val, reg);
2718                 } else {
2719                         /*
2720                          * Non-M series boards need two's complement values
2721                          * for bipolar ranges.
2722                          */
2723                         if (comedi_range_is_bipolar(s, range))
2724                                 val = comedi_offset_munge(s, val);
2725
2726                         ni_writew(dev, val, reg);
2727                 }
2728         }
2729
2730         return insn->n;
2731 }
2732
2733 static int ni_ao_insn_config(struct comedi_device *dev,
2734                              struct comedi_subdevice *s,
2735                              struct comedi_insn *insn, unsigned int *data)
2736 {
2737         const struct ni_board_struct *board = dev->board_ptr;
2738         struct ni_private *devpriv = dev->private;
2739         unsigned int nbytes;
2740
2741         switch (data[0]) {
2742         case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2743                 switch (data[1]) {
2744                 case COMEDI_OUTPUT:
2745                         nbytes = comedi_samples_to_bytes(s,
2746                                                          board->ao_fifo_depth);
2747                         data[2] = 1 + nbytes;
2748                         if (devpriv->mite)
2749                                 data[2] += devpriv->mite->fifo_size;
2750                         break;
2751                 case COMEDI_INPUT:
2752                         data[2] = 0;
2753                         break;
2754                 default:
2755                         return -EINVAL;
2756                 }
2757                 return 0;
2758         default:
2759                 break;
2760         }
2761
2762         return -EINVAL;
2763 }
2764
2765 static int ni_ao_inttrig(struct comedi_device *dev,
2766                          struct comedi_subdevice *s,
2767                          unsigned int trig_num)
2768 {
2769         struct ni_private *devpriv = dev->private;
2770         struct comedi_cmd *cmd = &s->async->cmd;
2771         int ret;
2772         int interrupt_b_bits;
2773         int i;
2774         static const int timeout = 1000;
2775
2776         /*
2777          * Require trig_num == cmd->start_arg when cmd->start_src == TRIG_INT.
2778          * For backwards compatibility, also allow trig_num == 0 when
2779          * cmd->start_src != TRIG_INT (i.e. when cmd->start_src == TRIG_EXT);
2780          * in that case, the internal trigger is being used as a pre-trigger
2781          * before the external trigger.
2782          */
2783         if (!(trig_num == cmd->start_arg ||
2784               (trig_num == 0 && cmd->start_src != TRIG_INT)))
2785                 return -EINVAL;
2786
2787         /*
2788          * Null trig at beginning prevent ao start trigger from executing more
2789          * than once per command (and doing things like trying to allocate the
2790          * ao dma channel multiple times).
2791          */
2792         s->async->inttrig = NULL;
2793
2794         ni_set_bits(dev, NISTC_INTB_ENA_REG,
2795                     NISTC_INTB_ENA_AO_FIFO | NISTC_INTB_ENA_AO_ERR, 0);
2796         interrupt_b_bits = NISTC_INTB_ENA_AO_ERR;
2797 #ifdef PCIDMA
2798         ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
2799         if (devpriv->is_6xxx)
2800                 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
2801         ret = ni_ao_setup_MITE_dma(dev);
2802         if (ret)
2803                 return ret;
2804         ret = ni_ao_wait_for_dma_load(dev);
2805         if (ret < 0)
2806                 return ret;
2807 #else
2808         ret = ni_ao_prep_fifo(dev, s);
2809         if (ret == 0)
2810                 return -EPIPE;
2811
2812         interrupt_b_bits |= NISTC_INTB_ENA_AO_FIFO;
2813 #endif
2814
2815         ni_stc_writew(dev, devpriv->ao_mode3 | NISTC_AO_MODE3_NOT_AN_UPDATE,
2816                       NISTC_AO_MODE3_REG);
2817         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2818         /* wait for DACs to be loaded */
2819         for (i = 0; i < timeout; i++) {
2820                 udelay(1);
2821                 if ((ni_stc_readw(dev, NISTC_STATUS2_REG) &
2822                      NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS) == 0)
2823                         break;
2824         }
2825         if (i == timeout) {
2826                 dev_err(dev->class_dev,
2827                         "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n");
2828                 return -EIO;
2829         }
2830         /*
2831          * stc manual says we are need to clear error interrupt after
2832          * AO_TMRDACWRs_In_Progress_St clears
2833          */
2834         ni_stc_writew(dev, NISTC_INTB_ACK_AO_ERR, NISTC_INTB_ACK_REG);
2835
2836         ni_set_bits(dev, NISTC_INTB_ENA_REG, interrupt_b_bits, 1);
2837
2838         ni_stc_writew(dev, NISTC_AO_CMD1_UI_ARM |
2839                            NISTC_AO_CMD1_UC_ARM |
2840                            NISTC_AO_CMD1_BC_ARM |
2841                            devpriv->ao_cmd1,
2842                       NISTC_AO_CMD1_REG);
2843
2844         ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2,
2845                       NISTC_AO_CMD2_REG);
2846
2847         return 0;
2848 }
2849
2850 /*
2851  * begin ni_ao_cmd.
2852  * Organized similar to NI-STC and MHDDK examples.
2853  * ni_ao_cmd is broken out into configuration sub-routines for clarity.
2854  */
2855
2856 static void ni_ao_cmd_personalize(struct comedi_device *dev,
2857                                   const struct comedi_cmd *cmd)
2858 {
2859         const struct ni_board_struct *board = dev->board_ptr;
2860         unsigned int bits;
2861
2862         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2863
2864         bits =
2865           /* fast CPU interface--only eseries */
2866           /* ((slow CPU interface) ? 0 : AO_Fast_CPU) | */
2867           NISTC_AO_PERSONAL_BC_SRC_SEL  |
2868           0 /* (use_original_pulse ? 0 : NISTC_AO_PERSONAL_UPDATE_TIMEBASE) */ |
2869           /*
2870            * FIXME:  start setting following bit when appropriate.  Need to
2871            * determine whether board is E4 or E1.
2872            * FROM MHHDK:
2873            * if board is E4 or E1
2874            *   Set bit "NISTC_AO_PERSONAL_UPDATE_PW" to 0
2875            * else
2876            *   set it to 1
2877            */
2878           NISTC_AO_PERSONAL_UPDATE_PW   |
2879           /* FIXME:  when should we set following bit to zero? */
2880           NISTC_AO_PERSONAL_TMRDACWR_PW |
2881           (board->ao_fifo_depth ?
2882             NISTC_AO_PERSONAL_FIFO_ENA : NISTC_AO_PERSONAL_DMA_PIO_CTRL)
2883           ;
2884 #if 0
2885         /*
2886          * FIXME:
2887          * add something like ".has_individual_dacs = 0" to ni_board_struct
2888          * since, as F Hess pointed out, not all in m series have singles.  not
2889          * sure if e-series all have duals...
2890          */
2891
2892         /*
2893          * F Hess: windows driver does not set NISTC_AO_PERSONAL_NUM_DAC bit for
2894          * 6281, verified with bus analyzer.
2895          */
2896         if (devpriv->is_m_series)
2897                 bits |= NISTC_AO_PERSONAL_NUM_DAC;
2898 #endif
2899         ni_stc_writew(dev, bits, NISTC_AO_PERSONAL_REG);
2900
2901         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
2902 }
2903
2904 static void ni_ao_cmd_set_trigger(struct comedi_device *dev,
2905                                   const struct comedi_cmd *cmd)
2906 {
2907         struct ni_private *devpriv = dev->private;
2908         unsigned int trigsel;
2909
2910         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2911
2912         /* sync */
2913         if (cmd->stop_src == TRIG_NONE) {
2914                 devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS;
2915                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE;
2916         } else {
2917                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS;
2918                 devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE;
2919         }
2920         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2921
2922         if (cmd->start_src == TRIG_INT) {
2923                 trigsel = NISTC_AO_TRIG_START1_EDGE |
2924                           NISTC_AO_TRIG_START1_SYNC;
2925         } else { /* TRIG_EXT */
2926                 trigsel = NISTC_AO_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) + 1);
2927                 /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
2928                 if (cmd->start_arg & CR_INVERT)
2929                         trigsel |= NISTC_AO_TRIG_START1_POLARITY;
2930                 /* 0=edge detection disabled, 1=enabled */
2931                 if (cmd->start_arg & CR_EDGE)
2932                         trigsel |= NISTC_AO_TRIG_START1_EDGE;
2933         }
2934         ni_stc_writew(dev, trigsel, NISTC_AO_TRIG_SEL_REG);
2935
2936         /* AO_Delayed_START1 = 0, we do not support delayed start...yet */
2937
2938         /* sync */
2939         /* select DA_START1 as PFI6/AO_START1 when configured as an output */
2940         devpriv->ao_mode3 &= ~NISTC_AO_MODE3_TRIG_LEN;
2941         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2942
2943         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
2944 }
2945
2946 static void ni_ao_cmd_set_counters(struct comedi_device *dev,
2947                                    const struct comedi_cmd *cmd)
2948 {
2949         struct ni_private *devpriv = dev->private;
2950         /* Not supporting 'waveform staging' or 'local buffer with pauses' */
2951
2952         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2953         /*
2954          * This relies on ao_mode1/(Trigger_Once | Continuous) being set in
2955          * set_trigger above.  It is unclear whether we really need to re-write
2956          * this register with these values.  The mhddk examples for e-series
2957          * show writing this in both places, but the examples for m-series show
2958          * a single write in the set_counters function (here).
2959          */
2960         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2961
2962         /* sync (upload number of buffer iterations -1) */
2963         /* indicate that we want to use BC_Load_A_Register as the source */
2964         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC;
2965         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
2966
2967         /*
2968          * if the BC_TC interrupt is still issued in spite of UC, BC, UI
2969          * ignoring BC_TC, then we will need to find a way to ignore that
2970          * interrupt in continuous mode.
2971          */
2972         ni_stc_writel(dev, 0, NISTC_AO_BC_LOADA_REG); /* iter once */
2973
2974         /* sync (issue command to load number of buffer iterations -1) */
2975         ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG);
2976
2977         /* sync (upload number of updates in buffer) */
2978         /* indicate that we want to use UC_Load_A_Register as the source */
2979         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC;
2980         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
2981
2982         /*
2983          * if a user specifies '0', this automatically assumes the entire 24bit
2984          * address space is available for the (multiple iterations of single
2985          * buffer) MISB.  Otherwise, stop_arg specifies the MISB length that
2986          * will be used, regardless of whether we are in continuous mode or not.
2987          * In continuous mode, the output will just iterate indefinitely over
2988          * the MISB.
2989          */
2990         {
2991                 unsigned int stop_arg = cmd->stop_arg > 0 ?
2992                         (cmd->stop_arg & 0xffffff) : 0xffffff;
2993
2994                 if (devpriv->is_m_series) {
2995                         /*
2996                          * this is how the NI example code does it for m-series
2997                          * boards, verified correct with 6259
2998                          */
2999                         ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
3000
3001                         /* sync (issue cmd to load number of updates in MISB) */
3002                         ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3003                                       NISTC_AO_CMD1_REG);
3004                 } else {
3005                         ni_stc_writel(dev, stop_arg, NISTC_AO_UC_LOADA_REG);
3006
3007                         /* sync (issue cmd to load number of updates in MISB) */
3008                         ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3009                                       NISTC_AO_CMD1_REG);
3010
3011                         /*
3012                          * sync (upload number of updates-1 in MISB)
3013                          * --eseries only?
3014                          */
3015                         ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
3016                 }
3017         }
3018
3019         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3020 }
3021
3022 static void ni_ao_cmd_set_update(struct comedi_device *dev,
3023                                  const struct comedi_cmd *cmd)
3024 {
3025         struct ni_private *devpriv = dev->private;
3026
3027         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3028
3029         /*
3030          * zero out these bit fields to be set below. Does an ao-reset do this
3031          * automatically?
3032          */
3033         devpriv->ao_mode1 &= ~(
3034           NISTC_AO_MODE1_UI_SRC_MASK         |
3035           NISTC_AO_MODE1_UI_SRC_POLARITY     |
3036           NISTC_AO_MODE1_UPDATE_SRC_MASK     |
3037           NISTC_AO_MODE1_UPDATE_SRC_POLARITY
3038         );
3039
3040         if (cmd->scan_begin_src == TRIG_TIMER) {
3041                 unsigned int trigvar;
3042
3043                 devpriv->ao_cmd2  &= ~NISTC_AO_CMD2_BC_GATE_ENA;
3044
3045                 /*
3046                  * NOTE: there are several other ways of configuring internal
3047                  * updates, but we'll only support one for now:  using
3048                  * AO_IN_TIMEBASE, w/o waveform staging, w/o a delay between
3049                  * START1 and first update, and also w/o local buffer mode w/
3050                  * pauses.
3051                  */
3052
3053                 /*
3054                  * This is already done above:
3055                  * devpriv->ao_mode1 &= ~(
3056                  *   // set UPDATE_Source to UI_TC:
3057                  *   NISTC_AO_MODE1_UPDATE_SRC_MASK |
3058                  *   // set UPDATE_Source_Polarity to rising (required?)
3059                  *   NISTC_AO_MODE1_UPDATE_SRC_POLARITY |
3060                  *   // set UI_Source to AO_IN_TIMEBASE1:
3061                  *   NISTC_AO_MODE1_UI_SRC_MASK     |
3062                  *   // set UI_Source_Polarity to rising (required?)
3063                  *   NISTC_AO_MODE1_UI_SRC_POLARITY
3064                  * );
3065                  */
3066
3067                 /*
3068                  * TODO:  use ao_ui_clock_source to allow all possible signals
3069                  * to be routed to UI_Source_Select.  See tSTC.h for
3070                  * eseries/ni67xx and tMSeries.h for mseries.
3071                  */
3072
3073                 trigvar = ni_ns_to_timer(dev, cmd->scan_begin_arg,
3074                                          CMDF_ROUND_NEAREST);
3075
3076                 /*
3077                  * Wait N TB3 ticks after the start trigger before
3078                  * clocking (N must be >=2).
3079                  */
3080                 /* following line: 2-1 per STC */
3081                 ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG);
3082                 ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, NISTC_AO_CMD1_REG);
3083                 ni_stc_writel(dev, trigvar, NISTC_AO_UI_LOADA_REG);
3084         } else { /* TRIG_EXT */
3085                 /* FIXME:  assert scan_begin_arg != 0, ret failure otherwise */
3086                 devpriv->ao_cmd2  |= NISTC_AO_CMD2_BC_GATE_ENA;
3087                 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC(
3088                                         CR_CHAN(cmd->scan_begin_arg));
3089                 if (cmd->scan_begin_arg & CR_INVERT)
3090                         devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY;
3091         }
3092
3093         ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3094         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3095         devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) |
3096                                NISTC_AO_MODE2_UI_INIT_LOAD_SRC);
3097         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3098
3099         /* Configure DAQ-STC for Timed update mode */
3100         devpriv->ao_cmd1 |= NISTC_AO_CMD1_DAC1_UPDATE_MODE |
3101                             NISTC_AO_CMD1_DAC0_UPDATE_MODE;
3102         /* We are not using UPDATE2-->don't have to set DACx_Source_Select */
3103         ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG);
3104
3105         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3106 }
3107
3108 static void ni_ao_cmd_set_channels(struct comedi_device *dev,
3109                                    struct comedi_subdevice *s)
3110 {
3111         struct ni_private *devpriv = dev->private;
3112         const struct comedi_cmd *cmd = &s->async->cmd;
3113         unsigned int bits = 0;
3114
3115         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3116
3117         if (devpriv->is_6xxx) {
3118                 unsigned int i;
3119
3120                 bits = 0;
3121                 for (i = 0; i < cmd->chanlist_len; ++i) {
3122                         int chan = CR_CHAN(cmd->chanlist[i]);
3123
3124                         bits |= 1 << chan;
3125                         ni_ao_win_outw(dev, chan, NI611X_AO_WAVEFORM_GEN_REG);
3126                 }
3127                 ni_ao_win_outw(dev, bits, NI611X_AO_TIMED_REG);
3128         }
3129
3130         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3131
3132         if (cmd->scan_end_arg > 1) {
3133                 devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN;
3134                 bits = NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1)
3135                                  | NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3136
3137         } else {
3138                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN;
3139                 bits = NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3140                 if (devpriv->is_m_series | devpriv->is_6xxx)
3141                         bits |= NISTC_AO_OUT_CTRL_CHANS(0);
3142                 else
3143                         bits |= NISTC_AO_OUT_CTRL_CHANS(
3144                                         CR_CHAN(cmd->chanlist[0]));
3145         }
3146
3147         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3148         ni_stc_writew(dev, bits,              NISTC_AO_OUT_CTRL_REG);
3149
3150         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3151 }
3152
3153 static void ni_ao_cmd_set_stop_conditions(struct comedi_device *dev,
3154                                           const struct comedi_cmd *cmd)
3155 {
3156         struct ni_private *devpriv = dev->private;
3157
3158         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3159
3160         devpriv->ao_mode3 |= NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR;
3161         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3162
3163         /*
3164          * Since we are not supporting waveform staging, we ignore these errors:
3165          * NISTC_AO_MODE3_STOP_ON_BC_TC_ERR,
3166          * NISTC_AO_MODE3_STOP_ON_BC_TC_TRIG_ERR
3167          */
3168
3169         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3170 }
3171
3172 static void ni_ao_cmd_set_fifo_mode(struct comedi_device *dev)
3173 {
3174         struct ni_private *devpriv = dev->private;
3175
3176         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3177
3178         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK;
3179 #ifdef PCIDMA
3180         devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F;
3181 #else
3182         devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF;
3183 #endif
3184         /* NOTE:  this is where use_onboard_memory=True would be implemented */
3185         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA;
3186         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3187
3188         /* enable sending of ao fifo requests (dma request) */
3189         ni_stc_writew(dev, NISTC_AO_START_AOFREQ_ENA, NISTC_AO_START_SEL_REG);
3190
3191         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3192
3193         /* we are not supporting boards with virtual fifos */
3194 }
3195
3196 static void ni_ao_cmd_set_interrupts(struct comedi_device *dev,
3197                                      struct comedi_subdevice *s)
3198 {
3199         if (s->async->cmd.stop_src == TRIG_COUNT)
3200                 ni_set_bits(dev, NISTC_INTB_ENA_REG,
3201                             NISTC_INTB_ENA_AO_BC_TC, 1);
3202
3203         s->async->inttrig = ni_ao_inttrig;
3204 }
3205
3206 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3207 {
3208         struct ni_private *devpriv = dev->private;
3209         const struct comedi_cmd *cmd = &s->async->cmd;
3210
3211         if (dev->irq == 0) {
3212                 dev_err(dev->class_dev, "cannot run command without an irq");
3213                 return -EIO;
3214         }
3215
3216         /* ni_ao_reset should have already been done */
3217         ni_ao_cmd_personalize(dev, cmd);
3218         /* clearing fifo and preload happens elsewhere */
3219
3220         ni_ao_cmd_set_trigger(dev, cmd);
3221         ni_ao_cmd_set_counters(dev, cmd);
3222         ni_ao_cmd_set_update(dev, cmd);
3223         ni_ao_cmd_set_channels(dev, s);
3224         ni_ao_cmd_set_stop_conditions(dev, cmd);
3225         ni_ao_cmd_set_fifo_mode(dev);
3226         ni_cmd_set_mite_transfer(devpriv->ao_mite_ring, s, cmd, 0x00ffffff);
3227         ni_ao_cmd_set_interrupts(dev, s);
3228
3229         /*
3230          * arm(ing) and star(ting) happen in ni_ao_inttrig, which _must_ be
3231          * called for ao commands since 1) TRIG_NOW is not supported and 2) DMA
3232          * must be setup and initially written to before arm/start happen.
3233          */
3234         return 0;
3235 }
3236
3237 /* end ni_ao_cmd */
3238
3239 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3240                          struct comedi_cmd *cmd)
3241 {
3242         const struct ni_board_struct *board = dev->board_ptr;
3243         struct ni_private *devpriv = dev->private;
3244         int err = 0;
3245         unsigned int tmp;
3246
3247         /* Step 1 : check if triggers are trivially valid */
3248
3249         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3250         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3251                                         TRIG_TIMER | TRIG_EXT);
3252         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3253         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3254         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3255
3256         if (err)
3257                 return 1;
3258
3259         /* Step 2a : make sure trigger sources are unique */
3260
3261         err |= comedi_check_trigger_is_unique(cmd->start_src);
3262         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3263         err |= comedi_check_trigger_is_unique(cmd->stop_src);
3264
3265         /* Step 2b : and mutually compatible */
3266
3267         if (err)
3268                 return 2;
3269
3270         /* Step 3: check if arguments are trivially valid */
3271
3272         switch (cmd->start_src) {
3273         case TRIG_INT:
3274                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3275                 break;
3276         case TRIG_EXT:
3277                 tmp = CR_CHAN(cmd->start_arg);
3278
3279                 if (tmp > 18)
3280                         tmp = 18;
3281                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3282                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
3283                 break;
3284         }
3285
3286         if (cmd->scan_begin_src == TRIG_TIMER) {
3287                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3288                                                     board->ao_speed);
3289                 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
3290                                                     devpriv->clock_ns *
3291                                                     0xffffff);
3292         }
3293
3294         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3295         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3296                                            cmd->chanlist_len);
3297         err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3298
3299         if (err)
3300                 return 3;
3301
3302         /* step 4: fix up any arguments */
3303         if (cmd->scan_begin_src == TRIG_TIMER) {
3304                 tmp = cmd->scan_begin_arg;
3305                 cmd->scan_begin_arg =
3306                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3307                                                        cmd->scan_begin_arg,
3308                                                        cmd->flags));
3309                 if (tmp != cmd->scan_begin_arg)
3310                         err++;
3311         }
3312         if (err)
3313                 return 4;
3314
3315         return 0;
3316 }
3317
3318 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3319 {
3320         /* See 3.6.1.2 "Resetting", of DAQ-STC Technical Reference Manual */
3321
3322         /*
3323          * In the following, the "--sync" comments are meant to denote
3324          * asynchronous boundaries for setting the registers as described in the
3325          * DAQ-STC mostly in the order also described in the DAQ-STC.
3326          */
3327
3328         struct ni_private *devpriv = dev->private;
3329
3330         ni_release_ao_mite_channel(dev);
3331
3332         /* --sync (reset AO) */
3333         if (devpriv->is_m_series)
3334                 /* following example in mhddk for m-series */
3335                 ni_stc_writew(dev, NISTC_RESET_AO, NISTC_RESET_REG);
3336
3337         /*--sync (start config) */
3338         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3339
3340         /*--sync (Disarm) */
3341         ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
3342
3343         /*
3344          * --sync
3345          * (clear bunch of registers--mseries mhddk examples do not include
3346          * this)
3347          */
3348         devpriv->ao_cmd1  = 0;
3349         devpriv->ao_cmd2  = 0;
3350         devpriv->ao_mode1 = 0;
3351         devpriv->ao_mode2 = 0;
3352         if (devpriv->is_m_series)
3353                 devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE;
3354         else
3355                 devpriv->ao_mode3 = 0;
3356
3357         ni_stc_writew(dev, 0, NISTC_AO_PERSONAL_REG);
3358         ni_stc_writew(dev, 0, NISTC_AO_CMD1_REG);
3359         ni_stc_writew(dev, 0, NISTC_AO_CMD2_REG);
3360         ni_stc_writew(dev, 0, NISTC_AO_MODE1_REG);
3361         ni_stc_writew(dev, 0, NISTC_AO_MODE2_REG);
3362         ni_stc_writew(dev, 0, NISTC_AO_OUT_CTRL_REG);
3363         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3364         ni_stc_writew(dev, 0, NISTC_AO_START_SEL_REG);
3365         ni_stc_writew(dev, 0, NISTC_AO_TRIG_SEL_REG);
3366
3367         /*--sync (disable interrupts) */
3368         ni_set_bits(dev, NISTC_INTB_ENA_REG, ~0, 0);
3369
3370         /*--sync (ack) */
3371         ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL, NISTC_AO_PERSONAL_REG);
3372         ni_stc_writew(dev, NISTC_INTB_ACK_AO_ALL, NISTC_INTB_ACK_REG);
3373
3374         /*--not in DAQ-STC.  which doc? */
3375         if (devpriv->is_6xxx) {
3376                 ni_ao_win_outw(dev, (1u << s->n_chan) - 1u,
3377                                NI671X_AO_IMMEDIATE_REG);
3378                 ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG,
3379                                NI611X_AO_MISC_REG);
3380         }
3381         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3382         /*--end */
3383
3384         return 0;
3385 }
3386
3387 /* digital io */
3388
3389 static int ni_dio_insn_config(struct comedi_device *dev,
3390                               struct comedi_subdevice *s,
3391                               struct comedi_insn *insn,
3392                               unsigned int *data)
3393 {
3394         struct ni_private *devpriv = dev->private;
3395         int ret;
3396
3397         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3398         if (ret)
3399                 return ret;
3400
3401         devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK;
3402         devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits);
3403         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3404
3405         return insn->n;
3406 }
3407
3408 static int ni_dio_insn_bits(struct comedi_device *dev,
3409                             struct comedi_subdevice *s,
3410                             struct comedi_insn *insn,
3411                             unsigned int *data)
3412 {
3413         struct ni_private *devpriv = dev->private;
3414
3415         /* Make sure we're not using the serial part of the dio */
3416         if ((data[0] & (NISTC_DIO_SDIN | NISTC_DIO_SDOUT)) &&
3417             devpriv->serial_interval_ns)
3418                 return -EBUSY;
3419
3420         if (comedi_dio_update_state(s, data)) {
3421                 devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK;
3422                 devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state);
3423                 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3424         }
3425
3426         data[1] = ni_stc_readw(dev, NISTC_DIO_IN_REG);
3427
3428         return insn->n;
3429 }
3430
3431 #ifdef PCIDMA
3432 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3433                                        struct comedi_subdevice *s,
3434                                        struct comedi_insn *insn,
3435                                        unsigned int *data)
3436 {
3437         int ret;
3438
3439         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3440         if (ret)
3441                 return ret;
3442
3443         ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
3444
3445         return insn->n;
3446 }
3447
3448 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3449                                      struct comedi_subdevice *s,
3450                                      struct comedi_insn *insn,
3451                                      unsigned int *data)
3452 {
3453         if (comedi_dio_update_state(s, data))
3454                 ni_writel(dev, s->state, NI_M_DIO_REG);
3455
3456         data[1] = ni_readl(dev, NI_M_DIO_REG);
3457
3458         return insn->n;
3459 }
3460
3461 static int ni_cdio_check_chanlist(struct comedi_device *dev,
3462                                   struct comedi_subdevice *s,
3463                                   struct comedi_cmd *cmd)
3464 {
3465         int i;
3466
3467         for (i = 0; i < cmd->chanlist_len; ++i) {
3468                 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3469
3470                 if (chan != i)
3471                         return -EINVAL;
3472         }
3473
3474         return 0;
3475 }
3476
3477 static int ni_cdio_cmdtest(struct comedi_device *dev,
3478                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
3479 {
3480         unsigned int bytes_per_scan;
3481         int err = 0;
3482         int tmp;
3483
3484         /* Step 1 : check if triggers are trivially valid */
3485
3486         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT);
3487         err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3488         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3489         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3490         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3491
3492         if (err)
3493                 return 1;
3494
3495         /* Step 2a : make sure trigger sources are unique */
3496         /* Step 2b : and mutually compatible */
3497
3498         /* Step 3: check if arguments are trivially valid */
3499
3500         err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3501
3502         tmp = cmd->scan_begin_arg;
3503         tmp &= CR_PACK_FLAGS(NI_M_CDO_MODE_SAMPLE_SRC_MASK, 0, 0, CR_INVERT);
3504         if (tmp != cmd->scan_begin_arg)
3505                 err |= -EINVAL;
3506
3507         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3508         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3509                                            cmd->chanlist_len);
3510         bytes_per_scan = comedi_bytes_per_scan_cmd(s, cmd);
3511         if (bytes_per_scan) {
3512                 err |= comedi_check_trigger_arg_max(&cmd->stop_arg,
3513                                                     s->async->prealloc_bufsz /
3514                                                     bytes_per_scan);
3515         }
3516
3517         if (err)
3518                 return 3;
3519
3520         /* Step 4: fix up any arguments */
3521
3522         /* Step 5: check channel list if it exists */
3523
3524         if (cmd->chanlist && cmd->chanlist_len > 0)
3525                 err |= ni_cdio_check_chanlist(dev, s, cmd);
3526
3527         if (err)
3528                 return 5;
3529
3530         return 0;
3531 }
3532
3533 static int ni_cdo_inttrig(struct comedi_device *dev,
3534                           struct comedi_subdevice *s,
3535                           unsigned int trig_num)
3536 {
3537         struct comedi_cmd *cmd = &s->async->cmd;
3538         const unsigned int timeout = 1000;
3539         int retval = 0;
3540         unsigned int i;
3541         struct ni_private *devpriv = dev->private;
3542         unsigned long flags;
3543
3544         if (trig_num != cmd->start_arg)
3545                 return -EINVAL;
3546
3547         s->async->inttrig = NULL;
3548
3549         /* read alloc the entire buffer */
3550         comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
3551
3552         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3553         if (devpriv->cdo_mite_chan) {
3554                 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3555                 mite_dma_arm(devpriv->cdo_mite_chan);
3556         } else {
3557                 dev_err(dev->class_dev, "BUG: no cdo mite channel?\n");
3558                 retval = -EIO;
3559         }
3560         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3561         if (retval < 0)
3562                 return retval;
3563
3564         /*
3565          * XXX not sure what interrupt C group does
3566          * wait for dma to fill output fifo
3567          * ni_writeb(dev, NI_M_INTC_ENA, NI_M_INTC_ENA_REG);
3568          */
3569         for (i = 0; i < timeout; ++i) {
3570                 if (ni_readl(dev, NI_M_CDIO_STATUS_REG) &
3571                     NI_M_CDIO_STATUS_CDO_FIFO_FULL)
3572                         break;
3573                 usleep_range(10, 100);
3574         }
3575         if (i == timeout) {
3576                 dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n");
3577                 s->cancel(dev, s);
3578                 return -EIO;
3579         }
3580         ni_writel(dev, NI_M_CDO_CMD_ARM |
3581                        NI_M_CDO_CMD_ERR_INT_ENA_SET |
3582                        NI_M_CDO_CMD_F_E_INT_ENA_SET,
3583                   NI_M_CDIO_CMD_REG);
3584         return retval;
3585 }
3586
3587 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3588 {
3589         struct ni_private *devpriv = dev->private;
3590         const struct comedi_cmd *cmd = &s->async->cmd;
3591         unsigned int cdo_mode_bits;
3592         int retval;
3593
3594         ni_writel(dev, NI_M_CDO_CMD_RESET, NI_M_CDIO_CMD_REG);
3595         cdo_mode_bits = NI_M_CDO_MODE_FIFO_MODE |
3596                         NI_M_CDO_MODE_HALT_ON_ERROR |
3597                         NI_M_CDO_MODE_SAMPLE_SRC(CR_CHAN(cmd->scan_begin_arg));
3598         if (cmd->scan_begin_arg & CR_INVERT)
3599                 cdo_mode_bits |= NI_M_CDO_MODE_POLARITY;
3600         ni_writel(dev, cdo_mode_bits, NI_M_CDO_MODE_REG);
3601         if (s->io_bits) {
3602                 ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG);
3603                 ni_writel(dev, NI_M_CDO_CMD_SW_UPDATE, NI_M_CDIO_CMD_REG);
3604                 ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG);
3605         } else {
3606                 dev_err(dev->class_dev,
3607                         "attempted to run digital output command with no lines configured as outputs\n");
3608                 return -EIO;
3609         }
3610         retval = ni_request_cdo_mite_channel(dev);
3611         if (retval < 0)
3612                 return retval;
3613
3614         ni_cmd_set_mite_transfer(devpriv->cdo_mite_ring, s, cmd,
3615                                  s->async->prealloc_bufsz /
3616                                  comedi_bytes_per_scan(s));
3617
3618         s->async->inttrig = ni_cdo_inttrig;
3619
3620         return 0;
3621 }
3622
3623 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3624 {
3625         ni_writel(dev, NI_M_CDO_CMD_DISARM |
3626                        NI_M_CDO_CMD_ERR_INT_ENA_CLR |
3627                        NI_M_CDO_CMD_F_E_INT_ENA_CLR |
3628                        NI_M_CDO_CMD_F_REQ_INT_ENA_CLR,
3629                   NI_M_CDIO_CMD_REG);
3630         /*
3631          * XXX not sure what interrupt C group does
3632          * ni_writeb(dev, 0, NI_M_INTC_ENA_REG);
3633          */
3634         ni_writel(dev, 0, NI_M_CDO_MASK_ENA_REG);
3635         ni_release_cdo_mite_channel(dev);
3636         return 0;
3637 }
3638
3639 static void handle_cdio_interrupt(struct comedi_device *dev)
3640 {
3641         struct ni_private *devpriv = dev->private;
3642         unsigned int cdio_status;
3643         struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3644         unsigned long flags;
3645
3646         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3647         if (devpriv->cdo_mite_chan)
3648                 mite_ack_linkc(devpriv->cdo_mite_chan, s, true);
3649         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3650
3651         cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG);
3652         if (cdio_status & NI_M_CDIO_STATUS_CDO_ERROR) {
3653                 /* XXX just guessing this is needed and does something useful */
3654                 ni_writel(dev, NI_M_CDO_CMD_ERR_INT_CONFIRM,
3655                           NI_M_CDIO_CMD_REG);
3656                 s->async->events |= COMEDI_CB_OVERFLOW;
3657         }
3658         if (cdio_status & NI_M_CDIO_STATUS_CDO_FIFO_EMPTY) {
3659                 ni_writel(dev, NI_M_CDO_CMD_F_E_INT_ENA_CLR,
3660                           NI_M_CDIO_CMD_REG);
3661                 /* s->async->events |= COMEDI_CB_EOA; */
3662         }
3663         comedi_handle_events(dev, s);
3664 }
3665 #endif /*  PCIDMA */
3666
3667 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3668                                    struct comedi_subdevice *s,
3669                                    unsigned char data_out,
3670                                    unsigned char *data_in)
3671 {
3672         struct ni_private *devpriv = dev->private;
3673         unsigned int status1;
3674         int err = 0, count = 20;
3675
3676         devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK;
3677         devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out);
3678         ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3679
3680         status1 = ni_stc_readw(dev, NISTC_STATUS1_REG);
3681         if (status1 & NISTC_STATUS1_SERIO_IN_PROG) {
3682                 err = -EBUSY;
3683                 goto error;
3684         }
3685
3686         devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START;
3687         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3688         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START;
3689
3690         /* Wait until STC says we're done, but don't loop infinitely. */
3691         while ((status1 = ni_stc_readw(dev, NISTC_STATUS1_REG)) &
3692                NISTC_STATUS1_SERIO_IN_PROG) {
3693                 /* Delay one bit per loop */
3694                 udelay((devpriv->serial_interval_ns + 999) / 1000);
3695                 if (--count < 0) {
3696                         dev_err(dev->class_dev,
3697                                 "SPI serial I/O didn't finish in time!\n");
3698                         err = -ETIME;
3699                         goto error;
3700                 }
3701         }
3702
3703         /*
3704          * Delay for last bit. This delay is absolutely necessary, because
3705          * NISTC_STATUS1_SERIO_IN_PROG goes high one bit too early.
3706          */
3707         udelay((devpriv->serial_interval_ns + 999) / 1000);
3708
3709         if (data_in)
3710                 *data_in = ni_stc_readw(dev, NISTC_DIO_SERIAL_IN_REG);
3711
3712 error:
3713         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3714
3715         return err;
3716 }
3717
3718 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3719                                    struct comedi_subdevice *s,
3720                                    unsigned char data_out,
3721                                    unsigned char *data_in)
3722 {
3723         struct ni_private *devpriv = dev->private;
3724         unsigned char mask, input = 0;
3725
3726         /* Wait for one bit before transfer */
3727         udelay((devpriv->serial_interval_ns + 999) / 1000);
3728
3729         for (mask = 0x80; mask; mask >>= 1) {
3730                 /*
3731                  * Output current bit; note that we cannot touch s->state
3732                  * because it is a per-subdevice field, and serial is
3733                  * a separate subdevice from DIO.
3734                  */
3735                 devpriv->dio_output &= ~NISTC_DIO_SDOUT;
3736                 if (data_out & mask)
3737                         devpriv->dio_output |= NISTC_DIO_SDOUT;
3738                 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3739
3740                 /*
3741                  * Assert SDCLK (active low, inverted), wait for half of
3742                  * the delay, deassert SDCLK, and wait for the other half.
3743                  */
3744                 devpriv->dio_control |= NISTC_DIO_SDCLK;
3745                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3746
3747                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3748
3749                 devpriv->dio_control &= ~NISTC_DIO_SDCLK;
3750                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3751
3752                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3753
3754                 /* Input current bit */
3755                 if (ni_stc_readw(dev, NISTC_DIO_IN_REG) & NISTC_DIO_SDIN)
3756                         input |= mask;
3757         }
3758
3759         if (data_in)
3760                 *data_in = input;
3761
3762         return 0;
3763 }
3764
3765 static int ni_serial_insn_config(struct comedi_device *dev,
3766                                  struct comedi_subdevice *s,
3767                                  struct comedi_insn *insn,
3768                                  unsigned int *data)
3769 {
3770         struct ni_private *devpriv = dev->private;
3771         unsigned int clk_fout = devpriv->clock_and_fout;
3772         int err = insn->n;
3773         unsigned char byte_out, byte_in = 0;
3774
3775         if (insn->n != 2)
3776                 return -EINVAL;
3777
3778         switch (data[0]) {
3779         case INSN_CONFIG_SERIAL_CLOCK:
3780                 devpriv->serial_hw_mode = 1;
3781                 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA;
3782
3783                 if (data[1] == SERIAL_DISABLED) {
3784                         devpriv->serial_hw_mode = 0;
3785                         devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3786                                                   NISTC_DIO_SDCLK);
3787                         data[1] = SERIAL_DISABLED;
3788                         devpriv->serial_interval_ns = data[1];
3789                 } else if (data[1] <= SERIAL_600NS) {
3790                         /*
3791                          * Warning: this clock speed is too fast to reliably
3792                          * control SCXI.
3793                          */
3794                         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3795                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE;
3796                         clk_fout &= ~NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3797                         data[1] = SERIAL_600NS;
3798                         devpriv->serial_interval_ns = data[1];
3799                 } else if (data[1] <= SERIAL_1_2US) {
3800                         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3801                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3802                                     NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3803                         data[1] = SERIAL_1_2US;
3804                         devpriv->serial_interval_ns = data[1];
3805                 } else if (data[1] <= SERIAL_10US) {
3806                         devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3807                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3808                                     NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3809                         /*
3810                          * Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects
3811                          * 600ns/1.2us. If you turn divide_by_2 off with the
3812                          * slow clock, you will still get 10us, except then
3813                          * all your delays are wrong.
3814                          */
3815                         data[1] = SERIAL_10US;
3816                         devpriv->serial_interval_ns = data[1];
3817                 } else {
3818                         devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3819                                                   NISTC_DIO_SDCLK);
3820                         devpriv->serial_hw_mode = 0;
3821                         data[1] = (data[1] / 1000) * 1000;
3822                         devpriv->serial_interval_ns = data[1];
3823                 }
3824                 devpriv->clock_and_fout = clk_fout;
3825
3826                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3827                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3828                 return 1;
3829
3830         case INSN_CONFIG_BIDIRECTIONAL_DATA:
3831
3832                 if (devpriv->serial_interval_ns == 0)
3833                         return -EINVAL;
3834
3835                 byte_out = data[1] & 0xFF;
3836
3837                 if (devpriv->serial_hw_mode) {
3838                         err = ni_serial_hw_readwrite8(dev, s, byte_out,
3839                                                       &byte_in);
3840                 } else if (devpriv->serial_interval_ns > 0) {
3841                         err = ni_serial_sw_readwrite8(dev, s, byte_out,
3842                                                       &byte_in);
3843                 } else {
3844                         dev_err(dev->class_dev, "serial disabled!\n");
3845                         return -EINVAL;
3846                 }
3847                 if (err < 0)
3848                         return err;
3849                 data[1] = byte_in & 0xFF;
3850                 return insn->n;
3851
3852                 break;
3853         default:
3854                 return -EINVAL;
3855         }
3856 }
3857
3858 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3859 {
3860         int i;
3861
3862         for (i = 0; i < s->n_chan; i++) {
3863                 ni_ao_win_outw(dev, NI_E_AO_DACSEL(i) | 0x0,
3864                                NI67XX_AO_CFG2_REG);
3865         }
3866         ni_ao_win_outw(dev, 0x0, NI67XX_AO_SP_UPDATES_REG);
3867 }
3868
3869 static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
3870         [NITIO_G0_AUTO_INC]     = { NISTC_G0_AUTOINC_REG, 2 },
3871         [NITIO_G1_AUTO_INC]     = { NISTC_G1_AUTOINC_REG, 2 },
3872         [NITIO_G0_CMD]          = { NISTC_G0_CMD_REG, 2 },
3873         [NITIO_G1_CMD]          = { NISTC_G1_CMD_REG, 2 },
3874         [NITIO_G0_HW_SAVE]      = { NISTC_G0_HW_SAVE_REG, 4 },
3875         [NITIO_G1_HW_SAVE]      = { NISTC_G1_HW_SAVE_REG, 4 },
3876         [NITIO_G0_SW_SAVE]      = { NISTC_G0_SAVE_REG, 4 },
3877         [NITIO_G1_SW_SAVE]      = { NISTC_G1_SAVE_REG, 4 },
3878         [NITIO_G0_MODE]         = { NISTC_G0_MODE_REG, 2 },
3879         [NITIO_G1_MODE]         = { NISTC_G1_MODE_REG, 2 },
3880         [NITIO_G0_LOADA]        = { NISTC_G0_LOADA_REG, 4 },
3881         [NITIO_G1_LOADA]        = { NISTC_G1_LOADA_REG, 4 },
3882         [NITIO_G0_LOADB]        = { NISTC_G0_LOADB_REG, 4 },
3883         [NITIO_G1_LOADB]        = { NISTC_G1_LOADB_REG, 4 },
3884         [NITIO_G0_INPUT_SEL]    = { NISTC_G0_INPUT_SEL_REG, 2 },
3885         [NITIO_G1_INPUT_SEL]    = { NISTC_G1_INPUT_SEL_REG, 2 },
3886         [NITIO_G0_CNT_MODE]     = { 0x1b0, 2 }, /* M-Series only */
3887         [NITIO_G1_CNT_MODE]     = { 0x1b2, 2 }, /* M-Series only */
3888         [NITIO_G0_GATE2]        = { 0x1b4, 2 }, /* M-Series only */
3889         [NITIO_G1_GATE2]        = { 0x1b6, 2 }, /* M-Series only */
3890         [NITIO_G01_STATUS]      = { NISTC_G01_STATUS_REG, 2 },
3891         [NITIO_G01_RESET]       = { NISTC_RESET_REG, 2 },
3892         [NITIO_G01_STATUS1]     = { NISTC_STATUS1_REG, 2 },
3893         [NITIO_G01_STATUS2]     = { NISTC_STATUS2_REG, 2 },
3894         [NITIO_G0_DMA_CFG]      = { 0x1b8, 2 }, /* M-Series only */
3895         [NITIO_G1_DMA_CFG]      = { 0x1ba, 2 }, /* M-Series only */
3896         [NITIO_G0_DMA_STATUS]   = { 0x1b8, 2 }, /* M-Series only */
3897         [NITIO_G1_DMA_STATUS]   = { 0x1ba, 2 }, /* M-Series only */
3898         [NITIO_G0_ABZ]          = { 0x1c0, 2 }, /* M-Series only */
3899         [NITIO_G1_ABZ]          = { 0x1c2, 2 }, /* M-Series only */
3900         [NITIO_G0_INT_ACK]      = { NISTC_INTA_ACK_REG, 2 },
3901         [NITIO_G1_INT_ACK]      = { NISTC_INTB_ACK_REG, 2 },
3902         [NITIO_G0_STATUS]       = { NISTC_AI_STATUS1_REG, 2 },
3903         [NITIO_G1_STATUS]       = { NISTC_AO_STATUS1_REG, 2 },
3904         [NITIO_G0_INT_ENA]      = { NISTC_INTA_ENA_REG, 2 },
3905         [NITIO_G1_INT_ENA]      = { NISTC_INTB_ENA_REG, 2 },
3906 };
3907
3908 static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev,
3909                                             enum ni_gpct_register reg)
3910 {
3911         const struct mio_regmap *regmap;
3912
3913         if (reg < ARRAY_SIZE(ni_gpct_to_stc_regmap)) {
3914                 regmap = &ni_gpct_to_stc_regmap[reg];
3915         } else {
3916                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
3917                          __func__, reg);
3918                 return 0;
3919         }
3920
3921         return regmap->mio_reg;
3922 }
3923
3924 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned int bits,
3925                                    enum ni_gpct_register reg)
3926 {
3927         struct comedi_device *dev = counter->counter_dev->dev;
3928         unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
3929
3930         if (stc_register == 0)
3931                 return;
3932
3933         switch (reg) {
3934                 /* m-series only registers */
3935         case NITIO_G0_CNT_MODE:
3936         case NITIO_G1_CNT_MODE:
3937         case NITIO_G0_GATE2:
3938         case NITIO_G1_GATE2:
3939         case NITIO_G0_DMA_CFG:
3940         case NITIO_G1_DMA_CFG:
3941         case NITIO_G0_ABZ:
3942         case NITIO_G1_ABZ:
3943                 ni_writew(dev, bits, stc_register);
3944                 break;
3945
3946                 /* 32 bit registers */
3947         case NITIO_G0_LOADA:
3948         case NITIO_G1_LOADA:
3949         case NITIO_G0_LOADB:
3950         case NITIO_G1_LOADB:
3951                 ni_stc_writel(dev, bits, stc_register);
3952                 break;
3953
3954                 /* 16 bit registers */
3955         case NITIO_G0_INT_ENA:
3956                 ni_set_bitfield(dev, stc_register,
3957                                 NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC,
3958                                 bits);
3959                 break;
3960         case NITIO_G1_INT_ENA:
3961                 ni_set_bitfield(dev, stc_register,
3962                                 NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC,
3963                                 bits);
3964                 break;
3965         default:
3966                 ni_stc_writew(dev, bits, stc_register);
3967         }
3968 }
3969
3970 static unsigned int ni_gpct_read_register(struct ni_gpct *counter,
3971                                           enum ni_gpct_register reg)
3972 {
3973         struct comedi_device *dev = counter->counter_dev->dev;
3974         unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
3975
3976         if (stc_register == 0)
3977                 return 0;
3978
3979         switch (reg) {
3980                 /* m-series only registers */
3981         case NITIO_G0_DMA_STATUS:
3982         case NITIO_G1_DMA_STATUS:
3983                 return ni_readw(dev, stc_register);
3984
3985                 /* 32 bit registers */
3986         case NITIO_G0_HW_SAVE:
3987         case NITIO_G1_HW_SAVE:
3988         case NITIO_G0_SW_SAVE:
3989         case NITIO_G1_SW_SAVE:
3990                 return ni_stc_readl(dev, stc_register);
3991
3992                 /* 16 bit registers */
3993         default:
3994                 return ni_stc_readw(dev, stc_register);
3995         }
3996 }
3997
3998 static int ni_freq_out_insn_read(struct comedi_device *dev,
3999                                  struct comedi_subdevice *s,
4000                                  struct comedi_insn *insn,
4001                                  unsigned int *data)
4002 {
4003         struct ni_private *devpriv = dev->private;
4004         unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout);
4005         int i;
4006
4007         for (i = 0; i < insn->n; i++)
4008                 data[i] = val;
4009
4010         return insn->n;
4011 }
4012
4013 static int ni_freq_out_insn_write(struct comedi_device *dev,
4014                                   struct comedi_subdevice *s,
4015                                   struct comedi_insn *insn,
4016                                   unsigned int *data)
4017 {
4018         struct ni_private *devpriv = dev->private;
4019
4020         if (insn->n) {
4021                 unsigned int val = data[insn->n - 1];
4022
4023                 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_ENA;
4024                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4025                 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_DIVIDER_MASK;
4026
4027                 /* use the last data value to set the fout divider */
4028                 devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val);
4029
4030                 devpriv->clock_and_fout |= NISTC_CLK_FOUT_ENA;
4031                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4032         }
4033         return insn->n;
4034 }
4035
4036 static int ni_freq_out_insn_config(struct comedi_device *dev,
4037                                    struct comedi_subdevice *s,
4038                                    struct comedi_insn *insn,
4039                                    unsigned int *data)
4040 {
4041         struct ni_private *devpriv = dev->private;
4042
4043         switch (data[0]) {
4044         case INSN_CONFIG_SET_CLOCK_SRC:
4045                 switch (data[1]) {
4046                 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4047                         devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_TIMEBASE_SEL;
4048                         break;
4049                 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4050                         devpriv->clock_and_fout |= NISTC_CLK_FOUT_TIMEBASE_SEL;
4051                         break;
4052                 default:
4053                         return -EINVAL;
4054                 }
4055                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4056                 break;
4057         case INSN_CONFIG_GET_CLOCK_SRC:
4058                 if (devpriv->clock_and_fout & NISTC_CLK_FOUT_TIMEBASE_SEL) {
4059                         data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4060                         data[2] = TIMEBASE_2_NS;
4061                 } else {
4062                         data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4063                         data[2] = TIMEBASE_1_NS * 2;
4064                 }
4065                 break;
4066         default:
4067                 return -EINVAL;
4068         }
4069         return insn->n;
4070 }
4071
4072 static int ni_8255_callback(struct comedi_device *dev,
4073                             int dir, int port, int data, unsigned long iobase)
4074 {
4075         if (dir) {
4076                 ni_writeb(dev, data, iobase + 2 * port);
4077                 return 0;
4078         }
4079
4080         return ni_readb(dev, iobase + 2 * port);
4081 }
4082
4083 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4084 {
4085         struct ni_private *devpriv = dev->private;
4086
4087         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4088         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4089         return 3;
4090 }
4091
4092 static int ni_m_series_pwm_config(struct comedi_device *dev,
4093                                   struct comedi_subdevice *s,
4094                                   struct comedi_insn *insn,
4095                                   unsigned int *data)
4096 {
4097         struct ni_private *devpriv = dev->private;
4098         unsigned int up_count, down_count;
4099
4100         switch (data[0]) {
4101         case INSN_CONFIG_PWM_OUTPUT:
4102                 switch (data[1]) {
4103                 case CMDF_ROUND_NEAREST:
4104                         up_count = DIV_ROUND_CLOSEST(data[2],
4105                                                      devpriv->clock_ns);
4106                         break;
4107                 case CMDF_ROUND_DOWN:
4108                         up_count = data[2] / devpriv->clock_ns;
4109                         break;
4110                 case CMDF_ROUND_UP:
4111                         up_count =
4112                             DIV_ROUND_UP(data[2], devpriv->clock_ns);
4113                         break;
4114                 default:
4115                         return -EINVAL;
4116                 }
4117                 switch (data[3]) {
4118                 case CMDF_ROUND_NEAREST:
4119                         down_count = DIV_ROUND_CLOSEST(data[4],
4120                                                        devpriv->clock_ns);
4121                         break;
4122                 case CMDF_ROUND_DOWN:
4123                         down_count = data[4] / devpriv->clock_ns;
4124                         break;
4125                 case CMDF_ROUND_UP:
4126                         down_count =
4127                             DIV_ROUND_UP(data[4], devpriv->clock_ns);
4128                         break;
4129                 default:
4130                         return -EINVAL;
4131                 }
4132                 if (up_count * devpriv->clock_ns != data[2] ||
4133                     down_count * devpriv->clock_ns != data[4]) {
4134                         data[2] = up_count * devpriv->clock_ns;
4135                         data[4] = down_count * devpriv->clock_ns;
4136                         return -EAGAIN;
4137                 }
4138                 ni_writel(dev, NI_M_CAL_PWM_HIGH_TIME(up_count) |
4139                                NI_M_CAL_PWM_LOW_TIME(down_count),
4140                           NI_M_CAL_PWM_REG);
4141                 devpriv->pwm_up_count = up_count;
4142                 devpriv->pwm_down_count = down_count;
4143                 return 5;
4144         case INSN_CONFIG_GET_PWM_OUTPUT:
4145                 return ni_get_pwm_config(dev, data);
4146         default:
4147                 return -EINVAL;
4148         }
4149         return 0;
4150 }
4151
4152 static int ni_6143_pwm_config(struct comedi_device *dev,
4153                               struct comedi_subdevice *s,
4154                               struct comedi_insn *insn,
4155                               unsigned int *data)
4156 {
4157         struct ni_private *devpriv = dev->private;
4158         unsigned int up_count, down_count;
4159
4160         switch (data[0]) {
4161         case INSN_CONFIG_PWM_OUTPUT:
4162                 switch (data[1]) {
4163                 case CMDF_ROUND_NEAREST:
4164                         up_count = DIV_ROUND_CLOSEST(data[2],
4165                                                      devpriv->clock_ns);
4166                         break;
4167                 case CMDF_ROUND_DOWN:
4168                         up_count = data[2] / devpriv->clock_ns;
4169                         break;
4170                 case CMDF_ROUND_UP:
4171                         up_count =
4172                             DIV_ROUND_UP(data[2], devpriv->clock_ns);
4173                         break;
4174                 default:
4175                         return -EINVAL;
4176                 }
4177                 switch (data[3]) {
4178                 case CMDF_ROUND_NEAREST:
4179                         down_count = DIV_ROUND_CLOSEST(data[4],
4180                                                        devpriv->clock_ns);
4181                         break;
4182                 case CMDF_ROUND_DOWN:
4183                         down_count = data[4] / devpriv->clock_ns;
4184                         break;
4185                 case CMDF_ROUND_UP:
4186                         down_count =
4187                             DIV_ROUND_UP(data[4], devpriv->clock_ns);
4188                         break;
4189                 default:
4190                         return -EINVAL;
4191                 }
4192                 if (up_count * devpriv->clock_ns != data[2] ||
4193                     down_count * devpriv->clock_ns != data[4]) {
4194                         data[2] = up_count * devpriv->clock_ns;
4195                         data[4] = down_count * devpriv->clock_ns;
4196                         return -EAGAIN;
4197                 }
4198                 ni_writel(dev, up_count, NI6143_CALIB_HI_TIME_REG);
4199                 devpriv->pwm_up_count = up_count;
4200                 ni_writel(dev, down_count, NI6143_CALIB_LO_TIME_REG);
4201                 devpriv->pwm_down_count = down_count;
4202                 return 5;
4203         case INSN_CONFIG_GET_PWM_OUTPUT:
4204                 return ni_get_pwm_config(dev, data);
4205         default:
4206                 return -EINVAL;
4207         }
4208         return 0;
4209 }
4210
4211 static int pack_mb88341(int addr, int val, int *bitstring)
4212 {
4213         /*
4214          * Fujitsu MB 88341
4215          * Note that address bits are reversed.  Thanks to
4216          * Ingo Keen for noticing this.
4217          *
4218          * Note also that the 88341 expects address values from
4219          * 1-12, whereas we use channel numbers 0-11.  The NI
4220          * docs use 1-12, also, so be careful here.
4221          */
4222         addr++;
4223         *bitstring = ((addr & 0x1) << 11) |
4224             ((addr & 0x2) << 9) |
4225             ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4226         return 12;
4227 }
4228
4229 static int pack_dac8800(int addr, int val, int *bitstring)
4230 {
4231         *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4232         return 11;
4233 }
4234
4235 static int pack_dac8043(int addr, int val, int *bitstring)
4236 {
4237         *bitstring = val & 0xfff;
4238         return 12;
4239 }
4240
4241 static int pack_ad8522(int addr, int val, int *bitstring)
4242 {
4243         *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4244         return 16;
4245 }
4246
4247 static int pack_ad8804(int addr, int val, int *bitstring)
4248 {
4249         *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4250         return 12;
4251 }
4252
4253 static int pack_ad8842(int addr, int val, int *bitstring)
4254 {
4255         *bitstring = ((addr + 1) << 8) | (val & 0xff);
4256         return 12;
4257 }
4258
4259 struct caldac_struct {
4260         int n_chans;
4261         int n_bits;
4262         int (*packbits)(int, int, int *);
4263 };
4264
4265 static struct caldac_struct caldacs[] = {
4266         [mb88341] = {12, 8, pack_mb88341},
4267         [dac8800] = {8, 8, pack_dac8800},
4268         [dac8043] = {1, 12, pack_dac8043},
4269         [ad8522] = {2, 12, pack_ad8522},
4270         [ad8804] = {12, 8, pack_ad8804},
4271         [ad8842] = {8, 8, pack_ad8842},
4272         [ad8804_debug] = {16, 8, pack_ad8804},
4273 };
4274
4275 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4276 {
4277         const struct ni_board_struct *board = dev->board_ptr;
4278         struct ni_private *devpriv = dev->private;
4279         unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4280         unsigned int cmd;
4281         int i;
4282         int type;
4283
4284         if (devpriv->caldacs[addr] == val)
4285                 return;
4286         devpriv->caldacs[addr] = val;
4287
4288         for (i = 0; i < 3; i++) {
4289                 type = board->caldac[i];
4290                 if (type == caldac_none)
4291                         break;
4292                 if (addr < caldacs[type].n_chans) {
4293                         bits = caldacs[type].packbits(addr, val, &bitstring);
4294                         loadbit = NI_E_SERIAL_CMD_DAC_LD(i);
4295                         break;
4296                 }
4297                 addr -= caldacs[type].n_chans;
4298         }
4299
4300         /* bits will be 0 if there is no caldac for the given addr */
4301         if (bits == 0)
4302                 return;
4303
4304         for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4305                 cmd = (bit & bitstring) ? NI_E_SERIAL_CMD_SDATA : 0;
4306                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4307                 udelay(1);
4308                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4309                 udelay(1);
4310         }
4311         ni_writeb(dev, loadbit, NI_E_SERIAL_CMD_REG);
4312         udelay(1);
4313         ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4314 }
4315
4316 static int ni_calib_insn_write(struct comedi_device *dev,
4317                                struct comedi_subdevice *s,
4318                                struct comedi_insn *insn,
4319                                unsigned int *data)
4320 {
4321         ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4322
4323         return 1;
4324 }
4325
4326 static int ni_calib_insn_read(struct comedi_device *dev,
4327                               struct comedi_subdevice *s,
4328                               struct comedi_insn *insn,
4329                               unsigned int *data)
4330 {
4331         struct ni_private *devpriv = dev->private;
4332
4333         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4334
4335         return 1;
4336 }
4337
4338 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4339 {
4340         const struct ni_board_struct *board = dev->board_ptr;
4341         struct ni_private *devpriv = dev->private;
4342         int i, j;
4343         int n_dacs;
4344         int n_chans = 0;
4345         int n_bits;
4346         int diffbits = 0;
4347         int type;
4348         int chan;
4349
4350         type = board->caldac[0];
4351         if (type == caldac_none)
4352                 return;
4353         n_bits = caldacs[type].n_bits;
4354         for (i = 0; i < 3; i++) {
4355                 type = board->caldac[i];
4356                 if (type == caldac_none)
4357                         break;
4358                 if (caldacs[type].n_bits != n_bits)
4359                         diffbits = 1;
4360                 n_chans += caldacs[type].n_chans;
4361         }
4362         n_dacs = i;
4363         s->n_chan = n_chans;
4364
4365         if (diffbits) {
4366                 unsigned int *maxdata_list = devpriv->caldac_maxdata_list;
4367
4368                 if (n_chans > MAX_N_CALDACS)
4369                         dev_err(dev->class_dev,
4370                                 "BUG! MAX_N_CALDACS too small\n");
4371                 s->maxdata_list = maxdata_list;
4372                 chan = 0;
4373                 for (i = 0; i < n_dacs; i++) {
4374                         type = board->caldac[i];
4375                         for (j = 0; j < caldacs[type].n_chans; j++) {
4376                                 maxdata_list[chan] =
4377                                     (1 << caldacs[type].n_bits) - 1;
4378                                 chan++;
4379                         }
4380                 }
4381
4382                 for (chan = 0; chan < s->n_chan; chan++)
4383                         ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4384         } else {
4385                 type = board->caldac[0];
4386                 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4387
4388                 for (chan = 0; chan < s->n_chan; chan++)
4389                         ni_write_caldac(dev, i, s->maxdata / 2);
4390         }
4391 }
4392
4393 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4394 {
4395         unsigned int cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4396         int bit;
4397         int bitstring;
4398
4399         bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4400         ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4401         for (bit = 0x8000; bit; bit >>= 1) {
4402                 if (bit & bitstring)
4403                         cmd |= NI_E_SERIAL_CMD_SDATA;
4404                 else
4405                         cmd &= ~NI_E_SERIAL_CMD_SDATA;
4406
4407                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4408                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4409         }
4410         cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4411         bitstring = 0;
4412         for (bit = 0x80; bit; bit >>= 1) {
4413                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4414                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4415                 if (ni_readb(dev, NI_E_STATUS_REG) & NI_E_STATUS_PROMOUT)
4416                         bitstring |= bit;
4417         }
4418         ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4419
4420         return bitstring;
4421 }
4422
4423 static int ni_eeprom_insn_read(struct comedi_device *dev,
4424                                struct comedi_subdevice *s,
4425                                struct comedi_insn *insn,
4426                                unsigned int *data)
4427 {
4428         data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4429
4430         return 1;
4431 }
4432
4433 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4434                                         struct comedi_subdevice *s,
4435                                         struct comedi_insn *insn,
4436                                         unsigned int *data)
4437 {
4438         struct ni_private *devpriv = dev->private;
4439
4440         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4441
4442         return 1;
4443 }
4444
4445 static unsigned int ni_old_get_pfi_routing(struct comedi_device *dev,
4446                                            unsigned int chan)
4447 {
4448         /*  pre-m-series boards have fixed signals on pfi pins */
4449         switch (chan) {
4450         case 0:
4451                 return NI_PFI_OUTPUT_AI_START1;
4452         case 1:
4453                 return NI_PFI_OUTPUT_AI_START2;
4454         case 2:
4455                 return NI_PFI_OUTPUT_AI_CONVERT;
4456         case 3:
4457                 return NI_PFI_OUTPUT_G_SRC1;
4458         case 4:
4459                 return NI_PFI_OUTPUT_G_GATE1;
4460         case 5:
4461                 return NI_PFI_OUTPUT_AO_UPDATE_N;
4462         case 6:
4463                 return NI_PFI_OUTPUT_AO_START1;
4464         case 7:
4465                 return NI_PFI_OUTPUT_AI_START_PULSE;
4466         case 8:
4467                 return NI_PFI_OUTPUT_G_SRC0;
4468         case 9:
4469                 return NI_PFI_OUTPUT_G_GATE0;
4470         default:
4471                 dev_err(dev->class_dev, "bug, unhandled case in switch.\n");
4472                 break;
4473         }
4474         return 0;
4475 }
4476
4477 static int ni_old_set_pfi_routing(struct comedi_device *dev,
4478                                   unsigned int chan, unsigned int source)
4479 {
4480         /*  pre-m-series boards have fixed signals on pfi pins */
4481         if (source != ni_old_get_pfi_routing(dev, chan))
4482                 return -EINVAL;
4483         return 2;
4484 }
4485
4486 static unsigned int ni_m_series_get_pfi_routing(struct comedi_device *dev,
4487                                                 unsigned int chan)
4488 {
4489         struct ni_private *devpriv = dev->private;
4490         const unsigned int array_offset = chan / 3;
4491
4492         return NI_M_PFI_OUT_SEL_TO_SRC(chan,
4493                                 devpriv->pfi_output_select_reg[array_offset]);
4494 }
4495
4496 static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4497                                        unsigned int chan, unsigned int source)
4498 {
4499         struct ni_private *devpriv = dev->private;
4500         unsigned int index = chan / 3;
4501         unsigned short val = devpriv->pfi_output_select_reg[index];
4502
4503         if ((source & 0x1f) != source)
4504                 return -EINVAL;
4505
4506         val &= ~NI_M_PFI_OUT_SEL_MASK(chan);
4507         val |= NI_M_PFI_OUT_SEL(chan, source);
4508         ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index));
4509         devpriv->pfi_output_select_reg[index] = val;
4510
4511         return 2;
4512 }
4513
4514 static unsigned int ni_get_pfi_routing(struct comedi_device *dev,
4515                                        unsigned int chan)
4516 {
4517         struct ni_private *devpriv = dev->private;
4518
4519         return (devpriv->is_m_series)
4520                         ? ni_m_series_get_pfi_routing(dev, chan)
4521                         : ni_old_get_pfi_routing(dev, chan);
4522 }
4523
4524 static int ni_set_pfi_routing(struct comedi_device *dev,
4525                               unsigned int chan, unsigned int source)
4526 {
4527         struct ni_private *devpriv = dev->private;
4528
4529         return (devpriv->is_m_series)
4530                         ? ni_m_series_set_pfi_routing(dev, chan, source)
4531                         : ni_old_set_pfi_routing(dev, chan, source);
4532 }
4533
4534 static int ni_config_filter(struct comedi_device *dev,
4535                             unsigned int pfi_channel,
4536                             enum ni_pfi_filter_select filter)
4537 {
4538         struct ni_private *devpriv = dev->private;
4539         unsigned int bits;
4540
4541         if (!devpriv->is_m_series)
4542                 return -ENOTSUPP;
4543
4544         bits = ni_readl(dev, NI_M_PFI_FILTER_REG);
4545         bits &= ~NI_M_PFI_FILTER_SEL_MASK(pfi_channel);
4546         bits |= NI_M_PFI_FILTER_SEL(pfi_channel, filter);
4547         ni_writel(dev, bits, NI_M_PFI_FILTER_REG);
4548         return 0;
4549 }
4550
4551 static int ni_pfi_insn_config(struct comedi_device *dev,
4552                               struct comedi_subdevice *s,
4553                               struct comedi_insn *insn,
4554                               unsigned int *data)
4555 {
4556         struct ni_private *devpriv = dev->private;
4557         unsigned int chan;
4558
4559         if (insn->n < 1)
4560                 return -EINVAL;
4561
4562         chan = CR_CHAN(insn->chanspec);
4563
4564         switch (data[0]) {
4565         case COMEDI_OUTPUT:
4566                 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 1);
4567                 break;
4568         case COMEDI_INPUT:
4569                 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 0);
4570                 break;
4571         case INSN_CONFIG_DIO_QUERY:
4572                 data[1] =
4573                     (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
4574                     COMEDI_OUTPUT : COMEDI_INPUT;
4575                 return 0;
4576         case INSN_CONFIG_SET_ROUTING:
4577                 return ni_set_pfi_routing(dev, chan, data[1]);
4578         case INSN_CONFIG_GET_ROUTING:
4579                 data[1] = ni_get_pfi_routing(dev, chan);
4580                 break;
4581         case INSN_CONFIG_FILTER:
4582                 return ni_config_filter(dev, chan, data[1]);
4583         default:
4584                 return -EINVAL;
4585         }
4586         return 0;
4587 }
4588
4589 static int ni_pfi_insn_bits(struct comedi_device *dev,
4590                             struct comedi_subdevice *s,
4591                             struct comedi_insn *insn,
4592                             unsigned int *data)
4593 {
4594         struct ni_private *devpriv = dev->private;
4595
4596         if (!devpriv->is_m_series)
4597                 return -ENOTSUPP;
4598
4599         if (comedi_dio_update_state(s, data))
4600                 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
4601
4602         data[1] = ni_readw(dev, NI_M_PFI_DI_REG);
4603
4604         return insn->n;
4605 }
4606
4607 static int cs5529_wait_for_idle(struct comedi_device *dev)
4608 {
4609         unsigned short status;
4610         const int timeout = HZ;
4611         int i;
4612
4613         for (i = 0; i < timeout; i++) {
4614                 status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4615                 if ((status & NI67XX_CAL_STATUS_BUSY) == 0)
4616                         break;
4617                 set_current_state(TASK_INTERRUPTIBLE);
4618                 if (schedule_timeout(1))
4619                         return -EIO;
4620         }
4621         if (i == timeout) {
4622                 dev_err(dev->class_dev, "timeout\n");
4623                 return -ETIME;
4624         }
4625         return 0;
4626 }
4627
4628 static void cs5529_command(struct comedi_device *dev, unsigned short value)
4629 {
4630         static const int timeout = 100;
4631         int i;
4632
4633         ni_ao_win_outw(dev, value, NI67XX_CAL_CMD_REG);
4634         /* give time for command to start being serially clocked into cs5529.
4635          * this insures that the NI67XX_CAL_STATUS_BUSY bit will get properly
4636          * set before we exit this function.
4637          */
4638         for (i = 0; i < timeout; i++) {
4639                 if (ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG) &
4640                     NI67XX_CAL_STATUS_BUSY)
4641                         break;
4642                 udelay(1);
4643         }
4644         if (i == timeout)
4645                 dev_err(dev->class_dev,
4646                         "possible problem - never saw adc go busy?\n");
4647 }
4648
4649 static int cs5529_do_conversion(struct comedi_device *dev,
4650                                 unsigned short *data)
4651 {
4652         int retval;
4653         unsigned short status;
4654
4655         cs5529_command(dev, CS5529_CMD_CB | CS5529_CMD_SINGLE_CONV);
4656         retval = cs5529_wait_for_idle(dev);
4657         if (retval) {
4658                 dev_err(dev->class_dev,
4659                         "timeout or signal in cs5529_do_conversion()\n");
4660                 return -ETIME;
4661         }
4662         status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4663         if (status & NI67XX_CAL_STATUS_OSC_DETECT) {
4664                 dev_err(dev->class_dev,
4665                         "cs5529 conversion error, status CSS_OSC_DETECT\n");
4666                 return -EIO;
4667         }
4668         if (status & NI67XX_CAL_STATUS_OVERRANGE) {
4669                 dev_err(dev->class_dev,
4670                         "cs5529 conversion error, overrange (ignoring)\n");
4671         }
4672         if (data) {
4673                 *data = ni_ao_win_inw(dev, NI67XX_CAL_DATA_REG);
4674                 /* cs5529 returns 16 bit signed data in bipolar mode */
4675                 *data ^= (1 << 15);
4676         }
4677         return 0;
4678 }
4679
4680 static int cs5529_ai_insn_read(struct comedi_device *dev,
4681                                struct comedi_subdevice *s,
4682                                struct comedi_insn *insn,
4683                                unsigned int *data)
4684 {
4685         int n, retval;
4686         unsigned short sample;
4687         unsigned int channel_select;
4688         const unsigned int INTERNAL_REF = 0x1000;
4689
4690         /*
4691          * Set calibration adc source.  Docs lie, reference select bits 8 to 11
4692          * do nothing. bit 12 seems to chooses internal reference voltage, bit
4693          * 13 causes the adc input to go overrange (maybe reads external
4694          * reference?)
4695          */
4696         if (insn->chanspec & CR_ALT_SOURCE)
4697                 channel_select = INTERNAL_REF;
4698         else
4699                 channel_select = CR_CHAN(insn->chanspec);
4700         ni_ao_win_outw(dev, channel_select, NI67XX_AO_CAL_CHAN_SEL_REG);
4701
4702         for (n = 0; n < insn->n; n++) {
4703                 retval = cs5529_do_conversion(dev, &sample);
4704                 if (retval < 0)
4705                         return retval;
4706                 data[n] = sample;
4707         }
4708         return insn->n;
4709 }
4710
4711 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
4712                                 unsigned int reg_select_bits)
4713 {
4714         ni_ao_win_outw(dev, (value >> 16) & 0xff, NI67XX_CAL_CFG_HI_REG);
4715         ni_ao_win_outw(dev, value & 0xffff, NI67XX_CAL_CFG_LO_REG);
4716         reg_select_bits &= CS5529_CMD_REG_MASK;
4717         cs5529_command(dev, CS5529_CMD_CB | reg_select_bits);
4718         if (cs5529_wait_for_idle(dev))
4719                 dev_err(dev->class_dev,
4720                         "timeout or signal in %s\n", __func__);
4721 }
4722
4723 static int init_cs5529(struct comedi_device *dev)
4724 {
4725         unsigned int config_bits = CS5529_CFG_PORT_FLAG |
4726                                    CS5529_CFG_WORD_RATE_2180;
4727
4728 #if 1
4729         /* do self-calibration */
4730         cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_BOTH_SELF,
4731                             CS5529_CFG_REG);
4732         /* need to force a conversion for calibration to run */
4733         cs5529_do_conversion(dev, NULL);
4734 #else
4735         /* force gain calibration to 1 */
4736         cs5529_config_write(dev, 0x400000, CS5529_GAIN_REG);
4737         cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_OFFSET_SELF,
4738                             CS5529_CFG_REG);
4739         if (cs5529_wait_for_idle(dev))
4740                 dev_err(dev->class_dev,
4741                         "timeout or signal in %s\n", __func__);
4742 #endif
4743         return 0;
4744 }
4745
4746 /*
4747  * Find best multiplier/divider to try and get the PLL running at 80 MHz
4748  * given an arbitrary frequency input clock.
4749  */
4750 static int ni_mseries_get_pll_parameters(unsigned int reference_period_ns,
4751                                          unsigned int *freq_divider,
4752                                          unsigned int *freq_multiplier,
4753                                          unsigned int *actual_period_ns)
4754 {
4755         unsigned int div;
4756         unsigned int best_div = 1;
4757         unsigned int mult;
4758         unsigned int best_mult = 1;
4759         static const unsigned int pico_per_nano = 1000;
4760         const unsigned int reference_picosec = reference_period_ns *
4761                                                pico_per_nano;
4762         /*
4763          * m-series wants the phased-locked loop to output 80MHz, which is
4764          * divided by 4 to 20 MHz for most timing clocks
4765          */
4766         static const unsigned int target_picosec = 12500;
4767         int best_period_picosec = 0;
4768
4769         for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) {
4770                 for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) {
4771                         unsigned int new_period_ps =
4772                             (reference_picosec * div) / mult;
4773                         if (abs(new_period_ps - target_picosec) <
4774                             abs(best_period_picosec - target_picosec)) {
4775                                 best_period_picosec = new_period_ps;
4776                                 best_div = div;
4777                                 best_mult = mult;
4778                         }
4779                 }
4780         }
4781         if (best_period_picosec == 0)
4782                 return -EIO;
4783
4784         *freq_divider = best_div;
4785         *freq_multiplier = best_mult;
4786         /* return the actual period (* fudge factor for 80 to 20 MHz) */
4787         *actual_period_ns = DIV_ROUND_CLOSEST(best_period_picosec * 4,
4788                                               pico_per_nano);
4789         return 0;
4790 }
4791
4792 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4793                                            unsigned int source,
4794                                            unsigned int period_ns)
4795 {
4796         struct ni_private *devpriv = dev->private;
4797         static const unsigned int min_period_ns = 50;
4798         static const unsigned int max_period_ns = 1000;
4799         static const unsigned int timeout = 1000;
4800         unsigned int pll_control_bits;
4801         unsigned int freq_divider;
4802         unsigned int freq_multiplier;
4803         unsigned int rtsi;
4804         unsigned int i;
4805         int retval;
4806
4807         if (source == NI_MIO_PLL_PXI10_CLOCK)
4808                 period_ns = 100;
4809         /*
4810          * These limits are somewhat arbitrary, but NI advertises 1 to 20MHz
4811          * range so we'll use that.
4812          */
4813         if (period_ns < min_period_ns || period_ns > max_period_ns) {
4814                 dev_err(dev->class_dev,
4815                         "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n",
4816                         __func__, min_period_ns, max_period_ns);
4817                 return -EINVAL;
4818         }
4819         devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4820         ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4821                       NISTC_RTSI_TRIG_DIR_REG);
4822         pll_control_bits = NI_M_PLL_CTRL_ENA | NI_M_PLL_CTRL_VCO_MODE_75_150MHZ;
4823         devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4824                                     NI_M_CLK_FOUT2_TIMEBASE3_PLL;
4825         devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK;
4826         switch (source) {
4827         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4828                 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR;
4829                 break;
4830         case NI_MIO_PLL_PXI10_CLOCK:
4831                 /* pxi clock is 10MHz */
4832                 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10;
4833                 break;
4834         default:
4835                 for (rtsi = 0; rtsi <= NI_M_MAX_RTSI_CHAN; ++rtsi) {
4836                         if (source == NI_MIO_PLL_RTSI_CLOCK(rtsi)) {
4837                                 devpriv->clock_and_fout2 |=
4838                                         NI_M_CLK_FOUT2_PLL_SRC_RTSI(rtsi);
4839                                 break;
4840                         }
4841                 }
4842                 if (rtsi > NI_M_MAX_RTSI_CHAN)
4843                         return -EINVAL;
4844                 break;
4845         }
4846         retval = ni_mseries_get_pll_parameters(period_ns,
4847                                                &freq_divider,
4848                                                &freq_multiplier,
4849                                                &devpriv->clock_ns);
4850         if (retval < 0) {
4851                 dev_err(dev->class_dev,
4852                         "bug, failed to find pll parameters\n");
4853                 return retval;
4854         }
4855
4856         ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG);
4857         pll_control_bits |= NI_M_PLL_CTRL_DIVISOR(freq_divider) |
4858                             NI_M_PLL_CTRL_MULTIPLIER(freq_multiplier);
4859
4860         ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG);
4861         devpriv->clock_source = source;
4862         /* it takes a few hundred microseconds for PLL to lock */
4863         for (i = 0; i < timeout; ++i) {
4864                 if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED)
4865                         break;
4866                 udelay(1);
4867         }
4868         if (i == timeout) {
4869                 dev_err(dev->class_dev,
4870                         "%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n",
4871                         __func__, source, period_ns);
4872                 return -ETIMEDOUT;
4873         }
4874         return 3;
4875 }
4876
4877 static int ni_set_master_clock(struct comedi_device *dev,
4878                                unsigned int source, unsigned int period_ns)
4879 {
4880         struct ni_private *devpriv = dev->private;
4881
4882         if (source == NI_MIO_INTERNAL_CLOCK) {
4883                 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4884                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4885                               NISTC_RTSI_TRIG_DIR_REG);
4886                 devpriv->clock_ns = TIMEBASE_1_NS;
4887                 if (devpriv->is_m_series) {
4888                         devpriv->clock_and_fout2 &=
4889                             ~(NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4890                               NI_M_CLK_FOUT2_TIMEBASE3_PLL);
4891                         ni_writew(dev, devpriv->clock_and_fout2,
4892                                   NI_M_CLK_FOUT2_REG);
4893                         ni_writew(dev, 0, NI_M_PLL_CTRL_REG);
4894                 }
4895                 devpriv->clock_source = source;
4896         } else {
4897                 if (devpriv->is_m_series) {
4898                         return ni_mseries_set_pll_master_clock(dev, source,
4899                                                                period_ns);
4900                 } else {
4901                         if (source == NI_MIO_RTSI_CLOCK) {
4902                                 devpriv->rtsi_trig_direction_reg |=
4903                                     NISTC_RTSI_TRIG_USE_CLK;
4904                                 ni_stc_writew(dev,
4905                                               devpriv->rtsi_trig_direction_reg,
4906                                               NISTC_RTSI_TRIG_DIR_REG);
4907                                 if (period_ns == 0) {
4908                                         dev_err(dev->class_dev,
4909                                                 "we don't handle an unspecified clock period correctly yet, returning error\n");
4910                                         return -EINVAL;
4911                                 }
4912                                 devpriv->clock_ns = period_ns;
4913                                 devpriv->clock_source = source;
4914                         } else {
4915                                 return -EINVAL;
4916                         }
4917                 }
4918         }
4919         return 3;
4920 }
4921
4922 static int ni_valid_rtsi_output_source(struct comedi_device *dev,
4923                                        unsigned int chan, unsigned int source)
4924 {
4925         struct ni_private *devpriv = dev->private;
4926
4927         if (chan >= NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
4928                 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4929                         if (source == NI_RTSI_OUTPUT_RTSI_OSC)
4930                                 return 1;
4931
4932                         dev_err(dev->class_dev,
4933                                 "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n",
4934                                 __func__, chan, NISTC_RTSI_TRIG_OLD_CLK_CHAN);
4935                         return 0;
4936                 }
4937                 return 0;
4938         }
4939         switch (source) {
4940         case NI_RTSI_OUTPUT_ADR_START1:
4941         case NI_RTSI_OUTPUT_ADR_START2:
4942         case NI_RTSI_OUTPUT_SCLKG:
4943         case NI_RTSI_OUTPUT_DACUPDN:
4944         case NI_RTSI_OUTPUT_DA_START1:
4945         case NI_RTSI_OUTPUT_G_SRC0:
4946         case NI_RTSI_OUTPUT_G_GATE0:
4947         case NI_RTSI_OUTPUT_RGOUT0:
4948         case NI_RTSI_OUTPUT_RTSI_BRD(0):
4949         case NI_RTSI_OUTPUT_RTSI_BRD(1):
4950         case NI_RTSI_OUTPUT_RTSI_BRD(2):
4951         case NI_RTSI_OUTPUT_RTSI_BRD(3):
4952                 return 1;
4953         case NI_RTSI_OUTPUT_RTSI_OSC:
4954                 return (devpriv->is_m_series) ? 1 : 0;
4955         default:
4956                 return 0;
4957         }
4958 }
4959
4960 static int ni_set_rtsi_routing(struct comedi_device *dev,
4961                                unsigned int chan, unsigned int src)
4962 {
4963         struct ni_private *devpriv = dev->private;
4964
4965         if (ni_valid_rtsi_output_source(dev, chan, src) == 0)
4966                 return -EINVAL;
4967         if (chan < 4) {
4968                 devpriv->rtsi_trig_a_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
4969                 devpriv->rtsi_trig_a_output_reg |= NISTC_RTSI_TRIG(chan, src);
4970                 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4971                               NISTC_RTSI_TRIGA_OUT_REG);
4972         } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
4973                 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
4974                 devpriv->rtsi_trig_b_output_reg |= NISTC_RTSI_TRIG(chan, src);
4975                 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4976                               NISTC_RTSI_TRIGB_OUT_REG);
4977         } else if (chan != NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4978                 /* probably should never reach this, since the
4979                  * ni_valid_rtsi_output_source above errors out if chan is too
4980                  * high
4981                  */
4982                 dev_err(dev->class_dev, "%s: unknown rtsi channel\n", __func__);
4983                 return -EINVAL;
4984         }
4985         return 2;
4986 }
4987
4988 static unsigned int ni_get_rtsi_routing(struct comedi_device *dev,
4989                                         unsigned int chan)
4990 {
4991         struct ni_private *devpriv = dev->private;
4992
4993         if (chan < 4) {
4994                 return NISTC_RTSI_TRIG_TO_SRC(chan,
4995                                               devpriv->rtsi_trig_a_output_reg);
4996         } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
4997                 return NISTC_RTSI_TRIG_TO_SRC(chan,
4998                                               devpriv->rtsi_trig_b_output_reg);
4999         } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5000                 return NI_RTSI_OUTPUT_RTSI_OSC;
5001         }
5002
5003         dev_err(dev->class_dev, "%s: unknown rtsi channel\n", __func__);
5004         return -EINVAL;
5005 }
5006
5007 static int ni_rtsi_insn_config(struct comedi_device *dev,
5008                                struct comedi_subdevice *s,
5009                                struct comedi_insn *insn,
5010                                unsigned int *data)
5011 {
5012         struct ni_private *devpriv = dev->private;
5013         unsigned int chan = CR_CHAN(insn->chanspec);
5014         unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series);
5015
5016         switch (data[0]) {
5017         case INSN_CONFIG_DIO_OUTPUT:
5018                 if (chan < max_chan) {
5019                         devpriv->rtsi_trig_direction_reg |=
5020                             NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
5021                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5022                         devpriv->rtsi_trig_direction_reg |=
5023                             NISTC_RTSI_TRIG_DRV_CLK;
5024                 }
5025                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5026                               NISTC_RTSI_TRIG_DIR_REG);
5027                 break;
5028         case INSN_CONFIG_DIO_INPUT:
5029                 if (chan < max_chan) {
5030                         devpriv->rtsi_trig_direction_reg &=
5031                             ~NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
5032                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5033                         devpriv->rtsi_trig_direction_reg &=
5034                             ~NISTC_RTSI_TRIG_DRV_CLK;
5035                 }
5036                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5037                               NISTC_RTSI_TRIG_DIR_REG);
5038                 break;
5039         case INSN_CONFIG_DIO_QUERY:
5040                 if (chan < max_chan) {
5041                         data[1] =
5042                             (devpriv->rtsi_trig_direction_reg &
5043                              NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series))
5044                                 ? INSN_CONFIG_DIO_OUTPUT
5045                                 : INSN_CONFIG_DIO_INPUT;
5046                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5047                         data[1] = (devpriv->rtsi_trig_direction_reg &
5048                                    NISTC_RTSI_TRIG_DRV_CLK)
5049                                   ? INSN_CONFIG_DIO_OUTPUT
5050                                   : INSN_CONFIG_DIO_INPUT;
5051                 }
5052                 return 2;
5053         case INSN_CONFIG_SET_CLOCK_SRC:
5054                 return ni_set_master_clock(dev, data[1], data[2]);
5055         case INSN_CONFIG_GET_CLOCK_SRC:
5056                 data[1] = devpriv->clock_source;
5057                 data[2] = devpriv->clock_ns;
5058                 return 3;
5059         case INSN_CONFIG_SET_ROUTING:
5060                 return ni_set_rtsi_routing(dev, chan, data[1]);
5061         case INSN_CONFIG_GET_ROUTING:
5062                 data[1] = ni_get_rtsi_routing(dev, chan);
5063                 return 2;
5064         default:
5065                 return -EINVAL;
5066         }
5067         return 1;
5068 }
5069
5070 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5071                              struct comedi_subdevice *s,
5072                              struct comedi_insn *insn,
5073                              unsigned int *data)
5074 {
5075         data[1] = 0;
5076
5077         return insn->n;
5078 }
5079
5080 static void ni_rtsi_init(struct comedi_device *dev)
5081 {
5082         struct ni_private *devpriv = dev->private;
5083
5084         /*  Initialises the RTSI bus signal switch to a default state */
5085
5086         /*
5087          * Use 10MHz instead of 20MHz for RTSI clock frequency. Appears
5088          * to have no effect, at least on pxi-6281, which always uses
5089          * 20MHz rtsi clock frequency
5090          */
5091         devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ;
5092         /*  Set clock mode to internal */
5093         if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
5094                 dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n");
5095         /*  default internal lines routing to RTSI bus lines */
5096         devpriv->rtsi_trig_a_output_reg =
5097             NISTC_RTSI_TRIG(0, NI_RTSI_OUTPUT_ADR_START1) |
5098             NISTC_RTSI_TRIG(1, NI_RTSI_OUTPUT_ADR_START2) |
5099             NISTC_RTSI_TRIG(2, NI_RTSI_OUTPUT_SCLKG) |
5100             NISTC_RTSI_TRIG(3, NI_RTSI_OUTPUT_DACUPDN);
5101         ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5102                       NISTC_RTSI_TRIGA_OUT_REG);
5103         devpriv->rtsi_trig_b_output_reg =
5104             NISTC_RTSI_TRIG(4, NI_RTSI_OUTPUT_DA_START1) |
5105             NISTC_RTSI_TRIG(5, NI_RTSI_OUTPUT_G_SRC0) |
5106             NISTC_RTSI_TRIG(6, NI_RTSI_OUTPUT_G_GATE0);
5107         if (devpriv->is_m_series)
5108                 devpriv->rtsi_trig_b_output_reg |=
5109                     NISTC_RTSI_TRIG(7, NI_RTSI_OUTPUT_RTSI_OSC);
5110         ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5111                       NISTC_RTSI_TRIGB_OUT_REG);
5112
5113         /*
5114          * Sets the source and direction of the 4 on board lines
5115          * ni_stc_writew(dev, 0, NISTC_RTSI_BOARD_REG);
5116          */
5117 }
5118
5119 #ifdef PCIDMA
5120 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5121 {
5122         struct ni_gpct *counter = s->private;
5123         int retval;
5124
5125         retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5126                                               COMEDI_INPUT);
5127         if (retval) {
5128                 dev_err(dev->class_dev,
5129                         "no dma channel available for use by counter\n");
5130                 return retval;
5131         }
5132         ni_tio_acknowledge(counter);
5133         ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5134
5135         return ni_tio_cmd(dev, s);
5136 }
5137
5138 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5139 {
5140         struct ni_gpct *counter = s->private;
5141         int retval;
5142
5143         retval = ni_tio_cancel(counter);
5144         ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5145         ni_release_gpct_mite_channel(dev, counter->counter_index);
5146         return retval;
5147 }
5148 #endif
5149
5150 static irqreturn_t ni_E_interrupt(int irq, void *d)
5151 {
5152         struct comedi_device *dev = d;
5153         struct comedi_subdevice *s_ai = dev->read_subdev;
5154         struct comedi_subdevice *s_ao = dev->write_subdev;
5155         unsigned short a_status;
5156         unsigned short b_status;
5157         unsigned long flags;
5158 #ifdef PCIDMA
5159         struct ni_private *devpriv = dev->private;
5160 #endif
5161
5162         if (!dev->attached)
5163                 return IRQ_NONE;
5164         smp_mb();               /* make sure dev->attached is checked */
5165
5166         /*  lock to avoid race with comedi_poll */
5167         spin_lock_irqsave(&dev->spinlock, flags);
5168         a_status = ni_stc_readw(dev, NISTC_AI_STATUS1_REG);
5169         b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
5170 #ifdef PCIDMA
5171         if (devpriv->mite) {
5172                 unsigned long flags_too;
5173
5174                 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
5175                 if (s_ai && devpriv->ai_mite_chan)
5176                         mite_ack_linkc(devpriv->ai_mite_chan, s_ai, false);
5177                 if (s_ao && devpriv->ao_mite_chan)
5178                         mite_ack_linkc(devpriv->ao_mite_chan, s_ao, false);
5179                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
5180         }
5181 #endif
5182         ack_a_interrupt(dev, a_status);
5183         ack_b_interrupt(dev, b_status);
5184         if (s_ai) {
5185                 if (a_status & NISTC_AI_STATUS1_INTA)
5186                         handle_a_interrupt(dev, s_ai, a_status);
5187                 /* handle any interrupt or dma events */
5188                 comedi_handle_events(dev, s_ai);
5189         }
5190         if (s_ao) {
5191                 if (b_status & NISTC_AO_STATUS1_INTB)
5192                         handle_b_interrupt(dev, s_ao, b_status);
5193                 /* handle any interrupt or dma events */
5194                 comedi_handle_events(dev, s_ao);
5195         }
5196         handle_gpct_interrupt(dev, 0);
5197         handle_gpct_interrupt(dev, 1);
5198 #ifdef PCIDMA
5199         if (devpriv->is_m_series)
5200                 handle_cdio_interrupt(dev);
5201 #endif
5202
5203         spin_unlock_irqrestore(&dev->spinlock, flags);
5204         return IRQ_HANDLED;
5205 }
5206
5207 static int ni_alloc_private(struct comedi_device *dev)
5208 {
5209         struct ni_private *devpriv;
5210
5211         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
5212         if (!devpriv)
5213                 return -ENOMEM;
5214
5215         spin_lock_init(&devpriv->window_lock);
5216         spin_lock_init(&devpriv->soft_reg_copy_lock);
5217         spin_lock_init(&devpriv->mite_channel_lock);
5218
5219         return 0;
5220 }
5221
5222 static int ni_E_init(struct comedi_device *dev,
5223                      unsigned int interrupt_pin, unsigned int irq_polarity)
5224 {
5225         const struct ni_board_struct *board = dev->board_ptr;
5226         struct ni_private *devpriv = dev->private;
5227         struct comedi_subdevice *s;
5228         int ret;
5229         int i;
5230
5231         if (board->n_aochan > MAX_N_AO_CHAN) {
5232                 dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n");
5233                 return -EINVAL;
5234         }
5235
5236         /* initialize clock dividers */
5237         devpriv->clock_and_fout = NISTC_CLK_FOUT_SLOW_DIV2 |
5238                                   NISTC_CLK_FOUT_SLOW_TIMEBASE |
5239                                   NISTC_CLK_FOUT_TO_BOARD_DIV2 |
5240                                   NISTC_CLK_FOUT_TO_BOARD;
5241         if (!devpriv->is_6xxx) {
5242                 /* BEAM is this needed for PCI-6143 ?? */
5243                 devpriv->clock_and_fout |= (NISTC_CLK_FOUT_AI_OUT_DIV2 |
5244                                             NISTC_CLK_FOUT_AO_OUT_DIV2);
5245         }
5246         ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
5247
5248         ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
5249         if (ret)
5250                 return ret;
5251
5252         /* Analog Input subdevice */
5253         s = &dev->subdevices[NI_AI_SUBDEV];
5254         if (board->n_adchan) {
5255                 s->type         = COMEDI_SUBD_AI;
5256                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER;
5257                 if (!devpriv->is_611x)
5258                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
5259                 if (board->ai_maxdata > 0xffff)
5260                         s->subdev_flags |= SDF_LSAMPL;
5261                 if (devpriv->is_m_series)
5262                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
5263                 s->n_chan       = board->n_adchan;
5264                 s->maxdata      = board->ai_maxdata;
5265                 s->range_table  = ni_range_lkup[board->gainlkup];
5266                 s->insn_read    = ni_ai_insn_read;
5267                 s->insn_config  = ni_ai_insn_config;
5268                 if (dev->irq) {
5269                         dev->read_subdev = s;
5270                         s->subdev_flags |= SDF_CMD_READ;
5271                         s->len_chanlist = 512;
5272                         s->do_cmdtest   = ni_ai_cmdtest;
5273                         s->do_cmd       = ni_ai_cmd;
5274                         s->cancel       = ni_ai_reset;
5275                         s->poll         = ni_ai_poll;
5276                         s->munge        = ni_ai_munge;
5277
5278                         if (devpriv->mite)
5279                                 s->async_dma_dir = DMA_FROM_DEVICE;
5280                 }
5281
5282                 /* reset the analog input configuration */
5283                 ni_ai_reset(dev, s);
5284         } else {
5285                 s->type         = COMEDI_SUBD_UNUSED;
5286         }
5287
5288         /* Analog Output subdevice */
5289         s = &dev->subdevices[NI_AO_SUBDEV];
5290         if (board->n_aochan) {
5291                 s->type         = COMEDI_SUBD_AO;
5292                 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
5293                 if (devpriv->is_m_series)
5294                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
5295                 s->n_chan       = board->n_aochan;
5296                 s->maxdata      = board->ao_maxdata;
5297                 s->range_table  = board->ao_range_table;
5298                 s->insn_config  = ni_ao_insn_config;
5299                 s->insn_write   = ni_ao_insn_write;
5300
5301                 ret = comedi_alloc_subdev_readback(s);
5302                 if (ret)
5303                         return ret;
5304
5305                 /*
5306                  * Along with the IRQ we need either a FIFO or DMA for
5307                  * async command support.
5308                  */
5309                 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) {
5310                         dev->write_subdev = s;
5311                         s->subdev_flags |= SDF_CMD_WRITE;
5312                         s->len_chanlist = s->n_chan;
5313                         s->do_cmdtest   = ni_ao_cmdtest;
5314                         s->do_cmd       = ni_ao_cmd;
5315                         s->cancel       = ni_ao_reset;
5316                         if (!devpriv->is_m_series)
5317                                 s->munge        = ni_ao_munge;
5318
5319                         if (devpriv->mite)
5320                                 s->async_dma_dir = DMA_TO_DEVICE;
5321                 }
5322
5323                 if (devpriv->is_67xx)
5324                         init_ao_67xx(dev, s);
5325
5326                 /* reset the analog output configuration */
5327                 ni_ao_reset(dev, s);
5328         } else {
5329                 s->type         = COMEDI_SUBD_UNUSED;
5330         }
5331
5332         /* Digital I/O subdevice */
5333         s = &dev->subdevices[NI_DIO_SUBDEV];
5334         s->type         = COMEDI_SUBD_DIO;
5335         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
5336         s->n_chan       = board->has_32dio_chan ? 32 : 8;
5337         s->maxdata      = 1;
5338         s->range_table  = &range_digital;
5339         if (devpriv->is_m_series) {
5340 #ifdef PCIDMA
5341                 s->subdev_flags |= SDF_LSAMPL;
5342                 s->insn_bits    = ni_m_series_dio_insn_bits;
5343                 s->insn_config  = ni_m_series_dio_insn_config;
5344                 if (dev->irq) {
5345                         s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */;
5346                         s->len_chanlist = s->n_chan;
5347                         s->do_cmdtest   = ni_cdio_cmdtest;
5348                         s->do_cmd       = ni_cdio_cmd;
5349                         s->cancel       = ni_cdio_cancel;
5350
5351                         /* M-series boards use DMA */
5352                         s->async_dma_dir = DMA_BIDIRECTIONAL;
5353                 }
5354
5355                 /* reset DIO and set all channels to inputs */
5356                 ni_writel(dev, NI_M_CDO_CMD_RESET |
5357                                NI_M_CDI_CMD_RESET,
5358                           NI_M_CDIO_CMD_REG);
5359                 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
5360 #endif /* PCIDMA */
5361         } else {
5362                 s->insn_bits    = ni_dio_insn_bits;
5363                 s->insn_config  = ni_dio_insn_config;
5364
5365                 /* set all channels to inputs */
5366                 devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits);
5367                 ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
5368         }
5369
5370         /* 8255 device */
5371         s = &dev->subdevices[NI_8255_DIO_SUBDEV];
5372         if (board->has_8255) {
5373                 ret = subdev_8255_init(dev, s, ni_8255_callback,
5374                                        NI_E_8255_BASE);
5375                 if (ret)
5376                         return ret;
5377         } else {
5378                 s->type = COMEDI_SUBD_UNUSED;
5379         }
5380
5381         /* formerly general purpose counter/timer device, but no longer used */
5382         s = &dev->subdevices[NI_UNUSED_SUBDEV];
5383         s->type = COMEDI_SUBD_UNUSED;
5384
5385         /* Calibration subdevice */
5386         s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
5387         s->type         = COMEDI_SUBD_CALIB;
5388         s->subdev_flags = SDF_INTERNAL;
5389         s->n_chan       = 1;
5390         s->maxdata      = 0;
5391         if (devpriv->is_m_series) {
5392                 /* internal PWM output used for AI nonlinearity calibration */
5393                 s->insn_config  = ni_m_series_pwm_config;
5394
5395                 ni_writel(dev, 0x0, NI_M_CAL_PWM_REG);
5396         } else if (devpriv->is_6143) {
5397                 /* internal PWM output used for AI nonlinearity calibration */
5398                 s->insn_config  = ni_6143_pwm_config;
5399         } else {
5400                 s->subdev_flags |= SDF_WRITABLE;
5401                 s->insn_read    = ni_calib_insn_read;
5402                 s->insn_write   = ni_calib_insn_write;
5403
5404                 /* setup the caldacs and find the real n_chan and maxdata */
5405                 caldac_setup(dev, s);
5406         }
5407
5408         /* EEPROM subdevice */
5409         s = &dev->subdevices[NI_EEPROM_SUBDEV];
5410         s->type         = COMEDI_SUBD_MEMORY;
5411         s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
5412         s->maxdata      = 0xff;
5413         if (devpriv->is_m_series) {
5414                 s->n_chan       = M_SERIES_EEPROM_SIZE;
5415                 s->insn_read    = ni_m_series_eeprom_insn_read;
5416         } else {
5417                 s->n_chan       = 512;
5418                 s->insn_read    = ni_eeprom_insn_read;
5419         }
5420
5421         /* Digital I/O (PFI) subdevice */
5422         s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
5423         s->type         = COMEDI_SUBD_DIO;
5424         s->maxdata      = 1;
5425         if (devpriv->is_m_series) {
5426                 s->n_chan       = 16;
5427                 s->insn_bits    = ni_pfi_insn_bits;
5428                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5429
5430                 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
5431                 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
5432                         ni_writew(dev, devpriv->pfi_output_select_reg[i],
5433                                   NI_M_PFI_OUT_SEL_REG(i));
5434                 }
5435         } else {
5436                 s->n_chan       = 10;
5437                 s->subdev_flags = SDF_INTERNAL;
5438         }
5439         s->insn_config  = ni_pfi_insn_config;
5440
5441         ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, ~0, 0);
5442
5443         /* cs5529 calibration adc */
5444         s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
5445         if (devpriv->is_67xx) {
5446                 s->type = COMEDI_SUBD_AI;
5447                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
5448                 /*  one channel for each analog output channel */
5449                 s->n_chan = board->n_aochan;
5450                 s->maxdata = (1 << 16) - 1;
5451                 s->range_table = &range_unknown;        /* XXX */
5452                 s->insn_read = cs5529_ai_insn_read;
5453                 s->insn_config = NULL;
5454                 init_cs5529(dev);
5455         } else {
5456                 s->type = COMEDI_SUBD_UNUSED;
5457         }
5458
5459         /* Serial */
5460         s = &dev->subdevices[NI_SERIAL_SUBDEV];
5461         s->type = COMEDI_SUBD_SERIAL;
5462         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5463         s->n_chan = 1;
5464         s->maxdata = 0xff;
5465         s->insn_config = ni_serial_insn_config;
5466         devpriv->serial_interval_ns = 0;
5467         devpriv->serial_hw_mode = 0;
5468
5469         /* RTSI */
5470         s = &dev->subdevices[NI_RTSI_SUBDEV];
5471         s->type = COMEDI_SUBD_DIO;
5472         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5473         s->n_chan = 8;
5474         s->maxdata = 1;
5475         s->insn_bits = ni_rtsi_insn_bits;
5476         s->insn_config = ni_rtsi_insn_config;
5477         ni_rtsi_init(dev);
5478
5479         /* allocate and initialize the gpct counter device */
5480         devpriv->counter_dev = ni_gpct_device_construct(dev,
5481                                         ni_gpct_write_register,
5482                                         ni_gpct_read_register,
5483                                         (devpriv->is_m_series)
5484                                                 ? ni_gpct_variant_m_series
5485                                                 : ni_gpct_variant_e_series,
5486                                         NUM_GPCT);
5487         if (!devpriv->counter_dev)
5488                 return -ENOMEM;
5489
5490         /* Counter (gpct) subdevices */
5491         for (i = 0; i < NUM_GPCT; ++i) {
5492                 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i];
5493
5494                 /* setup and initialize the counter */
5495                 gpct->chip_index = 0;
5496                 gpct->counter_index = i;
5497                 ni_tio_init_counter(gpct);
5498
5499                 s = &dev->subdevices[NI_GPCT_SUBDEV(i)];
5500                 s->type         = COMEDI_SUBD_COUNTER;
5501                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
5502                 s->n_chan       = 3;
5503                 s->maxdata      = (devpriv->is_m_series) ? 0xffffffff
5504                                                          : 0x00ffffff;
5505                 s->insn_read    = ni_tio_insn_read;
5506                 s->insn_write   = ni_tio_insn_write;
5507                 s->insn_config  = ni_tio_insn_config;
5508 #ifdef PCIDMA
5509                 if (dev->irq && devpriv->mite) {
5510                         s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
5511                         s->len_chanlist = 1;
5512                         s->do_cmdtest   = ni_tio_cmdtest;
5513                         s->do_cmd       = ni_gpct_cmd;
5514                         s->cancel       = ni_gpct_cancel;
5515
5516                         s->async_dma_dir = DMA_BIDIRECTIONAL;
5517                 }
5518 #endif
5519                 s->private      = gpct;
5520         }
5521
5522         /* Frequency output subdevice */
5523         s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
5524         s->type         = COMEDI_SUBD_COUNTER;
5525         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
5526         s->n_chan       = 1;
5527         s->maxdata      = 0xf;
5528         s->insn_read    = ni_freq_out_insn_read;
5529         s->insn_write   = ni_freq_out_insn_write;
5530         s->insn_config  = ni_freq_out_insn_config;
5531
5532         if (dev->irq) {
5533                 ni_stc_writew(dev,
5534                               (irq_polarity ? NISTC_INT_CTRL_INT_POL : 0) |
5535                               (NISTC_INT_CTRL_3PIN_INT & 0) |
5536                               NISTC_INT_CTRL_INTA_ENA |
5537                               NISTC_INT_CTRL_INTB_ENA |
5538                               NISTC_INT_CTRL_INTA_SEL(interrupt_pin) |
5539                               NISTC_INT_CTRL_INTB_SEL(interrupt_pin),
5540                               NISTC_INT_CTRL_REG);
5541         }
5542
5543         /* DMA setup */
5544         ni_writeb(dev, devpriv->ai_ao_select_reg, NI_E_DMA_AI_AO_SEL_REG);
5545         ni_writeb(dev, devpriv->g0_g1_select_reg, NI_E_DMA_G0_G1_SEL_REG);
5546
5547         if (devpriv->is_6xxx) {
5548                 ni_writeb(dev, 0, NI611X_MAGIC_REG);
5549         } else if (devpriv->is_m_series) {
5550                 int channel;
5551
5552                 for (channel = 0; channel < board->n_aochan; ++channel) {
5553                         ni_writeb(dev, 0xf,
5554                                   NI_M_AO_WAVEFORM_ORDER_REG(channel));
5555                         ni_writeb(dev, 0x0,
5556                                   NI_M_AO_REF_ATTENUATION_REG(channel));
5557                 }
5558                 ni_writeb(dev, 0x0, NI_M_AO_CALIB_REG);
5559         }
5560
5561         return 0;
5562 }
5563
5564 static void mio_common_detach(struct comedi_device *dev)
5565 {
5566         struct ni_private *devpriv = dev->private;
5567
5568         if (devpriv)
5569                 ni_gpct_device_destroy(devpriv->counter_dev);
5570 }