2 * Comedi driver for National Instruments AT-MIO16D board
3 * Copyright (C) 2000 Chris R. Baugher <baugher@enteract.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
18 * Description: National Instruments AT-MIO-16D
19 * Author: Chris R. Baugher <baugher@enteract.com>
21 * Devices: [National Instruments] AT-MIO-16 (atmio16), AT-MIO-16D (atmio16d)
23 * Configuration options:
25 * [1] - MIO irq (0 == no irq; or 3,4,5,6,7,9,10,11,12,14,15)
26 * [2] - DIO irq (0 == no irq; or 3,4,5,6,7,9)
27 * [3] - DMA1 channel (0 == no DMA; or 5,6,7)
28 * [4] - DMA2 channel (0 == no DMA; or 5,6,7)
29 * [5] - a/d mux (0=differential; 1=single)
30 * [6] - a/d range (0=bipolar10; 1=bipolar5; 2=unipolar10)
31 * [7] - dac0 range (0=bipolar; 1=unipolar)
32 * [8] - dac0 reference (0=internal; 1=external)
33 * [9] - dac0 coding (0=2's comp; 1=straight binary)
34 * [10] - dac1 range (same as dac0 options)
35 * [11] - dac1 reference (same as dac0 options)
36 * [12] - dac1 coding (same as dac0 options)
40 * I must give credit here to Michal Dobes <dobes@tesnet.cz> who
41 * wrote the driver for Advantec's pcl812 boards. I used the interrupt
42 * handling code from his driver as an example for this one.
49 #include <linux/module.h>
50 #include <linux/interrupt.h>
51 #include "../comedidev.h"
55 /* Configuration and Status Registers */
56 #define COM_REG_1 0x00 /* wo 16 */
57 #define STAT_REG 0x00 /* ro 16 */
58 #define COM_REG_2 0x02 /* wo 16 */
59 /* Event Strobe Registers */
60 #define START_CONVERT_REG 0x08 /* wo 16 */
61 #define START_DAQ_REG 0x0A /* wo 16 */
62 #define AD_CLEAR_REG 0x0C /* wo 16 */
63 #define EXT_STROBE_REG 0x0E /* wo 16 */
64 /* Analog Output Registers */
65 #define DAC0_REG 0x10 /* wo 16 */
66 #define DAC1_REG 0x12 /* wo 16 */
67 #define INT2CLR_REG 0x14 /* wo 16 */
68 /* Analog Input Registers */
69 #define MUX_CNTR_REG 0x04 /* wo 16 */
70 #define MUX_GAIN_REG 0x06 /* wo 16 */
71 #define AD_FIFO_REG 0x16 /* ro 16 */
72 #define DMA_TC_INT_CLR_REG 0x16 /* wo 16 */
73 /* AM9513A Counter/Timer Registers */
74 #define AM9513A_DATA_REG 0x18 /* rw 16 */
75 #define AM9513A_COM_REG 0x1A /* wo 16 */
76 #define AM9513A_STAT_REG 0x1A /* ro 16 */
77 /* MIO-16 Digital I/O Registers */
78 #define MIO_16_DIG_IN_REG 0x1C /* ro 16 */
79 #define MIO_16_DIG_OUT_REG 0x1C /* wo 16 */
80 /* RTSI Switch Registers */
81 #define RTSI_SW_SHIFT_REG 0x1E /* wo 8 */
82 #define RTSI_SW_STROBE_REG 0x1F /* wo 8 */
83 /* DIO-24 Registers */
84 #define DIO_24_PORTA_REG 0x00 /* rw 8 */
85 #define DIO_24_PORTB_REG 0x01 /* rw 8 */
86 #define DIO_24_PORTC_REG 0x02 /* rw 8 */
87 #define DIO_24_CNFG_REG 0x03 /* wo 8 */
89 /* Command Register bits */
90 #define COMREG1_2SCADC 0x0001
91 #define COMREG1_1632CNT 0x0002
92 #define COMREG1_SCANEN 0x0008
93 #define COMREG1_DAQEN 0x0010
94 #define COMREG1_DMAEN 0x0020
95 #define COMREG1_CONVINTEN 0x0080
96 #define COMREG2_SCN2 0x0010
97 #define COMREG2_INTEN 0x0080
98 #define COMREG2_DOUTEN0 0x0100
99 #define COMREG2_DOUTEN1 0x0200
100 /* Status Register bits */
101 #define STAT_AD_OVERRUN 0x0100
102 #define STAT_AD_OVERFLOW 0x0200
103 #define STAT_AD_DAQPROG 0x0800
104 #define STAT_AD_CONVAVAIL 0x2000
105 #define STAT_AD_DAQSTOPINT 0x4000
106 /* AM9513A Counter/Timer defines */
107 #define CLOCK_1_MHZ 0x8B25
108 #define CLOCK_100_KHZ 0x8C25
109 #define CLOCK_10_KHZ 0x8D25
110 #define CLOCK_1_KHZ 0x8E25
111 #define CLOCK_100_HZ 0x8F25
113 struct atmio16_board_t {
119 static const struct comedi_lrange range_atmio16d_ai_10_bipolar = {
128 static const struct comedi_lrange range_atmio16d_ai_5_bipolar = {
137 static const struct comedi_lrange range_atmio16d_ai_unipolar = {
146 /* private data struct */
147 struct atmio16d_private {
148 enum { adc_diff, adc_singleended } adc_mux;
149 enum { adc_bipolar10, adc_bipolar5, adc_unipolar10 } adc_range;
150 enum { adc_2comp, adc_straight } adc_coding;
151 enum { dac_bipolar, dac_unipolar } dac0_range, dac1_range;
152 enum { dac_internal, dac_external } dac0_reference, dac1_reference;
153 enum { dac_2comp, dac_straight } dac0_coding, dac1_coding;
154 const struct comedi_lrange *ao_range_type_list[2];
155 unsigned int com_reg_1_state; /* current state of command register 1 */
156 unsigned int com_reg_2_state; /* current state of command register 2 */
159 static void reset_counters(struct comedi_device *dev)
162 outw(0xFFC2, dev->iobase + AM9513A_COM_REG);
163 outw(0xFF02, dev->iobase + AM9513A_COM_REG);
164 outw(0x4, dev->iobase + AM9513A_DATA_REG);
165 outw(0xFF0A, dev->iobase + AM9513A_COM_REG);
166 outw(0x3, dev->iobase + AM9513A_DATA_REG);
167 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
168 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
170 outw(0xFFC4, dev->iobase + AM9513A_COM_REG);
171 outw(0xFF03, dev->iobase + AM9513A_COM_REG);
172 outw(0x4, dev->iobase + AM9513A_DATA_REG);
173 outw(0xFF0B, dev->iobase + AM9513A_COM_REG);
174 outw(0x3, dev->iobase + AM9513A_DATA_REG);
175 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
176 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
178 outw(0xFFC8, dev->iobase + AM9513A_COM_REG);
179 outw(0xFF04, dev->iobase + AM9513A_COM_REG);
180 outw(0x4, dev->iobase + AM9513A_DATA_REG);
181 outw(0xFF0C, dev->iobase + AM9513A_COM_REG);
182 outw(0x3, dev->iobase + AM9513A_DATA_REG);
183 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
184 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
186 outw(0xFFD0, dev->iobase + AM9513A_COM_REG);
187 outw(0xFF05, dev->iobase + AM9513A_COM_REG);
188 outw(0x4, dev->iobase + AM9513A_DATA_REG);
189 outw(0xFF0D, dev->iobase + AM9513A_COM_REG);
190 outw(0x3, dev->iobase + AM9513A_DATA_REG);
191 outw(0xFF50, dev->iobase + AM9513A_COM_REG);
192 outw(0xFF50, dev->iobase + AM9513A_COM_REG);
194 outw(0, dev->iobase + AD_CLEAR_REG);
197 static void reset_atmio16d(struct comedi_device *dev)
199 struct atmio16d_private *devpriv = dev->private;
202 /* now we need to initialize the board */
203 outw(0, dev->iobase + COM_REG_1);
204 outw(0, dev->iobase + COM_REG_2);
205 outw(0, dev->iobase + MUX_GAIN_REG);
206 /* init AM9513A timer */
207 outw(0xFFFF, dev->iobase + AM9513A_COM_REG);
208 outw(0xFFEF, dev->iobase + AM9513A_COM_REG);
209 outw(0xFF17, dev->iobase + AM9513A_COM_REG);
210 outw(0xF000, dev->iobase + AM9513A_DATA_REG);
211 for (i = 1; i <= 5; ++i) {
212 outw(0xFF00 + i, dev->iobase + AM9513A_COM_REG);
213 outw(0x0004, dev->iobase + AM9513A_DATA_REG);
214 outw(0xFF08 + i, dev->iobase + AM9513A_COM_REG);
215 outw(0x3, dev->iobase + AM9513A_DATA_REG);
217 outw(0xFF5F, dev->iobase + AM9513A_COM_REG);
218 /* timer init done */
219 outw(0, dev->iobase + AD_CLEAR_REG);
220 outw(0, dev->iobase + INT2CLR_REG);
221 /* select straight binary mode for Analog Input */
222 devpriv->com_reg_1_state |= 1;
223 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
224 devpriv->adc_coding = adc_straight;
225 /* zero the analog outputs */
226 outw(2048, dev->iobase + DAC0_REG);
227 outw(2048, dev->iobase + DAC1_REG);
230 static irqreturn_t atmio16d_interrupt(int irq, void *d)
232 struct comedi_device *dev = d;
233 struct comedi_subdevice *s = dev->read_subdev;
236 val = inw(dev->iobase + AD_FIFO_REG);
237 comedi_buf_write_samples(s, &val, 1);
238 comedi_handle_events(dev, s);
243 static int atmio16d_ai_cmdtest(struct comedi_device *dev,
244 struct comedi_subdevice *s,
245 struct comedi_cmd *cmd)
249 /* Step 1 : check if triggers are trivially valid */
251 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW);
252 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
253 TRIG_FOLLOW | TRIG_TIMER);
254 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_TIMER);
255 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
256 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
261 /* Step 2a : make sure trigger sources are unique */
263 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
264 err |= comedi_check_trigger_is_unique(cmd->stop_src);
266 /* Step 2b : and mutually compatible */
271 /* Step 3: check if arguments are trivially valid */
273 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
275 if (cmd->scan_begin_src == TRIG_FOLLOW) {
276 /* internal trigger */
277 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
280 /* external trigger */
281 /* should be level/edge, hi/lo specification here */
282 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
286 err |= comedi_check_trigger_arg_min(&cmd->convert_arg, 10000);
288 err |= comedi_check_trigger_arg_max(&cmd->convert_arg, SLOWEST_TIMER);
291 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
294 if (cmd->stop_src == TRIG_COUNT)
295 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
297 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
305 static int atmio16d_ai_cmd(struct comedi_device *dev,
306 struct comedi_subdevice *s)
308 struct atmio16d_private *devpriv = dev->private;
309 struct comedi_cmd *cmd = &s->async->cmd;
310 unsigned int timer, base_clock;
311 unsigned int sample_count, tmp, chan, gain;
315 * This is slowly becoming a working command interface.
316 * It is still uber-experimental
321 /* check if scanning multiple channels */
322 if (cmd->chanlist_len < 2) {
323 devpriv->com_reg_1_state &= ~COMREG1_SCANEN;
324 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
326 devpriv->com_reg_1_state |= COMREG1_SCANEN;
327 devpriv->com_reg_2_state |= COMREG2_SCN2;
328 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
329 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
332 /* Setup the Mux-Gain Counter */
333 for (i = 0; i < cmd->chanlist_len; ++i) {
334 chan = CR_CHAN(cmd->chanlist[i]);
335 gain = CR_RANGE(cmd->chanlist[i]);
336 outw(i, dev->iobase + MUX_CNTR_REG);
337 tmp = chan | (gain << 6);
338 if (i == cmd->scan_end_arg - 1)
339 tmp |= 0x0010; /* set LASTONE bit */
340 outw(tmp, dev->iobase + MUX_GAIN_REG);
344 * Now program the sample interval timer.
345 * Figure out which clock to use then get an appropriate timer value.
347 if (cmd->convert_arg < 65536000) {
348 base_clock = CLOCK_1_MHZ;
349 timer = cmd->convert_arg / 1000;
350 } else if (cmd->convert_arg < 655360000) {
351 base_clock = CLOCK_100_KHZ;
352 timer = cmd->convert_arg / 10000;
353 } else /* cmd->convert_arg < 6553600000 */ {
354 base_clock = CLOCK_10_KHZ;
355 timer = cmd->convert_arg / 100000;
357 outw(0xFF03, dev->iobase + AM9513A_COM_REG);
358 outw(base_clock, dev->iobase + AM9513A_DATA_REG);
359 outw(0xFF0B, dev->iobase + AM9513A_COM_REG);
360 outw(0x2, dev->iobase + AM9513A_DATA_REG);
361 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
362 outw(0xFFF3, dev->iobase + AM9513A_COM_REG);
363 outw(timer, dev->iobase + AM9513A_DATA_REG);
364 outw(0xFF24, dev->iobase + AM9513A_COM_REG);
366 /* Now figure out how many samples to get */
367 /* and program the sample counter */
368 sample_count = cmd->stop_arg * cmd->scan_end_arg;
369 outw(0xFF04, dev->iobase + AM9513A_COM_REG);
370 outw(0x1025, dev->iobase + AM9513A_DATA_REG);
371 outw(0xFF0C, dev->iobase + AM9513A_COM_REG);
372 if (sample_count < 65536) {
373 /* use only Counter 4 */
374 outw(sample_count, dev->iobase + AM9513A_DATA_REG);
375 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
376 outw(0xFFF4, dev->iobase + AM9513A_COM_REG);
377 outw(0xFF28, dev->iobase + AM9513A_COM_REG);
378 devpriv->com_reg_1_state &= ~COMREG1_1632CNT;
379 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
381 /* Counter 4 and 5 are needed */
383 tmp = sample_count & 0xFFFF;
385 outw(tmp - 1, dev->iobase + AM9513A_DATA_REG);
387 outw(0xFFFF, dev->iobase + AM9513A_DATA_REG);
389 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
390 outw(0, dev->iobase + AM9513A_DATA_REG);
391 outw(0xFF28, dev->iobase + AM9513A_COM_REG);
392 outw(0xFF05, dev->iobase + AM9513A_COM_REG);
393 outw(0x25, dev->iobase + AM9513A_DATA_REG);
394 outw(0xFF0D, dev->iobase + AM9513A_COM_REG);
395 tmp = sample_count & 0xFFFF;
396 if ((tmp == 0) || (tmp == 1)) {
397 outw((sample_count >> 16) & 0xFFFF,
398 dev->iobase + AM9513A_DATA_REG);
400 outw(((sample_count >> 16) & 0xFFFF) + 1,
401 dev->iobase + AM9513A_DATA_REG);
403 outw(0xFF70, dev->iobase + AM9513A_COM_REG);
404 devpriv->com_reg_1_state |= COMREG1_1632CNT;
405 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
409 * Program the scan interval timer ONLY IF SCANNING IS ENABLED.
410 * Figure out which clock to use then get an appropriate timer value.
412 if (cmd->chanlist_len > 1) {
413 if (cmd->scan_begin_arg < 65536000) {
414 base_clock = CLOCK_1_MHZ;
415 timer = cmd->scan_begin_arg / 1000;
416 } else if (cmd->scan_begin_arg < 655360000) {
417 base_clock = CLOCK_100_KHZ;
418 timer = cmd->scan_begin_arg / 10000;
419 } else /* cmd->scan_begin_arg < 6553600000 */ {
420 base_clock = CLOCK_10_KHZ;
421 timer = cmd->scan_begin_arg / 100000;
423 outw(0xFF02, dev->iobase + AM9513A_COM_REG);
424 outw(base_clock, dev->iobase + AM9513A_DATA_REG);
425 outw(0xFF0A, dev->iobase + AM9513A_COM_REG);
426 outw(0x2, dev->iobase + AM9513A_DATA_REG);
427 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
428 outw(0xFFF2, dev->iobase + AM9513A_COM_REG);
429 outw(timer, dev->iobase + AM9513A_DATA_REG);
430 outw(0xFF22, dev->iobase + AM9513A_COM_REG);
433 /* Clear the A/D FIFO and reset the MUX counter */
434 outw(0, dev->iobase + AD_CLEAR_REG);
435 outw(0, dev->iobase + MUX_CNTR_REG);
436 outw(0, dev->iobase + INT2CLR_REG);
437 /* enable this acquisition operation */
438 devpriv->com_reg_1_state |= COMREG1_DAQEN;
439 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
440 /* enable interrupts for conversion completion */
441 devpriv->com_reg_1_state |= COMREG1_CONVINTEN;
442 devpriv->com_reg_2_state |= COMREG2_INTEN;
443 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
444 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
445 /* apply a trigger. this starts the counters! */
446 outw(0, dev->iobase + START_DAQ_REG);
451 /* This will cancel a running acquisition operation */
452 static int atmio16d_ai_cancel(struct comedi_device *dev,
453 struct comedi_subdevice *s)
460 static int atmio16d_ai_eoc(struct comedi_device *dev,
461 struct comedi_subdevice *s,
462 struct comedi_insn *insn,
463 unsigned long context)
467 status = inw(dev->iobase + STAT_REG);
468 if (status & STAT_AD_CONVAVAIL)
470 if (status & STAT_AD_OVERFLOW) {
471 outw(0, dev->iobase + AD_CLEAR_REG);
477 static int atmio16d_ai_insn_read(struct comedi_device *dev,
478 struct comedi_subdevice *s,
479 struct comedi_insn *insn, unsigned int *data)
481 struct atmio16d_private *devpriv = dev->private;
487 chan = CR_CHAN(insn->chanspec);
488 gain = CR_RANGE(insn->chanspec);
490 /* reset the Analog input circuitry */
491 /* outw( 0, dev->iobase+AD_CLEAR_REG ); */
492 /* reset the Analog Input MUX Counter to 0 */
493 /* outw( 0, dev->iobase+MUX_CNTR_REG ); */
495 /* set the Input MUX gain */
496 outw(chan | (gain << 6), dev->iobase + MUX_GAIN_REG);
498 for (i = 0; i < insn->n; i++) {
499 /* start the conversion */
500 outw(0, dev->iobase + START_CONVERT_REG);
502 /* wait for it to finish */
503 ret = comedi_timeout(dev, s, insn, atmio16d_ai_eoc, 0);
507 /* read the data now */
508 data[i] = inw(dev->iobase + AD_FIFO_REG);
509 /* change to two's complement if need be */
510 if (devpriv->adc_coding == adc_2comp)
517 static int atmio16d_ao_insn_write(struct comedi_device *dev,
518 struct comedi_subdevice *s,
519 struct comedi_insn *insn,
522 struct atmio16d_private *devpriv = dev->private;
523 unsigned int chan = CR_CHAN(insn->chanspec);
524 unsigned int reg = (chan) ? DAC1_REG : DAC0_REG;
528 if (chan == 0 && devpriv->dac0_coding == dac_2comp)
530 if (chan == 1 && devpriv->dac1_coding == dac_2comp)
533 for (i = 0; i < insn->n; i++) {
534 unsigned int val = data[i];
536 s->readback[chan] = val;
541 outw(val, dev->iobase + reg);
547 static int atmio16d_dio_insn_bits(struct comedi_device *dev,
548 struct comedi_subdevice *s,
549 struct comedi_insn *insn,
552 if (comedi_dio_update_state(s, data))
553 outw(s->state, dev->iobase + MIO_16_DIG_OUT_REG);
555 data[1] = inw(dev->iobase + MIO_16_DIG_IN_REG);
560 static int atmio16d_dio_insn_config(struct comedi_device *dev,
561 struct comedi_subdevice *s,
562 struct comedi_insn *insn,
565 struct atmio16d_private *devpriv = dev->private;
566 unsigned int chan = CR_CHAN(insn->chanspec);
575 ret = comedi_dio_insn_config(dev, s, insn, data, mask);
579 devpriv->com_reg_2_state &= ~(COMREG2_DOUTEN0 | COMREG2_DOUTEN1);
580 if (s->io_bits & 0x0f)
581 devpriv->com_reg_2_state |= COMREG2_DOUTEN0;
582 if (s->io_bits & 0xf0)
583 devpriv->com_reg_2_state |= COMREG2_DOUTEN1;
584 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
589 static int atmio16d_attach(struct comedi_device *dev,
590 struct comedi_devconfig *it)
592 const struct atmio16_board_t *board = dev->board_ptr;
593 struct atmio16d_private *devpriv;
594 struct comedi_subdevice *s;
597 ret = comedi_request_region(dev, it->options[0], 0x20);
601 ret = comedi_alloc_subdevices(dev, 4);
605 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
609 /* reset the atmio16d hardware */
612 if (it->options[1]) {
613 ret = request_irq(it->options[1], atmio16d_interrupt, 0,
614 dev->board_name, dev);
616 dev->irq = it->options[1];
619 /* set device options */
620 devpriv->adc_mux = it->options[5];
621 devpriv->adc_range = it->options[6];
623 devpriv->dac0_range = it->options[7];
624 devpriv->dac0_reference = it->options[8];
625 devpriv->dac0_coding = it->options[9];
626 devpriv->dac1_range = it->options[10];
627 devpriv->dac1_reference = it->options[11];
628 devpriv->dac1_coding = it->options[12];
630 /* setup sub-devices */
631 s = &dev->subdevices[0];
633 s->type = COMEDI_SUBD_AI;
634 s->subdev_flags = SDF_READABLE | SDF_GROUND;
635 s->n_chan = (devpriv->adc_mux ? 16 : 8);
636 s->insn_read = atmio16d_ai_insn_read;
637 s->maxdata = 0xfff; /* 4095 decimal */
638 switch (devpriv->adc_range) {
640 s->range_table = &range_atmio16d_ai_10_bipolar;
643 s->range_table = &range_atmio16d_ai_5_bipolar;
646 s->range_table = &range_atmio16d_ai_unipolar;
650 dev->read_subdev = s;
651 s->subdev_flags |= SDF_CMD_READ;
652 s->len_chanlist = 16;
653 s->do_cmdtest = atmio16d_ai_cmdtest;
654 s->do_cmd = atmio16d_ai_cmd;
655 s->cancel = atmio16d_ai_cancel;
659 s = &dev->subdevices[1];
660 s->type = COMEDI_SUBD_AO;
661 s->subdev_flags = SDF_WRITABLE;
663 s->maxdata = 0xfff; /* 4095 decimal */
664 s->range_table_list = devpriv->ao_range_type_list;
665 switch (devpriv->dac0_range) {
667 devpriv->ao_range_type_list[0] = &range_bipolar10;
670 devpriv->ao_range_type_list[0] = &range_unipolar10;
673 switch (devpriv->dac1_range) {
675 devpriv->ao_range_type_list[1] = &range_bipolar10;
678 devpriv->ao_range_type_list[1] = &range_unipolar10;
681 s->insn_write = atmio16d_ao_insn_write;
683 ret = comedi_alloc_subdev_readback(s);
688 s = &dev->subdevices[2];
689 s->type = COMEDI_SUBD_DIO;
690 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
692 s->insn_bits = atmio16d_dio_insn_bits;
693 s->insn_config = atmio16d_dio_insn_config;
695 s->range_table = &range_digital;
698 s = &dev->subdevices[3];
699 if (board->has_8255) {
700 ret = subdev_8255_init(dev, s, NULL, 0x00);
704 s->type = COMEDI_SUBD_UNUSED;
707 /* don't yet know how to deal with counter/timers */
709 s = &dev->subdevices[4];
711 s->type = COMEDI_SUBD_TIMER;
719 static void atmio16d_detach(struct comedi_device *dev)
722 comedi_legacy_detach(dev);
725 static const struct atmio16_board_t atmio16_boards[] = {
735 static struct comedi_driver atmio16d_driver = {
736 .driver_name = "atmio16",
737 .module = THIS_MODULE,
738 .attach = atmio16d_attach,
739 .detach = atmio16d_detach,
740 .board_name = &atmio16_boards[0].name,
741 .num_names = ARRAY_SIZE(atmio16_boards),
742 .offset = sizeof(struct atmio16_board_t),
744 module_comedi_driver(atmio16d_driver);
746 MODULE_AUTHOR("Comedi http://www.comedi.org");
747 MODULE_DESCRIPTION("Comedi low-level driver");
748 MODULE_LICENSE("GPL");