1 // SPDX-License-Identifier: GPL-2.0+
3 * Hardware driver for NI 660x devices
8 * Description: National Instruments 660x counter/timer boards
9 * Devices: [National Instruments] PCI-6601 (ni_660x), PCI-6602, PXI-6602,
10 * PXI-6608, PCI-6624, PXI-6624
11 * Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
12 * Herman.Bruyninckx@mech.kuleuven.ac.be,
13 * Wim.Meeussen@mech.kuleuven.ac.be,
14 * Klaas.Gadeyne@mech.kuleuven.ac.be,
15 * Frank Mori Hess <fmhess@users.sourceforge.net>
16 * Updated: Mon, 16 Jan 2017 14:00:43 +0000
17 * Status: experimental
19 * Encoders work. PulseGeneration (both single pulse and pulse train)
20 * works. Buffered commands work for input but not output.
23 * DAQ 660x Register-Level Programmer Manual (NI 370505A-01)
24 * DAQ 6601/6602 User Manual (NI 322137B-01)
27 #include <linux/module.h>
28 #include <linux/interrupt.h>
30 #include "../comedi_pci.h"
35 /* See Register-Level Programmer Manual page 3.1 */
36 enum ni_660x_register {
37 /* see enum ni_gpct_register */
38 NI660X_STC_DIO_PARALLEL_INPUT = NITIO_NUM_REGS,
39 NI660X_STC_DIO_OUTPUT,
40 NI660X_STC_DIO_CONTROL,
41 NI660X_STC_DIO_SERIAL_INPUT,
45 NI660X_GLOBAL_INT_STATUS,
47 NI660X_GLOBAL_INT_CFG,
71 #define NI660X_CLK_CFG_COUNTER_SWAP BIT(21)
73 #define NI660X_GLOBAL_INT_COUNTER0 BIT(8)
74 #define NI660X_GLOBAL_INT_COUNTER1 BIT(9)
75 #define NI660X_GLOBAL_INT_COUNTER2 BIT(10)
76 #define NI660X_GLOBAL_INT_COUNTER3 BIT(11)
77 #define NI660X_GLOBAL_INT_CASCADE BIT(29)
78 #define NI660X_GLOBAL_INT_GLOBAL_POL BIT(30)
79 #define NI660X_GLOBAL_INT_GLOBAL BIT(31)
81 #define NI660X_DMA_CFG_SEL(_c, _s) (((_s) & 0x1f) << (8 * (_c)))
82 #define NI660X_DMA_CFG_SEL_MASK(_c) NI660X_DMA_CFG_SEL((_c), 0x1f)
83 #define NI660X_DMA_CFG_SEL_NONE(_c) NI660X_DMA_CFG_SEL((_c), 0x1f)
84 #define NI660X_DMA_CFG_RESET(_c) NI660X_DMA_CFG_SEL((_c), 0x80)
86 #define NI660X_IO_CFG(x) (NI660X_IO_CFG_0_1 + ((x) / 2))
87 #define NI660X_IO_CFG_OUT_SEL(_c, _s) (((_s) & 0x3) << (((_c) % 2) ? 0 : 8))
88 #define NI660X_IO_CFG_OUT_SEL_MASK(_c) NI660X_IO_CFG_OUT_SEL((_c), 0x3)
89 #define NI660X_IO_CFG_IN_SEL(_c, _s) (((_s) & 0x7) << (((_c) % 2) ? 4 : 12))
90 #define NI660X_IO_CFG_IN_SEL_MASK(_c) NI660X_IO_CFG_IN_SEL((_c), 0x7)
92 struct ni_660x_register_data {
93 int offset; /* Offset from base address from GPCT chip */
94 char size; /* 2 or 4 bytes */
97 static const struct ni_660x_register_data ni_660x_reg_data[NI660X_NUM_REGS] = {
98 [NITIO_G0_INT_ACK] = { 0x004, 2 }, /* write */
99 [NITIO_G0_STATUS] = { 0x004, 2 }, /* read */
100 [NITIO_G1_INT_ACK] = { 0x006, 2 }, /* write */
101 [NITIO_G1_STATUS] = { 0x006, 2 }, /* read */
102 [NITIO_G01_STATUS] = { 0x008, 2 }, /* read */
103 [NITIO_G0_CMD] = { 0x00c, 2 }, /* write */
104 [NI660X_STC_DIO_PARALLEL_INPUT] = { 0x00e, 2 }, /* read */
105 [NITIO_G1_CMD] = { 0x00e, 2 }, /* write */
106 [NITIO_G0_HW_SAVE] = { 0x010, 4 }, /* read */
107 [NITIO_G1_HW_SAVE] = { 0x014, 4 }, /* read */
108 [NI660X_STC_DIO_OUTPUT] = { 0x014, 2 }, /* write */
109 [NI660X_STC_DIO_CONTROL] = { 0x016, 2 }, /* write */
110 [NITIO_G0_SW_SAVE] = { 0x018, 4 }, /* read */
111 [NITIO_G1_SW_SAVE] = { 0x01c, 4 }, /* read */
112 [NITIO_G0_MODE] = { 0x034, 2 }, /* write */
113 [NITIO_G01_STATUS1] = { 0x036, 2 }, /* read */
114 [NITIO_G1_MODE] = { 0x036, 2 }, /* write */
115 [NI660X_STC_DIO_SERIAL_INPUT] = { 0x038, 2 }, /* read */
116 [NITIO_G0_LOADA] = { 0x038, 4 }, /* write */
117 [NITIO_G01_STATUS2] = { 0x03a, 2 }, /* read */
118 [NITIO_G0_LOADB] = { 0x03c, 4 }, /* write */
119 [NITIO_G1_LOADA] = { 0x040, 4 }, /* write */
120 [NITIO_G1_LOADB] = { 0x044, 4 }, /* write */
121 [NITIO_G0_INPUT_SEL] = { 0x048, 2 }, /* write */
122 [NITIO_G1_INPUT_SEL] = { 0x04a, 2 }, /* write */
123 [NITIO_G0_AUTO_INC] = { 0x088, 2 }, /* write */
124 [NITIO_G1_AUTO_INC] = { 0x08a, 2 }, /* write */
125 [NITIO_G01_RESET] = { 0x090, 2 }, /* write */
126 [NITIO_G0_INT_ENA] = { 0x092, 2 }, /* write */
127 [NITIO_G1_INT_ENA] = { 0x096, 2 }, /* write */
128 [NITIO_G0_CNT_MODE] = { 0x0b0, 2 }, /* write */
129 [NITIO_G1_CNT_MODE] = { 0x0b2, 2 }, /* write */
130 [NITIO_G0_GATE2] = { 0x0b4, 2 }, /* write */
131 [NITIO_G1_GATE2] = { 0x0b6, 2 }, /* write */
132 [NITIO_G0_DMA_CFG] = { 0x0b8, 2 }, /* write */
133 [NITIO_G0_DMA_STATUS] = { 0x0b8, 2 }, /* read */
134 [NITIO_G1_DMA_CFG] = { 0x0ba, 2 }, /* write */
135 [NITIO_G1_DMA_STATUS] = { 0x0ba, 2 }, /* read */
136 [NITIO_G2_INT_ACK] = { 0x104, 2 }, /* write */
137 [NITIO_G2_STATUS] = { 0x104, 2 }, /* read */
138 [NITIO_G3_INT_ACK] = { 0x106, 2 }, /* write */
139 [NITIO_G3_STATUS] = { 0x106, 2 }, /* read */
140 [NITIO_G23_STATUS] = { 0x108, 2 }, /* read */
141 [NITIO_G2_CMD] = { 0x10c, 2 }, /* write */
142 [NITIO_G3_CMD] = { 0x10e, 2 }, /* write */
143 [NITIO_G2_HW_SAVE] = { 0x110, 4 }, /* read */
144 [NITIO_G3_HW_SAVE] = { 0x114, 4 }, /* read */
145 [NITIO_G2_SW_SAVE] = { 0x118, 4 }, /* read */
146 [NITIO_G3_SW_SAVE] = { 0x11c, 4 }, /* read */
147 [NITIO_G2_MODE] = { 0x134, 2 }, /* write */
148 [NITIO_G23_STATUS1] = { 0x136, 2 }, /* read */
149 [NITIO_G3_MODE] = { 0x136, 2 }, /* write */
150 [NITIO_G2_LOADA] = { 0x138, 4 }, /* write */
151 [NITIO_G23_STATUS2] = { 0x13a, 2 }, /* read */
152 [NITIO_G2_LOADB] = { 0x13c, 4 }, /* write */
153 [NITIO_G3_LOADA] = { 0x140, 4 }, /* write */
154 [NITIO_G3_LOADB] = { 0x144, 4 }, /* write */
155 [NITIO_G2_INPUT_SEL] = { 0x148, 2 }, /* write */
156 [NITIO_G3_INPUT_SEL] = { 0x14a, 2 }, /* write */
157 [NITIO_G2_AUTO_INC] = { 0x188, 2 }, /* write */
158 [NITIO_G3_AUTO_INC] = { 0x18a, 2 }, /* write */
159 [NITIO_G23_RESET] = { 0x190, 2 }, /* write */
160 [NITIO_G2_INT_ENA] = { 0x192, 2 }, /* write */
161 [NITIO_G3_INT_ENA] = { 0x196, 2 }, /* write */
162 [NITIO_G2_CNT_MODE] = { 0x1b0, 2 }, /* write */
163 [NITIO_G3_CNT_MODE] = { 0x1b2, 2 }, /* write */
164 [NITIO_G2_GATE2] = { 0x1b4, 2 }, /* write */
165 [NITIO_G3_GATE2] = { 0x1b6, 2 }, /* write */
166 [NITIO_G2_DMA_CFG] = { 0x1b8, 2 }, /* write */
167 [NITIO_G2_DMA_STATUS] = { 0x1b8, 2 }, /* read */
168 [NITIO_G3_DMA_CFG] = { 0x1ba, 2 }, /* write */
169 [NITIO_G3_DMA_STATUS] = { 0x1ba, 2 }, /* read */
170 [NI660X_DIO32_INPUT] = { 0x414, 4 }, /* read */
171 [NI660X_DIO32_OUTPUT] = { 0x510, 4 }, /* write */
172 [NI660X_CLK_CFG] = { 0x73c, 4 }, /* write */
173 [NI660X_GLOBAL_INT_STATUS] = { 0x754, 4 }, /* read */
174 [NI660X_DMA_CFG] = { 0x76c, 4 }, /* write */
175 [NI660X_GLOBAL_INT_CFG] = { 0x770, 4 }, /* write */
176 [NI660X_IO_CFG_0_1] = { 0x77c, 2 }, /* read/write */
177 [NI660X_IO_CFG_2_3] = { 0x77e, 2 }, /* read/write */
178 [NI660X_IO_CFG_4_5] = { 0x780, 2 }, /* read/write */
179 [NI660X_IO_CFG_6_7] = { 0x782, 2 }, /* read/write */
180 [NI660X_IO_CFG_8_9] = { 0x784, 2 }, /* read/write */
181 [NI660X_IO_CFG_10_11] = { 0x786, 2 }, /* read/write */
182 [NI660X_IO_CFG_12_13] = { 0x788, 2 }, /* read/write */
183 [NI660X_IO_CFG_14_15] = { 0x78a, 2 }, /* read/write */
184 [NI660X_IO_CFG_16_17] = { 0x78c, 2 }, /* read/write */
185 [NI660X_IO_CFG_18_19] = { 0x78e, 2 }, /* read/write */
186 [NI660X_IO_CFG_20_21] = { 0x790, 2 }, /* read/write */
187 [NI660X_IO_CFG_22_23] = { 0x792, 2 }, /* read/write */
188 [NI660X_IO_CFG_24_25] = { 0x794, 2 }, /* read/write */
189 [NI660X_IO_CFG_26_27] = { 0x796, 2 }, /* read/write */
190 [NI660X_IO_CFG_28_29] = { 0x798, 2 }, /* read/write */
191 [NI660X_IO_CFG_30_31] = { 0x79a, 2 }, /* read/write */
192 [NI660X_IO_CFG_32_33] = { 0x79c, 2 }, /* read/write */
193 [NI660X_IO_CFG_34_35] = { 0x79e, 2 }, /* read/write */
194 [NI660X_IO_CFG_36_37] = { 0x7a0, 2 }, /* read/write */
195 [NI660X_IO_CFG_38_39] = { 0x7a2, 2 } /* read/write */
198 #define NI660X_CHIP_OFFSET 0x800
200 enum ni_660x_boardid {
209 struct ni_660x_board {
211 unsigned int n_chips; /* total number of TIO chips */
214 static const struct ni_660x_board ni_660x_boards[] = {
241 #define NI660X_NUM_PFI_CHANNELS 40
243 /* there are only up to 3 dma channels, but the register layout allows for 4 */
244 #define NI660X_MAX_DMA_CHANNEL 4
246 #define NI660X_COUNTERS_PER_CHIP 4
247 #define NI660X_MAX_CHIPS 2
248 #define NI660X_MAX_COUNTERS (NI660X_MAX_CHIPS * \
249 NI660X_COUNTERS_PER_CHIP)
251 struct ni_660x_private {
253 struct ni_gpct_device *counter_dev;
254 struct mite_ring *ring[NI660X_MAX_CHIPS][NI660X_COUNTERS_PER_CHIP];
255 /* protects mite channel request/release */
256 spinlock_t mite_channel_lock;
257 /* prevents races between interrupt and comedi_poll */
258 spinlock_t interrupt_lock;
259 unsigned int dma_cfg[NI660X_MAX_CHIPS];
260 unsigned int io_cfg[NI660X_NUM_PFI_CHANNELS];
264 static void ni_660x_write(struct comedi_device *dev, unsigned int chip,
265 unsigned int bits, unsigned int reg)
267 unsigned int addr = (chip * NI660X_CHIP_OFFSET) +
268 ni_660x_reg_data[reg].offset;
270 if (ni_660x_reg_data[reg].size == 2)
271 writew(bits, dev->mmio + addr);
273 writel(bits, dev->mmio + addr);
276 static unsigned int ni_660x_read(struct comedi_device *dev,
277 unsigned int chip, unsigned int reg)
279 unsigned int addr = (chip * NI660X_CHIP_OFFSET) +
280 ni_660x_reg_data[reg].offset;
282 if (ni_660x_reg_data[reg].size == 2)
283 return readw(dev->mmio + addr);
284 return readl(dev->mmio + addr);
287 static void ni_660x_gpct_write(struct ni_gpct *counter, unsigned int bits,
288 enum ni_gpct_register reg)
290 struct comedi_device *dev = counter->counter_dev->dev;
292 ni_660x_write(dev, counter->chip_index, bits, reg);
295 static unsigned int ni_660x_gpct_read(struct ni_gpct *counter,
296 enum ni_gpct_register reg)
298 struct comedi_device *dev = counter->counter_dev->dev;
300 return ni_660x_read(dev, counter->chip_index, reg);
303 static inline void ni_660x_set_dma_channel(struct comedi_device *dev,
304 unsigned int mite_channel,
305 struct ni_gpct *counter)
307 struct ni_660x_private *devpriv = dev->private;
308 unsigned int chip = counter->chip_index;
310 devpriv->dma_cfg[chip] &= ~NI660X_DMA_CFG_SEL_MASK(mite_channel);
311 devpriv->dma_cfg[chip] |= NI660X_DMA_CFG_SEL(mite_channel,
312 counter->counter_index);
313 ni_660x_write(dev, chip, devpriv->dma_cfg[chip] |
314 NI660X_DMA_CFG_RESET(mite_channel),
319 static inline void ni_660x_unset_dma_channel(struct comedi_device *dev,
320 unsigned int mite_channel,
321 struct ni_gpct *counter)
323 struct ni_660x_private *devpriv = dev->private;
324 unsigned int chip = counter->chip_index;
326 devpriv->dma_cfg[chip] &= ~NI660X_DMA_CFG_SEL_MASK(mite_channel);
327 devpriv->dma_cfg[chip] |= NI660X_DMA_CFG_SEL_NONE(mite_channel);
328 ni_660x_write(dev, chip, devpriv->dma_cfg[chip], NI660X_DMA_CFG);
332 static int ni_660x_request_mite_channel(struct comedi_device *dev,
333 struct ni_gpct *counter,
334 enum comedi_io_direction direction)
336 struct ni_660x_private *devpriv = dev->private;
337 struct mite_ring *ring;
338 struct mite_channel *mite_chan;
341 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
342 ring = devpriv->ring[counter->chip_index][counter->counter_index];
343 mite_chan = mite_request_channel(devpriv->mite, ring);
345 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
346 dev_err(dev->class_dev,
347 "failed to reserve mite dma channel for counter\n");
350 mite_chan->dir = direction;
351 ni_tio_set_mite_channel(counter, mite_chan);
352 ni_660x_set_dma_channel(dev, mite_chan->channel, counter);
353 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
357 static void ni_660x_release_mite_channel(struct comedi_device *dev,
358 struct ni_gpct *counter)
360 struct ni_660x_private *devpriv = dev->private;
363 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
364 if (counter->mite_chan) {
365 struct mite_channel *mite_chan = counter->mite_chan;
367 ni_660x_unset_dma_channel(dev, mite_chan->channel, counter);
368 ni_tio_set_mite_channel(counter, NULL);
369 mite_release_channel(mite_chan);
371 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
374 static int ni_660x_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
376 struct ni_gpct *counter = s->private;
379 retval = ni_660x_request_mite_channel(dev, counter, COMEDI_INPUT);
381 dev_err(dev->class_dev,
382 "no dma channel available for use by counter\n");
385 ni_tio_acknowledge(counter);
387 return ni_tio_cmd(dev, s);
390 static int ni_660x_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
392 struct ni_gpct *counter = s->private;
395 retval = ni_tio_cancel(counter);
396 ni_660x_release_mite_channel(dev, counter);
400 static void set_tio_counterswap(struct comedi_device *dev, int chip)
402 unsigned int bits = 0;
405 * See P. 3.5 of the Register-Level Programming manual.
406 * The CounterSwap bit has to be set on the second chip,
407 * otherwise it will try to use the same pins as the
411 bits = NI660X_CLK_CFG_COUNTER_SWAP;
413 ni_660x_write(dev, chip, bits, NI660X_CLK_CFG);
416 static void ni_660x_handle_gpct_interrupt(struct comedi_device *dev,
417 struct comedi_subdevice *s)
419 struct ni_gpct *counter = s->private;
421 ni_tio_handle_interrupt(counter, s);
422 comedi_handle_events(dev, s);
425 static irqreturn_t ni_660x_interrupt(int irq, void *d)
427 struct comedi_device *dev = d;
428 struct ni_660x_private *devpriv = dev->private;
429 struct comedi_subdevice *s;
435 /* make sure dev->attached is checked before doing anything else */
438 /* lock to avoid race with comedi_poll */
439 spin_lock_irqsave(&devpriv->interrupt_lock, flags);
440 for (i = 0; i < dev->n_subdevices; ++i) {
441 s = &dev->subdevices[i];
442 if (s->type == COMEDI_SUBD_COUNTER)
443 ni_660x_handle_gpct_interrupt(dev, s);
445 spin_unlock_irqrestore(&devpriv->interrupt_lock, flags);
449 static int ni_660x_input_poll(struct comedi_device *dev,
450 struct comedi_subdevice *s)
452 struct ni_660x_private *devpriv = dev->private;
453 struct ni_gpct *counter = s->private;
456 /* lock to avoid race with comedi_poll */
457 spin_lock_irqsave(&devpriv->interrupt_lock, flags);
458 mite_sync_dma(counter->mite_chan, s);
459 spin_unlock_irqrestore(&devpriv->interrupt_lock, flags);
460 return comedi_buf_read_n_available(s);
463 static int ni_660x_buf_change(struct comedi_device *dev,
464 struct comedi_subdevice *s)
466 struct ni_660x_private *devpriv = dev->private;
467 struct ni_gpct *counter = s->private;
468 struct mite_ring *ring;
471 ring = devpriv->ring[counter->chip_index][counter->counter_index];
472 ret = mite_buf_change(ring, s);
479 static int ni_660x_allocate_private(struct comedi_device *dev)
481 struct ni_660x_private *devpriv;
484 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
488 spin_lock_init(&devpriv->mite_channel_lock);
489 spin_lock_init(&devpriv->interrupt_lock);
490 for (i = 0; i < NI660X_NUM_PFI_CHANNELS; ++i)
491 devpriv->io_cfg[i] = NI_660X_PFI_OUTPUT_COUNTER;
496 static int ni_660x_alloc_mite_rings(struct comedi_device *dev)
498 const struct ni_660x_board *board = dev->board_ptr;
499 struct ni_660x_private *devpriv = dev->private;
503 for (i = 0; i < board->n_chips; ++i) {
504 for (j = 0; j < NI660X_COUNTERS_PER_CHIP; ++j) {
505 devpriv->ring[i][j] = mite_alloc_ring(devpriv->mite);
506 if (!devpriv->ring[i][j])
513 static void ni_660x_free_mite_rings(struct comedi_device *dev)
515 const struct ni_660x_board *board = dev->board_ptr;
516 struct ni_660x_private *devpriv = dev->private;
520 for (i = 0; i < board->n_chips; ++i) {
521 for (j = 0; j < NI660X_COUNTERS_PER_CHIP; ++j)
522 mite_free_ring(devpriv->ring[i][j]);
526 static int ni_660x_dio_insn_bits(struct comedi_device *dev,
527 struct comedi_subdevice *s,
528 struct comedi_insn *insn,
531 unsigned int shift = CR_CHAN(insn->chanspec);
532 unsigned int mask = data[0] << shift;
533 unsigned int bits = data[1] << shift;
536 * There are 40 channels in this subdevice but only 32 are usable
537 * as DIO. The shift adjusts the mask/bits to account for the base
538 * channel in insn->chanspec. The state update can then be handled
539 * normally for the 32 usable channels.
543 s->state |= (bits & mask);
544 ni_660x_write(dev, 0, s->state, NI660X_DIO32_OUTPUT);
548 * Return the input channels, shifted back to account for the base
551 data[1] = ni_660x_read(dev, 0, NI660X_DIO32_INPUT) >> shift;
556 static void ni_660x_select_pfi_output(struct comedi_device *dev,
557 unsigned int chan, unsigned int out_sel)
559 const struct ni_660x_board *board = dev->board_ptr;
560 unsigned int active_chip = 0;
561 unsigned int idle_chip = 0;
564 if (board->n_chips > 1) {
565 if (out_sel == NI_660X_PFI_OUTPUT_COUNTER &&
566 chan >= 8 && chan <= 23) {
567 /* counters 4-7 pfi channels */
571 /* counters 0-3 pfi channels */
577 if (idle_chip != active_chip) {
578 /* set the pfi channel to high-z on the inactive chip */
579 bits = ni_660x_read(dev, idle_chip, NI660X_IO_CFG(chan));
580 bits &= ~NI660X_IO_CFG_OUT_SEL_MASK(chan);
581 bits |= NI660X_IO_CFG_OUT_SEL(chan, 0); /* high-z */
582 ni_660x_write(dev, idle_chip, bits, NI660X_IO_CFG(chan));
585 /* set the pfi channel output on the active chip */
586 bits = ni_660x_read(dev, active_chip, NI660X_IO_CFG(chan));
587 bits &= ~NI660X_IO_CFG_OUT_SEL_MASK(chan);
588 bits |= NI660X_IO_CFG_OUT_SEL(chan, out_sel);
589 ni_660x_write(dev, active_chip, bits, NI660X_IO_CFG(chan));
592 static int ni_660x_set_pfi_routing(struct comedi_device *dev,
593 unsigned int chan, unsigned int source)
595 struct ni_660x_private *devpriv = dev->private;
598 case NI_660X_PFI_OUTPUT_COUNTER:
602 case NI_660X_PFI_OUTPUT_DIO:
610 devpriv->io_cfg[chan] = source;
611 if (devpriv->io_dir & (1ULL << chan))
612 ni_660x_select_pfi_output(dev, chan, devpriv->io_cfg[chan]);
616 static int ni_660x_dio_insn_config(struct comedi_device *dev,
617 struct comedi_subdevice *s,
618 struct comedi_insn *insn,
621 struct ni_660x_private *devpriv = dev->private;
622 unsigned int chan = CR_CHAN(insn->chanspec);
623 u64 bit = 1ULL << chan;
628 case INSN_CONFIG_DIO_OUTPUT:
629 devpriv->io_dir |= bit;
630 ni_660x_select_pfi_output(dev, chan, devpriv->io_cfg[chan]);
633 case INSN_CONFIG_DIO_INPUT:
634 devpriv->io_dir &= ~bit;
635 ni_660x_select_pfi_output(dev, chan, 0); /* high-z */
638 case INSN_CONFIG_DIO_QUERY:
639 data[1] = (devpriv->io_dir & bit) ? COMEDI_OUTPUT
643 case INSN_CONFIG_SET_ROUTING:
644 ret = ni_660x_set_pfi_routing(dev, chan, data[1]);
649 case INSN_CONFIG_GET_ROUTING:
650 data[1] = devpriv->io_cfg[chan];
653 case INSN_CONFIG_FILTER:
654 val = ni_660x_read(dev, 0, NI660X_IO_CFG(chan));
655 val &= ~NI660X_IO_CFG_IN_SEL_MASK(chan);
656 val |= NI660X_IO_CFG_IN_SEL(chan, data[1]);
657 ni_660x_write(dev, 0, val, NI660X_IO_CFG(chan));
667 static void ni_660x_init_tio_chips(struct comedi_device *dev,
668 unsigned int n_chips)
670 struct ni_660x_private *devpriv = dev->private;
675 * We use the ioconfig registers to control dio direction, so zero
676 * output enables in stc dio control reg.
678 ni_660x_write(dev, 0, 0, NI660X_STC_DIO_CONTROL);
680 for (chip = 0; chip < n_chips; ++chip) {
681 /* init dma configuration register */
682 devpriv->dma_cfg[chip] = 0;
683 for (chan = 0; chan < NI660X_MAX_DMA_CHANNEL; ++chan)
684 devpriv->dma_cfg[chip] |= NI660X_DMA_CFG_SEL_NONE(chan);
685 ni_660x_write(dev, chip, devpriv->dma_cfg[chip],
688 /* init ioconfig registers */
689 for (chan = 0; chan < NI660X_NUM_PFI_CHANNELS; ++chan)
690 ni_660x_write(dev, chip, 0, NI660X_IO_CFG(chan));
694 static int ni_660x_auto_attach(struct comedi_device *dev,
695 unsigned long context)
697 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
698 const struct ni_660x_board *board = NULL;
699 struct ni_660x_private *devpriv;
700 struct comedi_subdevice *s;
701 struct ni_gpct_device *gpct_dev;
702 unsigned int n_counters;
706 unsigned int global_interrupt_config_bits;
708 if (context < ARRAY_SIZE(ni_660x_boards))
709 board = &ni_660x_boards[context];
712 dev->board_ptr = board;
713 dev->board_name = board->name;
715 ret = comedi_pci_enable(dev);
719 ret = ni_660x_allocate_private(dev);
722 devpriv = dev->private;
724 devpriv->mite = mite_attach(dev, true); /* use win1 */
728 ret = ni_660x_alloc_mite_rings(dev);
732 ni_660x_init_tio_chips(dev, board->n_chips);
734 n_counters = board->n_chips * NI660X_COUNTERS_PER_CHIP;
735 gpct_dev = ni_gpct_device_construct(dev,
738 ni_gpct_variant_660x,
742 devpriv->counter_dev = gpct_dev;
744 ret = comedi_alloc_subdevices(dev, 2 + NI660X_MAX_COUNTERS);
750 s = &dev->subdevices[subdev++];
751 /* Old GENERAL-PURPOSE COUNTER/TIME (GPCT) subdevice, no longer used */
752 s->type = COMEDI_SUBD_UNUSED;
755 * Digital I/O subdevice
757 * There are 40 channels but only the first 32 can be digital I/Os.
758 * The last 8 are dedicated to counters 0 and 1.
760 * Counter 0-3 signals are from the first TIO chip.
761 * Counter 4-7 signals are from the second TIO chip.
764 * PFI Chan DIO Chan Counter Signal
765 * ------- -------- --------------
807 s = &dev->subdevices[subdev++];
808 s->type = COMEDI_SUBD_DIO;
809 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
810 s->n_chan = NI660X_NUM_PFI_CHANNELS;
812 s->range_table = &range_digital;
813 s->insn_bits = ni_660x_dio_insn_bits;
814 s->insn_config = ni_660x_dio_insn_config;
817 * Default the DIO channels as:
818 * chan 0-7: DIO inputs
819 * chan 8-39: counter signal inputs
821 for (i = 0; i < s->n_chan; ++i) {
822 unsigned int source = (i < 8) ? NI_660X_PFI_OUTPUT_DIO
823 : NI_660X_PFI_OUTPUT_COUNTER;
825 ni_660x_set_pfi_routing(dev, i, source);
826 ni_660x_select_pfi_output(dev, i, 0); /* high-z */
829 /* Counter subdevices (4 NI TIO General Purpose Counters per chip) */
830 for (i = 0; i < NI660X_MAX_COUNTERS; ++i) {
831 s = &dev->subdevices[subdev++];
832 if (i < n_counters) {
833 struct ni_gpct *counter = &gpct_dev->counters[i];
835 counter->chip_index = i / NI660X_COUNTERS_PER_CHIP;
836 counter->counter_index = i % NI660X_COUNTERS_PER_CHIP;
838 s->type = COMEDI_SUBD_COUNTER;
839 s->subdev_flags = SDF_READABLE | SDF_WRITABLE |
840 SDF_LSAMPL | SDF_CMD_READ;
842 s->maxdata = 0xffffffff;
843 s->insn_read = ni_tio_insn_read;
844 s->insn_write = ni_tio_insn_write;
845 s->insn_config = ni_tio_insn_config;
847 s->do_cmd = ni_660x_cmd;
848 s->do_cmdtest = ni_tio_cmdtest;
849 s->cancel = ni_660x_cancel;
850 s->poll = ni_660x_input_poll;
851 s->buf_change = ni_660x_buf_change;
852 s->async_dma_dir = DMA_BIDIRECTIONAL;
853 s->private = counter;
855 ni_tio_init_counter(counter);
857 s->type = COMEDI_SUBD_UNUSED;
862 * To be safe, set counterswap bits on tio chips after all the counter
863 * outputs have been set to high impedance mode.
865 for (i = 0; i < board->n_chips; ++i)
866 set_tio_counterswap(dev, i);
868 ret = request_irq(pcidev->irq, ni_660x_interrupt, IRQF_SHARED,
869 dev->board_name, dev);
871 dev_warn(dev->class_dev, " irq not available\n");
874 dev->irq = pcidev->irq;
875 global_interrupt_config_bits = NI660X_GLOBAL_INT_GLOBAL;
876 if (board->n_chips > 1)
877 global_interrupt_config_bits |= NI660X_GLOBAL_INT_CASCADE;
878 ni_660x_write(dev, 0, global_interrupt_config_bits,
879 NI660X_GLOBAL_INT_CFG);
884 static void ni_660x_detach(struct comedi_device *dev)
886 struct ni_660x_private *devpriv = dev->private;
889 ni_660x_write(dev, 0, 0, NI660X_GLOBAL_INT_CFG);
890 free_irq(dev->irq, dev);
893 ni_gpct_device_destroy(devpriv->counter_dev);
894 ni_660x_free_mite_rings(dev);
895 mite_detach(devpriv->mite);
899 comedi_pci_disable(dev);
902 static struct comedi_driver ni_660x_driver = {
903 .driver_name = "ni_660x",
904 .module = THIS_MODULE,
905 .auto_attach = ni_660x_auto_attach,
906 .detach = ni_660x_detach,
909 static int ni_660x_pci_probe(struct pci_dev *dev,
910 const struct pci_device_id *id)
912 return comedi_pci_auto_config(dev, &ni_660x_driver, id->driver_data);
915 static const struct pci_device_id ni_660x_pci_table[] = {
916 { PCI_VDEVICE(NI, 0x1310), BOARD_PCI6602 },
917 { PCI_VDEVICE(NI, 0x1360), BOARD_PXI6602 },
918 { PCI_VDEVICE(NI, 0x2c60), BOARD_PCI6601 },
919 { PCI_VDEVICE(NI, 0x2cc0), BOARD_PXI6608 },
920 { PCI_VDEVICE(NI, 0x1e30), BOARD_PCI6624 },
921 { PCI_VDEVICE(NI, 0x1e40), BOARD_PXI6624 },
924 MODULE_DEVICE_TABLE(pci, ni_660x_pci_table);
926 static struct pci_driver ni_660x_pci_driver = {
928 .id_table = ni_660x_pci_table,
929 .probe = ni_660x_pci_probe,
930 .remove = comedi_pci_auto_unconfig,
932 module_comedi_pci_driver(ni_660x_driver, ni_660x_pci_driver);
934 MODULE_AUTHOR("Comedi http://www.comedi.org");
935 MODULE_DESCRIPTION("Comedi driver for NI 660x counter/timer boards");
936 MODULE_LICENSE("GPL");