1 // SPDX-License-Identifier: GPL-2.0+
3 * comedi/drivers/daqboard2000.c
4 * hardware driver for IOtech DAQboard/2000
6 * COMEDI - Linux Control and Measurement Device Interface
7 * Copyright (C) 1999 Anders Blomdell <anders.blomdell@control.lth.se>
10 * Driver: daqboard2000
11 * Description: IOTech DAQBoard/2000
12 * Author: Anders Blomdell <anders.blomdell@control.lth.se>
14 * Updated: Mon, 14 Apr 2008 15:28:52 +0100
15 * Devices: [IOTech] DAQBoard/2000 (daqboard2000)
17 * Much of the functionality of this driver was determined from reading
18 * the source code for the Windows driver.
20 * The FPGA on the board requires firmware, which is available from
21 * https://www.comedi.org in the comedi_nonfree_firmware tarball.
23 * Configuration options: not applicable, uses PCI auto config
26 * This card was obviously never intended to leave the Windows world,
27 * since it lacked all kind of hardware documentation (except for cable
28 * pinouts, plug and pray has something to catch up with yet).
30 * With some help from our swedish distributor, we got the Windows sourcecode
31 * for the card, and here are the findings so far.
33 * 1. A good document that describes the PCI interface chip is 9080db-106.pdf
34 * available from http://www.plxtech.com/products/io/pci9080
36 * 2. The initialization done so far is:
37 * a. program the FPGA (windows code sans a lot of error messages)
40 * 3. Analog out seems to work OK with DAC's disabled, if DAC's are enabled,
41 * you have to output values to all enabled DAC's until result appears, I
42 * guess that it has something to do with pacer clocks, but the source
43 * gives me no clues. I'll keep it simple so far.
46 * Each channel in the scanlist seems to be controlled by four
50 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
51 * ! | | | ! | | | ! | | | ! | | | !
52 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
55 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
56 * ! | | | ! | | | ! | | | ! | | | !
57 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
59 * +------+------+ | | | | +-- Digital input (??)
60 * | | | | +---- 10 us settling time
61 * | | | +------ Suspend acquisition (last to scan)
62 * | | +-------- Simultaneous sample and hold
63 * | +---------- Signed data format
64 * +------------------------- Correction offset low
67 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
68 * ! | | | ! | | | ! | | | ! | | | !
69 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
71 * +-----+ +--+--+ +++ +++ +--+--+
72 * | | | | +----- Expansion channel
73 * | | | +----------- Expansion gain
74 * | | +--------------- Channel (low)
75 * | +--------------------- Correction offset high
76 * +----------------------------- Correction gain low
78 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
79 * ! | | | ! | | | ! | | | ! | | | !
80 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
82 * +------+------+ | | +-+-+ | | +-- Low bank enable
83 * | | | | | +---- High bank enable
84 * | | | | +------ Hi/low select
85 * | | | +---------- Gain (1,?,2,4,8,16,32,64)
86 * | | +-------------- differential/single ended
87 * | +---------------- Unipolar
88 * +------------------------- Correction gain high
90 * 999. The card seems to have an incredible amount of capabilities, but
91 * trying to reverse engineer them from the Windows source is beyond my
96 #include <linux/module.h>
97 #include <linux/delay.h>
98 #include <linux/interrupt.h>
100 #include "../comedi_pci.h"
105 #define DB2K_FIRMWARE "/*(DEBLOBBED)*/"
107 static const struct comedi_lrange db2k_ai_range = {
126 * Register Memory Map
128 #define DB2K_REG_ACQ_CONTROL 0x00 /* u16 (w) */
129 #define DB2K_REG_ACQ_STATUS 0x00 /* u16 (r) */
130 #define DB2K_REG_ACQ_SCAN_LIST_FIFO 0x02 /* u16 */
131 #define DB2K_REG_ACQ_PACER_CLOCK_DIV_LOW 0x04 /* u32 */
132 #define DB2K_REG_ACQ_SCAN_COUNTER 0x08 /* u16 */
133 #define DB2K_REG_ACQ_PACER_CLOCK_DIV_HIGH 0x0a /* u16 */
134 #define DB2K_REG_ACQ_TRIGGER_COUNT 0x0c /* u16 */
135 #define DB2K_REG_ACQ_RESULTS_FIFO 0x10 /* u16 */
136 #define DB2K_REG_ACQ_RESULTS_SHADOW 0x14 /* u16 */
137 #define DB2K_REG_ACQ_ADC_RESULT 0x18 /* u16 */
138 #define DB2K_REG_DAC_SCAN_COUNTER 0x1c /* u16 */
139 #define DB2K_REG_DAC_CONTROL 0x20 /* u16 (w) */
140 #define DB2K_REG_DAC_STATUS 0x20 /* u16 (r) */
141 #define DB2K_REG_DAC_FIFO 0x24 /* s16 */
142 #define DB2K_REG_DAC_PACER_CLOCK_DIV 0x2a /* u16 */
143 #define DB2K_REG_REF_DACS 0x2c /* u16 */
144 #define DB2K_REG_DIO_CONTROL 0x30 /* u16 */
145 #define DB2K_REG_P3_HSIO_DATA 0x32 /* s16 */
146 #define DB2K_REG_P3_CONTROL 0x34 /* u16 */
147 #define DB2K_REG_CAL_EEPROM_CONTROL 0x36 /* u16 */
148 #define DB2K_REG_DAC_SETTING(x) (0x38 + (x) * 2) /* s16 */
149 #define DB2K_REG_DIO_P2_EXP_IO_8_BIT 0x40 /* s16 */
150 #define DB2K_REG_COUNTER_TIMER_CONTROL 0x80 /* u16 */
151 #define DB2K_REG_COUNTER_INPUT(x) (0x88 + (x) * 2) /* s16 */
152 #define DB2K_REG_TIMER_DIV(x) (0xa0 + (x) * 2) /* u16 */
153 #define DB2K_REG_DMA_CONTROL 0xb0 /* u16 */
154 #define DB2K_REG_TRIG_CONTROL 0xb2 /* u16 */
155 #define DB2K_REG_CAL_EEPROM 0xb8 /* u16 */
156 #define DB2K_REG_ACQ_DIGITAL_MARK 0xba /* u16 */
157 #define DB2K_REG_TRIG_DACS 0xbc /* u16 */
158 #define DB2K_REG_DIO_P2_EXP_IO_16_BIT(x) (0xc0 + (x) * 2) /* s16 */
161 #define DB2K_REG_CPLD_STATUS 0x1000 /* u16 (r) */
162 #define DB2K_REG_CPLD_WDATA 0x1000 /* u16 (w) */
164 /* Scan Sequencer programming */
165 #define DB2K_ACQ_CONTROL_SEQ_START_SCAN_LIST 0x0011
166 #define DB2K_ACQ_CONTROL_SEQ_STOP_SCAN_LIST 0x0010
168 /* Prepare for acquisition */
169 #define DB2K_ACQ_CONTROL_RESET_SCAN_LIST_FIFO 0x0004
170 #define DB2K_ACQ_CONTROL_RESET_RESULTS_FIFO 0x0002
171 #define DB2K_ACQ_CONTROL_RESET_CONFIG_PIPE 0x0001
173 /* Pacer Clock Control */
174 #define DB2K_ACQ_CONTROL_ADC_PACER_INTERNAL 0x0030
175 #define DB2K_ACQ_CONTROL_ADC_PACER_EXTERNAL 0x0032
176 #define DB2K_ACQ_CONTROL_ADC_PACER_ENABLE 0x0031
177 #define DB2K_ACQ_CONTROL_ADC_PACER_ENABLE_DAC_PACER 0x0034
178 #define DB2K_ACQ_CONTROL_ADC_PACER_DISABLE 0x0030
179 #define DB2K_ACQ_CONTROL_ADC_PACER_NORMAL_MODE 0x0060
180 #define DB2K_ACQ_CONTROL_ADC_PACER_COMPATIBILITY_MODE 0x0061
181 #define DB2K_ACQ_CONTROL_ADC_PACER_INTERNAL_OUT_ENABLE 0x0008
182 #define DB2K_ACQ_CONTROL_ADC_PACER_EXTERNAL_RISING 0x0100
184 /* Acquisition status bits */
185 #define DB2K_ACQ_STATUS_RESULTS_FIFO_MORE_1_SAMPLE 0x0001
186 #define DB2K_ACQ_STATUS_RESULTS_FIFO_HAS_DATA 0x0002
187 #define DB2K_ACQ_STATUS_RESULTS_FIFO_OVERRUN 0x0004
188 #define DB2K_ACQ_STATUS_LOGIC_SCANNING 0x0008
189 #define DB2K_ACQ_STATUS_CONFIG_PIPE_FULL 0x0010
190 #define DB2K_ACQ_STATUS_SCAN_LIST_FIFO_EMPTY 0x0020
191 #define DB2K_ACQ_STATUS_ADC_NOT_READY 0x0040
192 #define DB2K_ACQ_STATUS_ARBITRATION_FAILURE 0x0080
193 #define DB2K_ACQ_STATUS_ADC_PACER_OVERRUN 0x0100
194 #define DB2K_ACQ_STATUS_DAC_PACER_OVERRUN 0x0200
197 #define DB2K_DAC_STATUS_DAC_FULL 0x0001
198 #define DB2K_DAC_STATUS_REF_BUSY 0x0002
199 #define DB2K_DAC_STATUS_TRIG_BUSY 0x0004
200 #define DB2K_DAC_STATUS_CAL_BUSY 0x0008
201 #define DB2K_DAC_STATUS_DAC_BUSY(x) (0x0010 << (x))
204 #define DB2K_DAC_CONTROL_ENABLE_BIT 0x0001
205 #define DB2K_DAC_CONTROL_DATA_IS_SIGNED 0x0002
206 #define DB2K_DAC_CONTROL_RESET_FIFO 0x0004
207 #define DB2K_DAC_CONTROL_DAC_DISABLE(x) (0x0020 + ((x) << 4))
208 #define DB2K_DAC_CONTROL_DAC_ENABLE(x) (0x0021 + ((x) << 4))
209 #define DB2K_DAC_CONTROL_PATTERN_DISABLE 0x0060
210 #define DB2K_DAC_CONTROL_PATTERN_ENABLE 0x0061
212 /* Trigger Control */
213 #define DB2K_TRIG_CONTROL_TYPE_ANALOG 0x0000
214 #define DB2K_TRIG_CONTROL_TYPE_TTL 0x0010
215 #define DB2K_TRIG_CONTROL_EDGE_HI_LO 0x0004
216 #define DB2K_TRIG_CONTROL_EDGE_LO_HI 0x0000
217 #define DB2K_TRIG_CONTROL_LEVEL_ABOVE 0x0000
218 #define DB2K_TRIG_CONTROL_LEVEL_BELOW 0x0004
219 #define DB2K_TRIG_CONTROL_SENSE_LEVEL 0x0002
220 #define DB2K_TRIG_CONTROL_SENSE_EDGE 0x0000
221 #define DB2K_TRIG_CONTROL_ENABLE 0x0001
222 #define DB2K_TRIG_CONTROL_DISABLE 0x0000
224 /* Reference Dac Selection */
225 #define DB2K_REF_DACS_SET 0x0080
226 #define DB2K_REF_DACS_SELECT_POS_REF 0x0100
227 #define DB2K_REF_DACS_SELECT_NEG_REF 0x0000
229 /* CPLD status bits */
230 #define DB2K_CPLD_STATUS_INIT 0x0002
231 #define DB2K_CPLD_STATUS_TXREADY 0x0004
232 #define DB2K_CPLD_VERSION_MASK 0xf000
233 /* "New CPLD" signature. */
234 #define DB2K_CPLD_VERSION_NEW 0x5000
241 struct db2k_boardtype {
243 unsigned int has_2_ao:1;/* false: 4 AO chans; true: 2 AO chans */
246 static const struct db2k_boardtype db2k_boardtypes[] = {
247 [BOARD_DAQBOARD2000] = {
248 .name = "daqboard2000",
251 [BOARD_DAQBOARD2001] = {
252 .name = "daqboard2001",
256 struct db2k_private {
260 static void db2k_write_acq_scan_list_entry(struct comedi_device *dev, u16 entry)
262 writew(entry & 0x00ff, dev->mmio + DB2K_REG_ACQ_SCAN_LIST_FIFO);
263 writew((entry >> 8) & 0x00ff,
264 dev->mmio + DB2K_REG_ACQ_SCAN_LIST_FIFO);
267 static void db2k_setup_sampling(struct comedi_device *dev, int chan, int gain)
269 u16 word0, word1, word2, word3;
271 /* Channel 0-7 diff, channel 8-23 single ended */
273 word1 = 0x0004; /* Last scan */
274 word2 = (chan << 6) & 0x00c0;
298 /* These should be read from EEPROM */
299 word2 |= 0x0800; /* offset */
300 word3 |= 0xc000; /* gain */
301 db2k_write_acq_scan_list_entry(dev, word0);
302 db2k_write_acq_scan_list_entry(dev, word1);
303 db2k_write_acq_scan_list_entry(dev, word2);
304 db2k_write_acq_scan_list_entry(dev, word3);
307 static int db2k_ai_status(struct comedi_device *dev, struct comedi_subdevice *s,
308 struct comedi_insn *insn, unsigned long context)
312 status = readw(dev->mmio + DB2K_REG_ACQ_STATUS);
313 if (status & context)
318 static int db2k_ai_insn_read(struct comedi_device *dev,
319 struct comedi_subdevice *s,
320 struct comedi_insn *insn, unsigned int *data)
326 writew(DB2K_ACQ_CONTROL_RESET_SCAN_LIST_FIFO |
327 DB2K_ACQ_CONTROL_RESET_RESULTS_FIFO |
328 DB2K_ACQ_CONTROL_RESET_CONFIG_PIPE,
329 dev->mmio + DB2K_REG_ACQ_CONTROL);
332 * If pacer clock is not set to some high value (> 10 us), we
333 * risk multiple samples to be put into the result FIFO.
335 /* 1 second, should be long enough */
336 writel(1000000, dev->mmio + DB2K_REG_ACQ_PACER_CLOCK_DIV_LOW);
337 writew(0, dev->mmio + DB2K_REG_ACQ_PACER_CLOCK_DIV_HIGH);
339 gain = CR_RANGE(insn->chanspec);
340 chan = CR_CHAN(insn->chanspec);
343 * This doesn't look efficient. I decided to take the conservative
344 * approach when I did the insn conversion. Perhaps it would be
345 * better to have broken it completely, then someone would have been
346 * forced to fix it. --ds
348 for (i = 0; i < insn->n; i++) {
349 db2k_setup_sampling(dev, chan, gain);
350 /* Enable reading from the scanlist FIFO */
351 writew(DB2K_ACQ_CONTROL_SEQ_START_SCAN_LIST,
352 dev->mmio + DB2K_REG_ACQ_CONTROL);
354 ret = comedi_timeout(dev, s, insn, db2k_ai_status,
355 DB2K_ACQ_STATUS_CONFIG_PIPE_FULL);
359 writew(DB2K_ACQ_CONTROL_ADC_PACER_ENABLE,
360 dev->mmio + DB2K_REG_ACQ_CONTROL);
362 ret = comedi_timeout(dev, s, insn, db2k_ai_status,
363 DB2K_ACQ_STATUS_LOGIC_SCANNING);
368 comedi_timeout(dev, s, insn, db2k_ai_status,
369 DB2K_ACQ_STATUS_RESULTS_FIFO_HAS_DATA);
373 data[i] = readw(dev->mmio + DB2K_REG_ACQ_RESULTS_FIFO);
374 writew(DB2K_ACQ_CONTROL_ADC_PACER_DISABLE,
375 dev->mmio + DB2K_REG_ACQ_CONTROL);
376 writew(DB2K_ACQ_CONTROL_SEQ_STOP_SCAN_LIST,
377 dev->mmio + DB2K_REG_ACQ_CONTROL);
383 static int db2k_ao_eoc(struct comedi_device *dev, struct comedi_subdevice *s,
384 struct comedi_insn *insn, unsigned long context)
386 unsigned int chan = CR_CHAN(insn->chanspec);
389 status = readw(dev->mmio + DB2K_REG_DAC_STATUS);
390 if ((status & DB2K_DAC_STATUS_DAC_BUSY(chan)) == 0)
395 static int db2k_ao_insn_write(struct comedi_device *dev,
396 struct comedi_subdevice *s,
397 struct comedi_insn *insn, unsigned int *data)
399 unsigned int chan = CR_CHAN(insn->chanspec);
402 for (i = 0; i < insn->n; i++) {
403 unsigned int val = data[i];
406 writew(val, dev->mmio + DB2K_REG_DAC_SETTING(chan));
408 ret = comedi_timeout(dev, s, insn, db2k_ao_eoc, 0);
412 s->readback[chan] = val;
418 static void db2k_reset_local_bus(struct comedi_device *dev)
420 struct db2k_private *devpriv = dev->private;
423 cntrl = readl(devpriv->plx + PLX_REG_CNTRL);
424 cntrl |= PLX_CNTRL_RESET;
425 writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
427 cntrl &= ~PLX_CNTRL_RESET;
428 writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
432 static void db2k_reload_plx(struct comedi_device *dev)
434 struct db2k_private *devpriv = dev->private;
437 cntrl = readl(devpriv->plx + PLX_REG_CNTRL);
438 cntrl &= ~PLX_CNTRL_EERELOAD;
439 writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
441 cntrl |= PLX_CNTRL_EERELOAD;
442 writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
444 cntrl &= ~PLX_CNTRL_EERELOAD;
445 writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
449 static void db2k_pulse_prog_pin(struct comedi_device *dev)
451 struct db2k_private *devpriv = dev->private;
454 cntrl = readl(devpriv->plx + PLX_REG_CNTRL);
455 cntrl |= PLX_CNTRL_USERO;
456 writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
458 cntrl &= ~PLX_CNTRL_USERO;
459 writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
460 mdelay(10); /* Not in the original code, but I like symmetry... */
463 static int db2k_wait_cpld_init(struct comedi_device *dev)
465 int result = -ETIMEDOUT;
469 /* timeout after 50 tries -> 5ms */
470 for (i = 0; i < 50; i++) {
471 cpld = readw(dev->mmio + DB2K_REG_CPLD_STATUS);
472 if (cpld & DB2K_CPLD_STATUS_INIT) {
476 usleep_range(100, 1000);
482 static int db2k_wait_cpld_txready(struct comedi_device *dev)
486 for (i = 0; i < 100; i++) {
487 if (readw(dev->mmio + DB2K_REG_CPLD_STATUS) &
488 DB2K_CPLD_STATUS_TXREADY) {
496 static int db2k_write_cpld(struct comedi_device *dev, u16 data, bool new_cpld)
501 result = db2k_wait_cpld_txready(dev);
505 usleep_range(10, 20);
507 writew(data, dev->mmio + DB2K_REG_CPLD_WDATA);
508 if (!(readw(dev->mmio + DB2K_REG_CPLD_STATUS) & DB2K_CPLD_STATUS_INIT))
514 static int db2k_wait_fpga_programmed(struct comedi_device *dev)
516 struct db2k_private *devpriv = dev->private;
519 /* Time out after 200 tries -> 20ms */
520 for (i = 0; i < 200; i++) {
521 u32 cntrl = readl(devpriv->plx + PLX_REG_CNTRL);
522 /* General Purpose Input (USERI) set on FPGA "DONE". */
523 if (cntrl & PLX_CNTRL_USERI)
526 usleep_range(100, 1000);
531 static int db2k_load_firmware(struct comedi_device *dev, const u8 *cpld_array,
532 size_t len, unsigned long context)
534 struct db2k_private *devpriv = dev->private;
541 /* Look for FPGA start sequence in firmware. */
542 for (i = 0; i + 1 < len; i++) {
543 if (cpld_array[i] == 0xff && cpld_array[i + 1] == 0x20)
547 dev_err(dev->class_dev, "bad firmware - no start sequence\n");
550 /* Check length is even. */
552 dev_err(dev->class_dev,
553 "bad firmware - odd length (%zu = %zu - %zu)\n",
557 /* Strip firmware header. */
561 /* Check to make sure the serial eeprom is present on the board */
562 cntrl = readl(devpriv->plx + PLX_REG_CNTRL);
563 if (!(cntrl & PLX_CNTRL_EEPRESENT))
566 for (retry = 0; retry < 3; retry++) {
567 db2k_reset_local_bus(dev);
568 db2k_reload_plx(dev);
569 db2k_pulse_prog_pin(dev);
570 result = db2k_wait_cpld_init(dev);
574 new_cpld = (readw(dev->mmio + DB2K_REG_CPLD_STATUS) &
575 DB2K_CPLD_VERSION_MASK) == DB2K_CPLD_VERSION_NEW;
576 for (; i < len; i += 2) {
577 u16 data = (cpld_array[i] << 8) + cpld_array[i + 1];
579 result = db2k_write_cpld(dev, data, new_cpld);
584 result = db2k_wait_fpga_programmed(dev);
586 db2k_reset_local_bus(dev);
587 db2k_reload_plx(dev);
594 static void db2k_adc_stop_dma_transfer(struct comedi_device *dev)
598 static void db2k_adc_disarm(struct comedi_device *dev)
600 /* Disable hardware triggers */
602 writew(DB2K_TRIG_CONTROL_TYPE_ANALOG | DB2K_TRIG_CONTROL_DISABLE,
603 dev->mmio + DB2K_REG_TRIG_CONTROL);
605 writew(DB2K_TRIG_CONTROL_TYPE_TTL | DB2K_TRIG_CONTROL_DISABLE,
606 dev->mmio + DB2K_REG_TRIG_CONTROL);
608 /* Stop the scan list FIFO from loading the configuration pipe */
610 writew(DB2K_ACQ_CONTROL_SEQ_STOP_SCAN_LIST,
611 dev->mmio + DB2K_REG_ACQ_CONTROL);
613 /* Stop the pacer clock */
615 writew(DB2K_ACQ_CONTROL_ADC_PACER_DISABLE,
616 dev->mmio + DB2K_REG_ACQ_CONTROL);
618 /* Stop the input dma (abort channel 1) */
619 db2k_adc_stop_dma_transfer(dev);
622 static void db2k_activate_reference_dacs(struct comedi_device *dev)
627 /* Set the + reference dac value in the FPGA */
628 writew(DB2K_REF_DACS_SET | DB2K_REF_DACS_SELECT_POS_REF,
629 dev->mmio + DB2K_REG_REF_DACS);
630 for (timeout = 0; timeout < 20; timeout++) {
631 val = readw(dev->mmio + DB2K_REG_DAC_STATUS);
632 if ((val & DB2K_DAC_STATUS_REF_BUSY) == 0)
637 /* Set the - reference dac value in the FPGA */
638 writew(DB2K_REF_DACS_SET | DB2K_REF_DACS_SELECT_NEG_REF,
639 dev->mmio + DB2K_REG_REF_DACS);
640 for (timeout = 0; timeout < 20; timeout++) {
641 val = readw(dev->mmio + DB2K_REG_DAC_STATUS);
642 if ((val & DB2K_DAC_STATUS_REF_BUSY) == 0)
648 static void db2k_initialize_ctrs(struct comedi_device *dev)
652 static void db2k_initialize_tmrs(struct comedi_device *dev)
656 static void db2k_dac_disarm(struct comedi_device *dev)
660 static void db2k_initialize_adc(struct comedi_device *dev)
662 db2k_adc_disarm(dev);
663 db2k_activate_reference_dacs(dev);
664 db2k_initialize_ctrs(dev);
665 db2k_initialize_tmrs(dev);
668 static int db2k_8255_cb(struct comedi_device *dev, int dir, int port, int data,
669 unsigned long iobase)
672 writew(data, dev->mmio + iobase + port * 2);
675 return readw(dev->mmio + iobase + port * 2);
678 static int db2k_auto_attach(struct comedi_device *dev, unsigned long context)
680 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
681 const struct db2k_boardtype *board;
682 struct db2k_private *devpriv;
683 struct comedi_subdevice *s;
686 if (context >= ARRAY_SIZE(db2k_boardtypes))
688 board = &db2k_boardtypes[context];
691 dev->board_ptr = board;
692 dev->board_name = board->name;
694 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
698 result = comedi_pci_enable(dev);
702 devpriv->plx = pci_ioremap_bar(pcidev, 0);
703 dev->mmio = pci_ioremap_bar(pcidev, 2);
704 if (!devpriv->plx || !dev->mmio)
707 result = comedi_alloc_subdevices(dev, 3);
711 result = comedi_load_firmware(dev, &comedi_to_pci_dev(dev)->dev,
712 DB2K_FIRMWARE, db2k_load_firmware, 0);
716 db2k_initialize_adc(dev);
717 db2k_dac_disarm(dev);
719 s = &dev->subdevices[0];
721 s->type = COMEDI_SUBD_AI;
722 s->subdev_flags = SDF_READABLE | SDF_GROUND;
725 s->insn_read = db2k_ai_insn_read;
726 s->range_table = &db2k_ai_range;
728 s = &dev->subdevices[1];
730 s->type = COMEDI_SUBD_AO;
731 s->subdev_flags = SDF_WRITABLE;
732 s->n_chan = board->has_2_ao ? 2 : 4;
734 s->insn_write = db2k_ao_insn_write;
735 s->range_table = &range_bipolar10;
737 result = comedi_alloc_subdev_readback(s);
741 s = &dev->subdevices[2];
742 return subdev_8255_init(dev, s, db2k_8255_cb,
743 DB2K_REG_DIO_P2_EXP_IO_8_BIT);
746 static void db2k_detach(struct comedi_device *dev)
748 struct db2k_private *devpriv = dev->private;
750 if (devpriv && devpriv->plx)
751 iounmap(devpriv->plx);
752 comedi_pci_detach(dev);
755 static struct comedi_driver db2k_driver = {
756 .driver_name = "daqboard2000",
757 .module = THIS_MODULE,
758 .auto_attach = db2k_auto_attach,
759 .detach = db2k_detach,
762 static int db2k_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
764 return comedi_pci_auto_config(dev, &db2k_driver, id->driver_data);
767 static const struct pci_device_id db2k_pci_table[] = {
768 { PCI_DEVICE_SUB(PCI_VENDOR_ID_IOTECH, 0x0409, PCI_VENDOR_ID_IOTECH,
769 0x0002), .driver_data = BOARD_DAQBOARD2000, },
770 { PCI_DEVICE_SUB(PCI_VENDOR_ID_IOTECH, 0x0409, PCI_VENDOR_ID_IOTECH,
771 0x0004), .driver_data = BOARD_DAQBOARD2001, },
774 MODULE_DEVICE_TABLE(pci, db2k_pci_table);
776 static struct pci_driver db2k_pci_driver = {
777 .name = "daqboard2000",
778 .id_table = db2k_pci_table,
779 .probe = db2k_pci_probe,
780 .remove = comedi_pci_auto_unconfig,
782 module_comedi_pci_driver(db2k_driver, db2k_pci_driver);
784 MODULE_AUTHOR("Comedi https://www.comedi.org");
785 MODULE_DESCRIPTION("Comedi low-level driver");
786 MODULE_LICENSE("GPL");