2 * comedi/drivers/cb_pcidas64.c
3 * This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
4 * 64xx, 60xx, and 4020 cards.
6 * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
7 * Copyright (C) 2001, 2002 Frank Mori Hess
9 * Thanks also go to the following people:
11 * Steve Rosenbluth, for providing the source code for
12 * his pci-das6402 driver, and source code for working QNX pci-6402
13 * drivers by Greg Laird and Mariusz Bogacz. None of the code was
14 * used directly here, but it was useful as an additional source of
15 * documentation on how to program the boards.
17 * John Sims, for much testing and feedback on pcidas-4020 support.
19 * COMEDI - Linux Control and Measurement Device Interface
20 * Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License as published by
24 * the Free Software Foundation; either version 2 of the License, or
25 * (at your option) any later version.
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU General Public License for more details.
35 * Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series
36 * with the PLX 9080 PCI controller
37 * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
39 * Updated: Fri, 02 Nov 2012 18:58:55 +0000
40 * Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
41 * PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
42 * PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
43 * PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
44 * PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
45 * PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
46 * PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
47 * PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
48 * PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
50 * Configuration options:
53 * Manual attachment of PCI cards with the comedi_config utility is not
54 * supported by this driver; they are attached automatically.
56 * These boards may be autocalibrated with the comedi_calibrate utility.
58 * To select the bnc trigger input on the 4020 (instead of the dio input),
59 * specify a nonzero channel in the chanspec. If you wish to use an external
60 * master clock on the 4020, you may do so by setting the scan_begin_src
61 * to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
62 * to configure the divisor to use for the external clock.
64 * Some devices are not identified because the PCI device IDs are not yet
65 * known. If you have such a board, please let the maintainers know.
70 * make it return error if user attempts an ai command that uses the
71 * external queue, and an ao command simultaneously user counter subdevice
72 * there are a number of boards this driver will support when they are
73 * fully released, but does not yet since the pci device id numbers
74 * are not yet available.
76 * support prescaled 100khz clock for slow pacing (not available on 6000
79 * make ao fifo size adjustable like ai fifo
82 #include <linux/module.h>
83 #include <linux/delay.h>
84 #include <linux/interrupt.h>
86 #include "../comedi_pci.h"
91 #define TIMER_BASE 25 /* 40MHz master clock */
93 * 100kHz 'prescaled' clock for slow acquisition,
94 * maybe I'll support this someday
96 #define PRESCALED_TIMER_BASE 10000
97 #define DMA_BUFFER_SIZE 0x1000
98 #define DAC_FIFO_SIZE 0x2000
100 /* maximum value that can be loaded into board's 24-bit counters */
101 static const int max_counter_value = 0xffffff;
103 /* PCI-DAS64xxx base addresses */
105 /* devpriv->main_iobase registers */
106 enum write_only_registers {
107 INTR_ENABLE_REG = 0x0, /* interrupt enable register */
108 HW_CONFIG_REG = 0x2, /* hardware config register */
110 DAQ_ATRIG_LOW_4020_REG = 0xc,
111 ADC_CONTROL0_REG = 0x10, /* adc control register 0 */
112 ADC_CONTROL1_REG = 0x12, /* adc control register 1 */
113 CALIBRATION_REG = 0x14,
114 /* lower 16 bits of adc sample interval counter */
115 ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16,
116 /* upper 8 bits of adc sample interval counter */
117 ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18,
118 /* lower 16 bits of delay interval counter */
119 ADC_DELAY_INTERVAL_LOWER_REG = 0x1a,
120 /* upper 8 bits of delay interval counter */
121 ADC_DELAY_INTERVAL_UPPER_REG = 0x1c,
122 /* lower 16 bits of hardware conversion/scan counter */
123 ADC_COUNT_LOWER_REG = 0x1e,
124 /* upper 8 bits of hardware conversion/scan counter */
125 ADC_COUNT_UPPER_REG = 0x20,
126 ADC_START_REG = 0x22, /* software trigger to start acquisition */
127 ADC_CONVERT_REG = 0x24, /* initiates single conversion */
128 ADC_QUEUE_CLEAR_REG = 0x26, /* clears adc queue */
129 ADC_QUEUE_LOAD_REG = 0x28, /* loads adc queue */
130 ADC_BUFFER_CLEAR_REG = 0x2a,
131 /* high channel for internal queue, use adc_chan_bits() inline above */
132 ADC_QUEUE_HIGH_REG = 0x2c,
133 DAC_CONTROL0_REG = 0x50, /* dac control register 0 */
134 DAC_CONTROL1_REG = 0x52, /* dac control register 0 */
135 /* lower 16 bits of dac sample interval counter */
136 DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54,
137 /* upper 8 bits of dac sample interval counter */
138 DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56,
139 DAC_SELECT_REG = 0x60,
140 DAC_START_REG = 0x64,
141 DAC_BUFFER_CLEAR_REG = 0x66, /* clear dac buffer */
144 static inline unsigned int dac_convert_reg(unsigned int channel)
146 return 0x70 + (2 * (channel & 0x1));
149 static inline unsigned int dac_lsb_4020_reg(unsigned int channel)
151 return 0x70 + (4 * (channel & 0x1));
154 static inline unsigned int dac_msb_4020_reg(unsigned int channel)
156 return 0x72 + (4 * (channel & 0x1));
159 enum read_only_registers {
161 * hardware status register,
162 * reading this apparently clears pending interrupts as well
165 PIPE1_READ_REG = 0x4,
166 ADC_READ_PNTR_REG = 0x8,
167 LOWER_XFER_REG = 0x10,
168 ADC_WRITE_PNTR_REG = 0xc,
172 enum read_write_registers {
173 I8255_4020_REG = 0x48, /* 8255 offset, for 4020 only */
174 /* external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */
175 ADC_QUEUE_FIFO_REG = 0x100,
176 ADC_FIFO_REG = 0x200, /* adc data fifo */
177 /* dac data fifo, has weird interactions with external channel queue */
178 DAC_FIFO_REG = 0x300,
181 /* dev->mmio registers */
182 enum dio_counter_registers {
183 DIO_8255_OFFSET = 0x0,
186 DIO_DIRECTION_60XX_REG = 0x40,
187 DIO_DATA_60XX_REG = 0x48,
190 /* bit definitions for write-only registers */
192 enum intr_enable_contents {
193 ADC_INTR_SRC_MASK = 0x3, /* adc interrupt source mask */
194 ADC_INTR_QFULL_BITS = 0x0, /* interrupt fifo quarter full */
195 ADC_INTR_EOC_BITS = 0x1, /* interrupt end of conversion */
196 ADC_INTR_EOSCAN_BITS = 0x2, /* interrupt end of scan */
197 ADC_INTR_EOSEQ_BITS = 0x3, /* interrupt end of sequence mask */
198 EN_ADC_INTR_SRC_BIT = 0x4, /* enable adc interrupt source */
199 EN_ADC_DONE_INTR_BIT = 0x8, /* enable adc acquisition done intr */
200 DAC_INTR_SRC_MASK = 0x30,
201 DAC_INTR_QEMPTY_BITS = 0x0,
202 DAC_INTR_HIGH_CHAN_BITS = 0x10,
203 EN_DAC_INTR_SRC_BIT = 0x40, /* enable dac interrupt source */
204 EN_DAC_DONE_INTR_BIT = 0x80,
205 EN_ADC_ACTIVE_INTR_BIT = 0x200, /* enable adc active interrupt */
206 EN_ADC_STOP_INTR_BIT = 0x400, /* enable adc stop trigger interrupt */
207 EN_DAC_ACTIVE_INTR_BIT = 0x800, /* enable dac active interrupt */
208 EN_DAC_UNDERRUN_BIT = 0x4000, /* enable dac underrun status bit */
209 EN_ADC_OVERRUN_BIT = 0x8000, /* enable adc overrun status bit */
212 enum hw_config_contents {
213 MASTER_CLOCK_4020_MASK = 0x3, /* master clock source mask for 4020 */
214 INTERNAL_CLOCK_4020_BITS = 0x1, /* use 40 MHz internal master clock */
215 BNC_CLOCK_4020_BITS = 0x2, /* use BNC input for master clock */
216 EXT_CLOCK_4020_BITS = 0x3, /* use dio input for master clock */
217 EXT_QUEUE_BIT = 0x200, /* use external channel/gain queue */
218 /* use 225 nanosec strobe when loading dac instead of 50 nanosec */
219 SLOW_DAC_BIT = 0x400,
221 * bit with unknown function yet given as default value in pci-das64
224 HW_CONFIG_DUMMY_BITS = 0x2000,
225 /* bit selects channels 1/0 for analog input/output, otherwise 0/1 */
226 DMA_CH_SELECT_BIT = 0x8000,
227 FIFO_SIZE_REG = 0x4, /* allows adjustment of fifo sizes */
228 DAC_FIFO_SIZE_MASK = 0xff00, /* bits that set dac fifo size */
229 DAC_FIFO_BITS = 0xf800, /* 8k sample ao fifo */
232 enum daq_atrig_low_4020_contents {
233 /* use trig/ext clk bnc input for analog gate signal */
234 EXT_AGATE_BNC_BIT = 0x8000,
235 /* use trig/ext clk bnc input for external stop trigger signal */
236 EXT_STOP_TRIG_BNC_BIT = 0x4000,
237 /* use trig/ext clk bnc input for external start trigger signal */
238 EXT_START_TRIG_BNC_BIT = 0x2000,
241 static inline u16 analog_trig_low_threshold_bits(u16 threshold)
243 return threshold & 0xfff;
246 enum adc_control0_contents {
247 ADC_GATE_SRC_MASK = 0x3, /* bits that select gate */
248 ADC_SOFT_GATE_BITS = 0x1, /* software gate */
249 ADC_EXT_GATE_BITS = 0x2, /* external digital gate */
250 ADC_ANALOG_GATE_BITS = 0x3, /* analog level gate */
251 /* level-sensitive gate (for digital) */
252 ADC_GATE_LEVEL_BIT = 0x4,
253 ADC_GATE_POLARITY_BIT = 0x8, /* gate active low */
254 ADC_START_TRIG_SOFT_BITS = 0x10,
255 ADC_START_TRIG_EXT_BITS = 0x20,
256 ADC_START_TRIG_ANALOG_BITS = 0x30,
257 ADC_START_TRIG_MASK = 0x30,
258 ADC_START_TRIG_FALLING_BIT = 0x40, /* trig 1 uses falling edge */
259 /* external pacing uses falling edge */
260 ADC_EXT_CONV_FALLING_BIT = 0x800,
261 /* enable hardware scan counter */
262 ADC_SAMPLE_COUNTER_EN_BIT = 0x1000,
263 ADC_DMA_DISABLE_BIT = 0x4000, /* disables dma */
264 ADC_ENABLE_BIT = 0x8000, /* master adc enable */
267 enum adc_control1_contents {
268 /* should be set for boards with > 16 channels */
269 ADC_QUEUE_CONFIG_BIT = 0x1,
270 CONVERT_POLARITY_BIT = 0x10,
271 EOC_POLARITY_BIT = 0x20,
272 ADC_SW_GATE_BIT = 0x40, /* software gate of adc */
273 ADC_DITHER_BIT = 0x200, /* turn on extra noise for dithering */
274 RETRIGGER_BIT = 0x800,
275 ADC_LO_CHANNEL_4020_MASK = 0x300,
276 ADC_HI_CHANNEL_4020_MASK = 0xc00,
277 TWO_CHANNEL_4020_BITS = 0x1000, /* two channel mode for 4020 */
278 FOUR_CHANNEL_4020_BITS = 0x2000, /* four channel mode for 4020 */
279 CHANNEL_MODE_4020_MASK = 0x3000,
280 ADC_MODE_MASK = 0xf000,
283 static inline u16 adc_lo_chan_4020_bits(unsigned int channel)
285 return (channel & 0x3) << 8;
288 static inline u16 adc_hi_chan_4020_bits(unsigned int channel)
290 return (channel & 0x3) << 10;
293 static inline u16 adc_mode_bits(unsigned int mode)
295 return (mode & 0xf) << 12;
298 enum calibration_contents {
299 SELECT_8800_BIT = 0x1,
300 SELECT_8402_64XX_BIT = 0x2,
301 SELECT_1590_60XX_BIT = 0x2,
302 CAL_EN_64XX_BIT = 0x40, /* calibration enable for 64xx series */
303 SERIAL_DATA_IN_BIT = 0x80,
304 SERIAL_CLOCK_BIT = 0x100,
305 CAL_EN_60XX_BIT = 0x200, /* calibration enable for 60xx series */
306 CAL_GAIN_BIT = 0x800,
310 * calibration sources for 6025 are:
321 static inline u16 adc_src_bits(unsigned int source)
323 return (source & 0xf) << 3;
326 static inline u16 adc_convert_chan_4020_bits(unsigned int channel)
328 return (channel & 0x3) << 8;
331 enum adc_queue_load_contents {
332 UNIP_BIT = 0x800, /* unipolar/bipolar bit */
333 ADC_SE_DIFF_BIT = 0x1000, /* single-ended/ differential bit */
334 /* non-referenced single-ended (common-mode input) */
335 ADC_COMMON_BIT = 0x2000,
336 QUEUE_EOSEQ_BIT = 0x4000, /* queue end of sequence */
337 QUEUE_EOSCAN_BIT = 0x8000, /* queue end of scan */
340 static inline u16 adc_chan_bits(unsigned int channel)
342 return channel & 0x3f;
345 enum dac_control0_contents {
346 DAC_ENABLE_BIT = 0x8000, /* dac controller enable bit */
347 DAC_CYCLIC_STOP_BIT = 0x4000,
348 DAC_WAVEFORM_MODE_BIT = 0x100,
349 DAC_EXT_UPDATE_FALLING_BIT = 0x80,
350 DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
351 WAVEFORM_TRIG_MASK = 0x30,
352 WAVEFORM_TRIG_DISABLED_BITS = 0x0,
353 WAVEFORM_TRIG_SOFT_BITS = 0x10,
354 WAVEFORM_TRIG_EXT_BITS = 0x20,
355 WAVEFORM_TRIG_ADC1_BITS = 0x30,
356 WAVEFORM_TRIG_FALLING_BIT = 0x8,
357 WAVEFORM_GATE_LEVEL_BIT = 0x4,
358 WAVEFORM_GATE_ENABLE_BIT = 0x2,
359 WAVEFORM_GATE_SELECT_BIT = 0x1,
362 enum dac_control1_contents {
363 DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */
364 DAC1_EXT_REF_BIT = 0x200,
365 DAC0_EXT_REF_BIT = 0x100,
366 DAC_OUTPUT_ENABLE_BIT = 0x80, /* dac output enable bit */
367 DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */
368 DAC_SW_GATE_BIT = 0x20,
369 DAC1_UNIPOLAR_BIT = 0x8,
370 DAC0_UNIPOLAR_BIT = 0x2,
373 /* bit definitions for read-only registers */
374 enum hw_status_contents {
375 DAC_UNDERRUN_BIT = 0x1,
376 ADC_OVERRUN_BIT = 0x2,
377 DAC_ACTIVE_BIT = 0x4,
378 ADC_ACTIVE_BIT = 0x8,
379 DAC_INTR_PENDING_BIT = 0x10,
380 ADC_INTR_PENDING_BIT = 0x20,
383 EXT_INTR_PENDING_BIT = 0x100,
384 ADC_STOP_BIT = 0x200,
387 static inline u16 pipe_full_bits(u16 hw_status_bits)
389 return (hw_status_bits >> 10) & 0x3;
392 static inline unsigned int dma_chain_flag_bits(u16 prepost_bits)
394 return (prepost_bits >> 6) & 0x3;
397 static inline unsigned int adc_upper_read_ptr_code(u16 prepost_bits)
399 return (prepost_bits >> 12) & 0x3;
402 static inline unsigned int adc_upper_write_ptr_code(u16 prepost_bits)
404 return (prepost_bits >> 14) & 0x3;
407 /* I2C addresses for 4020 */
409 RANGE_CAL_I2C_ADDR = 0x20,
410 CALDAC0_I2C_ADDR = 0xc,
411 CALDAC1_I2C_ADDR = 0xd,
414 enum range_cal_i2c_contents {
415 /* bits that set what source the adc converter measures */
416 ADC_SRC_4020_MASK = 0x70,
417 /* make bnc trig/ext clock threshold 0V instead of 2.5V */
418 BNC_TRIG_THRESHOLD_0V_BIT = 0x80,
421 static inline u8 adc_src_4020_bits(unsigned int source)
423 return (source << 4) & ADC_SRC_4020_MASK;
426 static inline u8 attenuate_bit(unsigned int channel)
428 /* attenuate channel (+-5V input range) */
429 return 1 << (channel & 0x3);
432 /* analog input ranges for 64xx boards */
433 static const struct comedi_lrange ai_ranges_64xx = {
446 static const u8 ai_range_code_64xx[8] = {
447 0x0, 0x1, 0x2, 0x3, /* bipolar 10, 5, 2,5, 1.25 */
448 0x8, 0x9, 0xa, 0xb /* unipolar 10, 5, 2.5, 1.25 */
451 /* analog input ranges for 64-Mx boards */
452 static const struct comedi_lrange ai_ranges_64_mx = {
464 static const u8 ai_range_code_64_mx[7] = {
465 0x0, 0x1, 0x2, 0x3, /* bipolar 5, 2.5, 1.25, 0.625 */
466 0x9, 0xa, 0xb /* unipolar 5, 2.5, 1.25 */
469 /* analog input ranges for 60xx boards */
470 static const struct comedi_lrange ai_ranges_60xx = {
479 static const u8 ai_range_code_60xx[4] = {
480 0x0, 0x1, 0x4, 0x7 /* bipolar 10, 5, 0.5, 0.05 */
483 /* analog input ranges for 6030, etc boards */
484 static const struct comedi_lrange ai_ranges_6030 = {
503 static const u8 ai_range_code_6030[14] = {
504 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, /* bip 10, 5, 2, 1, 0.5, 0.2, 0.1 */
505 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf /* uni 10, 5, 2, 1, 0.5, 0.2, 0.1 */
508 /* analog input ranges for 6052, etc boards */
509 static const struct comedi_lrange ai_ranges_6052 = {
529 static const u8 ai_range_code_6052[15] = {
530 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, /* bipolar 10 ... 0.05 */
531 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf /* unipolar 10 ... 0.1 */
534 /* analog input ranges for 4020 board */
535 static const struct comedi_lrange ai_ranges_4020 = {
542 /* analog output ranges */
543 static const struct comedi_lrange ao_ranges_64xx = {
552 static const int ao_range_code_64xx[] = {
559 static const int ao_range_code_60xx[] = {
563 static const struct comedi_lrange ao_ranges_6030 = {
570 static const int ao_range_code_6030[] = {
575 static const struct comedi_lrange ao_ranges_4020 = {
582 static const int ao_range_code_4020[] = {
587 enum register_layout {
593 struct hw_fifo_info {
594 unsigned int num_segments;
595 unsigned int max_segment_length;
596 unsigned int sample_packing_ratio;
597 u16 fifo_size_reg_mask;
600 enum pcidas64_boardid {
603 BOARD_PCIDAS64_M1_16,
604 BOARD_PCIDAS64_M2_16,
605 BOARD_PCIDAS64_M3_16,
622 BOARD_PCIDAS6402_16_JR,
623 BOARD_PCIDAS64_M1_16_JR,
624 BOARD_PCIDAS64_M2_16_JR,
625 BOARD_PCIDAS64_M3_16_JR,
626 BOARD_PCIDAS64_M1_14,
627 BOARD_PCIDAS64_M2_14,
628 BOARD_PCIDAS64_M3_14,
631 struct pcidas64_board {
633 int ai_se_chans; /* number of ai inputs in single-ended mode */
634 int ai_bits; /* analog input resolution */
635 int ai_speed; /* fastest conversion period in ns */
636 const struct comedi_lrange *ai_range_table;
637 const u8 *ai_range_code;
638 int ao_nchan; /* number of analog out channels */
639 int ao_bits; /* analog output resolution */
640 int ao_scan_speed; /* analog output scan speed */
641 const struct comedi_lrange *ao_range_table;
642 const int *ao_range_code;
643 const struct hw_fifo_info *const ai_fifo;
644 /* different board families have slightly different registers */
645 enum register_layout layout;
649 static const struct hw_fifo_info ai_fifo_4020 = {
651 .max_segment_length = 0x8000,
652 .sample_packing_ratio = 2,
653 .fifo_size_reg_mask = 0x7f,
656 static const struct hw_fifo_info ai_fifo_64xx = {
658 .max_segment_length = 0x800,
659 .sample_packing_ratio = 1,
660 .fifo_size_reg_mask = 0x3f,
663 static const struct hw_fifo_info ai_fifo_60xx = {
665 .max_segment_length = 0x800,
666 .sample_packing_ratio = 1,
667 .fifo_size_reg_mask = 0x7f,
671 * maximum number of dma transfers we will chain together into a ring
672 * (and the maximum number of dma buffers we maintain)
674 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
675 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
676 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
677 static inline unsigned int ai_dma_ring_count(const struct pcidas64_board *board)
679 if (board->layout == LAYOUT_4020)
680 return MAX_AI_DMA_RING_COUNT;
682 return MIN_AI_DMA_RING_COUNT;
685 static const int bytes_in_sample = 2;
687 static const struct pcidas64_board pcidas64_boards[] = {
688 [BOARD_PCIDAS6402_16] = {
689 .name = "pci-das6402/16",
695 .ao_scan_speed = 10000,
696 .layout = LAYOUT_64XX,
697 .ai_range_table = &ai_ranges_64xx,
698 .ai_range_code = ai_range_code_64xx,
699 .ao_range_table = &ao_ranges_64xx,
700 .ao_range_code = ao_range_code_64xx,
701 .ai_fifo = &ai_fifo_64xx,
704 [BOARD_PCIDAS6402_12] = {
705 .name = "pci-das6402/12", /* XXX check */
711 .ao_scan_speed = 10000,
712 .layout = LAYOUT_64XX,
713 .ai_range_table = &ai_ranges_64xx,
714 .ai_range_code = ai_range_code_64xx,
715 .ao_range_table = &ao_ranges_64xx,
716 .ao_range_code = ao_range_code_64xx,
717 .ai_fifo = &ai_fifo_64xx,
720 [BOARD_PCIDAS64_M1_16] = {
721 .name = "pci-das64/m1/16",
727 .ao_scan_speed = 10000,
728 .layout = LAYOUT_64XX,
729 .ai_range_table = &ai_ranges_64_mx,
730 .ai_range_code = ai_range_code_64_mx,
731 .ao_range_table = &ao_ranges_64xx,
732 .ao_range_code = ao_range_code_64xx,
733 .ai_fifo = &ai_fifo_64xx,
736 [BOARD_PCIDAS64_M2_16] = {
737 .name = "pci-das64/m2/16",
743 .ao_scan_speed = 10000,
744 .layout = LAYOUT_64XX,
745 .ai_range_table = &ai_ranges_64_mx,
746 .ai_range_code = ai_range_code_64_mx,
747 .ao_range_table = &ao_ranges_64xx,
748 .ao_range_code = ao_range_code_64xx,
749 .ai_fifo = &ai_fifo_64xx,
752 [BOARD_PCIDAS64_M3_16] = {
753 .name = "pci-das64/m3/16",
759 .ao_scan_speed = 10000,
760 .layout = LAYOUT_64XX,
761 .ai_range_table = &ai_ranges_64_mx,
762 .ai_range_code = ai_range_code_64_mx,
763 .ao_range_table = &ao_ranges_64xx,
764 .ao_range_code = ao_range_code_64xx,
765 .ai_fifo = &ai_fifo_64xx,
768 [BOARD_PCIDAS6013] = {
769 .name = "pci-das6013",
775 .layout = LAYOUT_60XX,
776 .ai_range_table = &ai_ranges_60xx,
777 .ai_range_code = ai_range_code_60xx,
778 .ao_range_table = &range_bipolar10,
779 .ao_range_code = ao_range_code_60xx,
780 .ai_fifo = &ai_fifo_60xx,
783 [BOARD_PCIDAS6014] = {
784 .name = "pci-das6014",
790 .ao_scan_speed = 100000,
791 .layout = LAYOUT_60XX,
792 .ai_range_table = &ai_ranges_60xx,
793 .ai_range_code = ai_range_code_60xx,
794 .ao_range_table = &range_bipolar10,
795 .ao_range_code = ao_range_code_60xx,
796 .ai_fifo = &ai_fifo_60xx,
799 [BOARD_PCIDAS6023] = {
800 .name = "pci-das6023",
805 .ao_scan_speed = 100000,
806 .layout = LAYOUT_60XX,
807 .ai_range_table = &ai_ranges_60xx,
808 .ai_range_code = ai_range_code_60xx,
809 .ao_range_table = &range_bipolar10,
810 .ao_range_code = ao_range_code_60xx,
811 .ai_fifo = &ai_fifo_60xx,
814 [BOARD_PCIDAS6025] = {
815 .name = "pci-das6025",
821 .ao_scan_speed = 100000,
822 .layout = LAYOUT_60XX,
823 .ai_range_table = &ai_ranges_60xx,
824 .ai_range_code = ai_range_code_60xx,
825 .ao_range_table = &range_bipolar10,
826 .ao_range_code = ao_range_code_60xx,
827 .ai_fifo = &ai_fifo_60xx,
830 [BOARD_PCIDAS6030] = {
831 .name = "pci-das6030",
837 .ao_scan_speed = 10000,
838 .layout = LAYOUT_60XX,
839 .ai_range_table = &ai_ranges_6030,
840 .ai_range_code = ai_range_code_6030,
841 .ao_range_table = &ao_ranges_6030,
842 .ao_range_code = ao_range_code_6030,
843 .ai_fifo = &ai_fifo_60xx,
846 [BOARD_PCIDAS6031] = {
847 .name = "pci-das6031",
853 .ao_scan_speed = 10000,
854 .layout = LAYOUT_60XX,
855 .ai_range_table = &ai_ranges_6030,
856 .ai_range_code = ai_range_code_6030,
857 .ao_range_table = &ao_ranges_6030,
858 .ao_range_code = ao_range_code_6030,
859 .ai_fifo = &ai_fifo_60xx,
862 [BOARD_PCIDAS6032] = {
863 .name = "pci-das6032",
868 .layout = LAYOUT_60XX,
869 .ai_range_table = &ai_ranges_6030,
870 .ai_range_code = ai_range_code_6030,
871 .ai_fifo = &ai_fifo_60xx,
874 [BOARD_PCIDAS6033] = {
875 .name = "pci-das6033",
880 .layout = LAYOUT_60XX,
881 .ai_range_table = &ai_ranges_6030,
882 .ai_range_code = ai_range_code_6030,
883 .ai_fifo = &ai_fifo_60xx,
886 [BOARD_PCIDAS6034] = {
887 .name = "pci-das6034",
893 .layout = LAYOUT_60XX,
894 .ai_range_table = &ai_ranges_60xx,
895 .ai_range_code = ai_range_code_60xx,
896 .ai_fifo = &ai_fifo_60xx,
899 [BOARD_PCIDAS6035] = {
900 .name = "pci-das6035",
906 .ao_scan_speed = 100000,
907 .layout = LAYOUT_60XX,
908 .ai_range_table = &ai_ranges_60xx,
909 .ai_range_code = ai_range_code_60xx,
910 .ao_range_table = &range_bipolar10,
911 .ao_range_code = ao_range_code_60xx,
912 .ai_fifo = &ai_fifo_60xx,
915 [BOARD_PCIDAS6036] = {
916 .name = "pci-das6036",
922 .ao_scan_speed = 100000,
923 .layout = LAYOUT_60XX,
924 .ai_range_table = &ai_ranges_60xx,
925 .ai_range_code = ai_range_code_60xx,
926 .ao_range_table = &range_bipolar10,
927 .ao_range_code = ao_range_code_60xx,
928 .ai_fifo = &ai_fifo_60xx,
931 [BOARD_PCIDAS6040] = {
932 .name = "pci-das6040",
938 .ao_scan_speed = 1000,
939 .layout = LAYOUT_60XX,
940 .ai_range_table = &ai_ranges_6052,
941 .ai_range_code = ai_range_code_6052,
942 .ao_range_table = &ao_ranges_6030,
943 .ao_range_code = ao_range_code_6030,
944 .ai_fifo = &ai_fifo_60xx,
947 [BOARD_PCIDAS6052] = {
948 .name = "pci-das6052",
954 .ao_scan_speed = 3333,
955 .layout = LAYOUT_60XX,
956 .ai_range_table = &ai_ranges_6052,
957 .ai_range_code = ai_range_code_6052,
958 .ao_range_table = &ao_ranges_6030,
959 .ao_range_code = ao_range_code_6030,
960 .ai_fifo = &ai_fifo_60xx,
963 [BOARD_PCIDAS6070] = {
964 .name = "pci-das6070",
970 .ao_scan_speed = 1000,
971 .layout = LAYOUT_60XX,
972 .ai_range_table = &ai_ranges_6052,
973 .ai_range_code = ai_range_code_6052,
974 .ao_range_table = &ao_ranges_6030,
975 .ao_range_code = ao_range_code_6030,
976 .ai_fifo = &ai_fifo_60xx,
979 [BOARD_PCIDAS6071] = {
980 .name = "pci-das6071",
986 .ao_scan_speed = 1000,
987 .layout = LAYOUT_60XX,
988 .ai_range_table = &ai_ranges_6052,
989 .ai_range_code = ai_range_code_6052,
990 .ao_range_table = &ao_ranges_6030,
991 .ao_range_code = ao_range_code_6030,
992 .ai_fifo = &ai_fifo_60xx,
995 [BOARD_PCIDAS4020_12] = {
996 .name = "pci-das4020/12",
1002 .ao_scan_speed = 0, /* no hardware pacing on ao */
1003 .layout = LAYOUT_4020,
1004 .ai_range_table = &ai_ranges_4020,
1005 .ao_range_table = &ao_ranges_4020,
1006 .ao_range_code = ao_range_code_4020,
1007 .ai_fifo = &ai_fifo_4020,
1011 /* The device id for these boards is unknown */
1013 [BOARD_PCIDAS6402_16_JR] = {
1014 .name = "pci-das6402/16/jr",
1019 .ao_scan_speed = 10000,
1020 .layout = LAYOUT_64XX,
1021 .ai_range_table = &ai_ranges_64xx,
1022 .ai_range_code = ai_range_code_64xx,
1023 .ai_fifo = ai_fifo_64xx,
1026 [BOARD_PCIDAS64_M1_16_JR] = {
1027 .name = "pci-das64/m1/16/jr",
1032 .ao_scan_speed = 10000,
1033 .layout = LAYOUT_64XX,
1034 .ai_range_table = &ai_ranges_64_mx,
1035 .ai_range_code = ai_range_code_64_mx,
1036 .ai_fifo = ai_fifo_64xx,
1039 [BOARD_PCIDAS64_M2_16_JR] = {
1040 .name = "pci-das64/m2/16/jr",
1045 .ao_scan_speed = 10000,
1046 .layout = LAYOUT_64XX,
1047 .ai_range_table = &ai_ranges_64_mx,
1048 .ai_range_code = ai_range_code_64_mx,
1049 .ai_fifo = ai_fifo_64xx,
1052 [BOARD_PCIDAS64_M3_16_JR] = {
1053 .name = "pci-das64/m3/16/jr",
1058 .ao_scan_speed = 10000,
1059 .layout = LAYOUT_64XX,
1060 .ai_range_table = &ai_ranges_64_mx,
1061 .ai_range_code = ai_range_code_64_mx,
1062 .ai_fifo = ai_fifo_64xx,
1065 [BOARD_PCIDAS64_M1_14] = {
1066 .name = "pci-das64/m1/14",
1071 .ao_scan_speed = 10000,
1072 .layout = LAYOUT_64XX,
1073 .ai_range_table = &ai_ranges_64_mx,
1074 .ai_range_code = ai_range_code_64_mx,
1075 .ai_fifo = ai_fifo_64xx,
1078 [BOARD_PCIDAS64_M2_14] = {
1079 .name = "pci-das64/m2/14",
1084 .ao_scan_speed = 10000,
1085 .layout = LAYOUT_64XX,
1086 .ai_range_table = &ai_ranges_64_mx,
1087 .ai_range_code = ai_range_code_64_mx,
1088 .ai_fifo = ai_fifo_64xx,
1091 [BOARD_PCIDAS64_M3_14] = {
1092 .name = "pci-das64/m3/14",
1097 .ao_scan_speed = 10000,
1098 .layout = LAYOUT_64XX,
1099 .ai_range_table = &ai_ranges_64_mx,
1100 .ai_range_code = ai_range_code_64_mx,
1101 .ai_fifo = ai_fifo_64xx,
1107 static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev,
1108 int use_differential)
1110 const struct pcidas64_board *board = dev->board_ptr;
1112 if ((board->layout == LAYOUT_64XX && !use_differential) ||
1113 (board->layout == LAYOUT_60XX && use_differential))
1114 return ADC_SE_DIFF_BIT;
1119 struct ext_clock_info {
1120 /* master clock divisor to use for scans with external master clock */
1121 unsigned int divisor;
1122 /* chanspec for master clock input when used as scan begin src */
1123 unsigned int chanspec;
1126 /* this structure is for data unique to this hardware driver. */
1127 struct pcidas64_private {
1128 /* base addresses (physical) */
1129 resource_size_t main_phys_iobase;
1130 resource_size_t dio_counter_phys_iobase;
1131 /* base addresses (ioremapped) */
1132 void __iomem *plx9080_iobase;
1133 void __iomem *main_iobase;
1134 /* local address (used by dma controller) */
1137 /* dma buffers for analog input */
1138 u16 *ai_buffer[MAX_AI_DMA_RING_COUNT];
1139 /* physical addresses of ai dma buffers */
1140 dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT];
1142 * array of ai dma descriptors read by plx9080,
1143 * allocated to get proper alignment
1145 struct plx_dma_desc *ai_dma_desc;
1146 /* physical address of ai dma descriptor array */
1147 dma_addr_t ai_dma_desc_bus_addr;
1149 * index of the ai dma descriptor/buffer
1150 * that is currently being used
1152 unsigned int ai_dma_index;
1153 /* dma buffers for analog output */
1154 u16 *ao_buffer[AO_DMA_RING_COUNT];
1155 /* physical addresses of ao dma buffers */
1156 dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT];
1157 struct plx_dma_desc *ao_dma_desc;
1158 dma_addr_t ao_dma_desc_bus_addr;
1159 /* keeps track of buffer where the next ao sample should go */
1160 unsigned int ao_dma_index;
1161 unsigned int hw_revision; /* stc chip hardware revision number */
1162 /* last bits sent to INTR_ENABLE_REG register */
1163 unsigned int intr_enable_bits;
1164 /* last bits sent to ADC_CONTROL1_REG register */
1165 u16 adc_control1_bits;
1166 /* last bits sent to FIFO_SIZE_REG register */
1168 /* last bits sent to HW_CONFIG_REG register */
1170 u16 dac_control1_bits;
1171 /* last bits written to plx9080 control register */
1172 u32 plx_control_bits;
1173 /* last bits written to plx interrupt control and status register */
1174 u32 plx_intcsr_bits;
1175 /* index of calibration source readable through ai ch0 */
1176 int calibration_source;
1177 /* bits written to i2c calibration/range register */
1178 u8 i2c_cal_range_bits;
1179 /* configure digital triggers to trigger on falling edge */
1180 unsigned int ext_trig_falling;
1181 short ai_cmd_running;
1182 unsigned int ai_fifo_segment_length;
1183 struct ext_clock_info ext_clock;
1184 unsigned short ao_bounce_buffer[DAC_FIFO_SIZE];
1187 static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev,
1188 unsigned int range_index)
1190 const struct pcidas64_board *board = dev->board_ptr;
1192 return board->ai_range_code[range_index] << 8;
1195 static unsigned int hw_revision(const struct comedi_device *dev,
1198 const struct pcidas64_board *board = dev->board_ptr;
1200 if (board->layout == LAYOUT_4020)
1201 return (hw_status_bits >> 13) & 0x7;
1203 return (hw_status_bits >> 12) & 0xf;
1206 static void set_dac_range_bits(struct comedi_device *dev,
1207 u16 *bits, unsigned int channel,
1210 const struct pcidas64_board *board = dev->board_ptr;
1211 unsigned int code = board->ao_range_code[range];
1214 dev_err(dev->class_dev, "bug! bad channel?\n");
1216 dev_err(dev->class_dev, "bug! bad range code?\n");
1218 *bits &= ~(0x3 << (2 * channel));
1219 *bits |= code << (2 * channel);
1222 static inline int ao_cmd_is_supported(const struct pcidas64_board *board)
1224 return board->ao_nchan && board->layout != LAYOUT_4020;
1227 static void abort_dma(struct comedi_device *dev, unsigned int channel)
1229 struct pcidas64_private *devpriv = dev->private;
1230 unsigned long flags;
1232 /* spinlock for plx dma control/status reg */
1233 spin_lock_irqsave(&dev->spinlock, flags);
1235 plx9080_abort_dma(devpriv->plx9080_iobase, channel);
1237 spin_unlock_irqrestore(&dev->spinlock, flags);
1240 static void disable_plx_interrupts(struct comedi_device *dev)
1242 struct pcidas64_private *devpriv = dev->private;
1244 devpriv->plx_intcsr_bits = 0;
1245 writel(devpriv->plx_intcsr_bits,
1246 devpriv->plx9080_iobase + PLX_REG_INTCSR);
1249 static void disable_ai_interrupts(struct comedi_device *dev)
1251 struct pcidas64_private *devpriv = dev->private;
1252 unsigned long flags;
1254 spin_lock_irqsave(&dev->spinlock, flags);
1255 devpriv->intr_enable_bits &=
1256 ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT &
1257 ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT &
1258 ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK;
1259 writew(devpriv->intr_enable_bits,
1260 devpriv->main_iobase + INTR_ENABLE_REG);
1261 spin_unlock_irqrestore(&dev->spinlock, flags);
1264 static void enable_ai_interrupts(struct comedi_device *dev,
1265 const struct comedi_cmd *cmd)
1267 const struct pcidas64_board *board = dev->board_ptr;
1268 struct pcidas64_private *devpriv = dev->private;
1270 unsigned long flags;
1272 bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
1273 EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
1275 * Use pio transfer and interrupt on end of conversion
1276 * if CMDF_WAKE_EOS flag is set.
1278 if (cmd->flags & CMDF_WAKE_EOS) {
1279 /* 4020 doesn't support pio transfers except for fifo dregs */
1280 if (board->layout != LAYOUT_4020)
1281 bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT;
1283 spin_lock_irqsave(&dev->spinlock, flags);
1284 devpriv->intr_enable_bits |= bits;
1285 writew(devpriv->intr_enable_bits,
1286 devpriv->main_iobase + INTR_ENABLE_REG);
1287 spin_unlock_irqrestore(&dev->spinlock, flags);
1290 /* initialize plx9080 chip */
1291 static void init_plx9080(struct comedi_device *dev)
1293 const struct pcidas64_board *board = dev->board_ptr;
1294 struct pcidas64_private *devpriv = dev->private;
1296 void __iomem *plx_iobase = devpriv->plx9080_iobase;
1298 devpriv->plx_control_bits =
1299 readl(devpriv->plx9080_iobase + PLX_REG_CNTRL);
1302 bits = PLX_BIGEND_DMA0 | PLX_BIGEND_DMA1;
1306 writel(bits, devpriv->plx9080_iobase + PLX_REG_BIGEND);
1308 disable_plx_interrupts(dev);
1313 /* configure dma0 mode */
1315 /* enable ready input, not sure if this is necessary */
1316 bits |= PLX_DMAMODE_READYIEN;
1317 /* enable bterm, not sure if this is necessary */
1318 bits |= PLX_DMAMODE_BTERMIEN;
1319 /* enable dma chaining */
1320 bits |= PLX_DMAMODE_CHAINEN;
1322 * enable interrupt on dma done
1323 * (probably don't need this, since chain never finishes)
1325 bits |= PLX_DMAMODE_DONEIEN;
1327 * don't increment local address during transfers
1328 * (we are transferring from a fixed fifo register)
1330 bits |= PLX_DMAMODE_LACONST;
1331 /* route dma interrupt to pci bus */
1332 bits |= PLX_DMAMODE_INTRPCI;
1333 /* enable demand mode */
1334 bits |= PLX_DMAMODE_DEMAND;
1335 /* enable local burst mode */
1336 bits |= PLX_DMAMODE_BURSTEN;
1337 /* 4020 uses 32 bit dma */
1338 if (board->layout == LAYOUT_4020)
1339 bits |= PLX_DMAMODE_WIDTH_32;
1340 else /* localspace0 bus is 16 bits wide */
1341 bits |= PLX_DMAMODE_WIDTH_16;
1342 writel(bits, plx_iobase + PLX_REG_DMAMODE1);
1343 if (ao_cmd_is_supported(board))
1344 writel(bits, plx_iobase + PLX_REG_DMAMODE0);
1346 /* enable interrupts on plx 9080 */
1347 devpriv->plx_intcsr_bits |=
1348 PLX_INTCSR_LSEABORTEN | PLX_INTCSR_LSEPARITYEN | PLX_INTCSR_PIEN |
1349 PLX_INTCSR_PLIEN | PLX_INTCSR_PABORTIEN | PLX_INTCSR_LIOEN |
1350 PLX_INTCSR_DMA0IEN | PLX_INTCSR_DMA1IEN;
1351 writel(devpriv->plx_intcsr_bits,
1352 devpriv->plx9080_iobase + PLX_REG_INTCSR);
1355 static void disable_ai_pacing(struct comedi_device *dev)
1357 struct pcidas64_private *devpriv = dev->private;
1358 unsigned long flags;
1360 disable_ai_interrupts(dev);
1362 spin_lock_irqsave(&dev->spinlock, flags);
1363 devpriv->adc_control1_bits &= ~ADC_SW_GATE_BIT;
1364 writew(devpriv->adc_control1_bits,
1365 devpriv->main_iobase + ADC_CONTROL1_REG);
1366 spin_unlock_irqrestore(&dev->spinlock, flags);
1368 /* disable pacing, triggering, etc */
1369 writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT,
1370 devpriv->main_iobase + ADC_CONTROL0_REG);
1373 static int set_ai_fifo_segment_length(struct comedi_device *dev,
1374 unsigned int num_entries)
1376 const struct pcidas64_board *board = dev->board_ptr;
1377 struct pcidas64_private *devpriv = dev->private;
1378 static const int increment_size = 0x100;
1379 const struct hw_fifo_info *const fifo = board->ai_fifo;
1380 unsigned int num_increments;
1383 if (num_entries < increment_size)
1384 num_entries = increment_size;
1385 if (num_entries > fifo->max_segment_length)
1386 num_entries = fifo->max_segment_length;
1388 /* 1 == 256 entries, 2 == 512 entries, etc */
1389 num_increments = DIV_ROUND_CLOSEST(num_entries, increment_size);
1391 bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask;
1392 devpriv->fifo_size_bits &= ~fifo->fifo_size_reg_mask;
1393 devpriv->fifo_size_bits |= bits;
1394 writew(devpriv->fifo_size_bits,
1395 devpriv->main_iobase + FIFO_SIZE_REG);
1397 devpriv->ai_fifo_segment_length = num_increments * increment_size;
1399 return devpriv->ai_fifo_segment_length;
1403 * adjusts the size of hardware fifo (which determines block size for dma xfers)
1405 static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples)
1407 const struct pcidas64_board *board = dev->board_ptr;
1408 unsigned int num_fifo_entries;
1410 const struct hw_fifo_info *const fifo = board->ai_fifo;
1412 num_fifo_entries = num_samples / fifo->sample_packing_ratio;
1414 retval = set_ai_fifo_segment_length(dev,
1416 fifo->num_segments);
1420 return retval * fifo->num_segments * fifo->sample_packing_ratio;
1423 /* query length of fifo */
1424 static unsigned int ai_fifo_size(struct comedi_device *dev)
1426 const struct pcidas64_board *board = dev->board_ptr;
1427 struct pcidas64_private *devpriv = dev->private;
1429 return devpriv->ai_fifo_segment_length *
1430 board->ai_fifo->num_segments *
1431 board->ai_fifo->sample_packing_ratio;
1434 static void init_stc_registers(struct comedi_device *dev)
1436 const struct pcidas64_board *board = dev->board_ptr;
1437 struct pcidas64_private *devpriv = dev->private;
1439 unsigned long flags;
1441 spin_lock_irqsave(&dev->spinlock, flags);
1444 * bit should be set for 6025,
1445 * although docs say boards with <= 16 chans should be cleared XXX
1448 devpriv->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
1449 writew(devpriv->adc_control1_bits,
1450 devpriv->main_iobase + ADC_CONTROL1_REG);
1452 /* 6402/16 manual says this register must be initialized to 0xff? */
1453 writew(0xff, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1455 bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT;
1456 if (board->layout == LAYOUT_4020)
1457 bits |= INTERNAL_CLOCK_4020_BITS;
1458 devpriv->hw_config_bits |= bits;
1459 writew(devpriv->hw_config_bits,
1460 devpriv->main_iobase + HW_CONFIG_REG);
1462 writew(0, devpriv->main_iobase + DAQ_SYNC_REG);
1463 writew(0, devpriv->main_iobase + CALIBRATION_REG);
1465 spin_unlock_irqrestore(&dev->spinlock, flags);
1467 /* set fifos to maximum size */
1468 devpriv->fifo_size_bits |= DAC_FIFO_BITS;
1469 set_ai_fifo_segment_length(dev, board->ai_fifo->max_segment_length);
1471 devpriv->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT;
1472 devpriv->intr_enable_bits =
1473 /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1474 EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT;
1475 writew(devpriv->intr_enable_bits,
1476 devpriv->main_iobase + INTR_ENABLE_REG);
1478 disable_ai_pacing(dev);
1481 static int alloc_and_init_dma_members(struct comedi_device *dev)
1483 const struct pcidas64_board *board = dev->board_ptr;
1484 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1485 struct pcidas64_private *devpriv = dev->private;
1488 /* allocate pci dma buffers */
1489 for (i = 0; i < ai_dma_ring_count(board); i++) {
1490 devpriv->ai_buffer[i] =
1491 dma_alloc_coherent(&pcidev->dev, DMA_BUFFER_SIZE,
1492 &devpriv->ai_buffer_bus_addr[i],
1494 if (!devpriv->ai_buffer[i])
1497 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1498 if (ao_cmd_is_supported(board)) {
1499 devpriv->ao_buffer[i] =
1500 dma_alloc_coherent(&pcidev->dev,
1503 ao_buffer_bus_addr[i],
1505 if (!devpriv->ao_buffer[i])
1509 /* allocate dma descriptors */
1510 devpriv->ai_dma_desc =
1511 dma_alloc_coherent(&pcidev->dev, sizeof(struct plx_dma_desc) *
1512 ai_dma_ring_count(board),
1513 &devpriv->ai_dma_desc_bus_addr, GFP_KERNEL);
1514 if (!devpriv->ai_dma_desc)
1517 if (ao_cmd_is_supported(board)) {
1518 devpriv->ao_dma_desc =
1519 dma_alloc_coherent(&pcidev->dev,
1520 sizeof(struct plx_dma_desc) *
1522 &devpriv->ao_dma_desc_bus_addr,
1524 if (!devpriv->ao_dma_desc)
1527 /* initialize dma descriptors */
1528 for (i = 0; i < ai_dma_ring_count(board); i++) {
1529 devpriv->ai_dma_desc[i].pci_start_addr =
1530 cpu_to_le32(devpriv->ai_buffer_bus_addr[i]);
1531 if (board->layout == LAYOUT_4020)
1532 devpriv->ai_dma_desc[i].local_start_addr =
1533 cpu_to_le32(devpriv->local1_iobase +
1536 devpriv->ai_dma_desc[i].local_start_addr =
1537 cpu_to_le32(devpriv->local0_iobase +
1539 devpriv->ai_dma_desc[i].transfer_size = cpu_to_le32(0);
1540 devpriv->ai_dma_desc[i].next =
1541 cpu_to_le32((devpriv->ai_dma_desc_bus_addr +
1542 ((i + 1) % ai_dma_ring_count(board)) *
1543 sizeof(devpriv->ai_dma_desc[0])) |
1544 PLX_DMADPR_DESCPCI | PLX_DMADPR_TCINTR |
1545 PLX_DMADPR_XFERL2P);
1547 if (ao_cmd_is_supported(board)) {
1548 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1549 devpriv->ao_dma_desc[i].pci_start_addr =
1550 cpu_to_le32(devpriv->ao_buffer_bus_addr[i]);
1551 devpriv->ao_dma_desc[i].local_start_addr =
1552 cpu_to_le32(devpriv->local0_iobase +
1554 devpriv->ao_dma_desc[i].transfer_size = cpu_to_le32(0);
1555 devpriv->ao_dma_desc[i].next =
1556 cpu_to_le32((devpriv->ao_dma_desc_bus_addr +
1557 ((i + 1) % (AO_DMA_RING_COUNT)) *
1558 sizeof(devpriv->ao_dma_desc[0])) |
1559 PLX_DMADPR_DESCPCI |
1566 static void cb_pcidas64_free_dma(struct comedi_device *dev)
1568 const struct pcidas64_board *board = dev->board_ptr;
1569 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1570 struct pcidas64_private *devpriv = dev->private;
1576 /* free pci dma buffers */
1577 for (i = 0; i < ai_dma_ring_count(board); i++) {
1578 if (devpriv->ai_buffer[i])
1579 dma_free_coherent(&pcidev->dev,
1581 devpriv->ai_buffer[i],
1582 devpriv->ai_buffer_bus_addr[i]);
1584 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1585 if (devpriv->ao_buffer[i])
1586 dma_free_coherent(&pcidev->dev,
1588 devpriv->ao_buffer[i],
1589 devpriv->ao_buffer_bus_addr[i]);
1591 /* free dma descriptors */
1592 if (devpriv->ai_dma_desc)
1593 dma_free_coherent(&pcidev->dev,
1594 sizeof(struct plx_dma_desc) *
1595 ai_dma_ring_count(board),
1596 devpriv->ai_dma_desc,
1597 devpriv->ai_dma_desc_bus_addr);
1598 if (devpriv->ao_dma_desc)
1599 dma_free_coherent(&pcidev->dev,
1600 sizeof(struct plx_dma_desc) *
1602 devpriv->ao_dma_desc,
1603 devpriv->ao_dma_desc_bus_addr);
1606 static inline void warn_external_queue(struct comedi_device *dev)
1608 dev_err(dev->class_dev,
1609 "AO command and AI external channel queue cannot be used simultaneously\n");
1610 dev_err(dev->class_dev,
1611 "Use internal AI channel queue (channels must be consecutive and use same range/aref)\n");
1615 * their i2c requires a huge delay on setting clock or data high for some reason
1617 static const int i2c_high_udelay = 1000;
1618 static const int i2c_low_udelay = 10;
1620 /* set i2c data line high or low */
1621 static void i2c_set_sda(struct comedi_device *dev, int state)
1623 struct pcidas64_private *devpriv = dev->private;
1624 static const int data_bit = PLX_CNTRL_EEWB;
1625 void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1628 if (state) { /* set data line high */
1629 devpriv->plx_control_bits &= ~data_bit;
1630 writel(devpriv->plx_control_bits, plx_control_addr);
1631 udelay(i2c_high_udelay);
1632 } else { /* set data line low */
1633 devpriv->plx_control_bits |= data_bit;
1634 writel(devpriv->plx_control_bits, plx_control_addr);
1635 udelay(i2c_low_udelay);
1639 /* set i2c clock line high or low */
1640 static void i2c_set_scl(struct comedi_device *dev, int state)
1642 struct pcidas64_private *devpriv = dev->private;
1643 static const int clock_bit = PLX_CNTRL_USERO;
1644 void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1647 if (state) { /* set clock line high */
1648 devpriv->plx_control_bits &= ~clock_bit;
1649 writel(devpriv->plx_control_bits, plx_control_addr);
1650 udelay(i2c_high_udelay);
1651 } else { /* set clock line low */
1652 devpriv->plx_control_bits |= clock_bit;
1653 writel(devpriv->plx_control_bits, plx_control_addr);
1654 udelay(i2c_low_udelay);
1658 static void i2c_write_byte(struct comedi_device *dev, u8 byte)
1661 unsigned int num_bits = 8;
1663 for (bit = 1 << (num_bits - 1); bit; bit >>= 1) {
1664 i2c_set_scl(dev, 0);
1666 i2c_set_sda(dev, 1);
1668 i2c_set_sda(dev, 0);
1669 i2c_set_scl(dev, 1);
1673 /* we can't really read the lines, so fake it */
1674 static int i2c_read_ack(struct comedi_device *dev)
1676 i2c_set_scl(dev, 0);
1677 i2c_set_sda(dev, 1);
1678 i2c_set_scl(dev, 1);
1680 return 0; /* return fake acknowledge bit */
1683 /* send start bit */
1684 static void i2c_start(struct comedi_device *dev)
1686 i2c_set_scl(dev, 1);
1687 i2c_set_sda(dev, 1);
1688 i2c_set_sda(dev, 0);
1692 static void i2c_stop(struct comedi_device *dev)
1694 i2c_set_scl(dev, 0);
1695 i2c_set_sda(dev, 0);
1696 i2c_set_scl(dev, 1);
1697 i2c_set_sda(dev, 1);
1700 static void i2c_write(struct comedi_device *dev, unsigned int address,
1701 const u8 *data, unsigned int length)
1703 struct pcidas64_private *devpriv = dev->private;
1706 static const int read_bit = 0x1;
1709 * XXX need mutex to prevent simultaneous attempts to access
1710 * eeprom and i2c bus
1713 /* make sure we dont send anything to eeprom */
1714 devpriv->plx_control_bits &= ~PLX_CNTRL_EECS;
1719 /* send address and write bit */
1720 bitstream = (address << 1) & ~read_bit;
1721 i2c_write_byte(dev, bitstream);
1723 /* get acknowledge */
1724 if (i2c_read_ack(dev) != 0) {
1725 dev_err(dev->class_dev, "failed: no acknowledge\n");
1729 /* write data bytes */
1730 for (i = 0; i < length; i++) {
1731 i2c_write_byte(dev, data[i]);
1732 if (i2c_read_ack(dev) != 0) {
1733 dev_err(dev->class_dev, "failed: no acknowledge\n");
1741 static int cb_pcidas64_ai_eoc(struct comedi_device *dev,
1742 struct comedi_subdevice *s,
1743 struct comedi_insn *insn,
1744 unsigned long context)
1746 const struct pcidas64_board *board = dev->board_ptr;
1747 struct pcidas64_private *devpriv = dev->private;
1748 unsigned int status;
1750 status = readw(devpriv->main_iobase + HW_STATUS_REG);
1751 if (board->layout == LAYOUT_4020) {
1752 status = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG);
1756 if (pipe_full_bits(status))
1762 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1763 struct comedi_insn *insn, unsigned int *data)
1765 const struct pcidas64_board *board = dev->board_ptr;
1766 struct pcidas64_private *devpriv = dev->private;
1767 unsigned int bits = 0, n;
1768 unsigned int channel, range, aref;
1769 unsigned long flags;
1772 channel = CR_CHAN(insn->chanspec);
1773 range = CR_RANGE(insn->chanspec);
1774 aref = CR_AREF(insn->chanspec);
1776 /* disable card's analog input interrupt sources and pacing */
1777 /* 4020 generates dac done interrupts even though they are disabled */
1778 disable_ai_pacing(dev);
1780 spin_lock_irqsave(&dev->spinlock, flags);
1781 if (insn->chanspec & CR_ALT_FILTER)
1782 devpriv->adc_control1_bits |= ADC_DITHER_BIT;
1784 devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
1785 writew(devpriv->adc_control1_bits,
1786 devpriv->main_iobase + ADC_CONTROL1_REG);
1787 spin_unlock_irqrestore(&dev->spinlock, flags);
1789 if (board->layout != LAYOUT_4020) {
1790 /* use internal queue */
1791 devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
1792 writew(devpriv->hw_config_bits,
1793 devpriv->main_iobase + HW_CONFIG_REG);
1795 /* ALT_SOURCE is internal calibration reference */
1796 if (insn->chanspec & CR_ALT_SOURCE) {
1797 unsigned int cal_en_bit;
1799 if (board->layout == LAYOUT_60XX)
1800 cal_en_bit = CAL_EN_60XX_BIT;
1802 cal_en_bit = CAL_EN_64XX_BIT;
1804 * select internal reference source to connect
1808 adc_src_bits(devpriv->calibration_source),
1809 devpriv->main_iobase + CALIBRATION_REG);
1812 * make sure internal calibration source
1815 writew(0, devpriv->main_iobase + CALIBRATION_REG);
1817 /* load internal queue */
1820 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec));
1821 /* set single-ended / differential */
1822 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF);
1823 if (aref == AREF_COMMON)
1824 bits |= ADC_COMMON_BIT;
1825 bits |= adc_chan_bits(channel);
1826 /* set stop channel */
1827 writew(adc_chan_bits(channel),
1828 devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
1829 /* set start channel, and rest of settings */
1830 writew(bits, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
1832 u8 old_cal_range_bits = devpriv->i2c_cal_range_bits;
1834 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
1835 if (insn->chanspec & CR_ALT_SOURCE) {
1836 devpriv->i2c_cal_range_bits |=
1837 adc_src_4020_bits(devpriv->calibration_source);
1838 } else { /* select BNC inputs */
1839 devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
1843 devpriv->i2c_cal_range_bits |= attenuate_bit(channel);
1845 devpriv->i2c_cal_range_bits &= ~attenuate_bit(channel);
1847 * update calibration/range i2c register only if necessary,
1848 * as it is very slow
1850 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
1851 u8 i2c_data = devpriv->i2c_cal_range_bits;
1853 i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
1858 * 4020 manual asks that sample interval register to be set
1859 * before writing to convert register.
1860 * Using somewhat arbitrary setting of 4 master clock ticks
1863 writew(0, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1864 writew(2, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
1867 for (n = 0; n < insn->n; n++) {
1868 /* clear adc buffer (inside loop for 4020 sake) */
1869 writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
1871 /* trigger conversion, bits sent only matter for 4020 */
1872 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)),
1873 devpriv->main_iobase + ADC_CONVERT_REG);
1876 ret = comedi_timeout(dev, s, insn, cb_pcidas64_ai_eoc, 0);
1880 if (board->layout == LAYOUT_4020)
1881 data[n] = readl(dev->mmio + ADC_FIFO_REG) & 0xffff;
1883 data[n] = readw(devpriv->main_iobase + PIPE1_READ_REG);
1889 static int ai_config_calibration_source(struct comedi_device *dev,
1892 const struct pcidas64_board *board = dev->board_ptr;
1893 struct pcidas64_private *devpriv = dev->private;
1894 unsigned int source = data[1];
1895 int num_calibration_sources;
1897 if (board->layout == LAYOUT_60XX)
1898 num_calibration_sources = 16;
1900 num_calibration_sources = 8;
1901 if (source >= num_calibration_sources) {
1902 dev_dbg(dev->class_dev, "invalid calibration source: %i\n",
1907 devpriv->calibration_source = source;
1912 static int ai_config_block_size(struct comedi_device *dev, unsigned int *data)
1914 const struct pcidas64_board *board = dev->board_ptr;
1916 const struct hw_fifo_info *const fifo = board->ai_fifo;
1917 unsigned int block_size, requested_block_size;
1920 requested_block_size = data[1];
1922 if (requested_block_size) {
1923 fifo_size = requested_block_size * fifo->num_segments /
1926 retval = set_ai_fifo_size(dev, fifo_size);
1931 block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample;
1933 data[1] = block_size;
1938 static int ai_config_master_clock_4020(struct comedi_device *dev,
1941 struct pcidas64_private *devpriv = dev->private;
1942 unsigned int divisor = data[4];
1951 case COMEDI_EV_SCAN_BEGIN:
1952 devpriv->ext_clock.divisor = divisor;
1953 devpriv->ext_clock.chanspec = data[2];
1961 return retval ? retval : 5;
1964 /* XXX could add support for 60xx series */
1965 static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data)
1967 const struct pcidas64_board *board = dev->board_ptr;
1969 switch (board->layout) {
1971 return ai_config_master_clock_4020(dev, data);
1979 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1980 struct comedi_insn *insn, unsigned int *data)
1985 case INSN_CONFIG_ALT_SOURCE:
1986 return ai_config_calibration_source(dev, data);
1987 case INSN_CONFIG_BLOCK_SIZE:
1988 return ai_config_block_size(dev, data);
1989 case INSN_CONFIG_TIMER_1:
1990 return ai_config_master_clock(dev, data);
1998 * Gets nearest achievable timing given master clock speed, does not
1999 * take into account possible minimum/maximum divisor values. Used
2000 * by other timing checking functions.
2002 static unsigned int get_divisor(unsigned int ns, unsigned int flags)
2004 unsigned int divisor;
2006 switch (flags & CMDF_ROUND_MASK) {
2008 divisor = DIV_ROUND_UP(ns, TIMER_BASE);
2010 case CMDF_ROUND_DOWN:
2011 divisor = ns / TIMER_BASE;
2013 case CMDF_ROUND_NEAREST:
2015 divisor = DIV_ROUND_CLOSEST(ns, TIMER_BASE);
2022 * utility function that rounds desired timing to an achievable time, and
2023 * sets cmd members appropriately.
2024 * adc paces conversions from master clock by dividing by (x + 3) where x is
2027 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
2029 const struct pcidas64_board *board = dev->board_ptr;
2030 unsigned long long convert_divisor = 0;
2031 unsigned int scan_divisor;
2032 static const int min_convert_divisor = 3;
2033 static const int max_convert_divisor =
2034 max_counter_value + min_convert_divisor;
2035 static const int min_scan_divisor_4020 = 2;
2036 unsigned long long max_scan_divisor, min_scan_divisor;
2038 if (cmd->convert_src == TRIG_TIMER) {
2039 if (board->layout == LAYOUT_4020) {
2040 cmd->convert_arg = 0;
2042 convert_divisor = get_divisor(cmd->convert_arg,
2044 if (convert_divisor > max_convert_divisor)
2045 convert_divisor = max_convert_divisor;
2046 if (convert_divisor < min_convert_divisor)
2047 convert_divisor = min_convert_divisor;
2048 cmd->convert_arg = convert_divisor * TIMER_BASE;
2050 } else if (cmd->convert_src == TRIG_NOW) {
2051 cmd->convert_arg = 0;
2054 if (cmd->scan_begin_src == TRIG_TIMER) {
2055 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags);
2056 if (cmd->convert_src == TRIG_TIMER) {
2057 min_scan_divisor = convert_divisor * cmd->chanlist_len;
2059 (convert_divisor * cmd->chanlist_len - 1) +
2062 min_scan_divisor = min_scan_divisor_4020;
2063 max_scan_divisor = max_counter_value + min_scan_divisor;
2065 if (scan_divisor > max_scan_divisor)
2066 scan_divisor = max_scan_divisor;
2067 if (scan_divisor < min_scan_divisor)
2068 scan_divisor = min_scan_divisor;
2069 cmd->scan_begin_arg = scan_divisor * TIMER_BASE;
2073 static int cb_pcidas64_ai_check_chanlist(struct comedi_device *dev,
2074 struct comedi_subdevice *s,
2075 struct comedi_cmd *cmd)
2077 const struct pcidas64_board *board = dev->board_ptr;
2078 unsigned int aref0 = CR_AREF(cmd->chanlist[0]);
2081 for (i = 1; i < cmd->chanlist_len; i++) {
2082 unsigned int aref = CR_AREF(cmd->chanlist[i]);
2084 if (aref != aref0) {
2085 dev_dbg(dev->class_dev,
2086 "all elements in chanlist must use the same analog reference\n");
2091 if (board->layout == LAYOUT_4020) {
2092 unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
2094 for (i = 1; i < cmd->chanlist_len; i++) {
2095 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
2097 if (chan != (chan0 + i)) {
2098 dev_dbg(dev->class_dev,
2099 "chanlist must use consecutive channels\n");
2103 if (cmd->chanlist_len == 3) {
2104 dev_dbg(dev->class_dev,
2105 "chanlist cannot be 3 channels long, use 1, 2, or 4 channels\n");
2113 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2114 struct comedi_cmd *cmd)
2116 const struct pcidas64_board *board = dev->board_ptr;
2118 unsigned int tmp_arg, tmp_arg2;
2119 unsigned int triggers;
2121 /* Step 1 : check if triggers are trivially valid */
2123 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
2125 triggers = TRIG_TIMER;
2126 if (board->layout == LAYOUT_4020)
2127 triggers |= TRIG_OTHER;
2129 triggers |= TRIG_FOLLOW;
2130 err |= comedi_check_trigger_src(&cmd->scan_begin_src, triggers);
2132 triggers = TRIG_TIMER;
2133 if (board->layout == LAYOUT_4020)
2134 triggers |= TRIG_NOW;
2136 triggers |= TRIG_EXT;
2137 err |= comedi_check_trigger_src(&cmd->convert_src, triggers);
2138 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2139 err |= comedi_check_trigger_src(&cmd->stop_src,
2140 TRIG_COUNT | TRIG_EXT | TRIG_NONE);
2145 /* Step 2a : make sure trigger sources are unique */
2147 err |= comedi_check_trigger_is_unique(cmd->start_src);
2148 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2149 err |= comedi_check_trigger_is_unique(cmd->convert_src);
2150 err |= comedi_check_trigger_is_unique(cmd->stop_src);
2152 /* Step 2b : and mutually compatible */
2154 if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
2160 /* Step 3: check if arguments are trivially valid */
2162 switch (cmd->start_src) {
2164 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2168 * start_arg is the CR_CHAN | CR_INVERT of the
2174 if (cmd->convert_src == TRIG_TIMER) {
2175 if (board->layout == LAYOUT_4020) {
2176 err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2179 err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2182 * if scans are timed faster than conversion rate
2185 if (cmd->scan_begin_src == TRIG_TIMER) {
2186 err |= comedi_check_trigger_arg_min(
2187 &cmd->scan_begin_arg,
2194 err |= comedi_check_trigger_arg_min(&cmd->chanlist_len, 1);
2195 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2198 switch (cmd->stop_src) {
2202 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2205 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2214 /* step 4: fix up any arguments */
2216 if (cmd->convert_src == TRIG_TIMER) {
2217 tmp_arg = cmd->convert_arg;
2218 tmp_arg2 = cmd->scan_begin_arg;
2219 check_adc_timing(dev, cmd);
2220 if (tmp_arg != cmd->convert_arg)
2222 if (tmp_arg2 != cmd->scan_begin_arg)
2229 /* Step 5: check channel list if it exists */
2230 if (cmd->chanlist && cmd->chanlist_len > 0)
2231 err |= cb_pcidas64_ai_check_chanlist(dev, s, cmd);
2239 static int use_hw_sample_counter(struct comedi_cmd *cmd)
2241 /* disable for now until I work out a race */
2244 if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value)
2250 static void setup_sample_counters(struct comedi_device *dev,
2251 struct comedi_cmd *cmd)
2253 struct pcidas64_private *devpriv = dev->private;
2255 /* load hardware conversion counter */
2256 if (use_hw_sample_counter(cmd)) {
2257 writew(cmd->stop_arg & 0xffff,
2258 devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2259 writew((cmd->stop_arg >> 16) & 0xff,
2260 devpriv->main_iobase + ADC_COUNT_UPPER_REG);
2262 writew(1, devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2266 static inline unsigned int dma_transfer_size(struct comedi_device *dev)
2268 const struct pcidas64_board *board = dev->board_ptr;
2269 struct pcidas64_private *devpriv = dev->private;
2270 unsigned int num_samples;
2272 num_samples = devpriv->ai_fifo_segment_length *
2273 board->ai_fifo->sample_packing_ratio;
2274 if (num_samples > DMA_BUFFER_SIZE / sizeof(u16))
2275 num_samples = DMA_BUFFER_SIZE / sizeof(u16);
2280 static u32 ai_convert_counter_6xxx(const struct comedi_device *dev,
2281 const struct comedi_cmd *cmd)
2283 /* supposed to load counter with desired divisor minus 3 */
2284 return cmd->convert_arg / TIMER_BASE - 3;
2287 static u32 ai_scan_counter_6xxx(struct comedi_device *dev,
2288 struct comedi_cmd *cmd)
2292 /* figure out how long we need to delay at end of scan */
2293 switch (cmd->scan_begin_src) {
2295 count = (cmd->scan_begin_arg -
2296 (cmd->convert_arg * (cmd->chanlist_len - 1))) /
2300 count = cmd->convert_arg / TIMER_BASE;
2308 static u32 ai_convert_counter_4020(struct comedi_device *dev,
2309 struct comedi_cmd *cmd)
2311 struct pcidas64_private *devpriv = dev->private;
2312 unsigned int divisor;
2314 switch (cmd->scan_begin_src) {
2316 divisor = cmd->scan_begin_arg / TIMER_BASE;
2319 divisor = devpriv->ext_clock.divisor;
2321 default: /* should never happen */
2322 dev_err(dev->class_dev, "bug! failed to set ai pacing!\n");
2327 /* supposed to load counter with desired divisor minus 2 for 4020 */
2331 static void select_master_clock_4020(struct comedi_device *dev,
2332 const struct comedi_cmd *cmd)
2334 struct pcidas64_private *devpriv = dev->private;
2336 /* select internal/external master clock */
2337 devpriv->hw_config_bits &= ~MASTER_CLOCK_4020_MASK;
2338 if (cmd->scan_begin_src == TRIG_OTHER) {
2339 int chanspec = devpriv->ext_clock.chanspec;
2341 if (CR_CHAN(chanspec))
2342 devpriv->hw_config_bits |= BNC_CLOCK_4020_BITS;
2344 devpriv->hw_config_bits |= EXT_CLOCK_4020_BITS;
2346 devpriv->hw_config_bits |= INTERNAL_CLOCK_4020_BITS;
2348 writew(devpriv->hw_config_bits,
2349 devpriv->main_iobase + HW_CONFIG_REG);
2352 static void select_master_clock(struct comedi_device *dev,
2353 const struct comedi_cmd *cmd)
2355 const struct pcidas64_board *board = dev->board_ptr;
2357 switch (board->layout) {
2359 select_master_clock_4020(dev, cmd);
2366 static inline void dma_start_sync(struct comedi_device *dev,
2367 unsigned int channel)
2369 struct pcidas64_private *devpriv = dev->private;
2370 unsigned long flags;
2372 /* spinlock for plx dma control/status reg */
2373 spin_lock_irqsave(&dev->spinlock, flags);
2374 writeb(PLX_DMACSR_ENABLE | PLX_DMACSR_START | PLX_DMACSR_CLEARINTR,
2375 devpriv->plx9080_iobase + PLX_REG_DMACSR(channel));
2376 spin_unlock_irqrestore(&dev->spinlock, flags);
2379 static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd)
2381 const struct pcidas64_board *board = dev->board_ptr;
2382 struct pcidas64_private *devpriv = dev->private;
2383 u32 convert_counter = 0, scan_counter = 0;
2385 check_adc_timing(dev, cmd);
2387 select_master_clock(dev, cmd);
2389 if (board->layout == LAYOUT_4020) {
2390 convert_counter = ai_convert_counter_4020(dev, cmd);
2392 convert_counter = ai_convert_counter_6xxx(dev, cmd);
2393 scan_counter = ai_scan_counter_6xxx(dev, cmd);
2396 /* load lower 16 bits of convert interval */
2397 writew(convert_counter & 0xffff,
2398 devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2399 /* load upper 8 bits of convert interval */
2400 writew((convert_counter >> 16) & 0xff,
2401 devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2402 /* load lower 16 bits of scan delay */
2403 writew(scan_counter & 0xffff,
2404 devpriv->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG);
2405 /* load upper 8 bits of scan delay */
2406 writew((scan_counter >> 16) & 0xff,
2407 devpriv->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG);
2410 static int use_internal_queue_6xxx(const struct comedi_cmd *cmd)
2414 for (i = 0; i + 1 < cmd->chanlist_len; i++) {
2415 if (CR_CHAN(cmd->chanlist[i + 1]) !=
2416 CR_CHAN(cmd->chanlist[i]) + 1)
2418 if (CR_RANGE(cmd->chanlist[i + 1]) !=
2419 CR_RANGE(cmd->chanlist[i]))
2421 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i]))
2427 static int setup_channel_queue(struct comedi_device *dev,
2428 const struct comedi_cmd *cmd)
2430 const struct pcidas64_board *board = dev->board_ptr;
2431 struct pcidas64_private *devpriv = dev->private;
2432 unsigned short bits;
2435 if (board->layout != LAYOUT_4020) {
2436 if (use_internal_queue_6xxx(cmd)) {
2437 devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
2438 writew(devpriv->hw_config_bits,
2439 devpriv->main_iobase + HW_CONFIG_REG);
2442 bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0]));
2444 bits |= ai_range_bits_6xxx(dev,
2445 CR_RANGE(cmd->chanlist[0]));
2446 /* set single-ended / differential */
2447 bits |= se_diff_bit_6xxx(dev,
2448 CR_AREF(cmd->chanlist[0]) ==
2450 if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON)
2451 bits |= ADC_COMMON_BIT;
2452 /* set stop channel */
2453 writew(adc_chan_bits
2454 (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])),
2455 devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
2456 /* set start channel, and rest of settings */
2458 devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2460 /* use external queue */
2461 if (dev->write_subdev && dev->write_subdev->busy) {
2462 warn_external_queue(dev);
2465 devpriv->hw_config_bits |= EXT_QUEUE_BIT;
2466 writew(devpriv->hw_config_bits,
2467 devpriv->main_iobase + HW_CONFIG_REG);
2468 /* clear DAC buffer to prevent weird interactions */
2470 devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
2471 /* clear queue pointer */
2472 writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2473 /* load external queue */
2474 for (i = 0; i < cmd->chanlist_len; i++) {
2477 bits |= adc_chan_bits(CR_CHAN(cmd->
2480 bits |= ai_range_bits_6xxx(dev,
2484 /* set single-ended / differential */
2485 bits |= se_diff_bit_6xxx(dev,
2489 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON)
2490 bits |= ADC_COMMON_BIT;
2491 /* mark end of queue */
2492 if (i == cmd->chanlist_len - 1)
2493 bits |= QUEUE_EOSCAN_BIT |
2496 devpriv->main_iobase +
2497 ADC_QUEUE_FIFO_REG);
2500 * doing a queue clear is not specified in board docs,
2501 * but required for reliable operation
2503 writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2504 /* prime queue holding register */
2505 writew(0, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2508 unsigned short old_cal_range_bits = devpriv->i2c_cal_range_bits;
2510 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2511 /* select BNC inputs */
2512 devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
2514 for (i = 0; i < cmd->chanlist_len; i++) {
2515 unsigned int channel = CR_CHAN(cmd->chanlist[i]);
2516 unsigned int range = CR_RANGE(cmd->chanlist[i]);
2519 devpriv->i2c_cal_range_bits |=
2520 attenuate_bit(channel);
2522 devpriv->i2c_cal_range_bits &=
2523 ~attenuate_bit(channel);
2526 * update calibration/range i2c register only if necessary,
2527 * as it is very slow
2529 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
2530 u8 i2c_data = devpriv->i2c_cal_range_bits;
2532 i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2539 static inline void load_first_dma_descriptor(struct comedi_device *dev,
2540 unsigned int dma_channel,
2541 unsigned int descriptor_bits)
2543 struct pcidas64_private *devpriv = dev->private;
2546 * The transfer size, pci address, and local address registers
2547 * are supposedly unused during chained dma,
2548 * but I have found that left over values from last operation
2549 * occasionally cause problems with transfer of first dma
2550 * block. Initializing them to zero seems to fix the problem.
2553 writel(0, devpriv->plx9080_iobase + PLX_REG_DMASIZ1);
2554 writel(0, devpriv->plx9080_iobase + PLX_REG_DMAPADR1);
2555 writel(0, devpriv->plx9080_iobase + PLX_REG_DMALADR1);
2556 writel(descriptor_bits,
2557 devpriv->plx9080_iobase + PLX_REG_DMADPR1);
2559 writel(0, devpriv->plx9080_iobase + PLX_REG_DMASIZ0);
2560 writel(0, devpriv->plx9080_iobase + PLX_REG_DMAPADR0);
2561 writel(0, devpriv->plx9080_iobase + PLX_REG_DMALADR0);
2562 writel(descriptor_bits,
2563 devpriv->plx9080_iobase + PLX_REG_DMADPR0);
2567 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2569 const struct pcidas64_board *board = dev->board_ptr;
2570 struct pcidas64_private *devpriv = dev->private;
2571 struct comedi_async *async = s->async;
2572 struct comedi_cmd *cmd = &async->cmd;
2575 unsigned long flags;
2578 disable_ai_pacing(dev);
2581 retval = setup_channel_queue(dev, cmd);
2585 /* make sure internal calibration source is turned off */
2586 writew(0, devpriv->main_iobase + CALIBRATION_REG);
2588 set_ai_pacing(dev, cmd);
2590 setup_sample_counters(dev, cmd);
2592 enable_ai_interrupts(dev, cmd);
2594 spin_lock_irqsave(&dev->spinlock, flags);
2595 /* set mode, allow conversions through software gate */
2596 devpriv->adc_control1_bits |= ADC_SW_GATE_BIT;
2597 devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
2598 if (board->layout != LAYOUT_4020) {
2599 devpriv->adc_control1_bits &= ~ADC_MODE_MASK;
2600 if (cmd->convert_src == TRIG_EXT)
2601 /* good old mode 13 */
2602 devpriv->adc_control1_bits |= adc_mode_bits(13);
2604 /* mode 8. What else could you need? */
2605 devpriv->adc_control1_bits |= adc_mode_bits(8);
2607 devpriv->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK;
2608 if (cmd->chanlist_len == 4)
2609 devpriv->adc_control1_bits |= FOUR_CHANNEL_4020_BITS;
2610 else if (cmd->chanlist_len == 2)
2611 devpriv->adc_control1_bits |= TWO_CHANNEL_4020_BITS;
2612 devpriv->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK;
2613 devpriv->adc_control1_bits |=
2614 adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0]));
2615 devpriv->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK;
2616 devpriv->adc_control1_bits |=
2617 adc_hi_chan_4020_bits(CR_CHAN(cmd->chanlist
2618 [cmd->chanlist_len - 1]));
2620 writew(devpriv->adc_control1_bits,
2621 devpriv->main_iobase + ADC_CONTROL1_REG);
2622 spin_unlock_irqrestore(&dev->spinlock, flags);
2624 /* clear adc buffer */
2625 writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
2627 if ((cmd->flags & CMDF_WAKE_EOS) == 0 ||
2628 board->layout == LAYOUT_4020) {
2629 devpriv->ai_dma_index = 0;
2631 /* set dma transfer size */
2632 for (i = 0; i < ai_dma_ring_count(board); i++)
2633 devpriv->ai_dma_desc[i].transfer_size =
2634 cpu_to_le32(dma_transfer_size(dev) *
2637 /* give location of first dma descriptor */
2638 load_first_dma_descriptor(dev, 1,
2639 devpriv->ai_dma_desc_bus_addr |
2640 PLX_DMADPR_DESCPCI |
2642 PLX_DMADPR_XFERL2P);
2644 dma_start_sync(dev, 1);
2647 if (board->layout == LAYOUT_4020) {
2648 /* set source for external triggers */
2650 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg))
2651 bits |= EXT_START_TRIG_BNC_BIT;
2652 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg))
2653 bits |= EXT_STOP_TRIG_BNC_BIT;
2654 writew(bits, devpriv->main_iobase + DAQ_ATRIG_LOW_4020_REG);
2657 spin_lock_irqsave(&dev->spinlock, flags);
2659 /* enable pacing, triggering, etc */
2660 bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT;
2661 if (cmd->flags & CMDF_WAKE_EOS)
2662 bits |= ADC_DMA_DISABLE_BIT;
2663 /* set start trigger */
2664 if (cmd->start_src == TRIG_EXT) {
2665 bits |= ADC_START_TRIG_EXT_BITS;
2666 if (cmd->start_arg & CR_INVERT)
2667 bits |= ADC_START_TRIG_FALLING_BIT;
2668 } else if (cmd->start_src == TRIG_NOW) {
2669 bits |= ADC_START_TRIG_SOFT_BITS;
2671 if (use_hw_sample_counter(cmd))
2672 bits |= ADC_SAMPLE_COUNTER_EN_BIT;
2673 writew(bits, devpriv->main_iobase + ADC_CONTROL0_REG);
2675 devpriv->ai_cmd_running = 1;
2677 spin_unlock_irqrestore(&dev->spinlock, flags);
2679 /* start acquisition */
2680 if (cmd->start_src == TRIG_NOW)
2681 writew(0, devpriv->main_iobase + ADC_START_REG);
2686 /* read num_samples from 16 bit wide ai fifo */
2687 static void pio_drain_ai_fifo_16(struct comedi_device *dev)
2689 struct pcidas64_private *devpriv = dev->private;
2690 struct comedi_subdevice *s = dev->read_subdev;
2693 int read_segment, read_index, write_segment, write_index;
2697 /* get least significant 15 bits */
2698 read_index = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2700 write_index = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) &
2703 * Get most significant bits (grey code).
2704 * Different boards use different code so use a scheme
2705 * that doesn't depend on encoding. This read must
2706 * occur after reading least significant 15 bits to avoid race
2707 * with fifo switching to next segment.
2709 prepost_bits = readw(devpriv->main_iobase + PREPOST_REG);
2712 * if read and write pointers are not on the same fifo segment,
2713 * read to the end of the read segment
2715 read_segment = adc_upper_read_ptr_code(prepost_bits);
2716 write_segment = adc_upper_write_ptr_code(prepost_bits);
2718 if (read_segment != write_segment)
2720 devpriv->ai_fifo_segment_length - read_index;
2722 num_samples = write_index - read_index;
2723 if (num_samples < 0) {
2724 dev_err(dev->class_dev,
2725 "cb_pcidas64: bug! num_samples < 0\n");
2729 num_samples = comedi_nsamples_left(s, num_samples);
2730 if (num_samples == 0)
2733 for (i = 0; i < num_samples; i++) {
2736 val = readw(devpriv->main_iobase + ADC_FIFO_REG);
2737 comedi_buf_write_samples(s, &val, 1);
2740 } while (read_segment != write_segment);
2744 * Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of
2745 * pointers. The pci-4020 hardware only supports dma transfers (it only
2746 * supports the use of pio for draining the last remaining points from the
2747 * fifo when a data acquisition operation has completed).
2749 static void pio_drain_ai_fifo_32(struct comedi_device *dev)
2751 struct pcidas64_private *devpriv = dev->private;
2752 struct comedi_subdevice *s = dev->read_subdev;
2753 unsigned int nsamples;
2757 readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2759 readw(devpriv->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2761 nsamples = comedi_nsamples_left(s, 100000);
2762 for (i = 0; read_code != write_code && i < nsamples;) {
2765 fifo_data = readl(dev->mmio + ADC_FIFO_REG);
2766 val = fifo_data & 0xffff;
2767 comedi_buf_write_samples(s, &val, 1);
2770 val = (fifo_data >> 16) & 0xffff;
2771 comedi_buf_write_samples(s, &val, 1);
2774 read_code = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2780 static void pio_drain_ai_fifo(struct comedi_device *dev)
2782 const struct pcidas64_board *board = dev->board_ptr;
2784 if (board->layout == LAYOUT_4020)
2785 pio_drain_ai_fifo_32(dev);
2787 pio_drain_ai_fifo_16(dev);
2790 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
2792 const struct pcidas64_board *board = dev->board_ptr;
2793 struct pcidas64_private *devpriv = dev->private;
2794 struct comedi_subdevice *s = dev->read_subdev;
2795 u32 next_transfer_addr;
2797 int num_samples = 0;
2798 void __iomem *pci_addr_reg;
2800 pci_addr_reg = devpriv->plx9080_iobase + PLX_REG_DMAPADR(channel);
2802 /* loop until we have read all the full buffers */
2803 for (j = 0, next_transfer_addr = readl(pci_addr_reg);
2804 (next_transfer_addr <
2805 devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] ||
2806 next_transfer_addr >=
2807 devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] +
2808 DMA_BUFFER_SIZE) && j < ai_dma_ring_count(board); j++) {
2809 /* transfer data from dma buffer to comedi buffer */
2810 num_samples = comedi_nsamples_left(s, dma_transfer_size(dev));
2811 comedi_buf_write_samples(s,
2812 devpriv->ai_buffer[devpriv->ai_dma_index],
2814 devpriv->ai_dma_index = (devpriv->ai_dma_index + 1) %
2815 ai_dma_ring_count(board);
2818 * XXX check for dma ring buffer overrun
2819 * (use end-of-chain bit to mark last unused buffer)
2823 static void handle_ai_interrupt(struct comedi_device *dev,
2824 unsigned short status,
2825 unsigned int plx_status)
2827 const struct pcidas64_board *board = dev->board_ptr;
2828 struct pcidas64_private *devpriv = dev->private;
2829 struct comedi_subdevice *s = dev->read_subdev;
2830 struct comedi_async *async = s->async;
2831 struct comedi_cmd *cmd = &async->cmd;
2833 unsigned long flags;
2835 /* check for fifo overrun */
2836 if (status & ADC_OVERRUN_BIT) {
2837 dev_err(dev->class_dev, "fifo overrun\n");
2838 async->events |= COMEDI_CB_ERROR;
2840 /* spin lock makes sure no one else changes plx dma control reg */
2841 spin_lock_irqsave(&dev->spinlock, flags);
2842 dma1_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR1);
2843 if (plx_status & PLX_INTCSR_DMA1IA) { /* dma chan 1 interrupt */
2844 writeb((dma1_status & PLX_DMACSR_ENABLE) | PLX_DMACSR_CLEARINTR,
2845 devpriv->plx9080_iobase + PLX_REG_DMACSR1);
2847 if (dma1_status & PLX_DMACSR_ENABLE)
2848 drain_dma_buffers(dev, 1);
2850 spin_unlock_irqrestore(&dev->spinlock, flags);
2852 /* drain fifo with pio */
2853 if ((status & ADC_DONE_BIT) ||
2854 ((cmd->flags & CMDF_WAKE_EOS) &&
2855 (status & ADC_INTR_PENDING_BIT) &&
2856 (board->layout != LAYOUT_4020))) {
2857 spin_lock_irqsave(&dev->spinlock, flags);
2858 if (devpriv->ai_cmd_running) {
2859 spin_unlock_irqrestore(&dev->spinlock, flags);
2860 pio_drain_ai_fifo(dev);
2862 spin_unlock_irqrestore(&dev->spinlock, flags);
2865 /* if we are have all the data, then quit */
2866 if ((cmd->stop_src == TRIG_COUNT &&
2867 async->scans_done >= cmd->stop_arg) ||
2868 (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT)))
2869 async->events |= COMEDI_CB_EOA;
2871 comedi_handle_events(dev, s);
2874 static inline unsigned int prev_ao_dma_index(struct comedi_device *dev)
2876 struct pcidas64_private *devpriv = dev->private;
2877 unsigned int buffer_index;
2879 if (devpriv->ao_dma_index == 0)
2880 buffer_index = AO_DMA_RING_COUNT - 1;
2882 buffer_index = devpriv->ao_dma_index - 1;
2883 return buffer_index;
2886 static int last_ao_dma_load_completed(struct comedi_device *dev)
2888 struct pcidas64_private *devpriv = dev->private;
2889 unsigned int buffer_index;
2890 unsigned int transfer_address;
2891 unsigned short dma_status;
2893 buffer_index = prev_ao_dma_index(dev);
2894 dma_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR0);
2895 if ((dma_status & PLX_DMACSR_DONE) == 0)
2899 readl(devpriv->plx9080_iobase + PLX_REG_DMAPADR0);
2900 if (transfer_address != devpriv->ao_buffer_bus_addr[buffer_index])
2906 static inline int ao_dma_needs_restart(struct comedi_device *dev,
2907 unsigned short dma_status)
2909 if ((dma_status & PLX_DMACSR_DONE) == 0 ||
2910 (dma_status & PLX_DMACSR_ENABLE) == 0)
2912 if (last_ao_dma_load_completed(dev))
2918 static void restart_ao_dma(struct comedi_device *dev)
2920 struct pcidas64_private *devpriv = dev->private;
2921 unsigned int dma_desc_bits;
2923 dma_desc_bits = readl(devpriv->plx9080_iobase + PLX_REG_DMADPR0);
2924 dma_desc_bits &= ~PLX_DMADPR_CHAINEND;
2925 load_first_dma_descriptor(dev, 0, dma_desc_bits);
2927 dma_start_sync(dev, 0);
2930 static unsigned int cb_pcidas64_ao_fill_buffer(struct comedi_device *dev,
2931 struct comedi_subdevice *s,
2932 unsigned short *dest,
2933 unsigned int max_bytes)
2935 unsigned int nsamples = comedi_bytes_to_samples(s, max_bytes);
2936 unsigned int actual_bytes;
2938 nsamples = comedi_nsamples_left(s, nsamples);
2939 actual_bytes = comedi_buf_read_samples(s, dest, nsamples);
2941 return comedi_bytes_to_samples(s, actual_bytes);
2944 static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
2945 const struct comedi_cmd *cmd)
2947 struct pcidas64_private *devpriv = dev->private;
2948 struct comedi_subdevice *s = dev->write_subdev;
2949 unsigned int buffer_index = devpriv->ao_dma_index;
2950 unsigned int prev_buffer_index = prev_ao_dma_index(dev);
2951 unsigned int nsamples;
2952 unsigned int nbytes;
2953 unsigned int next_bits;
2955 nsamples = cb_pcidas64_ao_fill_buffer(dev, s,
2956 devpriv->ao_buffer[buffer_index],
2961 nbytes = comedi_samples_to_bytes(s, nsamples);
2962 devpriv->ao_dma_desc[buffer_index].transfer_size = cpu_to_le32(nbytes);
2963 /* set end of chain bit so we catch underruns */
2964 next_bits = le32_to_cpu(devpriv->ao_dma_desc[buffer_index].next);
2965 next_bits |= PLX_DMADPR_CHAINEND;
2966 devpriv->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
2968 * clear end of chain bit on previous buffer now that we have set it
2969 * for the last buffer
2971 next_bits = le32_to_cpu(devpriv->ao_dma_desc[prev_buffer_index].next);
2972 next_bits &= ~PLX_DMADPR_CHAINEND;
2973 devpriv->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
2975 devpriv->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
2980 static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
2982 struct pcidas64_private *devpriv = dev->private;
2983 unsigned int num_bytes;
2984 unsigned int next_transfer_addr;
2985 void __iomem *pci_addr_reg = devpriv->plx9080_iobase + PLX_REG_DMAPADR0;
2986 unsigned int buffer_index;
2989 buffer_index = devpriv->ao_dma_index;
2990 /* don't overwrite data that hasn't been transferred yet */
2991 next_transfer_addr = readl(pci_addr_reg);
2992 if (next_transfer_addr >=
2993 devpriv->ao_buffer_bus_addr[buffer_index] &&
2994 next_transfer_addr <
2995 devpriv->ao_buffer_bus_addr[buffer_index] +
2998 num_bytes = load_ao_dma_buffer(dev, cmd);
2999 } while (num_bytes >= DMA_BUFFER_SIZE);
3002 static void handle_ao_interrupt(struct comedi_device *dev,
3003 unsigned short status, unsigned int plx_status)
3005 struct pcidas64_private *devpriv = dev->private;
3006 struct comedi_subdevice *s = dev->write_subdev;
3007 struct comedi_async *async;
3008 struct comedi_cmd *cmd;
3010 unsigned long flags;
3012 /* board might not support ao, in which case write_subdev is NULL */
3018 /* spin lock makes sure no one else changes plx dma control reg */
3019 spin_lock_irqsave(&dev->spinlock, flags);
3020 dma0_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR0);
3021 if (plx_status & PLX_INTCSR_DMA0IA) { /* dma chan 0 interrupt */
3022 if ((dma0_status & PLX_DMACSR_ENABLE) &&
3023 !(dma0_status & PLX_DMACSR_DONE)) {
3024 writeb(PLX_DMACSR_ENABLE | PLX_DMACSR_CLEARINTR,
3025 devpriv->plx9080_iobase + PLX_REG_DMACSR0);
3027 writeb(PLX_DMACSR_CLEARINTR,
3028 devpriv->plx9080_iobase + PLX_REG_DMACSR0);
3030 spin_unlock_irqrestore(&dev->spinlock, flags);
3031 if (dma0_status & PLX_DMACSR_ENABLE) {
3032 load_ao_dma(dev, cmd);
3033 /* try to recover from dma end-of-chain event */
3034 if (ao_dma_needs_restart(dev, dma0_status))
3035 restart_ao_dma(dev);
3038 spin_unlock_irqrestore(&dev->spinlock, flags);
3041 if ((status & DAC_DONE_BIT)) {
3042 if ((cmd->stop_src == TRIG_COUNT &&
3043 async->scans_done >= cmd->stop_arg) ||
3044 last_ao_dma_load_completed(dev))
3045 async->events |= COMEDI_CB_EOA;
3047 async->events |= COMEDI_CB_ERROR;
3049 comedi_handle_events(dev, s);
3052 static irqreturn_t handle_interrupt(int irq, void *d)
3054 struct comedi_device *dev = d;
3055 struct pcidas64_private *devpriv = dev->private;
3056 unsigned short status;
3060 plx_status = readl(devpriv->plx9080_iobase + PLX_REG_INTCSR);
3061 status = readw(devpriv->main_iobase + HW_STATUS_REG);
3064 * an interrupt before all the postconfig stuff gets done could
3065 * cause a NULL dereference if we continue through the
3071 handle_ai_interrupt(dev, status, plx_status);
3072 handle_ao_interrupt(dev, status, plx_status);
3074 /* clear possible plx9080 interrupt sources */
3075 if (plx_status & PLX_INTCSR_LDBIA) {
3076 /* clear local doorbell interrupt */
3077 plx_bits = readl(devpriv->plx9080_iobase + PLX_REG_L2PDBELL);
3078 writel(plx_bits, devpriv->plx9080_iobase + PLX_REG_L2PDBELL);
3084 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3086 struct pcidas64_private *devpriv = dev->private;
3087 unsigned long flags;
3089 spin_lock_irqsave(&dev->spinlock, flags);
3090 if (devpriv->ai_cmd_running == 0) {
3091 spin_unlock_irqrestore(&dev->spinlock, flags);
3094 devpriv->ai_cmd_running = 0;
3095 spin_unlock_irqrestore(&dev->spinlock, flags);
3097 disable_ai_pacing(dev);
3104 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
3105 struct comedi_insn *insn, unsigned int *data)
3107 const struct pcidas64_board *board = dev->board_ptr;
3108 struct pcidas64_private *devpriv = dev->private;
3109 int chan = CR_CHAN(insn->chanspec);
3110 int range = CR_RANGE(insn->chanspec);
3112 /* do some initializing */
3113 writew(0, devpriv->main_iobase + DAC_CONTROL0_REG);
3116 set_dac_range_bits(dev, &devpriv->dac_control1_bits, chan, range);
3117 writew(devpriv->dac_control1_bits,
3118 devpriv->main_iobase + DAC_CONTROL1_REG);
3120 /* write to channel */
3121 if (board->layout == LAYOUT_4020) {
3122 writew(data[0] & 0xff,
3123 devpriv->main_iobase + dac_lsb_4020_reg(chan));
3124 writew((data[0] >> 8) & 0xf,
3125 devpriv->main_iobase + dac_msb_4020_reg(chan));
3127 writew(data[0], devpriv->main_iobase + dac_convert_reg(chan));
3130 /* remember output value */
3131 s->readback[chan] = data[0];
3136 static void set_dac_control0_reg(struct comedi_device *dev,
3137 const struct comedi_cmd *cmd)
3139 struct pcidas64_private *devpriv = dev->private;
3140 unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT |
3141 WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT;
3143 if (cmd->start_src == TRIG_EXT) {
3144 bits |= WAVEFORM_TRIG_EXT_BITS;
3145 if (cmd->start_arg & CR_INVERT)
3146 bits |= WAVEFORM_TRIG_FALLING_BIT;
3148 bits |= WAVEFORM_TRIG_SOFT_BITS;
3150 if (cmd->scan_begin_src == TRIG_EXT) {
3151 bits |= DAC_EXT_UPDATE_ENABLE_BIT;
3152 if (cmd->scan_begin_arg & CR_INVERT)
3153 bits |= DAC_EXT_UPDATE_FALLING_BIT;
3155 writew(bits, devpriv->main_iobase + DAC_CONTROL0_REG);
3158 static void set_dac_control1_reg(struct comedi_device *dev,
3159 const struct comedi_cmd *cmd)
3161 struct pcidas64_private *devpriv = dev->private;
3164 for (i = 0; i < cmd->chanlist_len; i++) {
3167 channel = CR_CHAN(cmd->chanlist[i]);
3168 range = CR_RANGE(cmd->chanlist[i]);
3169 set_dac_range_bits(dev, &devpriv->dac_control1_bits, channel,
3172 devpriv->dac_control1_bits |= DAC_SW_GATE_BIT;
3173 writew(devpriv->dac_control1_bits,
3174 devpriv->main_iobase + DAC_CONTROL1_REG);
3177 static void set_dac_select_reg(struct comedi_device *dev,
3178 const struct comedi_cmd *cmd)
3180 struct pcidas64_private *devpriv = dev->private;
3182 unsigned int first_channel, last_channel;
3184 first_channel = CR_CHAN(cmd->chanlist[0]);
3185 last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
3186 if (last_channel < first_channel)
3187 dev_err(dev->class_dev,
3188 "bug! last ao channel < first ao channel\n");
3190 bits = (first_channel & 0x7) | (last_channel & 0x7) << 3;
3192 writew(bits, devpriv->main_iobase + DAC_SELECT_REG);
3195 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags)
3197 return get_divisor(ns, flags) - 2;
3200 static void set_dac_interval_regs(struct comedi_device *dev,
3201 const struct comedi_cmd *cmd)
3203 struct pcidas64_private *devpriv = dev->private;
3204 unsigned int divisor;
3206 if (cmd->scan_begin_src != TRIG_TIMER)
3209 divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags);
3210 if (divisor > max_counter_value) {
3211 dev_err(dev->class_dev, "bug! ao divisor too big\n");
3212 divisor = max_counter_value;
3214 writew(divisor & 0xffff,
3215 devpriv->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG);
3216 writew((divisor >> 16) & 0xff,
3217 devpriv->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG);
3220 static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3222 struct pcidas64_private *devpriv = dev->private;
3223 struct comedi_subdevice *s = dev->write_subdev;
3224 unsigned int nsamples;
3225 unsigned int nbytes;
3229 * clear queue pointer too, since external queue has
3230 * weird interactions with ao fifo
3232 writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
3233 writew(0, devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
3235 nsamples = cb_pcidas64_ao_fill_buffer(dev, s,
3236 devpriv->ao_bounce_buffer,
3241 for (i = 0; i < nsamples; i++) {
3242 writew(devpriv->ao_bounce_buffer[i],
3243 devpriv->main_iobase + DAC_FIFO_REG);
3246 if (cmd->stop_src == TRIG_COUNT &&
3247 s->async->scans_done >= cmd->stop_arg)
3250 nbytes = load_ao_dma_buffer(dev, cmd);
3253 load_ao_dma(dev, cmd);
3255 dma_start_sync(dev, 0);
3260 static inline int external_ai_queue_in_use(struct comedi_device *dev,
3261 struct comedi_subdevice *s,
3262 struct comedi_cmd *cmd)
3264 const struct pcidas64_board *board = dev->board_ptr;
3268 if (board->layout == LAYOUT_4020)
3270 else if (use_internal_queue_6xxx(cmd))
3275 static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3276 unsigned int trig_num)
3278 struct pcidas64_private *devpriv = dev->private;
3279 struct comedi_cmd *cmd = &s->async->cmd;
3282 if (trig_num != cmd->start_arg)
3285 retval = prep_ao_dma(dev, cmd);
3289 set_dac_control0_reg(dev, cmd);
3291 if (cmd->start_src == TRIG_INT)
3292 writew(0, devpriv->main_iobase + DAC_START_REG);
3294 s->async->inttrig = NULL;
3299 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3301 struct pcidas64_private *devpriv = dev->private;
3302 struct comedi_cmd *cmd = &s->async->cmd;
3304 if (external_ai_queue_in_use(dev, s, cmd)) {
3305 warn_external_queue(dev);
3308 /* disable analog output system during setup */
3309 writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3311 devpriv->ao_dma_index = 0;
3313 set_dac_select_reg(dev, cmd);
3314 set_dac_interval_regs(dev, cmd);
3315 load_first_dma_descriptor(dev, 0, devpriv->ao_dma_desc_bus_addr |
3316 PLX_DMADPR_DESCPCI | PLX_DMADPR_TCINTR);
3318 set_dac_control1_reg(dev, cmd);
3319 s->async->inttrig = ao_inttrig;
3324 static int cb_pcidas64_ao_check_chanlist(struct comedi_device *dev,
3325 struct comedi_subdevice *s,
3326 struct comedi_cmd *cmd)
3328 unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
3331 for (i = 1; i < cmd->chanlist_len; i++) {
3332 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3334 if (chan != (chan0 + i)) {
3335 dev_dbg(dev->class_dev,
3336 "chanlist must use consecutive channels\n");
3344 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3345 struct comedi_cmd *cmd)
3347 const struct pcidas64_board *board = dev->board_ptr;
3349 unsigned int tmp_arg;
3351 /* Step 1 : check if triggers are trivially valid */
3353 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3354 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3355 TRIG_TIMER | TRIG_EXT);
3356 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3357 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3358 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3363 /* Step 2a : make sure trigger sources are unique */
3365 err |= comedi_check_trigger_is_unique(cmd->start_src);
3366 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3368 /* Step 2b : and mutually compatible */
3370 if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
3372 if (cmd->stop_src != TRIG_COUNT &&
3373 cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
3379 /* Step 3: check if arguments are trivially valid */
3381 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3383 if (cmd->scan_begin_src == TRIG_TIMER) {
3384 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3385 board->ao_scan_speed);
3386 if (get_ao_divisor(cmd->scan_begin_arg, cmd->flags) >
3387 max_counter_value) {
3388 cmd->scan_begin_arg = (max_counter_value + 2) *
3394 err |= comedi_check_trigger_arg_min(&cmd->chanlist_len, 1);
3395 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3401 /* step 4: fix up any arguments */
3403 if (cmd->scan_begin_src == TRIG_TIMER) {
3404 tmp_arg = cmd->scan_begin_arg;
3405 cmd->scan_begin_arg = get_divisor(cmd->scan_begin_arg,
3406 cmd->flags) * TIMER_BASE;
3407 if (tmp_arg != cmd->scan_begin_arg)
3414 /* Step 5: check channel list if it exists */
3415 if (cmd->chanlist && cmd->chanlist_len > 0)
3416 err |= cb_pcidas64_ao_check_chanlist(dev, s, cmd);
3424 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3426 struct pcidas64_private *devpriv = dev->private;
3428 writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3433 static int dio_callback_4020(struct comedi_device *dev,
3434 int dir, int port, int data, unsigned long iobase)
3436 struct pcidas64_private *devpriv = dev->private;
3439 writew(data, devpriv->main_iobase + iobase + 2 * port);
3442 return readw(devpriv->main_iobase + iobase + 2 * port);
3445 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
3446 struct comedi_insn *insn, unsigned int *data)
3450 bits = readb(dev->mmio + DI_REG);
3458 static int do_wbits(struct comedi_device *dev,
3459 struct comedi_subdevice *s,
3460 struct comedi_insn *insn,
3463 if (comedi_dio_update_state(s, data))
3464 writeb(s->state, dev->mmio + DO_REG);
3471 static int dio_60xx_config_insn(struct comedi_device *dev,
3472 struct comedi_subdevice *s,
3473 struct comedi_insn *insn,
3478 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3482 writeb(s->io_bits, dev->mmio + DIO_DIRECTION_60XX_REG);
3487 static int dio_60xx_wbits(struct comedi_device *dev,
3488 struct comedi_subdevice *s,
3489 struct comedi_insn *insn,
3492 if (comedi_dio_update_state(s, data))
3493 writeb(s->state, dev->mmio + DIO_DATA_60XX_REG);
3495 data[1] = readb(dev->mmio + DIO_DATA_60XX_REG);
3501 * pci-6025 8800 caldac:
3502 * address 0 == dac channel 0 offset
3503 * address 1 == dac channel 0 gain
3504 * address 2 == dac channel 1 offset
3505 * address 3 == dac channel 1 gain
3506 * address 4 == fine adc offset
3507 * address 5 == coarse adc offset
3508 * address 6 == coarse adc gain
3509 * address 7 == fine adc gain
3512 * pci-6402/16 uses all 8 channels for dac:
3513 * address 0 == dac channel 0 fine gain
3514 * address 1 == dac channel 0 coarse gain
3515 * address 2 == dac channel 0 coarse offset
3516 * address 3 == dac channel 1 coarse offset
3517 * address 4 == dac channel 1 fine gain
3518 * address 5 == dac channel 1 coarse gain
3519 * address 6 == dac channel 0 fine offset
3520 * address 7 == dac channel 1 fine offset
3523 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
3526 struct pcidas64_private *devpriv = dev->private;
3527 static const int num_caldac_channels = 8;
3528 static const int bitstream_length = 11;
3529 unsigned int bitstream = ((address & 0x7) << 8) | value;
3530 unsigned int bit, register_bits;
3531 static const int caldac_8800_udelay = 1;
3533 if (address >= num_caldac_channels) {
3534 dev_err(dev->class_dev, "illegal caldac channel\n");
3537 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3539 if (bitstream & bit)
3540 register_bits |= SERIAL_DATA_IN_BIT;
3541 udelay(caldac_8800_udelay);
3542 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3543 register_bits |= SERIAL_CLOCK_BIT;
3544 udelay(caldac_8800_udelay);
3545 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3547 udelay(caldac_8800_udelay);
3548 writew(SELECT_8800_BIT, devpriv->main_iobase + CALIBRATION_REG);
3549 udelay(caldac_8800_udelay);
3550 writew(0, devpriv->main_iobase + CALIBRATION_REG);
3551 udelay(caldac_8800_udelay);
3556 static int caldac_i2c_write(struct comedi_device *dev,
3557 unsigned int caldac_channel, unsigned int value)
3562 /* manual has gain and offset bits switched */
3569 NOT_CLEAR_REGISTERS = 0x20,
3572 switch (caldac_channel) {
3573 case 0: /* chan 0 offset */
3574 i2c_addr = CALDAC0_I2C_ADDR;
3575 serial_bytes[0] = OFFSET_0_2;
3577 case 1: /* chan 1 offset */
3578 i2c_addr = CALDAC0_I2C_ADDR;
3579 serial_bytes[0] = OFFSET_1_3;
3581 case 2: /* chan 2 offset */
3582 i2c_addr = CALDAC1_I2C_ADDR;
3583 serial_bytes[0] = OFFSET_0_2;
3585 case 3: /* chan 3 offset */
3586 i2c_addr = CALDAC1_I2C_ADDR;
3587 serial_bytes[0] = OFFSET_1_3;
3589 case 4: /* chan 0 gain */
3590 i2c_addr = CALDAC0_I2C_ADDR;
3591 serial_bytes[0] = GAIN_0_2;
3593 case 5: /* chan 1 gain */
3594 i2c_addr = CALDAC0_I2C_ADDR;
3595 serial_bytes[0] = GAIN_1_3;
3597 case 6: /* chan 2 gain */
3598 i2c_addr = CALDAC1_I2C_ADDR;
3599 serial_bytes[0] = GAIN_0_2;
3601 case 7: /* chan 3 gain */
3602 i2c_addr = CALDAC1_I2C_ADDR;
3603 serial_bytes[0] = GAIN_1_3;
3606 dev_err(dev->class_dev, "invalid caldac channel\n");
3609 serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf);
3610 serial_bytes[2] = value & 0xff;
3611 i2c_write(dev, i2c_addr, serial_bytes, 3);
3615 static void caldac_write(struct comedi_device *dev, unsigned int channel,
3618 const struct pcidas64_board *board = dev->board_ptr;
3620 switch (board->layout) {
3623 caldac_8800_write(dev, channel, value);
3626 caldac_i2c_write(dev, channel, value);
3633 static int cb_pcidas64_calib_insn_write(struct comedi_device *dev,
3634 struct comedi_subdevice *s,
3635 struct comedi_insn *insn,
3638 unsigned int chan = CR_CHAN(insn->chanspec);
3641 * Programming the calib device is slow. Only write the
3642 * last data value if the value has changed.
3645 unsigned int val = data[insn->n - 1];
3647 if (s->readback[chan] != val) {
3648 caldac_write(dev, chan, val);
3649 s->readback[chan] = val;
3656 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
3659 struct pcidas64_private *devpriv = dev->private;
3660 static const int bitstream_length = 10;
3661 unsigned int bit, register_bits;
3662 unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff);
3663 static const int ad8402_udelay = 1;
3665 register_bits = SELECT_8402_64XX_BIT;
3666 udelay(ad8402_udelay);
3667 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3669 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3670 if (bitstream & bit)
3671 register_bits |= SERIAL_DATA_IN_BIT;
3673 register_bits &= ~SERIAL_DATA_IN_BIT;
3674 udelay(ad8402_udelay);
3675 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3676 udelay(ad8402_udelay);
3677 writew(register_bits | SERIAL_CLOCK_BIT,
3678 devpriv->main_iobase + CALIBRATION_REG);
3681 udelay(ad8402_udelay);
3682 writew(0, devpriv->main_iobase + CALIBRATION_REG);
3685 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
3686 static int cb_pcidas64_ad8402_insn_write(struct comedi_device *dev,
3687 struct comedi_subdevice *s,
3688 struct comedi_insn *insn,
3691 unsigned int chan = CR_CHAN(insn->chanspec);
3694 * Programming the calib device is slow. Only write the
3695 * last data value if the value has changed.
3698 unsigned int val = data[insn->n - 1];
3700 if (s->readback[chan] != val) {
3701 ad8402_write(dev, chan, val);
3702 s->readback[chan] = val;
3709 static u16 read_eeprom(struct comedi_device *dev, u8 address)
3711 struct pcidas64_private *devpriv = dev->private;
3712 static const int bitstream_length = 11;
3713 static const int read_command = 0x6;
3714 unsigned int bitstream = (read_command << 8) | address;
3716 void __iomem * const plx_control_addr =
3717 devpriv->plx9080_iobase + PLX_REG_CNTRL;
3719 static const int value_length = 16;
3720 static const int eeprom_udelay = 1;
3722 udelay(eeprom_udelay);
3723 devpriv->plx_control_bits &= ~PLX_CNTRL_EESK & ~PLX_CNTRL_EECS;
3724 /* make sure we don't send anything to the i2c bus on 4020 */
3725 devpriv->plx_control_bits |= PLX_CNTRL_USERO;
3726 writel(devpriv->plx_control_bits, plx_control_addr);
3727 /* activate serial eeprom */
3728 udelay(eeprom_udelay);
3729 devpriv->plx_control_bits |= PLX_CNTRL_EECS;
3730 writel(devpriv->plx_control_bits, plx_control_addr);
3732 /* write read command and desired memory address */
3733 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3734 /* set bit to be written */
3735 udelay(eeprom_udelay);
3736 if (bitstream & bit)
3737 devpriv->plx_control_bits |= PLX_CNTRL_EEWB;
3739 devpriv->plx_control_bits &= ~PLX_CNTRL_EEWB;
3740 writel(devpriv->plx_control_bits, plx_control_addr);
3742 udelay(eeprom_udelay);
3743 devpriv->plx_control_bits |= PLX_CNTRL_EESK;
3744 writel(devpriv->plx_control_bits, plx_control_addr);
3745 udelay(eeprom_udelay);
3746 devpriv->plx_control_bits &= ~PLX_CNTRL_EESK;
3747 writel(devpriv->plx_control_bits, plx_control_addr);
3749 /* read back value from eeprom memory location */
3751 for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
3753 udelay(eeprom_udelay);
3754 devpriv->plx_control_bits |= PLX_CNTRL_EESK;
3755 writel(devpriv->plx_control_bits, plx_control_addr);
3756 udelay(eeprom_udelay);
3757 devpriv->plx_control_bits &= ~PLX_CNTRL_EESK;
3758 writel(devpriv->plx_control_bits, plx_control_addr);
3759 udelay(eeprom_udelay);
3760 if (readl(plx_control_addr) & PLX_CNTRL_EERB)
3764 /* deactivate eeprom serial input */
3765 udelay(eeprom_udelay);
3766 devpriv->plx_control_bits &= ~PLX_CNTRL_EECS;
3767 writel(devpriv->plx_control_bits, plx_control_addr);
3772 static int eeprom_read_insn(struct comedi_device *dev,
3773 struct comedi_subdevice *s,
3774 struct comedi_insn *insn, unsigned int *data)
3776 data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec));
3781 /* Allocate and initialize the subdevice structures. */
3782 static int setup_subdevices(struct comedi_device *dev)
3784 const struct pcidas64_board *board = dev->board_ptr;
3785 struct pcidas64_private *devpriv = dev->private;
3786 struct comedi_subdevice *s;
3790 ret = comedi_alloc_subdevices(dev, 10);
3794 s = &dev->subdevices[0];
3795 /* analog input subdevice */
3796 dev->read_subdev = s;
3797 s->type = COMEDI_SUBD_AI;
3798 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ;
3799 if (board->layout == LAYOUT_60XX)
3800 s->subdev_flags |= SDF_COMMON | SDF_DIFF;
3801 else if (board->layout == LAYOUT_64XX)
3802 s->subdev_flags |= SDF_DIFF;
3803 /* XXX Number of inputs in differential mode is ignored */
3804 s->n_chan = board->ai_se_chans;
3805 s->len_chanlist = 0x2000;
3806 s->maxdata = (1 << board->ai_bits) - 1;
3807 s->range_table = board->ai_range_table;
3808 s->insn_read = ai_rinsn;
3809 s->insn_config = ai_config_insn;
3811 s->do_cmdtest = ai_cmdtest;
3812 s->cancel = ai_cancel;
3813 if (board->layout == LAYOUT_4020) {
3816 * set adc to read from inputs
3817 * (not internal calibration sources)
3819 devpriv->i2c_cal_range_bits = adc_src_4020_bits(4);
3820 /* set channels to +-5 volt input ranges */
3821 for (i = 0; i < s->n_chan; i++)
3822 devpriv->i2c_cal_range_bits |= attenuate_bit(i);
3823 data = devpriv->i2c_cal_range_bits;
3824 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data));
3827 /* analog output subdevice */
3828 s = &dev->subdevices[1];
3829 if (board->ao_nchan) {
3830 s->type = COMEDI_SUBD_AO;
3831 s->subdev_flags = SDF_READABLE | SDF_WRITABLE |
3832 SDF_GROUND | SDF_CMD_WRITE;
3833 s->n_chan = board->ao_nchan;
3834 s->maxdata = (1 << board->ao_bits) - 1;
3835 s->range_table = board->ao_range_table;
3836 s->insn_write = ao_winsn;
3838 ret = comedi_alloc_subdev_readback(s);
3842 if (ao_cmd_is_supported(board)) {
3843 dev->write_subdev = s;
3844 s->do_cmdtest = ao_cmdtest;
3846 s->len_chanlist = board->ao_nchan;
3847 s->cancel = ao_cancel;
3850 s->type = COMEDI_SUBD_UNUSED;
3854 s = &dev->subdevices[2];
3855 if (board->layout == LAYOUT_64XX) {
3856 s->type = COMEDI_SUBD_DI;
3857 s->subdev_flags = SDF_READABLE;
3860 s->range_table = &range_digital;
3861 s->insn_bits = di_rbits;
3863 s->type = COMEDI_SUBD_UNUSED;
3866 /* digital output */
3867 if (board->layout == LAYOUT_64XX) {
3868 s = &dev->subdevices[3];
3869 s->type = COMEDI_SUBD_DO;
3870 s->subdev_flags = SDF_WRITABLE;
3873 s->range_table = &range_digital;
3874 s->insn_bits = do_wbits;
3876 s->type = COMEDI_SUBD_UNUSED;
3880 s = &dev->subdevices[4];
3881 if (board->has_8255) {
3882 if (board->layout == LAYOUT_4020) {
3883 ret = subdev_8255_init(dev, s, dio_callback_4020,
3886 ret = subdev_8255_mm_init(dev, s, NULL,
3892 s->type = COMEDI_SUBD_UNUSED;
3895 /* 8 channel dio for 60xx */
3896 s = &dev->subdevices[5];
3897 if (board->layout == LAYOUT_60XX) {
3898 s->type = COMEDI_SUBD_DIO;
3899 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3902 s->range_table = &range_digital;
3903 s->insn_config = dio_60xx_config_insn;
3904 s->insn_bits = dio_60xx_wbits;
3906 s->type = COMEDI_SUBD_UNUSED;
3910 s = &dev->subdevices[6];
3911 s->type = COMEDI_SUBD_CALIB;
3912 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3914 if (board->layout == LAYOUT_4020)
3918 s->insn_write = cb_pcidas64_calib_insn_write;
3920 ret = comedi_alloc_subdev_readback(s);
3924 for (i = 0; i < s->n_chan; i++) {
3925 caldac_write(dev, i, s->maxdata / 2);
3926 s->readback[i] = s->maxdata / 2;
3929 /* 2 channel ad8402 potentiometer */
3930 s = &dev->subdevices[7];
3931 if (board->layout == LAYOUT_64XX) {
3932 s->type = COMEDI_SUBD_CALIB;
3933 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3936 s->insn_write = cb_pcidas64_ad8402_insn_write;
3938 ret = comedi_alloc_subdev_readback(s);
3942 for (i = 0; i < s->n_chan; i++) {
3943 ad8402_write(dev, i, s->maxdata / 2);
3944 s->readback[i] = s->maxdata / 2;
3947 s->type = COMEDI_SUBD_UNUSED;
3950 /* serial EEPROM, if present */
3951 s = &dev->subdevices[8];
3952 if (readl(devpriv->plx9080_iobase + PLX_REG_CNTRL) &
3953 PLX_CNTRL_EEPRESENT) {
3954 s->type = COMEDI_SUBD_MEMORY;
3955 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
3957 s->maxdata = 0xffff;
3958 s->insn_read = eeprom_read_insn;
3960 s->type = COMEDI_SUBD_UNUSED;
3963 /* user counter subd XXX */
3964 s = &dev->subdevices[9];
3965 s->type = COMEDI_SUBD_UNUSED;
3970 static int auto_attach(struct comedi_device *dev,
3971 unsigned long context)
3973 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
3974 const struct pcidas64_board *board = NULL;
3975 struct pcidas64_private *devpriv;
3976 u32 local_range, local_decode;
3979 if (context < ARRAY_SIZE(pcidas64_boards))
3980 board = &pcidas64_boards[context];
3983 dev->board_ptr = board;
3985 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
3989 retval = comedi_pci_enable(dev);
3992 pci_set_master(pcidev);
3994 /* Initialize dev->board_name */
3995 dev->board_name = board->name;
3997 devpriv->main_phys_iobase = pci_resource_start(pcidev, 2);
3998 devpriv->dio_counter_phys_iobase = pci_resource_start(pcidev, 3);
4000 devpriv->plx9080_iobase = pci_ioremap_bar(pcidev, 0);
4001 devpriv->main_iobase = pci_ioremap_bar(pcidev, 2);
4002 dev->mmio = pci_ioremap_bar(pcidev, 3);
4004 if (!devpriv->plx9080_iobase || !devpriv->main_iobase || !dev->mmio) {
4005 dev_warn(dev->class_dev, "failed to remap io memory\n");
4009 /* figure out what local addresses are */
4010 local_range = readl(devpriv->plx9080_iobase + PLX_REG_LAS0RR) &
4012 local_decode = readl(devpriv->plx9080_iobase + PLX_REG_LAS0BA) &
4013 local_range & PLX_LASBA_MEM_MASK;
4014 devpriv->local0_iobase = ((u32)devpriv->main_phys_iobase &
4015 ~local_range) | local_decode;
4016 local_range = readl(devpriv->plx9080_iobase + PLX_REG_LAS1RR) &
4018 local_decode = readl(devpriv->plx9080_iobase + PLX_REG_LAS1BA) &
4019 local_range & PLX_LASBA_MEM_MASK;
4020 devpriv->local1_iobase = ((u32)devpriv->dio_counter_phys_iobase &
4021 ~local_range) | local_decode;
4023 retval = alloc_and_init_dma_members(dev);
4027 devpriv->hw_revision =
4028 hw_revision(dev, readw(devpriv->main_iobase + HW_STATUS_REG));
4029 dev_dbg(dev->class_dev, "stc hardware revision %i\n",
4030 devpriv->hw_revision);
4032 init_stc_registers(dev);
4034 retval = request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
4035 "cb_pcidas64", dev);
4037 dev_dbg(dev->class_dev, "unable to allocate irq %u\n",
4041 dev->irq = pcidev->irq;
4042 dev_dbg(dev->class_dev, "irq %u\n", dev->irq);
4044 retval = setup_subdevices(dev);
4051 static void detach(struct comedi_device *dev)
4053 struct pcidas64_private *devpriv = dev->private;
4056 free_irq(dev->irq, dev);
4058 if (devpriv->plx9080_iobase) {
4059 disable_plx_interrupts(dev);
4060 iounmap(devpriv->plx9080_iobase);
4062 if (devpriv->main_iobase)
4063 iounmap(devpriv->main_iobase);
4067 comedi_pci_disable(dev);
4068 cb_pcidas64_free_dma(dev);
4071 static struct comedi_driver cb_pcidas64_driver = {
4072 .driver_name = "cb_pcidas64",
4073 .module = THIS_MODULE,
4074 .auto_attach = auto_attach,
4078 static int cb_pcidas64_pci_probe(struct pci_dev *dev,
4079 const struct pci_device_id *id)
4081 return comedi_pci_auto_config(dev, &cb_pcidas64_driver,
4085 static const struct pci_device_id cb_pcidas64_pci_table[] = {
4086 { PCI_VDEVICE(CB, 0x001d), BOARD_PCIDAS6402_16 },
4087 { PCI_VDEVICE(CB, 0x001e), BOARD_PCIDAS6402_12 },
4088 { PCI_VDEVICE(CB, 0x0035), BOARD_PCIDAS64_M1_16 },
4089 { PCI_VDEVICE(CB, 0x0036), BOARD_PCIDAS64_M2_16 },
4090 { PCI_VDEVICE(CB, 0x0037), BOARD_PCIDAS64_M3_16 },
4091 { PCI_VDEVICE(CB, 0x0052), BOARD_PCIDAS4020_12 },
4092 { PCI_VDEVICE(CB, 0x005d), BOARD_PCIDAS6023 },
4093 { PCI_VDEVICE(CB, 0x005e), BOARD_PCIDAS6025 },
4094 { PCI_VDEVICE(CB, 0x005f), BOARD_PCIDAS6030 },
4095 { PCI_VDEVICE(CB, 0x0060), BOARD_PCIDAS6031 },
4096 { PCI_VDEVICE(CB, 0x0061), BOARD_PCIDAS6032 },
4097 { PCI_VDEVICE(CB, 0x0062), BOARD_PCIDAS6033 },
4098 { PCI_VDEVICE(CB, 0x0063), BOARD_PCIDAS6034 },
4099 { PCI_VDEVICE(CB, 0x0064), BOARD_PCIDAS6035 },
4100 { PCI_VDEVICE(CB, 0x0065), BOARD_PCIDAS6040 },
4101 { PCI_VDEVICE(CB, 0x0066), BOARD_PCIDAS6052 },
4102 { PCI_VDEVICE(CB, 0x0067), BOARD_PCIDAS6070 },
4103 { PCI_VDEVICE(CB, 0x0068), BOARD_PCIDAS6071 },
4104 { PCI_VDEVICE(CB, 0x006f), BOARD_PCIDAS6036 },
4105 { PCI_VDEVICE(CB, 0x0078), BOARD_PCIDAS6013 },
4106 { PCI_VDEVICE(CB, 0x0079), BOARD_PCIDAS6014 },
4109 MODULE_DEVICE_TABLE(pci, cb_pcidas64_pci_table);
4111 static struct pci_driver cb_pcidas64_pci_driver = {
4112 .name = "cb_pcidas64",
4113 .id_table = cb_pcidas64_pci_table,
4114 .probe = cb_pcidas64_pci_probe,
4115 .remove = comedi_pci_auto_unconfig,
4117 module_comedi_pci_driver(cb_pcidas64_driver, cb_pcidas64_pci_driver);
4119 MODULE_AUTHOR("Comedi http://www.comedi.org");
4120 MODULE_DESCRIPTION("Comedi low-level driver");
4121 MODULE_LICENSE("GPL");