1 // SPDX-License-Identifier: GPL-2.0+
3 * comedi/drivers/amplc_dio200_common.c
5 * Common support code for "amplc_dio200" and "amplc_dio200_pci".
7 * Copyright (C) 2005-2013 MEV Ltd. <http://www.mev.co.uk/>
9 * COMEDI - Linux Control and Measurement Device Interface
10 * Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org>
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
16 #include "../comedidev.h"
18 #include "amplc_dio200.h"
19 #include "comedi_8254.h"
20 #include "8255.h" /* only for register defines */
22 /* 200 series registers */
23 #define DIO200_IO_SIZE 0x20
24 #define DIO200_PCIE_IO_SIZE 0x4000
25 #define DIO200_CLK_SCE(x) (0x18 + (x)) /* Group X/Y/Z clock sel reg */
26 #define DIO200_GAT_SCE(x) (0x1b + (x)) /* Group X/Y/Z gate sel reg */
27 #define DIO200_INT_SCE 0x1e /* Interrupt enable/status register */
28 /* Extra registers for new PCIe boards */
29 #define DIO200_ENHANCE 0x20 /* 1 to enable enhanced features */
30 #define DIO200_VERSION 0x24 /* Hardware version register */
31 #define DIO200_TS_CONFIG 0x600 /* Timestamp timer config register */
32 #define DIO200_TS_COUNT 0x602 /* Timestamp timer count register */
35 * Functions for constructing value for DIO_200_?CLK_SCE and
36 * DIO_200_?GAT_SCE registers:
38 * 'which' is: 0 for CTR-X1, CTR-Y1, CTR-Z1; 1 for CTR-X2, CTR-Y2 or CTR-Z2.
39 * 'chan' is the channel: 0, 1 or 2.
40 * 'source' is the signal source: 0 to 7, or 0 to 31 for "enhanced" boards.
42 static unsigned char clk_gat_sce(unsigned int which, unsigned int chan,
45 return (which << 5) | (chan << 3) |
46 ((source & 030) << 3) | (source & 007);
49 static unsigned char clk_sce(unsigned int which, unsigned int chan,
52 return clk_gat_sce(which, chan, source);
55 static unsigned char gat_sce(unsigned int which, unsigned int chan,
58 return clk_gat_sce(which, chan, source);
62 * Periods of the internal clock sources in nanoseconds.
64 static const unsigned int clock_period[32] = {
65 [1] = 100, /* 10 MHz */
66 [2] = 1000, /* 1 MHz */
67 [3] = 10000, /* 100 kHz */
68 [4] = 100000, /* 10 kHz */
69 [5] = 1000000, /* 1 kHz */
70 [11] = 50, /* 20 MHz (enhanced boards) */
71 /* clock sources 12 and later reserved for enhanced boards */
75 * Timestamp timer configuration register (for new PCIe boards).
77 #define TS_CONFIG_RESET 0x100 /* Reset counter to zero. */
78 #define TS_CONFIG_CLK_SRC_MASK 0x0FF /* Clock source. */
79 #define TS_CONFIG_MAX_CLK_SRC 2 /* Maximum clock source value. */
82 * Periods of the timestamp timer clock sources in nanoseconds.
84 static const unsigned int ts_clock_period[TS_CONFIG_MAX_CLK_SRC + 1] = {
85 1, /* 1 nanosecond (but with 20 ns granularity). */
86 1000, /* 1 microsecond. */
87 1000000, /* 1 millisecond. */
90 struct dio200_subdev_8255 {
91 unsigned int ofs; /* DIO base offset */
94 struct dio200_subdev_intr {
95 spinlock_t spinlock; /* protects the 'active' flag */
97 unsigned int valid_isns;
98 unsigned int enabled_isns;
99 unsigned int active:1;
102 static unsigned char dio200_read8(struct comedi_device *dev,
105 const struct dio200_board *board = dev->board_ptr;
111 return readb(dev->mmio + offset);
112 return inb(dev->iobase + offset);
115 static void dio200_write8(struct comedi_device *dev,
116 unsigned int offset, unsigned char val)
118 const struct dio200_board *board = dev->board_ptr;
124 writeb(val, dev->mmio + offset);
126 outb(val, dev->iobase + offset);
129 static unsigned int dio200_read32(struct comedi_device *dev,
132 const struct dio200_board *board = dev->board_ptr;
138 return readl(dev->mmio + offset);
139 return inl(dev->iobase + offset);
142 static void dio200_write32(struct comedi_device *dev,
143 unsigned int offset, unsigned int val)
145 const struct dio200_board *board = dev->board_ptr;
151 writel(val, dev->mmio + offset);
153 outl(val, dev->iobase + offset);
156 static unsigned int dio200_subdev_8254_offset(struct comedi_device *dev,
157 struct comedi_subdevice *s)
159 const struct dio200_board *board = dev->board_ptr;
160 struct comedi_8254 *i8254 = s->private;
163 /* get the offset that was passed to comedi_8254_*_init() */
165 offset = i8254->mmio - dev->mmio;
167 offset = i8254->iobase - dev->iobase;
169 /* remove the shift that was added for PCIe boards */
173 /* this offset now works for the dio200_{read,write} helpers */
177 static int dio200_subdev_intr_insn_bits(struct comedi_device *dev,
178 struct comedi_subdevice *s,
179 struct comedi_insn *insn,
182 const struct dio200_board *board = dev->board_ptr;
183 struct dio200_subdev_intr *subpriv = s->private;
185 if (board->has_int_sce) {
186 /* Just read the interrupt status register. */
187 data[1] = dio200_read8(dev, subpriv->ofs) & subpriv->valid_isns;
189 /* No interrupt status register. */
196 static void dio200_stop_intr(struct comedi_device *dev,
197 struct comedi_subdevice *s)
199 const struct dio200_board *board = dev->board_ptr;
200 struct dio200_subdev_intr *subpriv = s->private;
202 subpriv->active = false;
203 subpriv->enabled_isns = 0;
204 if (board->has_int_sce)
205 dio200_write8(dev, subpriv->ofs, 0);
208 static void dio200_start_intr(struct comedi_device *dev,
209 struct comedi_subdevice *s)
211 const struct dio200_board *board = dev->board_ptr;
212 struct dio200_subdev_intr *subpriv = s->private;
213 struct comedi_cmd *cmd = &s->async->cmd;
215 unsigned int isn_bits;
217 /* Determine interrupt sources to enable. */
220 for (n = 0; n < cmd->chanlist_len; n++)
221 isn_bits |= (1U << CR_CHAN(cmd->chanlist[n]));
223 isn_bits &= subpriv->valid_isns;
224 /* Enable interrupt sources. */
225 subpriv->enabled_isns = isn_bits;
226 if (board->has_int_sce)
227 dio200_write8(dev, subpriv->ofs, isn_bits);
230 static int dio200_inttrig_start_intr(struct comedi_device *dev,
231 struct comedi_subdevice *s,
232 unsigned int trig_num)
234 struct dio200_subdev_intr *subpriv = s->private;
235 struct comedi_cmd *cmd = &s->async->cmd;
238 if (trig_num != cmd->start_arg)
241 spin_lock_irqsave(&subpriv->spinlock, flags);
242 s->async->inttrig = NULL;
244 dio200_start_intr(dev, s);
246 spin_unlock_irqrestore(&subpriv->spinlock, flags);
251 static void dio200_read_scan_intr(struct comedi_device *dev,
252 struct comedi_subdevice *s,
253 unsigned int triggered)
255 struct comedi_cmd *cmd = &s->async->cmd;
260 for (n = 0; n < cmd->chanlist_len; n++) {
261 ch = CR_CHAN(cmd->chanlist[n]);
262 if (triggered & (1U << ch))
266 comedi_buf_write_samples(s, &val, 1);
268 if (cmd->stop_src == TRIG_COUNT &&
269 s->async->scans_done >= cmd->stop_arg)
270 s->async->events |= COMEDI_CB_EOA;
273 static int dio200_handle_read_intr(struct comedi_device *dev,
274 struct comedi_subdevice *s)
276 const struct dio200_board *board = dev->board_ptr;
277 struct dio200_subdev_intr *subpriv = s->private;
278 unsigned int triggered;
279 unsigned int intstat;
280 unsigned int cur_enabled;
285 spin_lock_irqsave(&subpriv->spinlock, flags);
286 if (board->has_int_sce) {
288 * Collect interrupt sources that have triggered and disable
289 * them temporarily. Loop around until no extra interrupt
290 * sources have triggered, at which point, the valid part of
291 * the interrupt status register will read zero, clearing the
292 * cause of the interrupt.
294 * Mask off interrupt sources already seen to avoid infinite
295 * loop in case of misconfiguration.
297 cur_enabled = subpriv->enabled_isns;
298 while ((intstat = (dio200_read8(dev, subpriv->ofs) &
299 subpriv->valid_isns & ~triggered)) != 0) {
300 triggered |= intstat;
301 cur_enabled &= ~triggered;
302 dio200_write8(dev, subpriv->ofs, cur_enabled);
306 * No interrupt status register. Assume the single interrupt
307 * source has triggered.
309 triggered = subpriv->enabled_isns;
314 * Some interrupt sources have triggered and have been
315 * temporarily disabled to clear the cause of the interrupt.
317 * Reenable them NOW to minimize the time they are disabled.
319 cur_enabled = subpriv->enabled_isns;
320 if (board->has_int_sce)
321 dio200_write8(dev, subpriv->ofs, cur_enabled);
323 if (subpriv->active) {
325 * The command is still active.
327 * Ignore interrupt sources that the command isn't
328 * interested in (just in case there's a race
331 if (triggered & subpriv->enabled_isns) {
332 /* Collect scan data. */
333 dio200_read_scan_intr(dev, s, triggered);
337 spin_unlock_irqrestore(&subpriv->spinlock, flags);
339 comedi_handle_events(dev, s);
341 return (triggered != 0);
344 static int dio200_subdev_intr_cancel(struct comedi_device *dev,
345 struct comedi_subdevice *s)
347 struct dio200_subdev_intr *subpriv = s->private;
350 spin_lock_irqsave(&subpriv->spinlock, flags);
352 dio200_stop_intr(dev, s);
354 spin_unlock_irqrestore(&subpriv->spinlock, flags);
359 static int dio200_subdev_intr_cmdtest(struct comedi_device *dev,
360 struct comedi_subdevice *s,
361 struct comedi_cmd *cmd)
365 /* Step 1 : check if triggers are trivially valid */
367 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
368 err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
369 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
370 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
371 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
376 /* Step 2a : make sure trigger sources are unique */
378 err |= comedi_check_trigger_is_unique(cmd->start_src);
379 err |= comedi_check_trigger_is_unique(cmd->stop_src);
381 /* Step 2b : and mutually compatible */
386 /* Step 3: check if arguments are trivially valid */
388 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
389 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
390 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
391 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
394 if (cmd->stop_src == TRIG_COUNT)
395 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
397 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
402 /* step 4: fix up any arguments */
404 /* if (err) return 4; */
409 static int dio200_subdev_intr_cmd(struct comedi_device *dev,
410 struct comedi_subdevice *s)
412 struct comedi_cmd *cmd = &s->async->cmd;
413 struct dio200_subdev_intr *subpriv = s->private;
416 spin_lock_irqsave(&subpriv->spinlock, flags);
418 subpriv->active = true;
420 if (cmd->start_src == TRIG_INT)
421 s->async->inttrig = dio200_inttrig_start_intr;
423 dio200_start_intr(dev, s);
425 spin_unlock_irqrestore(&subpriv->spinlock, flags);
430 static int dio200_subdev_intr_init(struct comedi_device *dev,
431 struct comedi_subdevice *s,
433 unsigned int valid_isns)
435 const struct dio200_board *board = dev->board_ptr;
436 struct dio200_subdev_intr *subpriv;
438 subpriv = comedi_alloc_spriv(s, sizeof(*subpriv));
442 subpriv->ofs = offset;
443 subpriv->valid_isns = valid_isns;
444 spin_lock_init(&subpriv->spinlock);
446 if (board->has_int_sce)
447 /* Disable interrupt sources. */
448 dio200_write8(dev, subpriv->ofs, 0);
450 s->type = COMEDI_SUBD_DI;
451 s->subdev_flags = SDF_READABLE | SDF_CMD_READ | SDF_PACKED;
452 if (board->has_int_sce) {
453 s->n_chan = DIO200_MAX_ISNS;
454 s->len_chanlist = DIO200_MAX_ISNS;
456 /* No interrupt source register. Support single channel. */
460 s->range_table = &range_digital;
462 s->insn_bits = dio200_subdev_intr_insn_bits;
463 s->do_cmdtest = dio200_subdev_intr_cmdtest;
464 s->do_cmd = dio200_subdev_intr_cmd;
465 s->cancel = dio200_subdev_intr_cancel;
470 static irqreturn_t dio200_interrupt(int irq, void *d)
472 struct comedi_device *dev = d;
473 struct comedi_subdevice *s = dev->read_subdev;
479 handled = dio200_handle_read_intr(dev, s);
481 return IRQ_RETVAL(handled);
484 static void dio200_subdev_8254_set_gate_src(struct comedi_device *dev,
485 struct comedi_subdevice *s,
489 unsigned int offset = dio200_subdev_8254_offset(dev, s);
491 dio200_write8(dev, DIO200_GAT_SCE(offset >> 3),
492 gat_sce((offset >> 2) & 1, chan, src));
495 static void dio200_subdev_8254_set_clock_src(struct comedi_device *dev,
496 struct comedi_subdevice *s,
500 unsigned int offset = dio200_subdev_8254_offset(dev, s);
502 dio200_write8(dev, DIO200_CLK_SCE(offset >> 3),
503 clk_sce((offset >> 2) & 1, chan, src));
506 static int dio200_subdev_8254_config(struct comedi_device *dev,
507 struct comedi_subdevice *s,
508 struct comedi_insn *insn,
511 const struct dio200_board *board = dev->board_ptr;
512 struct comedi_8254 *i8254 = s->private;
513 unsigned int chan = CR_CHAN(insn->chanspec);
514 unsigned int max_src = board->is_pcie ? 31 : 7;
517 if (!board->has_clk_gat_sce)
521 case INSN_CONFIG_SET_GATE_SRC:
526 dio200_subdev_8254_set_gate_src(dev, s, chan, src);
527 i8254->gate_src[chan] = src;
529 case INSN_CONFIG_GET_GATE_SRC:
530 data[2] = i8254->gate_src[chan];
532 case INSN_CONFIG_SET_CLOCK_SRC:
537 dio200_subdev_8254_set_clock_src(dev, s, chan, src);
538 i8254->clock_src[chan] = src;
540 case INSN_CONFIG_GET_CLOCK_SRC:
541 data[1] = i8254->clock_src[chan];
542 data[2] = clock_period[i8254->clock_src[chan]];
551 static int dio200_subdev_8254_init(struct comedi_device *dev,
552 struct comedi_subdevice *s,
555 const struct dio200_board *board = dev->board_ptr;
556 struct comedi_8254 *i8254;
557 unsigned int regshift;
561 * PCIe boards need the offset shifted in order to get the
562 * correct base address of the timer.
564 if (board->is_pcie) {
572 i8254 = comedi_8254_mm_init(dev->mmio + offset,
573 0, I8254_IO8, regshift);
575 i8254 = comedi_8254_init(dev->iobase + offset,
576 0, I8254_IO8, regshift);
581 comedi_8254_subdevice_init(s, i8254);
583 i8254->insn_config = dio200_subdev_8254_config;
586 * There could be multiple timers so this driver does not
587 * use dev->pacer to save the i8254 pointer. Instead,
588 * comedi_8254_subdevice_init() saved the i8254 pointer in
589 * s->private. Mark the subdevice as having private data
590 * to be automatically freed when the device is detached.
592 comedi_set_spriv_auto_free(s);
594 /* Initialize channels. */
595 if (board->has_clk_gat_sce) {
596 for (chan = 0; chan < 3; chan++) {
597 /* Gate source 0 is VCC (logic 1). */
598 dio200_subdev_8254_set_gate_src(dev, s, chan, 0);
599 /* Clock source 0 is the dedicated clock input. */
600 dio200_subdev_8254_set_clock_src(dev, s, chan, 0);
607 static void dio200_subdev_8255_set_dir(struct comedi_device *dev,
608 struct comedi_subdevice *s)
610 struct dio200_subdev_8255 *subpriv = s->private;
613 config = I8255_CTRL_CW;
614 /* 1 in io_bits indicates output, 1 in config indicates input */
615 if (!(s->io_bits & 0x0000ff))
616 config |= I8255_CTRL_A_IO;
617 if (!(s->io_bits & 0x00ff00))
618 config |= I8255_CTRL_B_IO;
619 if (!(s->io_bits & 0x0f0000))
620 config |= I8255_CTRL_C_LO_IO;
621 if (!(s->io_bits & 0xf00000))
622 config |= I8255_CTRL_C_HI_IO;
623 dio200_write8(dev, subpriv->ofs + I8255_CTRL_REG, config);
626 static int dio200_subdev_8255_bits(struct comedi_device *dev,
627 struct comedi_subdevice *s,
628 struct comedi_insn *insn,
631 struct dio200_subdev_8255 *subpriv = s->private;
635 mask = comedi_dio_update_state(s, data);
638 dio200_write8(dev, subpriv->ofs + I8255_DATA_A_REG,
642 dio200_write8(dev, subpriv->ofs + I8255_DATA_B_REG,
643 (s->state >> 8) & 0xff);
645 if (mask & 0xff0000) {
646 dio200_write8(dev, subpriv->ofs + I8255_DATA_C_REG,
647 (s->state >> 16) & 0xff);
651 val = dio200_read8(dev, subpriv->ofs + I8255_DATA_A_REG);
652 val |= dio200_read8(dev, subpriv->ofs + I8255_DATA_B_REG) << 8;
653 val |= dio200_read8(dev, subpriv->ofs + I8255_DATA_C_REG) << 16;
660 static int dio200_subdev_8255_config(struct comedi_device *dev,
661 struct comedi_subdevice *s,
662 struct comedi_insn *insn,
665 unsigned int chan = CR_CHAN(insn->chanspec);
678 ret = comedi_dio_insn_config(dev, s, insn, data, mask);
682 dio200_subdev_8255_set_dir(dev, s);
687 static int dio200_subdev_8255_init(struct comedi_device *dev,
688 struct comedi_subdevice *s,
691 struct dio200_subdev_8255 *subpriv;
693 subpriv = comedi_alloc_spriv(s, sizeof(*subpriv));
697 subpriv->ofs = offset;
699 s->type = COMEDI_SUBD_DIO;
700 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
702 s->range_table = &range_digital;
704 s->insn_bits = dio200_subdev_8255_bits;
705 s->insn_config = dio200_subdev_8255_config;
706 dio200_subdev_8255_set_dir(dev, s);
710 static int dio200_subdev_timer_read(struct comedi_device *dev,
711 struct comedi_subdevice *s,
712 struct comedi_insn *insn,
717 for (n = 0; n < insn->n; n++)
718 data[n] = dio200_read32(dev, DIO200_TS_COUNT);
722 static void dio200_subdev_timer_reset(struct comedi_device *dev,
723 struct comedi_subdevice *s)
727 clock = dio200_read32(dev, DIO200_TS_CONFIG) & TS_CONFIG_CLK_SRC_MASK;
728 dio200_write32(dev, DIO200_TS_CONFIG, clock | TS_CONFIG_RESET);
729 dio200_write32(dev, DIO200_TS_CONFIG, clock);
732 static void dio200_subdev_timer_get_clock_src(struct comedi_device *dev,
733 struct comedi_subdevice *s,
735 unsigned int *period)
739 clk = dio200_read32(dev, DIO200_TS_CONFIG) & TS_CONFIG_CLK_SRC_MASK;
741 *period = (clk < ARRAY_SIZE(ts_clock_period)) ?
742 ts_clock_period[clk] : 0;
745 static int dio200_subdev_timer_set_clock_src(struct comedi_device *dev,
746 struct comedi_subdevice *s,
749 if (src > TS_CONFIG_MAX_CLK_SRC)
751 dio200_write32(dev, DIO200_TS_CONFIG, src);
755 static int dio200_subdev_timer_config(struct comedi_device *dev,
756 struct comedi_subdevice *s,
757 struct comedi_insn *insn,
763 case INSN_CONFIG_RESET:
764 dio200_subdev_timer_reset(dev, s);
766 case INSN_CONFIG_SET_CLOCK_SRC:
767 ret = dio200_subdev_timer_set_clock_src(dev, s, data[1]);
771 case INSN_CONFIG_GET_CLOCK_SRC:
772 dio200_subdev_timer_get_clock_src(dev, s, &data[1], &data[2]);
778 return ret < 0 ? ret : insn->n;
781 void amplc_dio200_set_enhance(struct comedi_device *dev, unsigned char val)
783 dio200_write8(dev, DIO200_ENHANCE, val);
785 EXPORT_SYMBOL_GPL(amplc_dio200_set_enhance);
787 int amplc_dio200_common_attach(struct comedi_device *dev, unsigned int irq,
788 unsigned long req_irq_flags)
790 const struct dio200_board *board = dev->board_ptr;
791 struct comedi_subdevice *s;
795 ret = comedi_alloc_subdevices(dev, board->n_subdevs);
799 for (n = 0; n < dev->n_subdevices; n++) {
800 s = &dev->subdevices[n];
801 switch (board->sdtype[n]) {
803 /* counter subdevice (8254) */
804 ret = dio200_subdev_8254_init(dev, s,
810 /* digital i/o subdevice (8255) */
811 ret = dio200_subdev_8255_init(dev, s,
817 /* 'INTERRUPT' subdevice */
818 if (irq && !dev->read_subdev) {
819 ret = dio200_subdev_intr_init(dev, s,
824 dev->read_subdev = s;
826 s->type = COMEDI_SUBD_UNUSED;
830 s->type = COMEDI_SUBD_TIMER;
831 s->subdev_flags = SDF_READABLE | SDF_LSAMPL;
833 s->maxdata = 0xffffffff;
834 s->insn_read = dio200_subdev_timer_read;
835 s->insn_config = dio200_subdev_timer_config;
838 s->type = COMEDI_SUBD_UNUSED;
843 if (irq && dev->read_subdev) {
844 if (request_irq(irq, dio200_interrupt, req_irq_flags,
845 dev->board_name, dev) >= 0) {
848 dev_warn(dev->class_dev,
849 "warning! irq %u unavailable!\n", irq);
855 EXPORT_SYMBOL_GPL(amplc_dio200_common_attach);
857 static int __init amplc_dio200_common_init(void)
861 module_init(amplc_dio200_common_init);
863 static void __exit amplc_dio200_common_exit(void)
866 module_exit(amplc_dio200_common_exit);
868 MODULE_AUTHOR("Comedi http://www.comedi.org");
869 MODULE_DESCRIPTION("Comedi helper for amplc_dio200 and amplc_dio200_pci");
870 MODULE_LICENSE("GPL");