2 * COMEDI driver for the Advantech PCI-1760
3 * Copyright (C) 2015 H Hartley Sweeten <hsweeten@visionengravers.com>
5 * Based on the pci1760 support in the adv_pci_dio driver written by:
6 * Michal Dobes <dobes@tesnet.cz>
8 * COMEDI - Linux Control and Measurement Device Interface
9 * Copyright (C) 2000 David A. Schleef <ds@schleef.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
24 * Description: Advantech PCI-1760 Relay & Isolated Digital Input Card
25 * Devices: [Advantech] PCI-1760 (adv_pci1760)
26 * Author: H Hartley Sweeten <hsweeten@visionengravers.com>
27 * Updated: Fri, 13 Nov 2015 12:34:00 -0700
30 * Configuration Options: not applicable, uses PCI auto config
33 #include <linux/module.h>
35 #include "../comedi_pci.h"
38 * PCI-1760 Register Map
40 * Outgoing Mailbox Bytes
41 * OMB3: Not used (must be 0)
42 * OMB2: The command code to the PCI-1760
43 * OMB1: The hi byte of the parameter for the command in OMB2
44 * OMB0: The lo byte of the parameter for the command in OMB2
46 * Incoming Mailbox Bytes
47 * IMB3: The Isolated Digital Input status (updated every 100us)
48 * IMB2: The current command (matches OMB2 when command is successful)
49 * IMB1: The hi byte of the feedback data for the command in OMB2
50 * IMB0: The lo byte of the feedback data for the command in OMB2
52 * Interrupt Control/Status
53 * INTCSR3: Not used (must be 0)
54 * INTCSR2: The interrupt status (read only)
55 * INTCSR1: Interrupt enable/disable
56 * INTCSR0: Not used (must be 0)
58 #define PCI1760_OMB_REG(x) (0x0c + (x))
59 #define PCI1760_IMB_REG(x) (0x1c + (x))
60 #define PCI1760_INTCSR_REG(x) (0x38 + (x))
61 #define PCI1760_INTCSR1_IRQ_ENA BIT(5)
62 #define PCI1760_INTCSR2_OMB_IRQ BIT(0)
63 #define PCI1760_INTCSR2_IMB_IRQ BIT(1)
64 #define PCI1760_INTCSR2_IRQ_STATUS BIT(6)
65 #define PCI1760_INTCSR2_IRQ_ASSERTED BIT(7)
67 /* PCI-1760 command codes */
68 #define PCI1760_CMD_CLR_IMB2 0x00 /* Clears IMB2 */
69 #define PCI1760_CMD_SET_DO 0x01 /* Set output state */
70 #define PCI1760_CMD_GET_DO 0x02 /* Read output status */
71 #define PCI1760_CMD_GET_STATUS 0x03 /* Read current status */
72 #define PCI1760_CMD_GET_FW_VER 0x0e /* Read firware version */
73 #define PCI1760_CMD_GET_HW_VER 0x0f /* Read hardware version */
74 #define PCI1760_CMD_SET_PWM_HI(x) (0x10 + (x) * 2) /* Set "hi" period */
75 #define PCI1760_CMD_SET_PWM_LO(x) (0x11 + (x) * 2) /* Set "lo" period */
76 #define PCI1760_CMD_SET_PWM_CNT(x) (0x14 + (x)) /* Set burst count */
77 #define PCI1760_CMD_ENA_PWM 0x1f /* Enable PWM outputs */
78 #define PCI1760_CMD_ENA_FILT 0x20 /* Enable input filter */
79 #define PCI1760_CMD_ENA_PAT_MATCH 0x21 /* Enable input pattern match */
80 #define PCI1760_CMD_SET_PAT_MATCH 0x22 /* Set input pattern match */
81 #define PCI1760_CMD_ENA_RISE_EDGE 0x23 /* Enable input rising edge */
82 #define PCI1760_CMD_ENA_FALL_EDGE 0x24 /* Enable input falling edge */
83 #define PCI1760_CMD_ENA_CNT 0x28 /* Enable counter */
84 #define PCI1760_CMD_RST_CNT 0x29 /* Reset counter */
85 #define PCI1760_CMD_ENA_CNT_OFLOW 0x2a /* Enable counter overflow */
86 #define PCI1760_CMD_ENA_CNT_MATCH 0x2b /* Enable counter match */
87 #define PCI1760_CMD_SET_CNT_EDGE 0x2c /* Set counter edge */
88 #define PCI1760_CMD_GET_CNT 0x2f /* Reads counter value */
89 #define PCI1760_CMD_SET_HI_SAMP(x) (0x30 + (x)) /* Set "hi" sample time */
90 #define PCI1760_CMD_SET_LO_SAMP(x) (0x38 + (x)) /* Set "lo" sample time */
91 #define PCI1760_CMD_SET_CNT(x) (0x40 + (x)) /* Set counter reset val */
92 #define PCI1760_CMD_SET_CNT_MATCH(x) (0x48 + (x)) /* Set counter match val */
93 #define PCI1760_CMD_GET_INT_FLAGS 0x60 /* Read interrupt flags */
94 #define PCI1760_CMD_GET_INT_FLAGS_MATCH BIT(0)
95 #define PCI1760_CMD_GET_INT_FLAGS_COS BIT(1)
96 #define PCI1760_CMD_GET_INT_FLAGS_OFLOW BIT(2)
97 #define PCI1760_CMD_GET_OS 0x61 /* Read edge change flags */
98 #define PCI1760_CMD_GET_CNT_STATUS 0x62 /* Read counter oflow/match */
100 #define PCI1760_CMD_TIMEOUT 250 /* 250 usec timeout */
101 #define PCI1760_CMD_RETRIES 3 /* limit number of retries */
103 #define PCI1760_PWM_TIMEBASE 100000 /* 1 unit = 100 usec */
105 static int pci1760_send_cmd(struct comedi_device *dev,
106 unsigned char cmd, unsigned short val)
108 unsigned long timeout;
110 /* send the command and parameter */
111 outb(val & 0xff, dev->iobase + PCI1760_OMB_REG(0));
112 outb((val >> 8) & 0xff, dev->iobase + PCI1760_OMB_REG(1));
113 outb(cmd, dev->iobase + PCI1760_OMB_REG(2));
114 outb(0, dev->iobase + PCI1760_OMB_REG(3));
116 /* datasheet says to allow up to 250 usec for the command to complete */
117 timeout = jiffies + usecs_to_jiffies(PCI1760_CMD_TIMEOUT);
119 if (inb(dev->iobase + PCI1760_IMB_REG(2)) == cmd) {
120 /* command success; return the feedback data */
121 return inb(dev->iobase + PCI1760_IMB_REG(0)) |
122 (inb(dev->iobase + PCI1760_IMB_REG(1)) << 8);
125 } while (time_before(jiffies, timeout));
130 static int pci1760_cmd(struct comedi_device *dev,
131 unsigned char cmd, unsigned short val)
136 /* send PCI1760_CMD_CLR_IMB2 between identical commands */
137 if (inb(dev->iobase + PCI1760_IMB_REG(2)) == cmd) {
138 ret = pci1760_send_cmd(dev, PCI1760_CMD_CLR_IMB2, 0);
140 /* timeout? try it once more */
141 ret = pci1760_send_cmd(dev, PCI1760_CMD_CLR_IMB2, 0);
147 /* datasheet says to keep retrying the command */
148 for (repeats = 0; repeats < PCI1760_CMD_RETRIES; repeats++) {
149 ret = pci1760_send_cmd(dev, cmd, val);
154 /* command failed! */
158 static int pci1760_di_insn_bits(struct comedi_device *dev,
159 struct comedi_subdevice *s,
160 struct comedi_insn *insn,
163 data[1] = inb(dev->iobase + PCI1760_IMB_REG(3));
168 static int pci1760_do_insn_bits(struct comedi_device *dev,
169 struct comedi_subdevice *s,
170 struct comedi_insn *insn,
175 if (comedi_dio_update_state(s, data)) {
176 ret = pci1760_cmd(dev, PCI1760_CMD_SET_DO, s->state);
186 static int pci1760_pwm_ns_to_div(unsigned int flags, unsigned int ns)
188 unsigned int divisor;
191 case CMDF_ROUND_NEAREST:
192 divisor = DIV_ROUND_CLOSEST(ns, PCI1760_PWM_TIMEBASE);
195 divisor = DIV_ROUND_UP(ns, PCI1760_PWM_TIMEBASE);
197 case CMDF_ROUND_DOWN:
198 divisor = ns / PCI1760_PWM_TIMEBASE;
206 if (divisor > 0xffff)
212 static int pci1760_pwm_enable(struct comedi_device *dev,
213 unsigned int chan, bool enable)
217 ret = pci1760_cmd(dev, PCI1760_CMD_GET_STATUS, PCI1760_CMD_ENA_PWM);
226 return pci1760_cmd(dev, PCI1760_CMD_ENA_PWM, ret);
229 static int pci1760_pwm_insn_config(struct comedi_device *dev,
230 struct comedi_subdevice *s,
231 struct comedi_insn *insn,
234 unsigned int chan = CR_CHAN(insn->chanspec);
240 case INSN_CONFIG_ARM:
241 ret = pci1760_pwm_enable(dev, chan, false);
245 if (data[1] > 0xffff)
247 ret = pci1760_cmd(dev, PCI1760_CMD_SET_PWM_CNT(chan), data[1]);
251 ret = pci1760_pwm_enable(dev, chan, true);
255 case INSN_CONFIG_DISARM:
256 ret = pci1760_pwm_enable(dev, chan, false);
260 case INSN_CONFIG_PWM_OUTPUT:
261 ret = pci1760_pwm_enable(dev, chan, false);
265 hi_div = pci1760_pwm_ns_to_div(data[1], data[2]);
266 lo_div = pci1760_pwm_ns_to_div(data[3], data[4]);
267 if (hi_div < 0 || lo_div < 0)
269 if ((hi_div * PCI1760_PWM_TIMEBASE) != data[2] ||
270 (lo_div * PCI1760_PWM_TIMEBASE) != data[4]) {
271 data[2] = hi_div * PCI1760_PWM_TIMEBASE;
272 data[4] = lo_div * PCI1760_PWM_TIMEBASE;
275 ret = pci1760_cmd(dev, PCI1760_CMD_SET_PWM_HI(chan), hi_div);
278 ret = pci1760_cmd(dev, PCI1760_CMD_SET_PWM_LO(chan), lo_div);
282 case INSN_CONFIG_GET_PWM_OUTPUT:
283 hi_div = pci1760_cmd(dev, PCI1760_CMD_GET_STATUS,
284 PCI1760_CMD_SET_PWM_HI(chan));
285 lo_div = pci1760_cmd(dev, PCI1760_CMD_GET_STATUS,
286 PCI1760_CMD_SET_PWM_LO(chan));
287 if (hi_div < 0 || lo_div < 0)
290 data[1] = hi_div * PCI1760_PWM_TIMEBASE;
291 data[2] = lo_div * PCI1760_PWM_TIMEBASE;
293 case INSN_CONFIG_GET_PWM_STATUS:
294 ret = pci1760_cmd(dev, PCI1760_CMD_GET_STATUS,
295 PCI1760_CMD_ENA_PWM);
299 data[1] = (ret & BIT(chan)) ? 1 : 0;
308 static void pci1760_reset(struct comedi_device *dev)
312 /* disable interrupts (intcsr2 is read-only) */
313 outb(0, dev->iobase + PCI1760_INTCSR_REG(0));
314 outb(0, dev->iobase + PCI1760_INTCSR_REG(1));
315 outb(0, dev->iobase + PCI1760_INTCSR_REG(3));
317 /* disable counters */
318 pci1760_cmd(dev, PCI1760_CMD_ENA_CNT, 0);
320 /* disable overflow interrupts */
321 pci1760_cmd(dev, PCI1760_CMD_ENA_CNT_OFLOW, 0);
324 pci1760_cmd(dev, PCI1760_CMD_ENA_CNT_MATCH, 0);
326 /* set match and counter reset values */
327 for (i = 0; i < 8; i++) {
328 pci1760_cmd(dev, PCI1760_CMD_SET_CNT_MATCH(i), 0x8000);
329 pci1760_cmd(dev, PCI1760_CMD_SET_CNT(i), 0x0000);
332 /* reset counters to reset values */
333 pci1760_cmd(dev, PCI1760_CMD_RST_CNT, 0xff);
335 /* set counter count edges */
336 pci1760_cmd(dev, PCI1760_CMD_SET_CNT_EDGE, 0);
338 /* disable input filters */
339 pci1760_cmd(dev, PCI1760_CMD_ENA_FILT, 0);
341 /* disable pattern matching */
342 pci1760_cmd(dev, PCI1760_CMD_ENA_PAT_MATCH, 0);
344 /* set pattern match value */
345 pci1760_cmd(dev, PCI1760_CMD_SET_PAT_MATCH, 0);
348 static int pci1760_auto_attach(struct comedi_device *dev,
349 unsigned long context)
351 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
352 struct comedi_subdevice *s;
355 ret = comedi_pci_enable(dev);
358 dev->iobase = pci_resource_start(pcidev, 0);
362 ret = comedi_alloc_subdevices(dev, 4);
366 /* Digital Input subdevice */
367 s = &dev->subdevices[0];
368 s->type = COMEDI_SUBD_DI;
369 s->subdev_flags = SDF_READABLE;
372 s->range_table = &range_digital;
373 s->insn_bits = pci1760_di_insn_bits;
375 /* Digital Output subdevice */
376 s = &dev->subdevices[1];
377 s->type = COMEDI_SUBD_DO;
378 s->subdev_flags = SDF_WRITABLE;
381 s->range_table = &range_digital;
382 s->insn_bits = pci1760_do_insn_bits;
384 /* get the current state of the outputs */
385 ret = pci1760_cmd(dev, PCI1760_CMD_GET_DO, 0);
391 s = &dev->subdevices[2];
392 s->type = COMEDI_SUBD_PWM;
393 s->subdev_flags = SDF_PWM_COUNTER;
395 s->insn_config = pci1760_pwm_insn_config;
397 /* Counter subdevice */
398 s = &dev->subdevices[3];
399 s->type = COMEDI_SUBD_UNUSED;
404 static struct comedi_driver pci1760_driver = {
405 .driver_name = "adv_pci1760",
406 .module = THIS_MODULE,
407 .auto_attach = pci1760_auto_attach,
408 .detach = comedi_pci_detach,
411 static int pci1760_pci_probe(struct pci_dev *dev,
412 const struct pci_device_id *id)
414 return comedi_pci_auto_config(dev, &pci1760_driver, id->driver_data);
417 static const struct pci_device_id pci1760_pci_table[] = {
418 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1760) },
421 MODULE_DEVICE_TABLE(pci, pci1760_pci_table);
423 static struct pci_driver pci1760_pci_driver = {
424 .name = "adv_pci1760",
425 .id_table = pci1760_pci_table,
426 .probe = pci1760_pci_probe,
427 .remove = comedi_pci_auto_unconfig,
429 module_comedi_pci_driver(pci1760_driver, pci1760_pci_driver);
431 MODULE_AUTHOR("Comedi http://www.comedi.org");
432 MODULE_DESCRIPTION("Comedi driver for Advantech PCI-1760");
433 MODULE_LICENSE("GPL");