3 * Copyright (C) 2004,2005 ADDI-DATA GmbH for the source code of this module.
8 * Tel: +19(0)7223/9493-0
9 * Fax: +49(0)7223/9493-92
10 * http://www.addi-data.com
13 * This program is free software; you can redistribute it and/or modify it under
14 * the terms of the GNU General Public License as published by the Free Software
15 * Foundation; either version 2 of the License, or (at your option) any later
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
20 * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
24 #include <linux/module.h>
25 #include <linux/interrupt.h>
26 #include <linux/sched.h>
28 #include "../comedi_pci.h"
30 #include "addi_watchdog.h"
35 * PLD Revision 1.0 I/O Mapping
37 * 0x04 - 0x18 Timer 12-Bit
39 * PLD Revision 2.x I/O Mapping
41 * 0x04 - 0x14 Digital Input
42 * 0x18 - 0x25 Digital Output
43 * 0x28 - 0x44 Watchdog 8-Bit
44 * 0x48 - 0x64 Timer 12-Bit
46 #define APCI1564_EEPROM_REG 0x00
47 #define APCI1564_EEPROM_VCC_STATUS BIT(8)
48 #define APCI1564_EEPROM_TO_REV(x) (((x) >> 4) & 0xf)
49 #define APCI1564_EEPROM_DI BIT(3)
50 #define APCI1564_EEPROM_DO BIT(2)
51 #define APCI1564_EEPROM_CS BIT(1)
52 #define APCI1564_EEPROM_CLK BIT(0)
53 #define APCI1564_REV1_TIMER_IOBASE 0x04
54 #define APCI1564_REV2_MAIN_IOBASE 0x04
55 #define APCI1564_REV2_TIMER_IOBASE 0x48
60 * PLD Revision 1.0 I/O Mapping
61 * 0x00 - 0x10 Digital Input
62 * 0x14 - 0x20 Digital Output
63 * 0x24 - 0x3c Watchdog 8-Bit
65 * PLD Revision 2.x I/O Mapping
70 #define APCI1564_REV1_MAIN_IOBASE 0x00
73 * dev->iobase Register Map
74 * PLD Revision 1.0 - PCI BAR 1 + 0x00
75 * PLD Revision 2.x - PCI BAR 0 + 0x04
77 #define APCI1564_DI_REG 0x00
78 #define APCI1564_DI_INT_MODE1_REG 0x04
79 #define APCI1564_DI_INT_MODE2_REG 0x08
80 #define APCI1564_DI_INT_STATUS_REG 0x0c
81 #define APCI1564_DI_IRQ_REG 0x10
82 #define APCI1564_DI_IRQ_ENA BIT(2)
83 #define APCI1564_DI_IRQ_MODE BIT(1) /* 1=AND, 0=OR */
84 #define APCI1564_DO_REG 0x14
85 #define APCI1564_DO_INT_CTRL_REG 0x18
86 #define APCI1564_DO_INT_CTRL_CC_INT_ENA BIT(1)
87 #define APCI1564_DO_INT_CTRL_VCC_INT_ENA BIT(0)
88 #define APCI1564_DO_INT_STATUS_REG 0x1c
89 #define APCI1564_DO_INT_STATUS_CC BIT(1)
90 #define APCI1564_DO_INT_STATUS_VCC BIT(0)
91 #define APCI1564_DO_IRQ_REG 0x20
92 #define APCI1564_DO_IRQ_INTR BIT(0)
93 #define APCI1564_WDOG_REG 0x24
94 #define APCI1564_WDOG_RELOAD_REG 0x28
95 #define APCI1564_WDOG_TIMEBASE_REG 0x2c
96 #define APCI1564_WDOG_CTRL_REG 0x30
97 #define APCI1564_WDOG_STATUS_REG 0x34
98 #define APCI1564_WDOG_IRQ_REG 0x38
99 #define APCI1564_WDOG_WARN_TIMEVAL_REG 0x3c
100 #define APCI1564_WDOG_WARN_TIMEBASE_REG 0x40
103 * devpriv->timer Register Map (see addi_tcw.h for register/bit defines)
104 * PLD Revision 1.0 - PCI BAR 0 + 0x04
105 * PLD Revision 2.x - PCI BAR 0 + 0x48
109 * devpriv->counters Register Map (see addi_tcw.h for register/bit defines)
110 * PLD Revision 2.x - PCI BAR 1 + 0x00
112 #define APCI1564_COUNTER(x) ((x) * 0x20)
114 struct apci1564_private {
115 unsigned long eeprom; /* base address of EEPROM register */
116 unsigned long timer; /* base address of 12-bit timer */
117 unsigned long counters; /* base address of 32-bit counters */
118 unsigned int mode1; /* riding-edge/high level channels */
119 unsigned int mode2; /* falling-edge/low level channels */
120 unsigned int ctrl; /* interrupt mode OR (edge) . AND (level) */
121 struct task_struct *tsk_current;
124 #include "addi-data/hwdrv_apci1564.c"
126 static int apci1564_reset(struct comedi_device *dev)
128 struct apci1564_private *devpriv = dev->private;
130 /* Disable the input interrupts and reset status register */
131 outl(0x0, dev->iobase + APCI1564_DI_IRQ_REG);
132 inl(dev->iobase + APCI1564_DI_INT_STATUS_REG);
133 outl(0x0, dev->iobase + APCI1564_DI_INT_MODE1_REG);
134 outl(0x0, dev->iobase + APCI1564_DI_INT_MODE2_REG);
136 /* Reset the output channels and disable interrupts */
137 outl(0x0, dev->iobase + APCI1564_DO_REG);
138 outl(0x0, dev->iobase + APCI1564_DO_INT_CTRL_REG);
140 /* Reset the watchdog registers */
141 addi_watchdog_reset(dev->iobase + APCI1564_WDOG_REG);
143 /* Reset the timer registers */
144 outl(0x0, devpriv->timer + ADDI_TCW_CTRL_REG);
145 outl(0x0, devpriv->timer + ADDI_TCW_RELOAD_REG);
147 if (devpriv->counters) {
148 unsigned long iobase = devpriv->counters + ADDI_TCW_CTRL_REG;
150 /* Reset the counter registers */
151 outl(0x0, iobase + APCI1564_COUNTER(0));
152 outl(0x0, iobase + APCI1564_COUNTER(1));
153 outl(0x0, iobase + APCI1564_COUNTER(2));
159 static irqreturn_t apci1564_interrupt(int irq, void *d)
161 struct comedi_device *dev = d;
162 struct apci1564_private *devpriv = dev->private;
163 struct comedi_subdevice *s = dev->read_subdev;
168 status = inl(dev->iobase + APCI1564_DI_IRQ_REG);
169 if (status & APCI1564_DI_IRQ_ENA) {
170 /* disable the interrupt */
171 outl(status & ~APCI1564_DI_IRQ_ENA,
172 dev->iobase + APCI1564_DI_IRQ_REG);
174 s->state = inl(dev->iobase + APCI1564_DI_INT_STATUS_REG) &
176 comedi_buf_write_samples(s, &s->state, 1);
177 comedi_handle_events(dev, s);
179 /* enable the interrupt */
180 outl(status, dev->iobase + APCI1564_DI_IRQ_REG);
183 status = inl(devpriv->timer + ADDI_TCW_IRQ_REG);
185 /* Disable Timer Interrupt */
186 ctrl = inl(devpriv->timer + ADDI_TCW_CTRL_REG);
187 outl(0x0, devpriv->timer + ADDI_TCW_CTRL_REG);
189 /* Send a signal to from kernel to user space */
190 send_sig(SIGIO, devpriv->tsk_current, 0);
192 /* Enable Timer Interrupt */
193 outl(ctrl, devpriv->timer + ADDI_TCW_CTRL_REG);
196 if (devpriv->counters) {
197 for (chan = 0; chan < 4; chan++) {
198 unsigned long iobase;
200 iobase = devpriv->counters + APCI1564_COUNTER(chan);
202 status = inl(iobase + ADDI_TCW_IRQ_REG);
204 /* Disable Counter Interrupt */
205 ctrl = inl(iobase + ADDI_TCW_CTRL_REG);
206 outl(0x0, iobase + ADDI_TCW_CTRL_REG);
208 /* Send a signal to from kernel to user space */
209 send_sig(SIGIO, devpriv->tsk_current, 0);
211 /* Enable Counter Interrupt */
212 outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
220 static int apci1564_di_insn_bits(struct comedi_device *dev,
221 struct comedi_subdevice *s,
222 struct comedi_insn *insn,
225 data[1] = inl(dev->iobase + APCI1564_DI_REG);
230 static int apci1564_do_insn_bits(struct comedi_device *dev,
231 struct comedi_subdevice *s,
232 struct comedi_insn *insn,
235 s->state = inl(dev->iobase + APCI1564_DO_REG);
237 if (comedi_dio_update_state(s, data))
238 outl(s->state, dev->iobase + APCI1564_DO_REG);
245 static int apci1564_diag_insn_bits(struct comedi_device *dev,
246 struct comedi_subdevice *s,
247 struct comedi_insn *insn,
250 data[1] = inl(dev->iobase + APCI1564_DO_INT_STATUS_REG) & 3;
256 * Change-Of-State (COS) interrupt configuration
258 * Channels 0 to 15 are interruptible. These channels can be configured
259 * to generate interrupts based on AND/OR logic for the desired channels.
262 * - reacts to rising or falling edges
263 * - interrupt is generated when any enabled channel
264 * meet the desired interrupt condition
267 * - reacts to changes in level of the selected inputs
268 * - interrupt is generated when all enabled channels
269 * meet the desired interrupt condition
270 * - after an interrupt, a change in level must occur on
271 * the selected inputs to release the IRQ logic
273 * The COS interrupt must be configured before it can be enabled.
275 * data[0] : INSN_CONFIG_DIGITAL_TRIG
276 * data[1] : trigger number (= 0)
277 * data[2] : configuration operation:
278 * COMEDI_DIGITAL_TRIG_DISABLE = no interrupts
279 * COMEDI_DIGITAL_TRIG_ENABLE_EDGES = OR (edge) interrupts
280 * COMEDI_DIGITAL_TRIG_ENABLE_LEVELS = AND (level) interrupts
281 * data[3] : left-shift for data[4] and data[5]
282 * data[4] : rising-edge/high level channels
283 * data[5] : falling-edge/low level channels
285 static int apci1564_cos_insn_config(struct comedi_device *dev,
286 struct comedi_subdevice *s,
287 struct comedi_insn *insn,
290 struct apci1564_private *devpriv = dev->private;
291 unsigned int shift, oldmask, himask, lomask;
294 case INSN_CONFIG_DIGITAL_TRIG:
299 oldmask = (1U << shift) - 1;
300 himask = data[4] << shift;
301 lomask = data[5] << shift;
303 oldmask = 0xffffffffu;
308 case COMEDI_DIGITAL_TRIG_DISABLE:
312 outl(0x0, dev->iobase + APCI1564_DI_IRQ_REG);
313 inl(dev->iobase + APCI1564_DI_INT_STATUS_REG);
314 outl(0x0, dev->iobase + APCI1564_DI_INT_MODE1_REG);
315 outl(0x0, dev->iobase + APCI1564_DI_INT_MODE2_REG);
317 case COMEDI_DIGITAL_TRIG_ENABLE_EDGES:
318 if (devpriv->ctrl != APCI1564_DI_IRQ_ENA) {
319 /* switching to 'OR' mode */
320 devpriv->ctrl = APCI1564_DI_IRQ_ENA;
321 /* wipe old channels */
325 /* preserve unspecified channels */
326 devpriv->mode1 &= oldmask;
327 devpriv->mode2 &= oldmask;
329 /* configure specified channels */
330 devpriv->mode1 |= himask;
331 devpriv->mode2 |= lomask;
333 case COMEDI_DIGITAL_TRIG_ENABLE_LEVELS:
334 if (devpriv->ctrl != (APCI1564_DI_IRQ_ENA |
335 APCI1564_DI_IRQ_MODE)) {
336 /* switching to 'AND' mode */
337 devpriv->ctrl = APCI1564_DI_IRQ_ENA |
338 APCI1564_DI_IRQ_MODE;
339 /* wipe old channels */
343 /* preserve unspecified channels */
344 devpriv->mode1 &= oldmask;
345 devpriv->mode2 &= oldmask;
347 /* configure specified channels */
348 devpriv->mode1 |= himask;
349 devpriv->mode2 |= lomask;
361 static int apci1564_cos_insn_bits(struct comedi_device *dev,
362 struct comedi_subdevice *s,
363 struct comedi_insn *insn,
371 static int apci1564_cos_cmdtest(struct comedi_device *dev,
372 struct comedi_subdevice *s,
373 struct comedi_cmd *cmd)
377 /* Step 1 : check if triggers are trivially valid */
379 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW);
380 err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
381 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
382 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
383 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
388 /* Step 2a : make sure trigger sources are unique */
389 /* Step 2b : and mutually compatible */
391 /* Step 3: check if arguments are trivially valid */
393 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
394 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
395 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
396 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
398 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
403 /* Step 4: fix up any arguments */
405 /* Step 5: check channel list if it exists */
411 * Change-Of-State (COS) 'do_cmd' operation
413 * Enable the COS interrupt as configured by apci1564_cos_insn_config().
415 static int apci1564_cos_cmd(struct comedi_device *dev,
416 struct comedi_subdevice *s)
418 struct apci1564_private *devpriv = dev->private;
420 if (!devpriv->ctrl) {
421 dev_warn(dev->class_dev,
422 "Interrupts disabled due to mode configuration!\n");
426 outl(devpriv->mode1, dev->iobase + APCI1564_DI_INT_MODE1_REG);
427 outl(devpriv->mode2, dev->iobase + APCI1564_DI_INT_MODE2_REG);
428 outl(devpriv->ctrl, dev->iobase + APCI1564_DI_IRQ_REG);
433 static int apci1564_cos_cancel(struct comedi_device *dev,
434 struct comedi_subdevice *s)
436 outl(0x0, dev->iobase + APCI1564_DI_IRQ_REG);
437 inl(dev->iobase + APCI1564_DI_INT_STATUS_REG);
438 outl(0x0, dev->iobase + APCI1564_DI_INT_MODE1_REG);
439 outl(0x0, dev->iobase + APCI1564_DI_INT_MODE2_REG);
444 static int apci1564_auto_attach(struct comedi_device *dev,
445 unsigned long context_unused)
447 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
448 struct apci1564_private *devpriv;
449 struct comedi_subdevice *s;
453 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
457 ret = comedi_pci_enable(dev);
461 /* read the EEPROM register and check the I/O map revision */
462 devpriv->eeprom = pci_resource_start(pcidev, 0);
463 val = inl(devpriv->eeprom + APCI1564_EEPROM_REG);
464 if (APCI1564_EEPROM_TO_REV(val) == 0) {
465 /* PLD Revision 1.0 I/O Mapping */
466 dev->iobase = pci_resource_start(pcidev, 1) +
467 APCI1564_REV1_MAIN_IOBASE;
468 devpriv->timer = devpriv->eeprom + APCI1564_REV1_TIMER_IOBASE;
470 /* PLD Revision 2.x I/O Mapping */
471 dev->iobase = devpriv->eeprom + APCI1564_REV2_MAIN_IOBASE;
472 devpriv->timer = devpriv->eeprom + APCI1564_REV2_TIMER_IOBASE;
473 devpriv->counters = pci_resource_start(pcidev, 1);
478 if (pcidev->irq > 0) {
479 ret = request_irq(pcidev->irq, apci1564_interrupt, IRQF_SHARED,
480 dev->board_name, dev);
482 dev->irq = pcidev->irq;
485 ret = comedi_alloc_subdevices(dev, 7);
489 /* Allocate and Initialise DI Subdevice Structures */
490 s = &dev->subdevices[0];
491 s->type = COMEDI_SUBD_DI;
492 s->subdev_flags = SDF_READABLE;
495 s->range_table = &range_digital;
496 s->insn_bits = apci1564_di_insn_bits;
498 /* Allocate and Initialise DO Subdevice Structures */
499 s = &dev->subdevices[1];
500 s->type = COMEDI_SUBD_DO;
501 s->subdev_flags = SDF_WRITABLE;
504 s->range_table = &range_digital;
505 s->insn_bits = apci1564_do_insn_bits;
507 /* Change-Of-State (COS) interrupt subdevice */
508 s = &dev->subdevices[2];
510 dev->read_subdev = s;
511 s->type = COMEDI_SUBD_DI;
512 s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
515 s->range_table = &range_digital;
517 s->insn_config = apci1564_cos_insn_config;
518 s->insn_bits = apci1564_cos_insn_bits;
519 s->do_cmdtest = apci1564_cos_cmdtest;
520 s->do_cmd = apci1564_cos_cmd;
521 s->cancel = apci1564_cos_cancel;
523 s->type = COMEDI_SUBD_UNUSED;
526 /* Timer subdevice */
527 s = &dev->subdevices[3];
528 s->type = COMEDI_SUBD_TIMER;
529 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
532 s->range_table = &range_digital;
533 s->insn_config = apci1564_timer_insn_config;
534 s->insn_write = apci1564_timer_insn_write;
535 s->insn_read = apci1564_timer_insn_read;
537 /* Counter subdevice */
538 s = &dev->subdevices[4];
539 if (devpriv->counters) {
540 s->type = COMEDI_SUBD_COUNTER;
541 s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL;
543 s->maxdata = 0xffffffff;
544 s->range_table = &range_digital;
545 s->insn_config = apci1564_counter_insn_config;
546 s->insn_write = apci1564_counter_insn_write;
547 s->insn_read = apci1564_counter_insn_read;
549 s->type = COMEDI_SUBD_UNUSED;
552 /* Initialize the watchdog subdevice */
553 s = &dev->subdevices[5];
554 ret = addi_watchdog_init(s, dev->iobase + APCI1564_WDOG_REG);
558 /* Initialize the diagnostic status subdevice */
559 s = &dev->subdevices[6];
560 s->type = COMEDI_SUBD_DI;
561 s->subdev_flags = SDF_READABLE;
564 s->range_table = &range_digital;
565 s->insn_bits = apci1564_diag_insn_bits;
570 static void apci1564_detach(struct comedi_device *dev)
574 comedi_pci_detach(dev);
577 static struct comedi_driver apci1564_driver = {
578 .driver_name = "addi_apci_1564",
579 .module = THIS_MODULE,
580 .auto_attach = apci1564_auto_attach,
581 .detach = apci1564_detach,
584 static int apci1564_pci_probe(struct pci_dev *dev,
585 const struct pci_device_id *id)
587 return comedi_pci_auto_config(dev, &apci1564_driver, id->driver_data);
590 static const struct pci_device_id apci1564_pci_table[] = {
591 { PCI_DEVICE(PCI_VENDOR_ID_ADDIDATA, 0x1006) },
594 MODULE_DEVICE_TABLE(pci, apci1564_pci_table);
596 static struct pci_driver apci1564_pci_driver = {
597 .name = "addi_apci_1564",
598 .id_table = apci1564_pci_table,
599 .probe = apci1564_pci_probe,
600 .remove = comedi_pci_auto_unconfig,
602 module_comedi_pci_driver(apci1564_driver, apci1564_pci_driver);
604 MODULE_AUTHOR("Comedi http://www.comedi.org");
605 MODULE_DESCRIPTION("ADDI-DATA APCI-1564, 32 channel DI / 32 channel DO boards");
606 MODULE_LICENSE("GPL");