drivers/staging/ccree/dx_host.h

   1 /*
   2  * Copyright (C) 2012-2017 ARM Limited or its affiliates.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #ifndef __DX_HOST_H__
  18 #define __DX_HOST_H__
  19
  20 // --------------------------------------
  21 // BLOCK: HOST_P
  22 // --------------------------------------
  23 #define DX_HOST_IRR_REG_OFFSET  0xA00UL
  24 #define DX_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SHIFT        0x2UL
  25 #define DX_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SIZE 0x1UL
  26 #define DX_HOST_IRR_AXI_ERR_INT_BIT_SHIFT       0x8UL
  27 #define DX_HOST_IRR_AXI_ERR_INT_BIT_SIZE        0x1UL
  28 #define DX_HOST_IRR_GPR0_BIT_SHIFT      0xBUL
  29 #define DX_HOST_IRR_GPR0_BIT_SIZE       0x1UL
  30 #define DX_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SHIFT     0x13UL
  31 #define DX_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SIZE      0x1UL
  32 #define DX_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT     0x17UL
  33 #define DX_HOST_IRR_AXIM_COMP_INT_BIT_SIZE      0x1UL
  34 #define DX_HOST_IMR_REG_OFFSET  0xA04UL
  35 #define DX_HOST_IMR_NOT_USED_MASK_BIT_SHIFT     0x1UL
  36 #define DX_HOST_IMR_NOT_USED_MASK_BIT_SIZE      0x1UL
  37 #define DX_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SHIFT   0x2UL
  38 #define DX_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SIZE    0x1UL
  39 #define DX_HOST_IMR_AXI_ERR_MASK_BIT_SHIFT      0x8UL
  40 #define DX_HOST_IMR_AXI_ERR_MASK_BIT_SIZE       0x1UL
  41 #define DX_HOST_IMR_GPR0_BIT_SHIFT      0xBUL
  42 #define DX_HOST_IMR_GPR0_BIT_SIZE       0x1UL
  43 #define DX_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SHIFT   0x13UL
  44 #define DX_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SIZE    0x1UL
  45 #define DX_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SHIFT        0x17UL
  46 #define DX_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SIZE 0x1UL
  47 #define DX_HOST_ICR_REG_OFFSET  0xA08UL
  48 #define DX_HOST_ICR_DSCRPTR_COMPLETION_BIT_SHIFT        0x2UL
  49 #define DX_HOST_ICR_DSCRPTR_COMPLETION_BIT_SIZE 0x1UL
  50 #define DX_HOST_ICR_AXI_ERR_CLEAR_BIT_SHIFT     0x8UL
  51 #define DX_HOST_ICR_AXI_ERR_CLEAR_BIT_SIZE      0x1UL
  52 #define DX_HOST_ICR_GPR_INT_CLEAR_BIT_SHIFT     0xBUL
  53 #define DX_HOST_ICR_GPR_INT_CLEAR_BIT_SIZE      0x1UL
  54 #define DX_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SHIFT    0x13UL
  55 #define DX_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SIZE     0x1UL
  56 #define DX_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SHIFT       0x17UL
  57 #define DX_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SIZE        0x1UL
  58 #define DX_HOST_SIGNATURE_REG_OFFSET    0xA24UL
  59 #define DX_HOST_SIGNATURE_VALUE_BIT_SHIFT       0x0UL
  60 #define DX_HOST_SIGNATURE_VALUE_BIT_SIZE        0x20UL
  61 #define DX_HOST_BOOT_REG_OFFSET 0xA28UL
  62 #define DX_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SHIFT 0x0UL
  63 #define DX_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SIZE  0x1UL
  64 #define DX_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SHIFT 0x1UL
  65 #define DX_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SIZE  0x1UL
  66 #define DX_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SHIFT      0x2UL
  67 #define DX_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SIZE       0x1UL
  68 #define DX_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SHIFT    0x3UL
  69 #define DX_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SIZE     0x1UL
  70 #define DX_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SHIFT  0x5UL
  71 #define DX_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SIZE   0x1UL
  72 #define DX_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SHIFT  0x6UL
  73 #define DX_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SIZE   0x3UL
  74 #define DX_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SHIFT     0x9UL
  75 #define DX_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SIZE      0x1UL
  76 #define DX_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SHIFT 0xAUL
  77 #define DX_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SIZE  0x1UL
  78 #define DX_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SHIFT 0xBUL
  79 #define DX_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SIZE  0x1UL
  80 #define DX_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SHIFT 0xCUL
  81 #define DX_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SIZE  0x1UL
  82 #define DX_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SHIFT 0xDUL
  83 #define DX_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SIZE  0x1UL
  84 #define DX_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SHIFT      0xEUL
  85 #define DX_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SIZE       0x1UL
  86 #define DX_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SHIFT      0xFUL
  87 #define DX_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SIZE       0x1UL
  88 #define DX_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SHIFT  0x10UL
  89 #define DX_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SIZE   0x1UL
  90 #define DX_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SHIFT        0x11UL
  91 #define DX_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SIZE 0x1UL
  92 #define DX_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SHIFT  0x12UL
  93 #define DX_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SIZE   0x1UL
  94 #define DX_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SHIFT 0x13UL
  95 #define DX_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SIZE  0x1UL
  96 #define DX_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SHIFT        0x14UL
  97 #define DX_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SIZE 0x1UL
  98 #define DX_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SHIFT    0x15UL
  99 #define DX_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SIZE     0x1UL
 100 #define DX_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SHIFT     0x16UL
 101 #define DX_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SIZE      0x1UL
 102 #define DX_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SHIFT  0x17UL
 103 #define DX_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SIZE   0x1UL
 104 #define DX_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SHIFT     0x18UL
 105 #define DX_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SIZE      0x1UL
 106 #define DX_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SHIFT 0x19UL
 107 #define DX_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SIZE  0x1UL
 108 #define DX_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SHIFT    0x1AUL
 109 #define DX_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SIZE     0x1UL
 110 #define DX_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SHIFT      0x1BUL
 111 #define DX_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SIZE       0x1UL
 112 #define DX_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SHIFT        0x1CUL
 113 #define DX_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SIZE 0x1UL
 114 #define DX_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SHIFT       0x1DUL
 115 #define DX_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SIZE        0x1UL
 116 #define DX_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SHIFT 0x1EUL
 117 #define DX_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SIZE  0x1UL
 118 #define DX_HOST_VERSION_REG_OFFSET      0xA40UL
 119 #define DX_HOST_VERSION_VALUE_BIT_SHIFT 0x0UL
 120 #define DX_HOST_VERSION_VALUE_BIT_SIZE  0x20UL
 121 #define DX_HOST_KFDE0_VALID_REG_OFFSET  0xA60UL
 122 #define DX_HOST_KFDE0_VALID_VALUE_BIT_SHIFT     0x0UL
 123 #define DX_HOST_KFDE0_VALID_VALUE_BIT_SIZE      0x1UL
 124 #define DX_HOST_KFDE1_VALID_REG_OFFSET  0xA64UL
 125 #define DX_HOST_KFDE1_VALID_VALUE_BIT_SHIFT     0x0UL
 126 #define DX_HOST_KFDE1_VALID_VALUE_BIT_SIZE      0x1UL
 127 #define DX_HOST_KFDE2_VALID_REG_OFFSET  0xA68UL
 128 #define DX_HOST_KFDE2_VALID_VALUE_BIT_SHIFT     0x0UL
 129 #define DX_HOST_KFDE2_VALID_VALUE_BIT_SIZE      0x1UL
 130 #define DX_HOST_KFDE3_VALID_REG_OFFSET  0xA6CUL
 131 #define DX_HOST_KFDE3_VALID_VALUE_BIT_SHIFT     0x0UL
 132 #define DX_HOST_KFDE3_VALID_VALUE_BIT_SIZE      0x1UL
 133 #define DX_HOST_GPR0_REG_OFFSET 0xA70UL
 134 #define DX_HOST_GPR0_VALUE_BIT_SHIFT    0x0UL
 135 #define DX_HOST_GPR0_VALUE_BIT_SIZE     0x20UL
 136 #define DX_GPR_HOST_REG_OFFSET  0xA74UL
 137 #define DX_GPR_HOST_VALUE_BIT_SHIFT     0x0UL
 138 #define DX_GPR_HOST_VALUE_BIT_SIZE      0x20UL
 139 #define DX_HOST_POWER_DOWN_EN_REG_OFFSET        0xA78UL
 140 #define DX_HOST_POWER_DOWN_EN_VALUE_BIT_SHIFT   0x0UL
 141 #define DX_HOST_POWER_DOWN_EN_VALUE_BIT_SIZE    0x1UL
 142 // --------------------------------------
 143 // BLOCK: HOST_SRAM
 144 // --------------------------------------
 145 #define DX_SRAM_DATA_REG_OFFSET 0xF00UL
 146 #define DX_SRAM_DATA_VALUE_BIT_SHIFT    0x0UL
 147 #define DX_SRAM_DATA_VALUE_BIT_SIZE     0x20UL
 148 #define DX_SRAM_ADDR_REG_OFFSET 0xF04UL
 149 #define DX_SRAM_ADDR_VALUE_BIT_SHIFT    0x0UL
 150 #define DX_SRAM_ADDR_VALUE_BIT_SIZE     0xFUL
 151 #define DX_SRAM_DATA_READY_REG_OFFSET   0xF08UL
 152 #define DX_SRAM_DATA_READY_VALUE_BIT_SHIFT      0x0UL
 153 #define DX_SRAM_DATA_READY_VALUE_BIT_SIZE       0x1UL
 154
 155 #endif //__DX_HOST_H__