2 * Copyright (C) 2012-2017 ARM Limited or its affiliates.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, see <http://www.gnu.org/licenses/>.
17 #ifndef __CC_HW_QUEUE_DEFS_H__
18 #define __CC_HW_QUEUE_DEFS_H__
20 #include <linux/types.h>
22 #include "dx_crys_kernel.h"
23 #include <linux/bitfield.h>
25 /******************************************************************************
27 ******************************************************************************/
29 #define HW_DESC_SIZE_WORDS 6
30 /* Define max. available slots in HW queue */
31 #define HW_QUEUE_SLOTS_MAX 15
33 #define CC_REG_NAME(word, name) DX_DSCRPTR_QUEUE_WORD ## word ## _ ## name
35 #define CC_REG_LOW(word, name) \
36 (DX_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SHIFT)
38 #define CC_REG_HIGH(word, name) \
39 (CC_REG_LOW(word, name) + \
40 DX_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SIZE - 1)
42 #define CC_GENMASK(word, name) \
43 GENMASK(CC_REG_HIGH(word, name), CC_REG_LOW(word, name))
45 #define WORD0_VALUE CC_GENMASK(0, VALUE)
46 #define WORD1_DIN_CONST_VALUE CC_GENMASK(1, DIN_CONST_VALUE)
47 #define WORD1_DIN_DMA_MODE CC_GENMASK(1, DIN_DMA_MODE)
48 #define WORD1_DIN_SIZE CC_GENMASK(1, DIN_SIZE)
49 #define WORD1_NOT_LAST CC_GENMASK(1, NOT_LAST)
50 #define WORD1_NS_BIT CC_GENMASK(1, NS_BIT)
51 #define WORD2_VALUE CC_GENMASK(2, VALUE)
52 #define WORD3_DOUT_DMA_MODE CC_GENMASK(3, DOUT_DMA_MODE)
53 #define WORD3_DOUT_LAST_IND CC_GENMASK(3, DOUT_LAST_IND)
54 #define WORD3_DOUT_SIZE CC_GENMASK(3, DOUT_SIZE)
55 #define WORD3_HASH_XOR_BIT CC_GENMASK(3, HASH_XOR_BIT)
56 #define WORD3_NS_BIT CC_GENMASK(3, NS_BIT)
57 #define WORD3_QUEUE_LAST_IND CC_GENMASK(3, QUEUE_LAST_IND)
58 #define WORD4_ACK_NEEDED CC_GENMASK(4, ACK_NEEDED)
59 #define WORD4_AES_SEL_N_HASH CC_GENMASK(4, AES_SEL_N_HASH)
60 #define WORD4_BYTES_SWAP CC_GENMASK(4, BYTES_SWAP)
61 #define WORD4_CIPHER_CONF0 CC_GENMASK(4, CIPHER_CONF0)
62 #define WORD4_CIPHER_CONF1 CC_GENMASK(4, CIPHER_CONF1)
63 #define WORD4_CIPHER_CONF2 CC_GENMASK(4, CIPHER_CONF2)
64 #define WORD4_CIPHER_DO CC_GENMASK(4, CIPHER_DO)
65 #define WORD4_CIPHER_MODE CC_GENMASK(4, CIPHER_MODE)
66 #define WORD4_CMAC_SIZE0 CC_GENMASK(4, CMAC_SIZE0)
67 #define WORD4_DATA_FLOW_MODE CC_GENMASK(4, DATA_FLOW_MODE)
68 #define WORD4_KEY_SIZE CC_GENMASK(4, KEY_SIZE)
69 #define WORD4_SETUP_OPERATION CC_GENMASK(4, SETUP_OPERATION)
70 #define WORD5_DIN_ADDR_HIGH CC_GENMASK(5, DIN_ADDR_HIGH)
71 #define WORD5_DOUT_ADDR_HIGH CC_GENMASK(5, DOUT_ADDR_HIGH)
73 /******************************************************************************
75 ******************************************************************************/
79 u32 word[HW_DESC_SIZE_WORDS];
80 u16 hword[HW_DESC_SIZE_WORDS * 2];
89 enum cc_desc_direction {
90 DESC_DIRECTION_ILLEGAL = -1,
91 DESC_DIRECTION_ENCRYPT_ENCRYPT = 0,
92 DESC_DIRECTION_DECRYPT_DECRYPT = 1,
93 DESC_DIRECTION_DECRYPT_ENCRYPT = 3,
94 DESC_DIRECTION_END = S32_MAX,
103 DMA_MODE_END = S32_MAX,
117 DIN_HASH_and_BYPASS = 8,
118 AESMAC_and_BYPASS = 9,
119 AES_to_HASH_and_DOUT = 10,
121 DES_to_HASH_and_DOUT = 12,
122 AES_to_AES_to_HASH_and_DOUT = 13,
123 AES_to_AES_to_HASH = 14,
124 AES_to_HASH_and_AES = 15,
125 DIN_MULTI2_DOUT = 16,
133 S_DIN_to_MULTI2 = 36,
141 FLOW_MODE_END = S32_MAX,
145 TUNNEL_OP_INVALID = -1,
148 TUNNEL_OP_END = S32_MAX,
153 SETUP_LOAD_STATE0 = 1,
154 SETUP_LOAD_STATE1 = 2,
155 SETUP_LOAD_STATE2 = 3,
157 SETUP_LOAD_XEX_KEY = 5,
158 SETUP_WRITE_STATE0 = 8,
159 SETUP_WRITE_STATE1 = 9,
160 SETUP_WRITE_STATE2 = 10,
161 SETUP_WRITE_STATE3 = 11,
162 SETUP_OP_END = S32_MAX,
165 enum cc_aes_mac_selector {
169 AES_MAC_END = S32_MAX,
172 #define HW_KEY_MASK_CIPHER_DO 0x3
173 #define HW_KEY_SHIFT_CIPHER_CFG2 2
175 /* HwCryptoKey[1:0] is mapped to cipher_do[1:0] */
176 /* HwCryptoKey[2:3] is mapped to cipher_config2[1:0] */
177 enum cc_hw_crypto_key {
178 USER_KEY = 0, /* 0x0000 */
179 ROOT_KEY = 1, /* 0x0001 */
180 PROVISIONING_KEY = 2, /* 0x0010 */ /* ==KCP */
181 SESSION_KEY = 3, /* 0x0011 */
182 RESERVED_KEY = 4, /* NA */
183 PLATFORM_KEY = 5, /* 0x0101 */
184 CUSTOMER_KEY = 6, /* 0x0110 */
185 KFDE0_KEY = 7, /* 0x0111 */
186 KFDE1_KEY = 9, /* 0x1001 */
187 KFDE2_KEY = 10, /* 0x1010 */
188 KFDE3_KEY = 11, /* 0x1011 */
189 END_OF_KEYS = S32_MAX,
192 enum cc_hw_aes_key_size {
196 END_OF_AES_KEYS = S32_MAX,
199 enum cc_hw_des_key_size {
203 END_OF_DES_KEYS = S32_MAX,
206 /*****************************/
207 /* Descriptor packing macros */
208 /*****************************/
211 * Init a HW descriptor struct
212 * @pdesc: pointer HW descriptor struct
214 static inline void hw_desc_init(struct cc_hw_desc *pdesc)
216 memset(pdesc, 0, sizeof(struct cc_hw_desc));
220 * Indicates the end of current HW descriptors flow and release the HW engines.
222 * @pdesc: pointer HW descriptor struct
224 static inline void set_queue_last_ind(struct cc_hw_desc *pdesc)
226 pdesc->word[3] |= FIELD_PREP(WORD3_QUEUE_LAST_IND, 1);
230 * Set the DIN field of a HW descriptors
232 * @pdesc: pointer HW descriptor struct
233 * @dma_mode: dmaMode The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT
234 * @addr: dinAdr DIN address
235 * @size: Data size in bytes
236 * @axi_sec: AXI secure bit
238 static inline void set_din_type(struct cc_hw_desc *pdesc,
239 enum cc_dma_mode dma_mode, dma_addr_t addr,
240 u32 size, enum cc_axi_sec axi_sec)
242 pdesc->word[0] = (u32)addr;
243 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
244 pdesc->word[5] |= FIELD_PREP(WORD5_DIN_ADDR_HIGH, ((u16)(addr >> 32)));
246 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_DMA_MODE, dma_mode) |
247 FIELD_PREP(WORD1_DIN_SIZE, size) |
248 FIELD_PREP(WORD1_NS_BIT, axi_sec);
252 * Set the DIN field of a HW descriptors to NO DMA mode.
253 * Used for NOP descriptor, register patches and other special modes.
255 * @pdesc: pointer HW descriptor struct
257 * @size: Data size in bytes
259 static inline void set_din_no_dma(struct cc_hw_desc *pdesc, u32 addr, u32 size)
261 pdesc->word[0] = addr;
262 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size);
266 * Set the DIN field of a HW descriptors to SRAM mode.
267 * Note: No need to check SRAM alignment since host requests do not use SRAM and
268 * adaptor will enforce alignment check.
270 * @pdesc: pointer HW descriptor struct
272 * @size Data size in bytes
274 static inline void set_din_sram(struct cc_hw_desc *pdesc, dma_addr_t addr,
277 pdesc->word[0] = (u32)addr;
278 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size) |
279 FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM);
283 * Set the DIN field of a HW descriptors to CONST mode
285 * @pdesc: pointer HW descriptor struct
286 * @val: DIN const value
287 * @size: Data size in bytes
289 static inline void set_din_const(struct cc_hw_desc *pdesc, u32 val, u32 size)
291 pdesc->word[0] = val;
292 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_CONST_VALUE, 1) |
293 FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM) |
294 FIELD_PREP(WORD1_DIN_SIZE, size);
298 * Set the DIN not last input data indicator
300 * @pdesc: pointer HW descriptor struct
302 static inline void set_din_not_last_indication(struct cc_hw_desc *pdesc)
304 pdesc->word[1] |= FIELD_PREP(WORD1_NOT_LAST, 1);
308 * Set the DOUT field of a HW descriptors
310 * @pdesc: pointer HW descriptor struct
311 * @dma_mode: The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT
312 * @addr: DOUT address
313 * @size: Data size in bytes
314 * @axi_sec: AXI secure bit
316 static inline void set_dout_type(struct cc_hw_desc *pdesc,
317 enum cc_dma_mode dma_mode, dma_addr_t addr,
318 u32 size, enum cc_axi_sec axi_sec)
320 pdesc->word[2] = (u32)addr;
321 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
322 pdesc->word[5] |= FIELD_PREP(WORD5_DOUT_ADDR_HIGH, ((u16)(addr >> 32)));
324 pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_DMA_MODE, dma_mode) |
325 FIELD_PREP(WORD3_DOUT_SIZE, size) |
326 FIELD_PREP(WORD3_NS_BIT, axi_sec);
330 * Set the DOUT field of a HW descriptors to DLLI type
331 * The LAST INDICATION is provided by the user
333 * @pdesc pointer HW descriptor struct
334 * @addr: DOUT address
335 * @size: Data size in bytes
336 * @last_ind: The last indication bit
337 * @axi_sec: AXI secure bit
339 static inline void set_dout_dlli(struct cc_hw_desc *pdesc, dma_addr_t addr,
340 u32 size, enum cc_axi_sec axi_sec,
343 set_dout_type(pdesc, DMA_DLLI, addr, size, axi_sec);
344 pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_LAST_IND, last_ind);
348 * Set the DOUT field of a HW descriptors to DLLI type
349 * The LAST INDICATION is provided by the user
351 * @pdesc: pointer HW descriptor struct
352 * @addr: DOUT address
353 * @size: Data size in bytes
354 * @last_ind: The last indication bit
355 * @axi_sec: AXI secure bit
357 static inline void set_dout_mlli(struct cc_hw_desc *pdesc, dma_addr_t addr,
358 u32 size, enum cc_axi_sec axi_sec,
361 set_dout_type(pdesc, DMA_MLLI, addr, size, axi_sec);
362 pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_LAST_IND, last_ind);
366 * Set the DOUT field of a HW descriptors to NO DMA mode.
367 * Used for NOP descriptor, register patches and other special modes.
369 * @pdesc: pointer HW descriptor struct
370 * @addr: DOUT address
371 * @size: Data size in bytes
372 * @write_enable: Enables a write operation to a register
374 static inline void set_dout_no_dma(struct cc_hw_desc *pdesc, u32 addr,
375 u32 size, bool write_enable)
377 pdesc->word[2] = addr;
378 pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_SIZE, size) |
379 FIELD_PREP(WORD3_DOUT_LAST_IND, write_enable);
383 * Set the word for the XOR operation.
385 * @pdesc: pointer HW descriptor struct
386 * @val: xor data value
388 static inline void set_xor_val(struct cc_hw_desc *pdesc, u32 val)
390 pdesc->word[2] = val;
394 * Sets the XOR indicator bit in the descriptor
396 * @pdesc: pointer HW descriptor struct
398 static inline void set_xor_active(struct cc_hw_desc *pdesc)
400 pdesc->word[3] |= FIELD_PREP(WORD3_HASH_XOR_BIT, 1);
404 * Select the AES engine instead of HASH engine when setting up combined mode
407 * @pdesc: pointer HW descriptor struct
409 static inline void set_aes_not_hash_mode(struct cc_hw_desc *pdesc)
411 pdesc->word[4] |= FIELD_PREP(WORD4_AES_SEL_N_HASH, 1);
415 * Set the DOUT field of a HW descriptors to SRAM mode
416 * Note: No need to check SRAM alignment since host requests do not use SRAM and
417 * adaptor will enforce alignment check.
419 * @pdesc: pointer HW descriptor struct
420 * @addr: DOUT address
421 * @size: Data size in bytes
423 static inline void set_dout_sram(struct cc_hw_desc *pdesc, u32 addr, u32 size)
425 pdesc->word[2] = addr;
426 pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_DMA_MODE, DMA_SRAM) |
427 FIELD_PREP(WORD3_DOUT_SIZE, size);
431 * Sets the data unit size for XEX mode in data_out_addr[15:0]
433 * @pdesc: pDesc pointer HW descriptor struct
434 * @size: data unit size for XEX mode
436 static inline void set_xex_data_unit_size(struct cc_hw_desc *pdesc, u32 size)
438 pdesc->word[2] = size;
442 * Set the number of rounds for Multi2 in data_out_addr[15:0]
444 * @pdesc: pointer HW descriptor struct
445 * @num: number of rounds for Multi2
447 static inline void set_multi2_num_rounds(struct cc_hw_desc *pdesc, u32 num)
449 pdesc->word[2] = num;
455 * @pdesc: pointer HW descriptor struct
456 * @mode: Any one of the modes defined in [CC7x-DESC]
458 static inline void set_flow_mode(struct cc_hw_desc *pdesc,
459 enum cc_flow_mode mode)
461 pdesc->word[4] |= FIELD_PREP(WORD4_DATA_FLOW_MODE, mode);
465 * Set the cipher mode.
467 * @pdesc: pointer HW descriptor struct
468 * @mode: Any one of the modes defined in [CC7x-DESC]
470 static inline void set_cipher_mode(struct cc_hw_desc *pdesc, int mode)
472 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_MODE, mode);
476 * Set the cipher configuration fields.
478 * @pdesc: pointer HW descriptor struct
479 * @mode: Any one of the modes defined in [CC7x-DESC]
481 static inline void set_cipher_config0(struct cc_hw_desc *pdesc, int mode)
483 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF0, mode);
487 * Set the cipher configuration fields.
489 * @pdesc: pointer HW descriptor struct
490 * @config: Any one of the modes defined in [CC7x-DESC]
492 static inline void set_cipher_config1(struct cc_hw_desc *pdesc,
493 enum cc_hash_conf_pad config)
495 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF1, config);
499 * Set HW key configuration fields.
501 * @pdesc: pointer HW descriptor struct
502 * @hw_key: The HW key slot asdefined in enum cc_hw_crypto_key
504 static inline void set_hw_crypto_key(struct cc_hw_desc *pdesc,
505 enum cc_hw_crypto_key hw_key)
507 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO,
508 (hw_key & HW_KEY_MASK_CIPHER_DO)) |
509 FIELD_PREP(WORD4_CIPHER_CONF2,
510 (hw_key >> HW_KEY_SHIFT_CIPHER_CFG2));
514 * Set byte order of all setup-finalize descriptors.
516 * @pdesc: pointer HW descriptor struct
517 * @config: Any one of the modes defined in [CC7x-DESC]
519 static inline void set_bytes_swap(struct cc_hw_desc *pdesc, bool config)
521 pdesc->word[4] |= FIELD_PREP(WORD4_BYTES_SWAP, config);
525 * Set CMAC_SIZE0 mode.
527 * @pdesc: pointer HW descriptor struct
529 static inline void set_cmac_size0_mode(struct cc_hw_desc *pdesc)
531 pdesc->word[4] |= FIELD_PREP(WORD4_CMAC_SIZE0, 1);
535 * Set key size descriptor field.
537 * @pdesc: pointer HW descriptor struct
538 * @size: key size in bytes (NOT size code)
540 static inline void set_key_size(struct cc_hw_desc *pdesc, u32 size)
542 pdesc->word[4] |= FIELD_PREP(WORD4_KEY_SIZE, size);
548 * @pdesc: pointer HW descriptor struct
549 * @size: key size in bytes (NOT size code)
551 static inline void set_key_size_aes(struct cc_hw_desc *pdesc, u32 size)
553 set_key_size(pdesc, ((size >> 3) - 2));
559 * @pdesc: pointer HW descriptor struct
560 * @size: key size in bytes (NOT size code)
562 static inline void set_key_size_des(struct cc_hw_desc *pdesc, u32 size)
564 set_key_size(pdesc, ((size >> 3) - 1));
568 * Set the descriptor setup mode
570 * @pdesc: pointer HW descriptor struct
571 * @mode: Any one of the setup modes defined in [CC7x-DESC]
573 static inline void set_setup_mode(struct cc_hw_desc *pdesc,
574 enum cc_setup_op mode)
576 pdesc->word[4] |= FIELD_PREP(WORD4_SETUP_OPERATION, mode);
580 * Set the descriptor cipher DO
582 * @pdesc: pointer HW descriptor struct
583 * @config: Any one of the cipher do defined in [CC7x-DESC]
585 static inline void set_cipher_do(struct cc_hw_desc *pdesc,
586 enum cc_hash_cipher_pad config)
588 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO,
589 (config & HW_KEY_MASK_CIPHER_DO));
592 #endif /*__CC_HW_QUEUE_DEFS_H__*/