drivers/staging/ccree/cc_crypto_ctx.h

   1 /*
   2  * Copyright (C) 2012-2017 ARM Limited or its affiliates.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #ifndef _CC_CRYPTO_CTX_H_
  18 #define _CC_CRYPTO_CTX_H_
  19
  20 #include <linux/types.h>
  21
  22 /* context size */
  23 #ifndef CC_CTX_SIZE_LOG2
  24 #if (CC_SUPPORT_SHA > 256)
  25 #define CC_CTX_SIZE_LOG2 8
  26 #else
  27 #define CC_CTX_SIZE_LOG2 7
  28 #endif
  29 #endif
  30 #define CC_CTX_SIZE BIT(CC_CTX_SIZE_LOG2)
  31 #define CC_DRV_CTX_SIZE_WORDS (CC_CTX_SIZE >> 2)
  32
  33 #define CC_DRV_DES_IV_SIZE 8
  34 #define CC_DRV_DES_BLOCK_SIZE 8
  35
  36 #define CC_DRV_DES_ONE_KEY_SIZE 8
  37 #define CC_DRV_DES_DOUBLE_KEY_SIZE 16
  38 #define CC_DRV_DES_TRIPLE_KEY_SIZE 24
  39 #define CC_DRV_DES_KEY_SIZE_MAX CC_DRV_DES_TRIPLE_KEY_SIZE
  40
  41 #define CC_AES_IV_SIZE 16
  42 #define CC_AES_IV_SIZE_WORDS (CC_AES_IV_SIZE >> 2)
  43
  44 #define CC_AES_BLOCK_SIZE 16
  45 #define CC_AES_BLOCK_SIZE_WORDS 4
  46
  47 #define CC_AES_128_BIT_KEY_SIZE 16
  48 #define CC_AES_128_BIT_KEY_SIZE_WORDS   (CC_AES_128_BIT_KEY_SIZE >> 2)
  49 #define CC_AES_192_BIT_KEY_SIZE 24
  50 #define CC_AES_192_BIT_KEY_SIZE_WORDS   (CC_AES_192_BIT_KEY_SIZE >> 2)
  51 #define CC_AES_256_BIT_KEY_SIZE 32
  52 #define CC_AES_256_BIT_KEY_SIZE_WORDS   (CC_AES_256_BIT_KEY_SIZE >> 2)
  53 #define CC_AES_KEY_SIZE_MAX                     CC_AES_256_BIT_KEY_SIZE
  54 #define CC_AES_KEY_SIZE_WORDS_MAX               (CC_AES_KEY_SIZE_MAX >> 2)
  55
  56 #define CC_MD5_DIGEST_SIZE      16
  57 #define CC_SHA1_DIGEST_SIZE     20
  58 #define CC_SHA224_DIGEST_SIZE   28
  59 #define CC_SHA256_DIGEST_SIZE   32
  60 #define CC_SHA256_DIGEST_SIZE_IN_WORDS 8
  61 #define CC_SHA384_DIGEST_SIZE   48
  62 #define CC_SHA512_DIGEST_SIZE   64
  63
  64 #define CC_SHA1_BLOCK_SIZE 64
  65 #define CC_SHA1_BLOCK_SIZE_IN_WORDS 16
  66 #define CC_MD5_BLOCK_SIZE 64
  67 #define CC_MD5_BLOCK_SIZE_IN_WORDS 16
  68 #define CC_SHA224_BLOCK_SIZE 64
  69 #define CC_SHA256_BLOCK_SIZE 64
  70 #define CC_SHA256_BLOCK_SIZE_IN_WORDS 16
  71 #define CC_SHA1_224_256_BLOCK_SIZE 64
  72 #define CC_SHA384_BLOCK_SIZE 128
  73 #define CC_SHA512_BLOCK_SIZE 128
  74
  75 #if (CC_SUPPORT_SHA > 256)
  76 #define CC_DIGEST_SIZE_MAX CC_SHA512_DIGEST_SIZE
  77 #define CC_HASH_BLOCK_SIZE_MAX CC_SHA512_BLOCK_SIZE /*1024b*/
  78 #else /* Only up to SHA256 */
  79 #define CC_DIGEST_SIZE_MAX CC_SHA256_DIGEST_SIZE
  80 #define CC_HASH_BLOCK_SIZE_MAX CC_SHA256_BLOCK_SIZE /*512b*/
  81 #endif
  82
  83 #define CC_HMAC_BLOCK_SIZE_MAX CC_HASH_BLOCK_SIZE_MAX
  84
  85 #define CC_MULTI2_SYSTEM_KEY_SIZE               32
  86 #define CC_MULTI2_DATA_KEY_SIZE         8
  87 #define CC_MULTI2_SYSTEM_N_DATA_KEY_SIZE \
  88                 (CC_MULTI2_SYSTEM_KEY_SIZE + CC_MULTI2_DATA_KEY_SIZE)
  89 #define CC_MULTI2_BLOCK_SIZE                                    8
  90 #define CC_MULTI2_IV_SIZE                                       8
  91 #define CC_MULTI2_MIN_NUM_ROUNDS                                8
  92 #define CC_MULTI2_MAX_NUM_ROUNDS                                128
  93
  94 #define CC_DRV_ALG_MAX_BLOCK_SIZE CC_HASH_BLOCK_SIZE_MAX
  95
  96 enum drv_engine_type {
  97         DRV_ENGINE_NULL = 0,
  98         DRV_ENGINE_AES = 1,
  99         DRV_ENGINE_DES = 2,
 100         DRV_ENGINE_HASH = 3,
 101         DRV_ENGINE_RC4 = 4,
 102         DRV_ENGINE_DOUT = 5,
 103         DRV_ENGINE_RESERVE32B = S32_MAX,
 104 };
 105
 106 enum drv_crypto_alg {
 107         DRV_CRYPTO_ALG_NULL = -1,
 108         DRV_CRYPTO_ALG_AES  = 0,
 109         DRV_CRYPTO_ALG_DES  = 1,
 110         DRV_CRYPTO_ALG_HASH = 2,
 111         DRV_CRYPTO_ALG_C2   = 3,
 112         DRV_CRYPTO_ALG_HMAC = 4,
 113         DRV_CRYPTO_ALG_AEAD = 5,
 114         DRV_CRYPTO_ALG_BYPASS = 6,
 115         DRV_CRYPTO_ALG_NUM = 7,
 116         DRV_CRYPTO_ALG_RESERVE32B = S32_MAX
 117 };
 118
 119 enum drv_crypto_direction {
 120         DRV_CRYPTO_DIRECTION_NULL = -1,
 121         DRV_CRYPTO_DIRECTION_ENCRYPT = 0,
 122         DRV_CRYPTO_DIRECTION_DECRYPT = 1,
 123         DRV_CRYPTO_DIRECTION_DECRYPT_ENCRYPT = 3,
 124         DRV_CRYPTO_DIRECTION_RESERVE32B = S32_MAX
 125 };
 126
 127 enum drv_cipher_mode {
 128         DRV_CIPHER_NULL_MODE = -1,
 129         DRV_CIPHER_ECB = 0,
 130         DRV_CIPHER_CBC = 1,
 131         DRV_CIPHER_CTR = 2,
 132         DRV_CIPHER_CBC_MAC = 3,
 133         DRV_CIPHER_XTS = 4,
 134         DRV_CIPHER_XCBC_MAC = 5,
 135         DRV_CIPHER_OFB = 6,
 136         DRV_CIPHER_CMAC = 7,
 137         DRV_CIPHER_CCM = 8,
 138         DRV_CIPHER_CBC_CTS = 11,
 139         DRV_CIPHER_GCTR = 12,
 140         DRV_CIPHER_ESSIV = 13,
 141         DRV_CIPHER_BITLOCKER = 14,
 142         DRV_CIPHER_RESERVE32B = S32_MAX
 143 };
 144
 145 enum drv_hash_mode {
 146         DRV_HASH_NULL = -1,
 147         DRV_HASH_SHA1 = 0,
 148         DRV_HASH_SHA256 = 1,
 149         DRV_HASH_SHA224 = 2,
 150         DRV_HASH_SHA512 = 3,
 151         DRV_HASH_SHA384 = 4,
 152         DRV_HASH_MD5 = 5,
 153         DRV_HASH_CBC_MAC = 6,
 154         DRV_HASH_XCBC_MAC = 7,
 155         DRV_HASH_CMAC = 8,
 156         DRV_HASH_MODE_NUM = 9,
 157         DRV_HASH_RESERVE32B = S32_MAX
 158 };
 159
 160 enum drv_hash_hw_mode {
 161         DRV_HASH_HW_MD5 = 0,
 162         DRV_HASH_HW_SHA1 = 1,
 163         DRV_HASH_HW_SHA256 = 2,
 164         DRV_HASH_HW_SHA224 = 10,
 165         DRV_HASH_HW_SHA512 = 4,
 166         DRV_HASH_HW_SHA384 = 12,
 167         DRV_HASH_HW_GHASH = 6,
 168         DRV_HASH_HW_RESERVE32B = S32_MAX
 169 };
 170
 171 enum drv_multi2_mode {
 172         DRV_MULTI2_NULL = -1,
 173         DRV_MULTI2_ECB = 0,
 174         DRV_MULTI2_CBC = 1,
 175         DRV_MULTI2_OFB = 2,
 176         DRV_MULTI2_RESERVE32B = S32_MAX
 177 };
 178
 179 /* drv_crypto_key_type[1:0] is mapped to cipher_do[1:0] */
 180 /* drv_crypto_key_type[2] is mapped to cipher_config2 */
 181 enum drv_crypto_key_type {
 182         DRV_NULL_KEY = -1,
 183         DRV_USER_KEY = 0,               /* 0x000 */
 184         DRV_ROOT_KEY = 1,               /* 0x001 */
 185         DRV_PROVISIONING_KEY = 2,       /* 0x010 */
 186         DRV_SESSION_KEY = 3,            /* 0x011 */
 187         DRV_APPLET_KEY = 4,             /* NA */
 188         DRV_PLATFORM_KEY = 5,           /* 0x101 */
 189         DRV_CUSTOMER_KEY = 6,           /* 0x110 */
 190         DRV_END_OF_KEYS = S32_MAX,
 191 };
 192
 193 enum drv_crypto_padding_type {
 194         DRV_PADDING_NONE = 0,
 195         DRV_PADDING_PKCS7 = 1,
 196         DRV_PADDING_RESERVE32B = S32_MAX
 197 };
 198
 199 #endif /* _CC_CRYPTO_CTX_H_ */
 200