drivers/spmi/spmi-pmic-arb.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2012-2015, 2017, 2021, The Linux Foundation. All rights reserved.
   4  */
   5 #include <linux/bitmap.h>
   6 #include <linux/delay.h>
   7 #include <linux/err.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/io.h>
  10 #include <linux/irqchip/chained_irq.h>
  11 #include <linux/irqdomain.h>
  12 #include <linux/irq.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/slab.h>
  18 #include <linux/spmi.h>
  19
  20 /* PMIC Arbiter configuration registers */
  21 #define PMIC_ARB_VERSION                0x0000
  22 #define PMIC_ARB_VERSION_V2_MIN         0x20010000
  23 #define PMIC_ARB_VERSION_V3_MIN         0x30000000
  24 #define PMIC_ARB_VERSION_V5_MIN         0x50000000
  25 #define PMIC_ARB_INT_EN                 0x0004
  26
  27 /* PMIC Arbiter channel registers offsets */
  28 #define PMIC_ARB_CMD                    0x00
  29 #define PMIC_ARB_CONFIG                 0x04
  30 #define PMIC_ARB_STATUS                 0x08
  31 #define PMIC_ARB_WDATA0                 0x10
  32 #define PMIC_ARB_WDATA1                 0x14
  33 #define PMIC_ARB_RDATA0                 0x18
  34 #define PMIC_ARB_RDATA1                 0x1C
  35
  36 /* Mapping Table */
  37 #define SPMI_MAPPING_TABLE_REG(N)       (0x0B00 + (4 * (N)))
  38 #define SPMI_MAPPING_BIT_INDEX(X)       (((X) >> 18) & 0xF)
  39 #define SPMI_MAPPING_BIT_IS_0_FLAG(X)   (((X) >> 17) & 0x1)
  40 #define SPMI_MAPPING_BIT_IS_0_RESULT(X) (((X) >> 9) & 0xFF)
  41 #define SPMI_MAPPING_BIT_IS_1_FLAG(X)   (((X) >> 8) & 0x1)
  42 #define SPMI_MAPPING_BIT_IS_1_RESULT(X) (((X) >> 0) & 0xFF)
  43
  44 #define SPMI_MAPPING_TABLE_TREE_DEPTH   16      /* Maximum of 16-bits */
  45 #define PMIC_ARB_MAX_PPID               BIT(12) /* PPID is 12bit */
  46 #define PMIC_ARB_APID_VALID             BIT(15)
  47 #define PMIC_ARB_CHAN_IS_IRQ_OWNER(reg) ((reg) & BIT(24))
  48 #define INVALID_EE                              0xFF
  49
  50 /* Ownership Table */
  51 #define SPMI_OWNERSHIP_TABLE_REG(N)     (0x0700 + (4 * (N)))
  52 #define SPMI_OWNERSHIP_PERIPH2OWNER(X)  ((X) & 0x7)
  53
  54 /* Channel Status fields */
  55 enum pmic_arb_chnl_status {
  56         PMIC_ARB_STATUS_DONE    = BIT(0),
  57         PMIC_ARB_STATUS_FAILURE = BIT(1),
  58         PMIC_ARB_STATUS_DENIED  = BIT(2),
  59         PMIC_ARB_STATUS_DROPPED = BIT(3),
  60 };
  61
  62 /* Command register fields */
  63 #define PMIC_ARB_CMD_MAX_BYTE_COUNT     8
  64
  65 /* Command Opcodes */
  66 enum pmic_arb_cmd_op_code {
  67         PMIC_ARB_OP_EXT_WRITEL = 0,
  68         PMIC_ARB_OP_EXT_READL = 1,
  69         PMIC_ARB_OP_EXT_WRITE = 2,
  70         PMIC_ARB_OP_RESET = 3,
  71         PMIC_ARB_OP_SLEEP = 4,
  72         PMIC_ARB_OP_SHUTDOWN = 5,
  73         PMIC_ARB_OP_WAKEUP = 6,
  74         PMIC_ARB_OP_AUTHENTICATE = 7,
  75         PMIC_ARB_OP_MSTR_READ = 8,
  76         PMIC_ARB_OP_MSTR_WRITE = 9,
  77         PMIC_ARB_OP_EXT_READ = 13,
  78         PMIC_ARB_OP_WRITE = 14,
  79         PMIC_ARB_OP_READ = 15,
  80         PMIC_ARB_OP_ZERO_WRITE = 16,
  81 };
  82
  83 /*
  84  * PMIC arbiter version 5 uses different register offsets for read/write vs
  85  * observer channels.
  86  */
  87 enum pmic_arb_channel {
  88         PMIC_ARB_CHANNEL_RW,
  89         PMIC_ARB_CHANNEL_OBS,
  90 };
  91
  92 /* Maximum number of support PMIC peripherals */
  93 #define PMIC_ARB_MAX_PERIPHS            512
  94 #define PMIC_ARB_TIMEOUT_US             1000
  95 #define PMIC_ARB_MAX_TRANS_BYTES        (8)
  96
  97 #define PMIC_ARB_APID_MASK              0xFF
  98 #define PMIC_ARB_PPID_MASK              0xFFF
  99
 100 /* interrupt enable bit */
 101 #define SPMI_PIC_ACC_ENABLE_BIT         BIT(0)
 102
 103 #define spec_to_hwirq(slave_id, periph_id, irq_id, apid) \
 104         ((((slave_id) & 0xF)   << 28) | \
 105         (((periph_id) & 0xFF)  << 20) | \
 106         (((irq_id)    & 0x7)   << 16) | \
 107         (((apid)      & 0x1FF) << 0))
 108
 109 #define hwirq_to_sid(hwirq)  (((hwirq) >> 28) & 0xF)
 110 #define hwirq_to_per(hwirq)  (((hwirq) >> 20) & 0xFF)
 111 #define hwirq_to_irq(hwirq)  (((hwirq) >> 16) & 0x7)
 112 #define hwirq_to_apid(hwirq) (((hwirq) >> 0)  & 0x1FF)
 113
 114 struct pmic_arb_ver_ops;
 115
 116 struct apid_data {
 117         u16             ppid;
 118         u8              write_ee;
 119         u8              irq_ee;
 120 };
 121
 122 /**
 123  * spmi_pmic_arb - SPMI PMIC Arbiter object
 124  *
 125  * @rd_base:            on v1 "core", on v2 "observer" register base off DT.
 126  * @wr_base:            on v1 "core", on v2 "chnls"    register base off DT.
 127  * @intr:               address of the SPMI interrupt control registers.
 128  * @cnfg:               address of the PMIC Arbiter configuration registers.
 129  * @lock:               lock to synchronize accesses.
 130  * @channel:            execution environment channel to use for accesses.
 131  * @irq:                PMIC ARB interrupt.
 132  * @ee:                 the current Execution Environment
 133  * @min_apid:           minimum APID (used for bounding IRQ search)
 134  * @max_apid:           maximum APID
 135  * @mapping_table:      in-memory copy of PPID -> APID mapping table.
 136  * @domain:             irq domain object for PMIC IRQ domain
 137  * @spmic:              SPMI controller object
 138  * @ver_ops:            version dependent operations.
 139  * @ppid_to_apid        in-memory copy of PPID -> APID mapping table.
 140  */
 141 struct spmi_pmic_arb {
 142         void __iomem            *rd_base;
 143         void __iomem            *wr_base;
 144         void __iomem            *intr;
 145         void __iomem            *cnfg;
 146         void __iomem            *core;
 147         resource_size_t         core_size;
 148         raw_spinlock_t          lock;
 149         u8                      channel;
 150         int                     irq;
 151         u8                      ee;
 152         u16                     min_apid;
 153         u16                     max_apid;
 154         u32                     *mapping_table;
 155         DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS);
 156         struct irq_domain       *domain;
 157         struct spmi_controller  *spmic;
 158         const struct pmic_arb_ver_ops *ver_ops;
 159         u16                     *ppid_to_apid;
 160         u16                     last_apid;
 161         struct apid_data        apid_data[PMIC_ARB_MAX_PERIPHS];
 162 };
 163
 164 /**
 165  * pmic_arb_ver: version dependent functionality.
 166  *
 167  * @ver_str:            version string.
 168  * @ppid_to_apid:       finds the apid for a given ppid.
 169  * @non_data_cmd:       on v1 issues an spmi non-data command.
 170  *                      on v2 no HW support, returns -EOPNOTSUPP.
 171  * @offset:             on v1 offset of per-ee channel.
 172  *                      on v2 offset of per-ee and per-ppid channel.
 173  * @fmt_cmd:            formats a GENI/SPMI command.
 174  * @owner_acc_status:   on v1 address of PMIC_ARB_SPMI_PIC_OWNERm_ACC_STATUSn
 175  *                      on v2 address of SPMI_PIC_OWNERm_ACC_STATUSn.
 176  * @acc_enable:         on v1 address of PMIC_ARB_SPMI_PIC_ACC_ENABLEn
 177  *                      on v2 address of SPMI_PIC_ACC_ENABLEn.
 178  * @irq_status:         on v1 address of PMIC_ARB_SPMI_PIC_IRQ_STATUSn
 179  *                      on v2 address of SPMI_PIC_IRQ_STATUSn.
 180  * @irq_clear:          on v1 address of PMIC_ARB_SPMI_PIC_IRQ_CLEARn
 181  *                      on v2 address of SPMI_PIC_IRQ_CLEARn.
 182  * @apid_map_offset:    offset of PMIC_ARB_REG_CHNLn
 183  */
 184 struct pmic_arb_ver_ops {
 185         const char *ver_str;
 186         int (*ppid_to_apid)(struct spmi_pmic_arb *pmic_arb, u16 ppid);
 187         /* spmi commands (read_cmd, write_cmd, cmd) functionality */
 188         int (*offset)(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
 189                         enum pmic_arb_channel ch_type);
 190         u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc);
 191         int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid);
 192         /* Interrupts controller functionality (offset of PIC registers) */
 193         void __iomem *(*owner_acc_status)(struct spmi_pmic_arb *pmic_arb, u8 m,
 194                                           u16 n);
 195         void __iomem *(*acc_enable)(struct spmi_pmic_arb *pmic_arb, u16 n);
 196         void __iomem *(*irq_status)(struct spmi_pmic_arb *pmic_arb, u16 n);
 197         void __iomem *(*irq_clear)(struct spmi_pmic_arb *pmic_arb, u16 n);
 198         u32 (*apid_map_offset)(u16 n);
 199 };
 200
 201 static inline void pmic_arb_base_write(struct spmi_pmic_arb *pmic_arb,
 202                                        u32 offset, u32 val)
 203 {
 204         writel_relaxed(val, pmic_arb->wr_base + offset);
 205 }
 206
 207 static inline void pmic_arb_set_rd_cmd(struct spmi_pmic_arb *pmic_arb,
 208                                        u32 offset, u32 val)
 209 {
 210         writel_relaxed(val, pmic_arb->rd_base + offset);
 211 }
 212
 213 /**
 214  * pmic_arb_read_data: reads pmic-arb's register and copy 1..4 bytes to buf
 215  * @bc:         byte count -1. range: 0..3
 216  * @reg:        register's address
 217  * @buf:        output parameter, length must be bc + 1
 218  */
 219 static void
 220 pmic_arb_read_data(struct spmi_pmic_arb *pmic_arb, u8 *buf, u32 reg, u8 bc)
 221 {
 222         u32 data = __raw_readl(pmic_arb->rd_base + reg);
 223
 224         memcpy(buf, &data, (bc & 3) + 1);
 225 }
 226
 227 /**
 228  * pmic_arb_write_data: write 1..4 bytes from buf to pmic-arb's register
 229  * @bc:         byte-count -1. range: 0..3.
 230  * @reg:        register's address.
 231  * @buf:        buffer to write. length must be bc + 1.
 232  */
 233 static void pmic_arb_write_data(struct spmi_pmic_arb *pmic_arb, const u8 *buf,
 234                                 u32 reg, u8 bc)
 235 {
 236         u32 data = 0;
 237
 238         memcpy(&data, buf, (bc & 3) + 1);
 239         __raw_writel(data, pmic_arb->wr_base + reg);
 240 }
 241
 242 static int pmic_arb_wait_for_done(struct spmi_controller *ctrl,
 243                                   void __iomem *base, u8 sid, u16 addr,
 244                                   enum pmic_arb_channel ch_type)
 245 {
 246         struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
 247         u32 status = 0;
 248         u32 timeout = PMIC_ARB_TIMEOUT_US;
 249         u32 offset;
 250         int rc;
 251
 252         rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr, ch_type);
 253         if (rc < 0)
 254                 return rc;
 255
 256         offset = rc;
 257         offset += PMIC_ARB_STATUS;
 258
 259         while (timeout--) {
 260                 status = readl_relaxed(base + offset);
 261
 262                 if (status & PMIC_ARB_STATUS_DONE) {
 263                         if (status & PMIC_ARB_STATUS_DENIED) {
 264                                 dev_err(&ctrl->dev, "%s: %#x %#x: transaction denied (%#x)\n",
 265                                         __func__, sid, addr, status);
 266                                 return -EPERM;
 267                         }
 268
 269                         if (status & PMIC_ARB_STATUS_FAILURE) {
 270                                 dev_err(&ctrl->dev, "%s: %#x %#x: transaction failed (%#x)\n",
 271                                         __func__, sid, addr, status);
 272                                 WARN_ON(1);
 273                                 return -EIO;
 274                         }
 275
 276                         if (status & PMIC_ARB_STATUS_DROPPED) {
 277                                 dev_err(&ctrl->dev, "%s: %#x %#x: transaction dropped (%#x)\n",
 278                                         __func__, sid, addr, status);
 279                                 return -EIO;
 280                         }
 281
 282                         return 0;
 283                 }
 284                 udelay(1);
 285         }
 286
 287         dev_err(&ctrl->dev, "%s: %#x %#x: timeout, status %#x\n",
 288                 __func__, sid, addr, status);
 289         return -ETIMEDOUT;
 290 }
 291
 292 static int
 293 pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid)
 294 {
 295         struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
 296         unsigned long flags;
 297         u32 cmd;
 298         int rc;
 299         u32 offset;
 300
 301         rc = pmic_arb->ver_ops->offset(pmic_arb, sid, 0, PMIC_ARB_CHANNEL_RW);
 302         if (rc < 0)
 303                 return rc;
 304
 305         offset = rc;
 306         cmd = ((opc | 0x40) << 27) | ((sid & 0xf) << 20);
 307
 308         raw_spin_lock_irqsave(&pmic_arb->lock, flags);
 309         pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
 310         rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, 0,
 311                                     PMIC_ARB_CHANNEL_RW);
 312         raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
 313
 314         return rc;
 315 }
 316
 317 static int
 318 pmic_arb_non_data_cmd_v2(struct spmi_controller *ctrl, u8 opc, u8 sid)
 319 {
 320         return -EOPNOTSUPP;
 321 }
 322
 323 /* Non-data command */
 324 static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
 325 {
 326         struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
 327
 328         dev_dbg(&ctrl->dev, "cmd op:0x%x sid:%d\n", opc, sid);
 329
 330         /* Check for valid non-data command */
 331         if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP)
 332                 return -EINVAL;
 333
 334         return pmic_arb->ver_ops->non_data_cmd(ctrl, opc, sid);
 335 }
 336
 337 static int pmic_arb_fmt_read_cmd(struct spmi_pmic_arb *pmic_arb, u8 opc, u8 sid,
 338                                  u16 addr, size_t len, u32 *cmd, u32 *offset)
 339 {
 340         u8 bc = len - 1;
 341         int rc;
 342
 343         rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr,
 344                                        PMIC_ARB_CHANNEL_OBS);
 345         if (rc < 0)
 346                 return rc;
 347
 348         *offset = rc;
 349         if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {
 350                 dev_err(&pmic_arb->spmic->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
 351                         PMIC_ARB_MAX_TRANS_BYTES, len);
 352                 return  -EINVAL;
 353         }
 354
 355         /* Check the opcode */
 356         if (opc >= 0x60 && opc <= 0x7F)
 357                 opc = PMIC_ARB_OP_READ;
 358         else if (opc >= 0x20 && opc <= 0x2F)
 359                 opc = PMIC_ARB_OP_EXT_READ;
 360         else if (opc >= 0x38 && opc <= 0x3F)
 361                 opc = PMIC_ARB_OP_EXT_READL;
 362         else
 363                 return -EINVAL;
 364
 365         *cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);
 366
 367         return 0;
 368 }
 369
 370 static int pmic_arb_read_cmd_unlocked(struct spmi_controller *ctrl, u32 cmd,
 371                                       u32 offset, u8 sid, u16 addr, u8 *buf,
 372                                       size_t len)
 373 {
 374         struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
 375         u8 bc = len - 1;
 376         int rc;
 377
 378         pmic_arb_set_rd_cmd(pmic_arb, offset + PMIC_ARB_CMD, cmd);
 379         rc = pmic_arb_wait_for_done(ctrl, pmic_arb->rd_base, sid, addr,
 380                                     PMIC_ARB_CHANNEL_OBS);
 381         if (rc)
 382                 return rc;
 383
 384         pmic_arb_read_data(pmic_arb, buf, offset + PMIC_ARB_RDATA0,
 385                      min_t(u8, bc, 3));
 386
 387         if (bc > 3)
 388                 pmic_arb_read_data(pmic_arb, buf + 4, offset + PMIC_ARB_RDATA1,
 389                                         bc - 4);
 390         return 0;
 391 }
 392
 393 static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
 394                              u16 addr, u8 *buf, size_t len)
 395 {
 396         struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
 397         unsigned long flags;
 398         u32 cmd, offset;
 399         int rc;
 400
 401         rc = pmic_arb_fmt_read_cmd(pmic_arb, opc, sid, addr, len, &cmd,
 402                                    &offset);
 403         if (rc)
 404                 return rc;
 405
 406         raw_spin_lock_irqsave(&pmic_arb->lock, flags);
 407         rc = pmic_arb_read_cmd_unlocked(ctrl, cmd, offset, sid, addr, buf, len);
 408         raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
 409
 410         return rc;
 411 }
 412
 413 static int pmic_arb_fmt_write_cmd(struct spmi_pmic_arb *pmic_arb, u8 opc,
 414                                   u8 sid, u16 addr, size_t len, u32 *cmd,
 415                                   u32 *offset)
 416 {
 417         u8 bc = len - 1;
 418         int rc;
 419
 420         rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr,
 421                                         PMIC_ARB_CHANNEL_RW);
 422         if (rc < 0)
 423                 return rc;
 424
 425         *offset = rc;
 426         if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {
 427                 dev_err(&pmic_arb->spmic->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
 428                         PMIC_ARB_MAX_TRANS_BYTES, len);
 429                 return  -EINVAL;
 430         }
 431
 432         /* Check the opcode */
 433         if (opc >= 0x40 && opc <= 0x5F)
 434                 opc = PMIC_ARB_OP_WRITE;
 435         else if (opc <= 0x0F)
 436                 opc = PMIC_ARB_OP_EXT_WRITE;
 437         else if (opc >= 0x30 && opc <= 0x37)
 438                 opc = PMIC_ARB_OP_EXT_WRITEL;
 439         else if (opc >= 0x80)
 440                 opc = PMIC_ARB_OP_ZERO_WRITE;
 441         else
 442                 return -EINVAL;
 443
 444         *cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);
 445
 446         return 0;
 447 }
 448
 449 static int pmic_arb_write_cmd_unlocked(struct spmi_controller *ctrl, u32 cmd,
 450                                       u32 offset, u8 sid, u16 addr,
 451                                       const u8 *buf, size_t len)
 452 {
 453         struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
 454         u8 bc = len - 1;
 455
 456         /* Write data to FIFOs */
 457         pmic_arb_write_data(pmic_arb, buf, offset + PMIC_ARB_WDATA0,
 458                                 min_t(u8, bc, 3));
 459         if (bc > 3)
 460                 pmic_arb_write_data(pmic_arb, buf + 4, offset + PMIC_ARB_WDATA1,
 461                                         bc - 4);
 462
 463         /* Start the transaction */
 464         pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
 465         return pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, addr,
 466                                       PMIC_ARB_CHANNEL_RW);
 467 }
 468
 469 static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
 470                               u16 addr, const u8 *buf, size_t len)
 471 {
 472         struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
 473         unsigned long flags;
 474         u32 cmd, offset;
 475         int rc;
 476
 477         rc = pmic_arb_fmt_write_cmd(pmic_arb, opc, sid, addr, len, &cmd,
 478                                     &offset);
 479         if (rc)
 480                 return rc;
 481
 482         raw_spin_lock_irqsave(&pmic_arb->lock, flags);
 483         rc = pmic_arb_write_cmd_unlocked(ctrl, cmd, offset, sid, addr, buf,
 484                                          len);
 485         raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
 486
 487         return rc;
 488 }
 489
 490 static int pmic_arb_masked_write(struct spmi_controller *ctrl, u8 sid, u16 addr,
 491                                  const u8 *buf, const u8 *mask, size_t len)
 492 {
 493         struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
 494         u32 read_cmd, read_offset, write_cmd, write_offset;
 495         u8 temp[PMIC_ARB_MAX_TRANS_BYTES];
 496         unsigned long flags;
 497         int rc, i;
 498
 499         rc = pmic_arb_fmt_read_cmd(pmic_arb, SPMI_CMD_EXT_READL, sid, addr, len,
 500                                    &read_cmd, &read_offset);
 501         if (rc)
 502                 return rc;
 503
 504         rc = pmic_arb_fmt_write_cmd(pmic_arb, SPMI_CMD_EXT_WRITEL, sid, addr,
 505                                     len, &write_cmd, &write_offset);
 506         if (rc)
 507                 return rc;
 508
 509         raw_spin_lock_irqsave(&pmic_arb->lock, flags);
 510         rc = pmic_arb_read_cmd_unlocked(ctrl, read_cmd, read_offset, sid, addr,
 511                                         temp, len);
 512         if (rc)
 513                 goto done;
 514
 515         for (i = 0; i < len; i++)
 516                 temp[i] = (temp[i] & ~mask[i]) | (buf[i] & mask[i]);
 517
 518         rc = pmic_arb_write_cmd_unlocked(ctrl, write_cmd, write_offset, sid,
 519                                          addr, temp, len);
 520 done:
 521         raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
 522
 523         return rc;
 524 }
 525
 526 enum qpnpint_regs {
 527         QPNPINT_REG_RT_STS              = 0x10,
 528         QPNPINT_REG_SET_TYPE            = 0x11,
 529         QPNPINT_REG_POLARITY_HIGH       = 0x12,
 530         QPNPINT_REG_POLARITY_LOW        = 0x13,
 531         QPNPINT_REG_LATCHED_CLR         = 0x14,
 532         QPNPINT_REG_EN_SET              = 0x15,
 533         QPNPINT_REG_EN_CLR              = 0x16,
 534         QPNPINT_REG_LATCHED_STS         = 0x18,
 535 };
 536
 537 struct spmi_pmic_arb_qpnpint_type {
 538         u8 type; /* 1 -> edge */
 539         u8 polarity_high;
 540         u8 polarity_low;
 541 } __packed;
 542
 543 /* Simplified accessor functions for irqchip callbacks */
 544 static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf,
 545                                size_t len)
 546 {
 547         struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
 548         u8 sid = hwirq_to_sid(d->hwirq);
 549         u8 per = hwirq_to_per(d->hwirq);
 550
 551         if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
 552                                (per << 8) + reg, buf, len))
 553                 dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x\n",
 554                                     d->irq);
 555 }
 556
 557 static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len)
 558 {
 559         struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
 560         u8 sid = hwirq_to_sid(d->hwirq);
 561         u8 per = hwirq_to_per(d->hwirq);
 562
 563         if (pmic_arb_read_cmd(pmic_arb->spmic, SPMI_CMD_EXT_READL, sid,
 564                               (per << 8) + reg, buf, len))
 565                 dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x\n",
 566                                     d->irq);
 567 }
 568
 569 static int qpnpint_spmi_masked_write(struct irq_data *d, u8 reg,
 570                                      const void *buf, const void *mask,
 571                                      size_t len)
 572 {
 573         struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
 574         u8 sid = hwirq_to_sid(d->hwirq);
 575         u8 per = hwirq_to_per(d->hwirq);
 576         int rc;
 577
 578         rc = pmic_arb_masked_write(pmic_arb->spmic, sid, (per << 8) + reg, buf,
 579                                    mask, len);
 580         if (rc)
 581                 dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x rc=%d\n",
 582                                     d->irq, rc);
 583         return rc;
 584 }
 585
 586 static void cleanup_irq(struct spmi_pmic_arb *pmic_arb, u16 apid, int id)
 587 {
 588         u16 ppid = pmic_arb->apid_data[apid].ppid;
 589         u8 sid = ppid >> 8;
 590         u8 per = ppid & 0xFF;
 591         u8 irq_mask = BIT(id);
 592
 593         dev_err_ratelimited(&pmic_arb->spmic->dev, "%s apid=%d sid=0x%x per=0x%x irq=%d\n",
 594                         __func__, apid, sid, per, id);
 595         writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(pmic_arb, apid));
 596 }
 597
 598 static int periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid)
 599 {
 600         unsigned int irq;
 601         u32 status, id;
 602         int handled = 0;
 603         u8 sid = (pmic_arb->apid_data[apid].ppid >> 8) & 0xF;
 604         u8 per = pmic_arb->apid_data[apid].ppid & 0xFF;
 605
 606         status = readl_relaxed(pmic_arb->ver_ops->irq_status(pmic_arb, apid));
 607         while (status) {
 608                 id = ffs(status) - 1;
 609                 status &= ~BIT(id);
 610                 irq = irq_find_mapping(pmic_arb->domain,
 611                                         spec_to_hwirq(sid, per, id, apid));
 612                 if (irq == 0) {
 613                         cleanup_irq(pmic_arb, apid, id);
 614                         continue;
 615                 }
 616                 generic_handle_irq(irq);
 617                 handled++;
 618         }
 619
 620         return handled;
 621 }
 622
 623 static void pmic_arb_chained_irq(struct irq_desc *desc)
 624 {
 625         struct spmi_pmic_arb *pmic_arb = irq_desc_get_handler_data(desc);
 626         const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops;
 627         struct irq_chip *chip = irq_desc_get_chip(desc);
 628         int first = pmic_arb->min_apid;
 629         int last = pmic_arb->max_apid;
 630         u8 ee = pmic_arb->ee;
 631         u32 status, enable, handled = 0;
 632         int i, id, apid;
 633         /* status based dispatch */
 634         bool acc_valid = false;
 635         u32 irq_status = 0;
 636
 637         chained_irq_enter(chip, desc);
 638
 639         for (i = first >> 5; i <= last >> 5; ++i) {
 640                 status = readl_relaxed(
 641                                 ver_ops->owner_acc_status(pmic_arb, ee, i));
 642                 if (status)
 643                         acc_valid = true;
 644
 645                 while (status) {
 646                         id = ffs(status) - 1;
 647                         status &= ~BIT(id);
 648                         apid = id + i * 32;
 649                         if (apid < first || apid > last) {
 650                                 WARN_ONCE(true, "spurious spmi irq received for apid=%d\n",
 651                                         apid);
 652                                 continue;
 653                         }
 654                         enable = readl_relaxed(
 655                                         ver_ops->acc_enable(pmic_arb, apid));
 656                         if (enable & SPMI_PIC_ACC_ENABLE_BIT)
 657                                 if (periph_interrupt(pmic_arb, apid) != 0)
 658                                         handled++;
 659                 }
 660         }
 661
 662         /* ACC_STATUS is empty but IRQ fired check IRQ_STATUS */
 663         if (!acc_valid) {
 664                 for (i = first; i <= last; i++) {
 665                         /* skip if APPS is not irq owner */
 666                         if (pmic_arb->apid_data[i].irq_ee != pmic_arb->ee)
 667                                 continue;
 668
 669                         irq_status = readl_relaxed(
 670                                              ver_ops->irq_status(pmic_arb, i));
 671                         if (irq_status) {
 672                                 enable = readl_relaxed(
 673                                              ver_ops->acc_enable(pmic_arb, i));
 674                                 if (enable & SPMI_PIC_ACC_ENABLE_BIT) {
 675                                         dev_dbg(&pmic_arb->spmic->dev,
 676                                                 "Dispatching IRQ for apid=%d status=%x\n",
 677                                                 i, irq_status);
 678                                         if (periph_interrupt(pmic_arb, i) != 0)
 679                                                 handled++;
 680                                 }
 681                         }
 682                 }
 683         }
 684
 685         if (handled == 0)
 686                 handle_bad_irq(desc);
 687
 688         chained_irq_exit(chip, desc);
 689 }
 690
 691 static void qpnpint_irq_ack(struct irq_data *d)
 692 {
 693         struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
 694         u8 irq = hwirq_to_irq(d->hwirq);
 695         u16 apid = hwirq_to_apid(d->hwirq);
 696         u8 data;
 697
 698         writel_relaxed(BIT(irq), pmic_arb->ver_ops->irq_clear(pmic_arb, apid));
 699
 700         data = BIT(irq);
 701         qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1);
 702 }
 703
 704 static void qpnpint_irq_mask(struct irq_data *d)
 705 {
 706         u8 irq = hwirq_to_irq(d->hwirq);
 707         u8 data = BIT(irq);
 708
 709         qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &data, 1);
 710 }
 711
 712 static void qpnpint_irq_unmask(struct irq_data *d)
 713 {
 714         struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
 715         const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops;
 716         u8 irq = hwirq_to_irq(d->hwirq);
 717         u16 apid = hwirq_to_apid(d->hwirq);
 718         u8 buf[2];
 719
 720         writel_relaxed(SPMI_PIC_ACC_ENABLE_BIT,
 721                         ver_ops->acc_enable(pmic_arb, apid));
 722
 723         qpnpint_spmi_read(d, QPNPINT_REG_EN_SET, &buf[0], 1);
 724         if (!(buf[0] & BIT(irq))) {
 725                 /*
 726                  * Since the interrupt is currently disabled, write to both the
 727                  * LATCHED_CLR and EN_SET registers so that a spurious interrupt
 728                  * cannot be triggered when the interrupt is enabled
 729                  */
 730                 buf[0] = BIT(irq);
 731                 buf[1] = BIT(irq);
 732                 qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 2);
 733         }
 734 }
 735
 736 static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type)
 737 {
 738         struct spmi_pmic_arb_qpnpint_type type = {0};
 739         struct spmi_pmic_arb_qpnpint_type mask;
 740         irq_flow_handler_t flow_handler;
 741         u8 irq_bit = BIT(hwirq_to_irq(d->hwirq));
 742         int rc;
 743
 744         if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
 745                 type.type = irq_bit;
 746                 if (flow_type & IRQF_TRIGGER_RISING)
 747                         type.polarity_high = irq_bit;
 748                 if (flow_type & IRQF_TRIGGER_FALLING)
 749                         type.polarity_low = irq_bit;
 750
 751                 flow_handler = handle_edge_irq;
 752         } else {
 753                 if ((flow_type & (IRQF_TRIGGER_HIGH)) &&
 754                     (flow_type & (IRQF_TRIGGER_LOW)))
 755                         return -EINVAL;
 756
 757                 if (flow_type & IRQF_TRIGGER_HIGH)
 758                         type.polarity_high = irq_bit;
 759                 else
 760                         type.polarity_low = irq_bit;
 761
 762                 flow_handler = handle_level_irq;
 763         }
 764
 765         mask.type = irq_bit;
 766         mask.polarity_high = irq_bit;
 767         mask.polarity_low = irq_bit;
 768
 769         rc = qpnpint_spmi_masked_write(d, QPNPINT_REG_SET_TYPE, &type, &mask,
 770                                        sizeof(type));
 771         irq_set_handler_locked(d, flow_handler);
 772
 773         return rc;
 774 }
 775
 776 static int qpnpint_irq_set_wake(struct irq_data *d, unsigned int on)
 777 {
 778         struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
 779
 780         return irq_set_irq_wake(pmic_arb->irq, on);
 781 }
 782
 783 static int qpnpint_get_irqchip_state(struct irq_data *d,
 784                                      enum irqchip_irq_state which,
 785                                      bool *state)
 786 {
 787         u8 irq = hwirq_to_irq(d->hwirq);
 788         u8 status = 0;
 789
 790         if (which != IRQCHIP_STATE_LINE_LEVEL)
 791                 return -EINVAL;
 792
 793         qpnpint_spmi_read(d, QPNPINT_REG_RT_STS, &status, 1);
 794         *state = !!(status & BIT(irq));
 795
 796         return 0;
 797 }
 798
 799 static int qpnpint_irq_domain_activate(struct irq_domain *domain,
 800                                        struct irq_data *d, bool reserve)
 801 {
 802         struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
 803         u16 periph = hwirq_to_per(d->hwirq);
 804         u16 apid = hwirq_to_apid(d->hwirq);
 805         u16 sid = hwirq_to_sid(d->hwirq);
 806         u16 irq = hwirq_to_irq(d->hwirq);
 807         u8 buf;
 808
 809         if (pmic_arb->apid_data[apid].irq_ee != pmic_arb->ee) {
 810                 dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u: ee=%u but owner=%u\n",
 811                         sid, periph, irq, pmic_arb->ee,
 812                         pmic_arb->apid_data[apid].irq_ee);
 813                 return -ENODEV;
 814         }
 815
 816         buf = BIT(irq);
 817         qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &buf, 1);
 818         qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 1);
 819
 820         return 0;
 821 }
 822
 823 static struct irq_chip pmic_arb_irqchip = {
 824         .name           = "pmic_arb",
 825         .irq_ack        = qpnpint_irq_ack,
 826         .irq_mask       = qpnpint_irq_mask,
 827         .irq_unmask     = qpnpint_irq_unmask,
 828         .irq_set_type   = qpnpint_irq_set_type,
 829         .irq_set_wake   = qpnpint_irq_set_wake,
 830         .irq_get_irqchip_state  = qpnpint_get_irqchip_state,
 831         .flags          = IRQCHIP_MASK_ON_SUSPEND,
 832 };
 833
 834 static int qpnpint_irq_domain_translate(struct irq_domain *d,
 835                                         struct irq_fwspec *fwspec,
 836                                         unsigned long *out_hwirq,
 837                                         unsigned int *out_type)
 838 {
 839         struct spmi_pmic_arb *pmic_arb = d->host_data;
 840         u32 *intspec = fwspec->param;
 841         u16 apid, ppid;
 842         int rc;
 843
 844         dev_dbg(&pmic_arb->spmic->dev, "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n",
 845                 intspec[0], intspec[1], intspec[2]);
 846
 847         if (irq_domain_get_of_node(d) != pmic_arb->spmic->dev.of_node)
 848                 return -EINVAL;
 849         if (fwspec->param_count != 4)
 850                 return -EINVAL;
 851         if (intspec[0] > 0xF || intspec[1] > 0xFF || intspec[2] > 0x7)
 852                 return -EINVAL;
 853
 854         ppid = intspec[0] << 8 | intspec[1];
 855         rc = pmic_arb->ver_ops->ppid_to_apid(pmic_arb, ppid);
 856         if (rc < 0) {
 857                 dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u rc = %d\n",
 858                 intspec[0], intspec[1], intspec[2], rc);
 859                 return rc;
 860         }
 861
 862         apid = rc;
 863         /* Keep track of {max,min}_apid for bounding search during interrupt */
 864         if (apid > pmic_arb->max_apid)
 865                 pmic_arb->max_apid = apid;
 866         if (apid < pmic_arb->min_apid)
 867                 pmic_arb->min_apid = apid;
 868
 869         *out_hwirq = spec_to_hwirq(intspec[0], intspec[1], intspec[2], apid);
 870         *out_type  = intspec[3] & IRQ_TYPE_SENSE_MASK;
 871
 872         dev_dbg(&pmic_arb->spmic->dev, "out_hwirq = %lu\n", *out_hwirq);
 873
 874         return 0;
 875 }
 876
 877 static struct lock_class_key qpnpint_irq_lock_class, qpnpint_irq_request_class;
 878
 879 static void qpnpint_irq_domain_map(struct spmi_pmic_arb *pmic_arb,
 880                                    struct irq_domain *domain, unsigned int virq,
 881                                    irq_hw_number_t hwirq, unsigned int type)
 882 {
 883         irq_flow_handler_t handler;
 884
 885         dev_dbg(&pmic_arb->spmic->dev, "virq = %u, hwirq = %lu, type = %u\n",
 886                 virq, hwirq, type);
 887
 888         if (type & IRQ_TYPE_EDGE_BOTH)
 889                 handler = handle_edge_irq;
 890         else
 891                 handler = handle_level_irq;
 892
 893
 894         irq_set_lockdep_class(virq, &qpnpint_irq_lock_class,
 895                               &qpnpint_irq_request_class);
 896         irq_domain_set_info(domain, virq, hwirq, &pmic_arb_irqchip, pmic_arb,
 897                             handler, NULL, NULL);
 898 }
 899
 900 static int qpnpint_irq_domain_alloc(struct irq_domain *domain,
 901                                     unsigned int virq, unsigned int nr_irqs,
 902                                     void *data)
 903 {
 904         struct spmi_pmic_arb *pmic_arb = domain->host_data;
 905         struct irq_fwspec *fwspec = data;
 906         irq_hw_number_t hwirq;
 907         unsigned int type;
 908         int ret, i;
 909
 910         ret = qpnpint_irq_domain_translate(domain, fwspec, &hwirq, &type);
 911         if (ret)
 912                 return ret;
 913
 914         for (i = 0; i < nr_irqs; i++)
 915                 qpnpint_irq_domain_map(pmic_arb, domain, virq + i, hwirq + i,
 916                                        type);
 917
 918         return 0;
 919 }
 920
 921 static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pmic_arb, u16 ppid)
 922 {
 923         u32 *mapping_table = pmic_arb->mapping_table;
 924         int index = 0, i;
 925         u16 apid_valid;
 926         u16 apid;
 927         u32 data;
 928
 929         apid_valid = pmic_arb->ppid_to_apid[ppid];
 930         if (apid_valid & PMIC_ARB_APID_VALID) {
 931                 apid = apid_valid & ~PMIC_ARB_APID_VALID;
 932                 return apid;
 933         }
 934
 935         for (i = 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) {
 936                 if (!test_and_set_bit(index, pmic_arb->mapping_table_valid))
 937                         mapping_table[index] = readl_relaxed(pmic_arb->cnfg +
 938                                                 SPMI_MAPPING_TABLE_REG(index));
 939
 940                 data = mapping_table[index];
 941
 942                 if (ppid & BIT(SPMI_MAPPING_BIT_INDEX(data))) {
 943                         if (SPMI_MAPPING_BIT_IS_1_FLAG(data)) {
 944                                 index = SPMI_MAPPING_BIT_IS_1_RESULT(data);
 945                         } else {
 946                                 apid = SPMI_MAPPING_BIT_IS_1_RESULT(data);
 947                                 pmic_arb->ppid_to_apid[ppid]
 948                                         = apid | PMIC_ARB_APID_VALID;
 949                                 pmic_arb->apid_data[apid].ppid = ppid;
 950                                 return apid;
 951                         }
 952                 } else {
 953                         if (SPMI_MAPPING_BIT_IS_0_FLAG(data)) {
 954                                 index = SPMI_MAPPING_BIT_IS_0_RESULT(data);
 955                         } else {
 956                                 apid = SPMI_MAPPING_BIT_IS_0_RESULT(data);
 957                                 pmic_arb->ppid_to_apid[ppid]
 958                                         = apid | PMIC_ARB_APID_VALID;
 959                                 pmic_arb->apid_data[apid].ppid = ppid;
 960                                 return apid;
 961                         }
 962                 }
 963         }
 964
 965         return -ENODEV;
 966 }
 967
 968 /* v1 offset per ee */
 969 static int pmic_arb_offset_v1(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
 970                         enum pmic_arb_channel ch_type)
 971 {
 972         return 0x800 + 0x80 * pmic_arb->channel;
 973 }
 974
 975 static u16 pmic_arb_find_apid(struct spmi_pmic_arb *pmic_arb, u16 ppid)
 976 {
 977         struct apid_data *apidd = &pmic_arb->apid_data[pmic_arb->last_apid];
 978         u32 regval, offset;
 979         u16 id, apid;
 980
 981         for (apid = pmic_arb->last_apid; ; apid++, apidd++) {
 982                 offset = pmic_arb->ver_ops->apid_map_offset(apid);
 983                 if (offset >= pmic_arb->core_size)
 984                         break;
 985
 986                 regval = readl_relaxed(pmic_arb->cnfg +
 987                                       SPMI_OWNERSHIP_TABLE_REG(apid));
 988                 apidd->irq_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
 989                 apidd->write_ee = apidd->irq_ee;
 990
 991                 regval = readl_relaxed(pmic_arb->core + offset);
 992                 if (!regval)
 993                         continue;
 994
 995                 id = (regval >> 8) & PMIC_ARB_PPID_MASK;
 996                 pmic_arb->ppid_to_apid[id] = apid | PMIC_ARB_APID_VALID;
 997                 apidd->ppid = id;
 998                 if (id == ppid) {
 999                         apid |= PMIC_ARB_APID_VALID;
1000                         break;
1001                 }
1002         }
1003         pmic_arb->last_apid = apid & ~PMIC_ARB_APID_VALID;
1004
1005         return apid;
1006 }
1007
1008 static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb *pmic_arb, u16 ppid)
1009 {
1010         u16 apid_valid;
1011
1012         apid_valid = pmic_arb->ppid_to_apid[ppid];
1013         if (!(apid_valid & PMIC_ARB_APID_VALID))
1014                 apid_valid = pmic_arb_find_apid(pmic_arb, ppid);
1015         if (!(apid_valid & PMIC_ARB_APID_VALID))
1016                 return -ENODEV;
1017
1018         return apid_valid & ~PMIC_ARB_APID_VALID;
1019 }
1020
1021 static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb)
1022 {
1023         struct apid_data *apidd = pmic_arb->apid_data;
1024         struct apid_data *prev_apidd;
1025         u16 i, apid, ppid;
1026         bool valid, is_irq_ee;
1027         u32 regval, offset;
1028
1029         /*
1030          * In order to allow multiple EEs to write to a single PPID in arbiter
1031          * version 5, there is more than one APID mapped to each PPID.
1032          * The owner field for each of these mappings specifies the EE which is
1033          * allowed to write to the APID.  The owner of the last (highest) APID
1034          * which has the IRQ owner bit set for a given PPID will receive
1035          * interrupts from the PPID.
1036          */
1037         for (i = 0; ; i++, apidd++) {
1038                 offset = pmic_arb->ver_ops->apid_map_offset(i);
1039                 if (offset >= pmic_arb->core_size)
1040                         break;
1041
1042                 regval = readl_relaxed(pmic_arb->core + offset);
1043                 if (!regval)
1044                         continue;
1045                 ppid = (regval >> 8) & PMIC_ARB_PPID_MASK;
1046                 is_irq_ee = PMIC_ARB_CHAN_IS_IRQ_OWNER(regval);
1047
1048                 regval = readl_relaxed(pmic_arb->cnfg +
1049                                       SPMI_OWNERSHIP_TABLE_REG(i));
1050                 apidd->write_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
1051
1052                 apidd->irq_ee = is_irq_ee ? apidd->write_ee : INVALID_EE;
1053
1054                 valid = pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID;
1055                 apid = pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
1056                 prev_apidd = &pmic_arb->apid_data[apid];
1057
1058                 if (!valid || apidd->write_ee == pmic_arb->ee) {
1059                         /* First PPID mapping or one for this EE */
1060                         pmic_arb->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID;
1061                 } else if (valid && is_irq_ee &&
1062                            prev_apidd->write_ee == pmic_arb->ee) {
1063                         /*
1064                          * Duplicate PPID mapping after the one for this EE;
1065                          * override the irq owner
1066                          */
1067                         prev_apidd->irq_ee = apidd->irq_ee;
1068                 }
1069
1070                 apidd->ppid = ppid;
1071                 pmic_arb->last_apid = i;
1072         }
1073
1074         /* Dump the mapping table for debug purposes. */
1075         dev_dbg(&pmic_arb->spmic->dev, "PPID APID Write-EE IRQ-EE\n");
1076         for (ppid = 0; ppid < PMIC_ARB_MAX_PPID; ppid++) {
1077                 apid = pmic_arb->ppid_to_apid[ppid];
1078                 if (apid & PMIC_ARB_APID_VALID) {
1079                         apid &= ~PMIC_ARB_APID_VALID;
1080                         apidd = &pmic_arb->apid_data[apid];
1081                         dev_dbg(&pmic_arb->spmic->dev, "%#03X %3u %2u %2u\n",
1082                               ppid, apid, apidd->write_ee, apidd->irq_ee);
1083                 }
1084         }
1085
1086         return 0;
1087 }
1088
1089 static int pmic_arb_ppid_to_apid_v5(struct spmi_pmic_arb *pmic_arb, u16 ppid)
1090 {
1091         if (!(pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID))
1092                 return -ENODEV;
1093
1094         return pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
1095 }
1096
1097 /* v2 offset per ppid and per ee */
1098 static int pmic_arb_offset_v2(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
1099                            enum pmic_arb_channel ch_type)
1100 {
1101         u16 apid;
1102         u16 ppid;
1103         int rc;
1104
1105         ppid = sid << 8 | ((addr >> 8) & 0xFF);
1106         rc = pmic_arb_ppid_to_apid_v2(pmic_arb, ppid);
1107         if (rc < 0)
1108                 return rc;
1109
1110         apid = rc;
1111         return 0x1000 * pmic_arb->ee + 0x8000 * apid;
1112 }
1113
1114 /*
1115  * v5 offset per ee and per apid for observer channels and per apid for
1116  * read/write channels.
1117  */
1118 static int pmic_arb_offset_v5(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
1119                            enum pmic_arb_channel ch_type)
1120 {
1121         u16 apid;
1122         int rc;
1123         u32 offset = 0;
1124         u16 ppid = (sid << 8) | (addr >> 8);
1125
1126         rc = pmic_arb_ppid_to_apid_v5(pmic_arb, ppid);
1127         if (rc < 0)
1128                 return rc;
1129
1130         apid = rc;
1131         switch (ch_type) {
1132         case PMIC_ARB_CHANNEL_OBS:
1133                 offset = 0x10000 * pmic_arb->ee + 0x80 * apid;
1134                 break;
1135         case PMIC_ARB_CHANNEL_RW:
1136                 if (pmic_arb->apid_data[apid].write_ee != pmic_arb->ee) {
1137                         dev_err(&pmic_arb->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n",
1138                                 sid, addr);
1139                         return -EPERM;
1140                 }
1141                 offset = 0x10000 * apid;
1142                 break;
1143         }
1144
1145         return offset;
1146 }
1147
1148 static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u16 addr, u8 bc)
1149 {
1150         return (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) | (bc & 0x7);
1151 }
1152
1153 static u32 pmic_arb_fmt_cmd_v2(u8 opc, u8 sid, u16 addr, u8 bc)
1154 {
1155         return (opc << 27) | ((addr & 0xff) << 4) | (bc & 0x7);
1156 }
1157
1158 static void __iomem *
1159 pmic_arb_owner_acc_status_v1(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
1160 {
1161         return pmic_arb->intr + 0x20 * m + 0x4 * n;
1162 }
1163
1164 static void __iomem *
1165 pmic_arb_owner_acc_status_v2(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
1166 {
1167         return pmic_arb->intr + 0x100000 + 0x1000 * m + 0x4 * n;
1168 }
1169
1170 static void __iomem *
1171 pmic_arb_owner_acc_status_v3(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
1172 {
1173         return pmic_arb->intr + 0x200000 + 0x1000 * m + 0x4 * n;
1174 }
1175
1176 static void __iomem *
1177 pmic_arb_owner_acc_status_v5(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
1178 {
1179         return pmic_arb->intr + 0x10000 * m + 0x4 * n;
1180 }
1181
1182 static void __iomem *
1183 pmic_arb_acc_enable_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
1184 {
1185         return pmic_arb->intr + 0x200 + 0x4 * n;
1186 }
1187
1188 static void __iomem *
1189 pmic_arb_acc_enable_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
1190 {
1191         return pmic_arb->intr + 0x1000 * n;
1192 }
1193
1194 static void __iomem *
1195 pmic_arb_acc_enable_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
1196 {
1197         return pmic_arb->wr_base + 0x100 + 0x10000 * n;
1198 }
1199
1200 static void __iomem *
1201 pmic_arb_irq_status_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
1202 {
1203         return pmic_arb->intr + 0x600 + 0x4 * n;
1204 }
1205
1206 static void __iomem *
1207 pmic_arb_irq_status_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
1208 {
1209         return pmic_arb->intr + 0x4 + 0x1000 * n;
1210 }
1211
1212 static void __iomem *
1213 pmic_arb_irq_status_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
1214 {
1215         return pmic_arb->wr_base + 0x104 + 0x10000 * n;
1216 }
1217
1218 static void __iomem *
1219 pmic_arb_irq_clear_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
1220 {
1221         return pmic_arb->intr + 0xA00 + 0x4 * n;
1222 }
1223
1224 static void __iomem *
1225 pmic_arb_irq_clear_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
1226 {
1227         return pmic_arb->intr + 0x8 + 0x1000 * n;
1228 }
1229
1230 static void __iomem *
1231 pmic_arb_irq_clear_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
1232 {
1233         return pmic_arb->wr_base + 0x108 + 0x10000 * n;
1234 }
1235
1236 static u32 pmic_arb_apid_map_offset_v2(u16 n)
1237 {
1238         return 0x800 + 0x4 * n;
1239 }
1240
1241 static u32 pmic_arb_apid_map_offset_v5(u16 n)
1242 {
1243         return 0x900 + 0x4 * n;
1244 }
1245
1246 static const struct pmic_arb_ver_ops pmic_arb_v1 = {
1247         .ver_str                = "v1",
1248         .ppid_to_apid           = pmic_arb_ppid_to_apid_v1,
1249         .non_data_cmd           = pmic_arb_non_data_cmd_v1,
1250         .offset                 = pmic_arb_offset_v1,
1251         .fmt_cmd                = pmic_arb_fmt_cmd_v1,
1252         .owner_acc_status       = pmic_arb_owner_acc_status_v1,
1253         .acc_enable             = pmic_arb_acc_enable_v1,
1254         .irq_status             = pmic_arb_irq_status_v1,
1255         .irq_clear              = pmic_arb_irq_clear_v1,
1256         .apid_map_offset        = pmic_arb_apid_map_offset_v2,
1257 };
1258
1259 static const struct pmic_arb_ver_ops pmic_arb_v2 = {
1260         .ver_str                = "v2",
1261         .ppid_to_apid           = pmic_arb_ppid_to_apid_v2,
1262         .non_data_cmd           = pmic_arb_non_data_cmd_v2,
1263         .offset                 = pmic_arb_offset_v2,
1264         .fmt_cmd                = pmic_arb_fmt_cmd_v2,
1265         .owner_acc_status       = pmic_arb_owner_acc_status_v2,
1266         .acc_enable             = pmic_arb_acc_enable_v2,
1267         .irq_status             = pmic_arb_irq_status_v2,
1268         .irq_clear              = pmic_arb_irq_clear_v2,
1269         .apid_map_offset        = pmic_arb_apid_map_offset_v2,
1270 };
1271
1272 static const struct pmic_arb_ver_ops pmic_arb_v3 = {
1273         .ver_str                = "v3",
1274         .ppid_to_apid           = pmic_arb_ppid_to_apid_v2,
1275         .non_data_cmd           = pmic_arb_non_data_cmd_v2,
1276         .offset                 = pmic_arb_offset_v2,
1277         .fmt_cmd                = pmic_arb_fmt_cmd_v2,
1278         .owner_acc_status       = pmic_arb_owner_acc_status_v3,
1279         .acc_enable             = pmic_arb_acc_enable_v2,
1280         .irq_status             = pmic_arb_irq_status_v2,
1281         .irq_clear              = pmic_arb_irq_clear_v2,
1282         .apid_map_offset        = pmic_arb_apid_map_offset_v2,
1283 };
1284
1285 static const struct pmic_arb_ver_ops pmic_arb_v5 = {
1286         .ver_str                = "v5",
1287         .ppid_to_apid           = pmic_arb_ppid_to_apid_v5,
1288         .non_data_cmd           = pmic_arb_non_data_cmd_v2,
1289         .offset                 = pmic_arb_offset_v5,
1290         .fmt_cmd                = pmic_arb_fmt_cmd_v2,
1291         .owner_acc_status       = pmic_arb_owner_acc_status_v5,
1292         .acc_enable             = pmic_arb_acc_enable_v5,
1293         .irq_status             = pmic_arb_irq_status_v5,
1294         .irq_clear              = pmic_arb_irq_clear_v5,
1295         .apid_map_offset        = pmic_arb_apid_map_offset_v5,
1296 };
1297
1298 static const struct irq_domain_ops pmic_arb_irq_domain_ops = {
1299         .activate = qpnpint_irq_domain_activate,
1300         .alloc = qpnpint_irq_domain_alloc,
1301         .free = irq_domain_free_irqs_common,
1302         .translate = qpnpint_irq_domain_translate,
1303 };
1304
1305 static int spmi_pmic_arb_probe(struct platform_device *pdev)
1306 {
1307         struct spmi_pmic_arb *pmic_arb;
1308         struct spmi_controller *ctrl;
1309         struct resource *res;
1310         void __iomem *core;
1311         u32 *mapping_table;
1312         u32 channel, ee, hw_ver;
1313         int err;
1314
1315         ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pmic_arb));
1316         if (!ctrl)
1317                 return -ENOMEM;
1318
1319         pmic_arb = spmi_controller_get_drvdata(ctrl);
1320         pmic_arb->spmic = ctrl;
1321
1322         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
1323         core = devm_ioremap_resource(&ctrl->dev, res);
1324         if (IS_ERR(core)) {
1325                 err = PTR_ERR(core);
1326                 goto err_put_ctrl;
1327         }
1328
1329         pmic_arb->core_size = resource_size(res);
1330
1331         pmic_arb->ppid_to_apid = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PPID,
1332                                               sizeof(*pmic_arb->ppid_to_apid),
1333                                               GFP_KERNEL);
1334         if (!pmic_arb->ppid_to_apid) {
1335                 err = -ENOMEM;
1336                 goto err_put_ctrl;
1337         }
1338
1339         hw_ver = readl_relaxed(core + PMIC_ARB_VERSION);
1340
1341         if (hw_ver < PMIC_ARB_VERSION_V2_MIN) {
1342                 pmic_arb->ver_ops = &pmic_arb_v1;
1343                 pmic_arb->wr_base = core;
1344                 pmic_arb->rd_base = core;
1345         } else {
1346                 pmic_arb->core = core;
1347
1348                 if (hw_ver < PMIC_ARB_VERSION_V3_MIN)
1349                         pmic_arb->ver_ops = &pmic_arb_v2;
1350                 else if (hw_ver < PMIC_ARB_VERSION_V5_MIN)
1351                         pmic_arb->ver_ops = &pmic_arb_v3;
1352                 else
1353                         pmic_arb->ver_ops = &pmic_arb_v5;
1354
1355                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1356                                                    "obsrvr");
1357                 pmic_arb->rd_base = devm_ioremap_resource(&ctrl->dev, res);
1358                 if (IS_ERR(pmic_arb->rd_base)) {
1359                         err = PTR_ERR(pmic_arb->rd_base);
1360                         goto err_put_ctrl;
1361                 }
1362
1363                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1364                                                    "chnls");
1365                 pmic_arb->wr_base = devm_ioremap_resource(&ctrl->dev, res);
1366                 if (IS_ERR(pmic_arb->wr_base)) {
1367                         err = PTR_ERR(pmic_arb->wr_base);
1368                         goto err_put_ctrl;
1369                 }
1370         }
1371
1372         dev_info(&ctrl->dev, "PMIC arbiter version %s (0x%x)\n",
1373                  pmic_arb->ver_ops->ver_str, hw_ver);
1374
1375         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr");
1376         pmic_arb->intr = devm_ioremap_resource(&ctrl->dev, res);
1377         if (IS_ERR(pmic_arb->intr)) {
1378                 err = PTR_ERR(pmic_arb->intr);
1379                 goto err_put_ctrl;
1380         }
1381
1382         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cnfg");
1383         pmic_arb->cnfg = devm_ioremap_resource(&ctrl->dev, res);
1384         if (IS_ERR(pmic_arb->cnfg)) {
1385                 err = PTR_ERR(pmic_arb->cnfg);
1386                 goto err_put_ctrl;
1387         }
1388
1389         pmic_arb->irq = platform_get_irq_byname(pdev, "periph_irq");
1390         if (pmic_arb->irq < 0) {
1391                 err = pmic_arb->irq;
1392                 goto err_put_ctrl;
1393         }
1394
1395         err = of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel);
1396         if (err) {
1397                 dev_err(&pdev->dev, "channel unspecified.\n");
1398                 goto err_put_ctrl;
1399         }
1400
1401         if (channel > 5) {
1402                 dev_err(&pdev->dev, "invalid channel (%u) specified.\n",
1403                         channel);
1404                 err = -EINVAL;
1405                 goto err_put_ctrl;
1406         }
1407
1408         pmic_arb->channel = channel;
1409
1410         err = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &ee);
1411         if (err) {
1412                 dev_err(&pdev->dev, "EE unspecified.\n");
1413                 goto err_put_ctrl;
1414         }
1415
1416         if (ee > 5) {
1417                 dev_err(&pdev->dev, "invalid EE (%u) specified\n", ee);
1418                 err = -EINVAL;
1419                 goto err_put_ctrl;
1420         }
1421
1422         pmic_arb->ee = ee;
1423         mapping_table = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PERIPHS,
1424                                         sizeof(*mapping_table), GFP_KERNEL);
1425         if (!mapping_table) {
1426                 err = -ENOMEM;
1427                 goto err_put_ctrl;
1428         }
1429
1430         pmic_arb->mapping_table = mapping_table;
1431         /* Initialize max_apid/min_apid to the opposite bounds, during
1432          * the irq domain translation, we are sure to update these */
1433         pmic_arb->max_apid = 0;
1434         pmic_arb->min_apid = PMIC_ARB_MAX_PERIPHS - 1;
1435
1436         platform_set_drvdata(pdev, ctrl);
1437         raw_spin_lock_init(&pmic_arb->lock);
1438
1439         ctrl->cmd = pmic_arb_cmd;
1440         ctrl->read_cmd = pmic_arb_read_cmd;
1441         ctrl->write_cmd = pmic_arb_write_cmd;
1442
1443         if (hw_ver >= PMIC_ARB_VERSION_V5_MIN) {
1444                 err = pmic_arb_read_apid_map_v5(pmic_arb);
1445                 if (err) {
1446                         dev_err(&pdev->dev, "could not read APID->PPID mapping table, rc= %d\n",
1447                                 err);
1448                         goto err_put_ctrl;
1449                 }
1450         }
1451
1452         dev_dbg(&pdev->dev, "adding irq domain\n");
1453         pmic_arb->domain = irq_domain_add_tree(pdev->dev.of_node,
1454                                          &pmic_arb_irq_domain_ops, pmic_arb);
1455         if (!pmic_arb->domain) {
1456                 dev_err(&pdev->dev, "unable to create irq_domain\n");
1457                 err = -ENOMEM;
1458                 goto err_put_ctrl;
1459         }
1460
1461         irq_set_chained_handler_and_data(pmic_arb->irq, pmic_arb_chained_irq,
1462                                         pmic_arb);
1463         err = spmi_controller_add(ctrl);
1464         if (err)
1465                 goto err_domain_remove;
1466
1467         return 0;
1468
1469 err_domain_remove:
1470         irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL);
1471         irq_domain_remove(pmic_arb->domain);
1472 err_put_ctrl:
1473         spmi_controller_put(ctrl);
1474         return err;
1475 }
1476
1477 static int spmi_pmic_arb_remove(struct platform_device *pdev)
1478 {
1479         struct spmi_controller *ctrl = platform_get_drvdata(pdev);
1480         struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
1481         spmi_controller_remove(ctrl);
1482         irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL);
1483         irq_domain_remove(pmic_arb->domain);
1484         spmi_controller_put(ctrl);
1485         return 0;
1486 }
1487
1488 static const struct of_device_id spmi_pmic_arb_match_table[] = {
1489         { .compatible = "qcom,spmi-pmic-arb", },
1490         {},
1491 };
1492 MODULE_DEVICE_TABLE(of, spmi_pmic_arb_match_table);
1493
1494 static struct platform_driver spmi_pmic_arb_driver = {
1495         .probe          = spmi_pmic_arb_probe,
1496         .remove         = spmi_pmic_arb_remove,
1497         .driver         = {
1498                 .name   = "spmi_pmic_arb",
1499                 .of_match_table = spmi_pmic_arb_match_table,
1500         },
1501 };
1502 module_platform_driver(spmi_pmic_arb_driver);
1503
1504 MODULE_LICENSE("GPL v2");
1505 MODULE_ALIAS("platform:spmi_pmic_arb");