2 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
5 * Copyright (C) 2009 - 2015 Xilinx, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/dmaengine.h>
17 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_address.h>
22 #include <linux/platform_device.h>
23 #include <linux/spi/spi.h>
24 #include <linux/spinlock.h>
25 #include <linux/workqueue.h>
27 /* Generic QSPI register offsets */
28 #define GQSPI_CONFIG_OFST 0x00000100
29 #define GQSPI_ISR_OFST 0x00000104
30 #define GQSPI_IDR_OFST 0x0000010C
31 #define GQSPI_IER_OFST 0x00000108
32 #define GQSPI_IMASK_OFST 0x00000110
33 #define GQSPI_EN_OFST 0x00000114
34 #define GQSPI_TXD_OFST 0x0000011C
35 #define GQSPI_RXD_OFST 0x00000120
36 #define GQSPI_TX_THRESHOLD_OFST 0x00000128
37 #define GQSPI_RX_THRESHOLD_OFST 0x0000012C
38 #define GQSPI_LPBK_DLY_ADJ_OFST 0x00000138
39 #define GQSPI_GEN_FIFO_OFST 0x00000140
40 #define GQSPI_SEL_OFST 0x00000144
41 #define GQSPI_GF_THRESHOLD_OFST 0x00000150
42 #define GQSPI_FIFO_CTRL_OFST 0x0000014C
43 #define GQSPI_QSPIDMA_DST_CTRL_OFST 0x0000080C
44 #define GQSPI_QSPIDMA_DST_SIZE_OFST 0x00000804
45 #define GQSPI_QSPIDMA_DST_STS_OFST 0x00000808
46 #define GQSPI_QSPIDMA_DST_I_STS_OFST 0x00000814
47 #define GQSPI_QSPIDMA_DST_I_EN_OFST 0x00000818
48 #define GQSPI_QSPIDMA_DST_I_DIS_OFST 0x0000081C
49 #define GQSPI_QSPIDMA_DST_I_MASK_OFST 0x00000820
50 #define GQSPI_QSPIDMA_DST_ADDR_OFST 0x00000800
51 #define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x00000828
53 /* GQSPI register bit masks */
54 #define GQSPI_SEL_MASK 0x00000001
55 #define GQSPI_EN_MASK 0x00000001
56 #define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020
57 #define GQSPI_ISR_WR_TO_CLR_MASK 0x00000002
58 #define GQSPI_IDR_ALL_MASK 0x00000FBE
59 #define GQSPI_CFG_MODE_EN_MASK 0xC0000000
60 #define GQSPI_CFG_GEN_FIFO_START_MODE_MASK 0x20000000
61 #define GQSPI_CFG_ENDIAN_MASK 0x04000000
62 #define GQSPI_CFG_EN_POLL_TO_MASK 0x00100000
63 #define GQSPI_CFG_WP_HOLD_MASK 0x00080000
64 #define GQSPI_CFG_BAUD_RATE_DIV_MASK 0x00000038
65 #define GQSPI_CFG_CLK_PHA_MASK 0x00000004
66 #define GQSPI_CFG_CLK_POL_MASK 0x00000002
67 #define GQSPI_CFG_START_GEN_FIFO_MASK 0x10000000
68 #define GQSPI_GENFIFO_IMM_DATA_MASK 0x000000FF
69 #define GQSPI_GENFIFO_DATA_XFER 0x00000100
70 #define GQSPI_GENFIFO_EXP 0x00000200
71 #define GQSPI_GENFIFO_MODE_SPI 0x00000400
72 #define GQSPI_GENFIFO_MODE_DUALSPI 0x00000800
73 #define GQSPI_GENFIFO_MODE_QUADSPI 0x00000C00
74 #define GQSPI_GENFIFO_MODE_MASK 0x00000C00
75 #define GQSPI_GENFIFO_CS_LOWER 0x00001000
76 #define GQSPI_GENFIFO_CS_UPPER 0x00002000
77 #define GQSPI_GENFIFO_BUS_LOWER 0x00004000
78 #define GQSPI_GENFIFO_BUS_UPPER 0x00008000
79 #define GQSPI_GENFIFO_BUS_BOTH 0x0000C000
80 #define GQSPI_GENFIFO_BUS_MASK 0x0000C000
81 #define GQSPI_GENFIFO_TX 0x00010000
82 #define GQSPI_GENFIFO_RX 0x00020000
83 #define GQSPI_GENFIFO_STRIPE 0x00040000
84 #define GQSPI_GENFIFO_POLL 0x00080000
85 #define GQSPI_GENFIFO_EXP_START 0x00000100
86 #define GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK 0x00000004
87 #define GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK 0x00000002
88 #define GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK 0x00000001
89 #define GQSPI_ISR_RXEMPTY_MASK 0x00000800
90 #define GQSPI_ISR_GENFIFOFULL_MASK 0x00000400
91 #define GQSPI_ISR_GENFIFONOT_FULL_MASK 0x00000200
92 #define GQSPI_ISR_TXEMPTY_MASK 0x00000100
93 #define GQSPI_ISR_GENFIFOEMPTY_MASK 0x00000080
94 #define GQSPI_ISR_RXFULL_MASK 0x00000020
95 #define GQSPI_ISR_RXNEMPTY_MASK 0x00000010
96 #define GQSPI_ISR_TXFULL_MASK 0x00000008
97 #define GQSPI_ISR_TXNOT_FULL_MASK 0x00000004
98 #define GQSPI_ISR_POLL_TIME_EXPIRE_MASK 0x00000002
99 #define GQSPI_IER_TXNOT_FULL_MASK 0x00000004
100 #define GQSPI_IER_RXEMPTY_MASK 0x00000800
101 #define GQSPI_IER_POLL_TIME_EXPIRE_MASK 0x00000002
102 #define GQSPI_IER_RXNEMPTY_MASK 0x00000010
103 #define GQSPI_IER_GENFIFOEMPTY_MASK 0x00000080
104 #define GQSPI_IER_TXEMPTY_MASK 0x00000100
105 #define GQSPI_QSPIDMA_DST_INTR_ALL_MASK 0x000000FE
106 #define GQSPI_QSPIDMA_DST_STS_WTC 0x0000E000
107 #define GQSPI_CFG_MODE_EN_DMA_MASK 0x80000000
108 #define GQSPI_ISR_IDR_MASK 0x00000994
109 #define GQSPI_QSPIDMA_DST_I_EN_DONE_MASK 0x00000002
110 #define GQSPI_QSPIDMA_DST_I_STS_DONE_MASK 0x00000002
111 #define GQSPI_IRQ_MASK 0x00000980
113 #define GQSPI_CFG_BAUD_RATE_DIV_SHIFT 3
114 #define GQSPI_GENFIFO_CS_SETUP 0x4
115 #define GQSPI_GENFIFO_CS_HOLD 0x3
116 #define GQSPI_TXD_DEPTH 64
117 #define GQSPI_RX_FIFO_THRESHOLD 32
118 #define GQSPI_RX_FIFO_FILL (GQSPI_RX_FIFO_THRESHOLD * 4)
119 #define GQSPI_TX_FIFO_THRESHOLD_RESET_VAL 32
120 #define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
121 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL)
122 #define GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL 0X10
123 #define GQSPI_QSPIDMA_DST_CTRL_RESET_VAL 0x803FFA00
124 #define GQSPI_SELECT_FLASH_CS_LOWER 0x1
125 #define GQSPI_SELECT_FLASH_CS_UPPER 0x2
126 #define GQSPI_SELECT_FLASH_CS_BOTH 0x3
127 #define GQSPI_SELECT_FLASH_BUS_LOWER 0x1
128 #define GQSPI_SELECT_FLASH_BUS_UPPER 0x2
129 #define GQSPI_SELECT_FLASH_BUS_BOTH 0x3
130 #define GQSPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
131 #define GQSPI_BAUD_DIV_SHIFT 2 /* Baud rate divisor shift */
132 #define GQSPI_SELECT_MODE_SPI 0x1
133 #define GQSPI_SELECT_MODE_DUALSPI 0x2
134 #define GQSPI_SELECT_MODE_QUADSPI 0x4
135 #define GQSPI_DMA_UNALIGN 0x3
136 #define GQSPI_DEFAULT_NUM_CS 1 /* Default number of chip selects */
138 enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
141 * struct zynqmp_qspi - Defines qspi driver instance
142 * @regs: Virtual address of the QSPI controller registers
143 * @refclk: Pointer to the peripheral clock
144 * @pclk: Pointer to the APB clock
146 * @dev: Pointer to struct device
147 * @txbuf: Pointer to the TX buffer
148 * @rxbuf: Pointer to the RX buffer
149 * @bytes_to_transfer: Number of bytes left to transfer
150 * @bytes_to_receive: Number of bytes left to receive
151 * @genfifocs: Used for chip select
152 * @genfifobus: Used to select the upper or lower bus
153 * @dma_rx_bytes: Remaining bytes to receive by DMA mode
154 * @dma_addr: DMA address after mapping the kernel buffer
155 * @genfifoentry: Used for storing the genfifoentry instruction.
156 * @mode: Defines the mode in which QSPI is operating
166 int bytes_to_transfer;
167 int bytes_to_receive;
177 * zynqmp_gqspi_read: For GQSPI controller read operation
178 * @xqspi: Pointer to the zynqmp_qspi structure
179 * @offset: Offset from where to read
181 static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset)
183 return readl_relaxed(xqspi->regs + offset);
187 * zynqmp_gqspi_write: For GQSPI controller write operation
188 * @xqspi: Pointer to the zynqmp_qspi structure
189 * @offset: Offset where to write
190 * @val: Value to be written
192 static inline void zynqmp_gqspi_write(struct zynqmp_qspi *xqspi, u32 offset,
195 writel_relaxed(val, (xqspi->regs + offset));
199 * zynqmp_gqspi_selectslave: For selection of slave device
200 * @instanceptr: Pointer to the zynqmp_qspi structure
201 * @flashcs: For chip select
202 * @flashbus: To check which bus is selected- upper or lower
204 static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr,
205 u8 slavecs, u8 slavebus)
208 * Bus and CS lines selected here will be updated in the instance and
209 * used for subsequent GENFIFO entries during transfer.
212 /* Choose slave select line */
214 case GQSPI_SELECT_FLASH_CS_BOTH:
215 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER |
216 GQSPI_GENFIFO_CS_UPPER;
218 case GQSPI_SELECT_FLASH_CS_UPPER:
219 instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER;
221 case GQSPI_SELECT_FLASH_CS_LOWER:
222 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER;
225 dev_warn(instanceptr->dev, "Invalid slave select\n");
230 case GQSPI_SELECT_FLASH_BUS_BOTH:
231 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER |
232 GQSPI_GENFIFO_BUS_UPPER;
234 case GQSPI_SELECT_FLASH_BUS_UPPER:
235 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
237 case GQSPI_SELECT_FLASH_BUS_LOWER:
238 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
241 dev_warn(instanceptr->dev, "Invalid slave bus\n");
246 * zynqmp_qspi_init_hw: Initialize the hardware
247 * @xqspi: Pointer to the zynqmp_qspi structure
249 * The default settings of the QSPI controller's configurable parameters on
252 * - TX threshold set to 1
253 * - RX threshold set to 1
254 * - Flash memory interface mode enabled
255 * This function performs the following actions
256 * - Disable and clear all the interrupts
257 * - Enable manual slave select
258 * - Enable manual start
259 * - Deselect all the chip select lines
260 * - Set the little endian mode of TX FIFO and
261 * - Enable the QSPI controller
263 static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
267 /* Select the GQSPI mode */
268 zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK);
269 /* Clear and disable interrupts */
270 zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST,
271 zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST) |
272 GQSPI_ISR_WR_TO_CLR_MASK);
273 /* Clear the DMA STS */
274 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
275 zynqmp_gqspi_read(xqspi,
276 GQSPI_QSPIDMA_DST_I_STS_OFST));
277 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_STS_OFST,
278 zynqmp_gqspi_read(xqspi,
279 GQSPI_QSPIDMA_DST_STS_OFST) |
280 GQSPI_QSPIDMA_DST_STS_WTC);
281 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_IDR_ALL_MASK);
282 zynqmp_gqspi_write(xqspi,
283 GQSPI_QSPIDMA_DST_I_DIS_OFST,
284 GQSPI_QSPIDMA_DST_INTR_ALL_MASK);
285 /* Disable the GQSPI */
286 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
287 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
288 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
290 config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK;
291 /* Little endian by default */
292 config_reg &= ~GQSPI_CFG_ENDIAN_MASK;
293 /* Disable poll time out */
294 config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK;
296 config_reg |= GQSPI_CFG_WP_HOLD_MASK;
297 /* Clear pre-scalar by default */
298 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
300 config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
302 config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
303 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
305 /* Clear the TX and RX FIFO */
306 zynqmp_gqspi_write(xqspi, GQSPI_FIFO_CTRL_OFST,
307 GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK |
308 GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK |
309 GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK);
310 /* Set by default to allow for high frequencies */
311 zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST,
312 zynqmp_gqspi_read(xqspi, GQSPI_LPBK_DLY_ADJ_OFST) |
313 GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
314 /* Reset thresholds */
315 zynqmp_gqspi_write(xqspi, GQSPI_TX_THRESHOLD_OFST,
316 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL);
317 zynqmp_gqspi_write(xqspi, GQSPI_RX_THRESHOLD_OFST,
318 GQSPI_RX_FIFO_THRESHOLD);
319 zynqmp_gqspi_write(xqspi, GQSPI_GF_THRESHOLD_OFST,
320 GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL);
321 zynqmp_gqspi_selectslave(xqspi,
322 GQSPI_SELECT_FLASH_CS_LOWER,
323 GQSPI_SELECT_FLASH_BUS_LOWER);
325 zynqmp_gqspi_write(xqspi,
326 GQSPI_QSPIDMA_DST_CTRL_OFST,
327 GQSPI_QSPIDMA_DST_CTRL_RESET_VAL);
329 /* Enable the GQSPI */
330 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
334 * zynqmp_qspi_copy_read_data: Copy data to RX buffer
335 * @xqspi: Pointer to the zynqmp_qspi structure
336 * @data: The variable where data is stored
337 * @size: Number of bytes to be copied from data to RX buffer
339 static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi,
342 memcpy(xqspi->rxbuf, &data, size);
343 xqspi->rxbuf += size;
344 xqspi->bytes_to_receive -= size;
348 * zynqmp_prepare_transfer_hardware: Prepares hardware for transfer.
349 * @master: Pointer to the spi_master structure which provides
350 * information about the controller.
352 * This function enables SPI master controller.
354 * Return: 0 on success; error value otherwise
356 static int zynqmp_prepare_transfer_hardware(struct spi_master *master)
358 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
361 ret = clk_enable(xqspi->refclk);
365 ret = clk_enable(xqspi->pclk);
369 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
372 clk_disable(xqspi->refclk);
377 * zynqmp_unprepare_transfer_hardware: Relaxes hardware after transfer
378 * @master: Pointer to the spi_master structure which provides
379 * information about the controller.
381 * This function disables the SPI master controller.
385 static int zynqmp_unprepare_transfer_hardware(struct spi_master *master)
387 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
389 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
390 clk_disable(xqspi->refclk);
391 clk_disable(xqspi->pclk);
396 * zynqmp_qspi_chipselect: Select or deselect the chip select line
397 * @qspi: Pointer to the spi_device structure
398 * @is_high: Select(0) or deselect (1) the chip select line
400 static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
402 struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
404 u32 genfifoentry = 0x0, statusreg;
406 genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
407 genfifoentry |= xqspi->genfifobus;
410 genfifoentry |= xqspi->genfifocs;
411 genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
413 genfifoentry |= GQSPI_GENFIFO_CS_HOLD;
416 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
418 /* Manually start the generic FIFO command */
419 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
420 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
421 GQSPI_CFG_START_GEN_FIFO_MASK);
423 timeout = jiffies + msecs_to_jiffies(1000);
425 /* Wait until the generic FIFO command is empty */
427 statusreg = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
429 if ((statusreg & GQSPI_ISR_GENFIFOEMPTY_MASK) &&
430 (statusreg & GQSPI_ISR_TXEMPTY_MASK))
434 } while (!time_after_eq(jiffies, timeout));
436 if (time_after_eq(jiffies, timeout))
437 dev_err(xqspi->dev, "Chip select timed out\n");
441 * zynqmp_qspi_setup_transfer: Configure QSPI controller for specified
443 * @qspi: Pointer to the spi_device structure
444 * @transfer: Pointer to the spi_transfer structure which provides
445 * information about next transfer setup parameters
447 * Sets the operational mode of QSPI controller for the next QSPI transfer and
448 * sets the requested clock frequency.
453 * If the requested frequency is not an exact match with what can be
454 * obtained using the pre-scalar value, the driver sets the clock
455 * frequency which is lower than the requested frequency (maximum lower)
458 * If the requested frequency is higher or lower than that is supported
459 * by the QSPI controller the driver will set the highest or lowest
460 * frequency supported by controller.
462 static int zynqmp_qspi_setup_transfer(struct spi_device *qspi,
463 struct spi_transfer *transfer)
465 struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
467 u32 config_reg, req_hz, baud_rate_val = 0;
470 req_hz = transfer->speed_hz;
472 req_hz = qspi->max_speed_hz;
474 /* Set the clock frequency */
475 /* If req_hz == 0, default to lowest speed */
476 clk_rate = clk_get_rate(xqspi->refclk);
478 while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
480 (GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > req_hz)
483 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
485 /* Set the QSPI clock phase and clock polarity */
486 config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK);
488 if (qspi->mode & SPI_CPHA)
489 config_reg |= GQSPI_CFG_CLK_PHA_MASK;
490 if (qspi->mode & SPI_CPOL)
491 config_reg |= GQSPI_CFG_CLK_POL_MASK;
493 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
494 config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
495 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
500 * zynqmp_qspi_setup: Configure the QSPI controller
501 * @qspi: Pointer to the spi_device structure
503 * Sets the operational mode of QSPI controller for the next QSPI transfer,
504 * baud rate and divisor value to setup the requested qspi clock.
506 * Return: 0 on success; error value otherwise.
508 static int zynqmp_qspi_setup(struct spi_device *qspi)
510 if (qspi->master->busy)
516 * zynqmp_qspi_filltxfifo: Fills the TX FIFO as long as there is room in
517 * the FIFO or the bytes required to be
519 * @xqspi: Pointer to the zynqmp_qspi structure
520 * @size: Number of bytes to be copied from TX buffer to TX FIFO
522 static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size)
524 u32 count = 0, intermediate;
526 while ((xqspi->bytes_to_transfer > 0) && (count < size)) {
527 memcpy(&intermediate, xqspi->txbuf, 4);
528 zynqmp_gqspi_write(xqspi, GQSPI_TXD_OFST, intermediate);
530 if (xqspi->bytes_to_transfer >= 4) {
532 xqspi->bytes_to_transfer -= 4;
534 xqspi->txbuf += xqspi->bytes_to_transfer;
535 xqspi->bytes_to_transfer = 0;
542 * zynqmp_qspi_readrxfifo: Fills the RX FIFO as long as there is room in
544 * @xqspi: Pointer to the zynqmp_qspi structure
545 * @size: Number of bytes to be copied from RX buffer to RX FIFO
547 static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size)
552 while ((count < size) && (xqspi->bytes_to_receive > 0)) {
553 if (xqspi->bytes_to_receive >= 4) {
554 (*(u32 *) xqspi->rxbuf) =
555 zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
557 xqspi->bytes_to_receive -= 4;
560 data = zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
561 count += xqspi->bytes_to_receive;
562 zynqmp_qspi_copy_read_data(xqspi, data,
563 xqspi->bytes_to_receive);
564 xqspi->bytes_to_receive = 0;
570 * zynqmp_process_dma_irq: Handler for DMA done interrupt of QSPI
572 * @xqspi: zynqmp_qspi instance pointer
574 * This function handles DMA interrupt only.
576 static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
578 u32 config_reg, genfifoentry;
580 dma_unmap_single(xqspi->dev, xqspi->dma_addr,
581 xqspi->dma_rx_bytes, DMA_FROM_DEVICE);
582 xqspi->rxbuf += xqspi->dma_rx_bytes;
583 xqspi->bytes_to_receive -= xqspi->dma_rx_bytes;
584 xqspi->dma_rx_bytes = 0;
586 /* Disabling the DMA interrupts */
587 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_DIS_OFST,
588 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
590 if (xqspi->bytes_to_receive > 0) {
591 /* Switch to IO mode,for remaining bytes to receive */
592 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
593 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
594 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
596 /* Initiate the transfer of remaining bytes */
597 genfifoentry = xqspi->genfifoentry;
598 genfifoentry |= xqspi->bytes_to_receive;
599 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
601 /* Dummy generic FIFO entry */
602 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
605 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
606 (zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
607 GQSPI_CFG_START_GEN_FIFO_MASK));
609 /* Enable the RX interrupts for IO mode */
610 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
611 GQSPI_IER_GENFIFOEMPTY_MASK |
612 GQSPI_IER_RXNEMPTY_MASK |
613 GQSPI_IER_RXEMPTY_MASK);
618 * zynqmp_qspi_irq: Interrupt service routine of the QSPI controller
620 * @dev_id: Pointer to the xqspi structure
622 * This function handles TX empty only.
623 * On TX empty interrupt this function reads the received data from RX FIFO
624 * and fills the TX FIFO if there is any data remaining to be transferred.
626 * Return: IRQ_HANDLED when interrupt is handled
627 * IRQ_NONE otherwise.
629 static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
631 struct spi_master *master = dev_id;
632 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
634 u32 status, mask, dma_status = 0;
636 status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
637 zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, status);
638 mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST)));
640 /* Read and clear DMA status */
641 if (xqspi->mode == GQSPI_MODE_DMA) {
643 zynqmp_gqspi_read(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST);
644 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
648 if (mask & GQSPI_ISR_TXNOT_FULL_MASK) {
649 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL);
653 if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) {
654 zynqmp_process_dma_irq(xqspi);
656 } else if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&
657 (mask & GQSPI_IER_GENFIFOEMPTY_MASK)) {
658 zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL);
662 if ((xqspi->bytes_to_receive == 0) && (xqspi->bytes_to_transfer == 0)
663 && ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
664 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
665 spi_finalize_current_transfer(master);
672 * zynqmp_qspi_selectspimode: Selects SPI mode - x1 or x2 or x4.
673 * @xqspi: xqspi is a pointer to the GQSPI instance
674 * @spimode: spimode - SPI or DUAL or QUAD.
675 * Return: Mask to set desired SPI mode in GENFIFO entry.
677 static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi,
683 case GQSPI_SELECT_MODE_DUALSPI:
684 mask = GQSPI_GENFIFO_MODE_DUALSPI;
686 case GQSPI_SELECT_MODE_QUADSPI:
687 mask = GQSPI_GENFIFO_MODE_QUADSPI;
689 case GQSPI_SELECT_MODE_SPI:
690 mask = GQSPI_GENFIFO_MODE_SPI;
693 dev_warn(xqspi->dev, "Invalid SPI mode\n");
700 * zynq_qspi_setuprxdma: This function sets up the RX DMA operation
701 * @xqspi: xqspi is a pointer to the GQSPI instance.
703 static void zynq_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
705 u32 rx_bytes, rx_rem, config_reg;
707 u64 dma_align = (u64)(uintptr_t)xqspi->rxbuf;
709 if ((xqspi->bytes_to_receive < 8) ||
710 ((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) {
711 /* Setting to IO mode */
712 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
713 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
714 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
715 xqspi->mode = GQSPI_MODE_IO;
716 xqspi->dma_rx_bytes = 0;
720 rx_rem = xqspi->bytes_to_receive % 4;
721 rx_bytes = (xqspi->bytes_to_receive - rx_rem);
723 addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf,
724 rx_bytes, DMA_FROM_DEVICE);
725 if (dma_mapping_error(xqspi->dev, addr))
726 dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n");
728 xqspi->dma_rx_bytes = rx_bytes;
729 xqspi->dma_addr = addr;
730 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_OFST,
731 (u32)(addr & 0xffffffff));
732 addr = ((addr >> 16) >> 16);
733 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST,
734 ((u32)addr) & 0xfff);
736 /* Enabling the DMA mode */
737 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
738 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
739 config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
740 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
742 /* Switch to DMA mode */
743 xqspi->mode = GQSPI_MODE_DMA;
745 /* Write the number of bytes to transfer */
746 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes);
750 * zynqmp_qspi_txrxsetup: This function checks the TX/RX buffers in
751 * the transfer and sets up the GENFIFO entries,
752 * TX FIFO as required.
753 * @xqspi: xqspi is a pointer to the GQSPI instance.
754 * @transfer: It is a pointer to the structure containing transfer data.
755 * @genfifoentry: genfifoentry is pointer to the variable in which
756 * GENFIFO mask is returned to calling function
758 static void zynqmp_qspi_txrxsetup(struct zynqmp_qspi *xqspi,
759 struct spi_transfer *transfer,
765 if ((xqspi->txbuf != NULL) && (xqspi->rxbuf == NULL)) {
766 /* Setup data to be TXed */
767 *genfifoentry &= ~GQSPI_GENFIFO_RX;
768 *genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
769 *genfifoentry |= GQSPI_GENFIFO_TX;
771 zynqmp_qspi_selectspimode(xqspi, transfer->tx_nbits);
772 xqspi->bytes_to_transfer = transfer->len;
773 if (xqspi->mode == GQSPI_MODE_DMA) {
774 config_reg = zynqmp_gqspi_read(xqspi,
776 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
777 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
779 xqspi->mode = GQSPI_MODE_IO;
781 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);
782 /* Discard RX data */
783 xqspi->bytes_to_receive = 0;
784 } else if ((xqspi->txbuf == NULL) && (xqspi->rxbuf != NULL)) {
788 *genfifoentry &= ~GQSPI_GENFIFO_TX;
790 *genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
791 *genfifoentry |= GQSPI_GENFIFO_RX;
793 zynqmp_qspi_selectspimode(xqspi, transfer->rx_nbits);
794 xqspi->bytes_to_transfer = 0;
795 xqspi->bytes_to_receive = transfer->len;
796 zynq_qspi_setuprxdma(xqspi);
801 * zynqmp_qspi_start_transfer: Initiates the QSPI transfer
802 * @master: Pointer to the spi_master structure which provides
803 * information about the controller.
804 * @qspi: Pointer to the spi_device structure
805 * @transfer: Pointer to the spi_transfer structure which provide information
806 * about next transfer parameters
808 * This function fills the TX FIFO, starts the QSPI transfer, and waits for the
809 * transfer to be completed.
811 * Return: Number of bytes transferred in the last transfer
813 static int zynqmp_qspi_start_transfer(struct spi_master *master,
814 struct spi_device *qspi,
815 struct spi_transfer *transfer)
817 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
818 u32 genfifoentry = 0x0, transfer_len;
820 xqspi->txbuf = transfer->tx_buf;
821 xqspi->rxbuf = transfer->rx_buf;
823 zynqmp_qspi_setup_transfer(qspi, transfer);
825 genfifoentry |= xqspi->genfifocs;
826 genfifoentry |= xqspi->genfifobus;
828 zynqmp_qspi_txrxsetup(xqspi, transfer, &genfifoentry);
830 if (xqspi->mode == GQSPI_MODE_DMA)
831 transfer_len = xqspi->dma_rx_bytes;
833 transfer_len = transfer->len;
835 xqspi->genfifoentry = genfifoentry;
836 if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) {
837 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
838 genfifoentry |= transfer_len;
839 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
841 int tempcount = transfer_len;
842 u32 exponent = 8; /* 2^8 = 256 */
843 u8 imm_data = tempcount & 0xFF;
845 tempcount &= ~(tempcount & 0xFF);
846 /* Immediate entry */
847 if (tempcount != 0) {
848 /* Exponent entries */
849 genfifoentry |= GQSPI_GENFIFO_EXP;
850 while (tempcount != 0) {
851 if (tempcount & GQSPI_GENFIFO_EXP_START) {
853 ~GQSPI_GENFIFO_IMM_DATA_MASK;
854 genfifoentry |= exponent;
855 zynqmp_gqspi_write(xqspi,
859 tempcount = tempcount >> 1;
864 genfifoentry &= ~GQSPI_GENFIFO_EXP;
865 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
866 genfifoentry |= (u8) (imm_data & 0xFF);
867 zynqmp_gqspi_write(xqspi,
868 GQSPI_GEN_FIFO_OFST, genfifoentry);
872 if ((xqspi->mode == GQSPI_MODE_IO) &&
873 (xqspi->rxbuf != NULL)) {
874 /* Dummy generic FIFO entry */
875 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
878 /* Since we are using manual mode */
879 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
880 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
881 GQSPI_CFG_START_GEN_FIFO_MASK);
883 if (xqspi->txbuf != NULL)
884 /* Enable interrupts for TX */
885 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
886 GQSPI_IER_TXEMPTY_MASK |
887 GQSPI_IER_GENFIFOEMPTY_MASK |
888 GQSPI_IER_TXNOT_FULL_MASK);
890 if (xqspi->rxbuf != NULL) {
891 /* Enable interrupts for RX */
892 if (xqspi->mode == GQSPI_MODE_DMA) {
893 /* Enable DMA interrupts */
894 zynqmp_gqspi_write(xqspi,
895 GQSPI_QSPIDMA_DST_I_EN_OFST,
896 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
898 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
899 GQSPI_IER_GENFIFOEMPTY_MASK |
900 GQSPI_IER_RXNEMPTY_MASK |
901 GQSPI_IER_RXEMPTY_MASK);
905 return transfer->len;
909 * zynqmp_qspi_suspend: Suspend method for the QSPI driver
910 * @_dev: Address of the platform_device structure
912 * This function stops the QSPI driver queue and disables the QSPI controller
916 static int __maybe_unused zynqmp_qspi_suspend(struct device *dev)
918 struct platform_device *pdev = to_platform_device(dev);
919 struct spi_master *master = platform_get_drvdata(pdev);
921 spi_master_suspend(master);
923 zynqmp_unprepare_transfer_hardware(master);
929 * zynqmp_qspi_resume: Resume method for the QSPI driver
930 * @dev: Address of the platform_device structure
932 * The function starts the QSPI driver queue and initializes the QSPI
935 * Return: 0 on success; error value otherwise
937 static int __maybe_unused zynqmp_qspi_resume(struct device *dev)
939 struct platform_device *pdev = to_platform_device(dev);
940 struct spi_master *master = platform_get_drvdata(pdev);
941 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
944 ret = clk_enable(xqspi->pclk);
946 dev_err(dev, "Cannot enable APB clock.\n");
950 ret = clk_enable(xqspi->refclk);
952 dev_err(dev, "Cannot enable device clock.\n");
953 clk_disable(xqspi->pclk);
957 spi_master_resume(master);
962 static SIMPLE_DEV_PM_OPS(zynqmp_qspi_dev_pm_ops, zynqmp_qspi_suspend,
966 * zynqmp_qspi_probe: Probe method for the QSPI driver
967 * @pdev: Pointer to the platform_device structure
969 * This function initializes the driver data structures and the hardware.
971 * Return: 0 on success; error value otherwise
973 static int zynqmp_qspi_probe(struct platform_device *pdev)
976 struct spi_master *master;
977 struct zynqmp_qspi *xqspi;
978 struct resource *res;
979 struct device *dev = &pdev->dev;
981 master = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
985 xqspi = spi_master_get_devdata(master);
986 master->dev.of_node = pdev->dev.of_node;
987 platform_set_drvdata(pdev, master);
989 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
990 xqspi->regs = devm_ioremap_resource(&pdev->dev, res);
991 if (IS_ERR(xqspi->regs)) {
992 ret = PTR_ERR(xqspi->regs);
997 xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
998 if (IS_ERR(xqspi->pclk)) {
999 dev_err(dev, "pclk clock not found.\n");
1000 ret = PTR_ERR(xqspi->pclk);
1004 ret = clk_prepare_enable(xqspi->pclk);
1006 dev_err(dev, "Unable to enable APB clock.\n");
1010 xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1011 if (IS_ERR(xqspi->refclk)) {
1012 dev_err(dev, "ref_clk clock not found.\n");
1013 ret = PTR_ERR(xqspi->refclk);
1017 ret = clk_prepare_enable(xqspi->refclk);
1019 dev_err(dev, "Unable to enable device clock.\n");
1023 /* QSPI controller initializations */
1024 zynqmp_qspi_init_hw(xqspi);
1026 xqspi->irq = platform_get_irq(pdev, 0);
1027 if (xqspi->irq <= 0) {
1029 dev_err(dev, "irq resource not found\n");
1032 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq,
1033 0, pdev->name, master);
1036 dev_err(dev, "request_irq failed\n");
1040 master->num_chipselect = GQSPI_DEFAULT_NUM_CS;
1042 master->setup = zynqmp_qspi_setup;
1043 master->set_cs = zynqmp_qspi_chipselect;
1044 master->transfer_one = zynqmp_qspi_start_transfer;
1045 master->prepare_transfer_hardware = zynqmp_prepare_transfer_hardware;
1046 master->unprepare_transfer_hardware =
1047 zynqmp_unprepare_transfer_hardware;
1048 master->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
1049 master->bits_per_word_mask = SPI_BPW_MASK(8);
1050 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
1051 SPI_TX_DUAL | SPI_TX_QUAD;
1053 if (master->dev.parent == NULL)
1054 master->dev.parent = &master->dev;
1056 ret = spi_register_master(master);
1063 clk_disable_unprepare(xqspi->refclk);
1065 clk_disable_unprepare(xqspi->pclk);
1067 spi_master_put(master);
1073 * zynqmp_qspi_remove: Remove method for the QSPI driver
1074 * @pdev: Pointer to the platform_device structure
1076 * This function is called if a device is physically removed from the system or
1077 * if the driver module is being unloaded. It frees all resources allocated to
1082 static int zynqmp_qspi_remove(struct platform_device *pdev)
1084 struct spi_master *master = platform_get_drvdata(pdev);
1085 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
1087 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
1088 clk_disable_unprepare(xqspi->refclk);
1089 clk_disable_unprepare(xqspi->pclk);
1091 spi_unregister_master(master);
1096 static const struct of_device_id zynqmp_qspi_of_match[] = {
1097 { .compatible = "xlnx,zynqmp-qspi-1.0", },
1098 { /* End of table */ }
1101 MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match);
1103 static struct platform_driver zynqmp_qspi_driver = {
1104 .probe = zynqmp_qspi_probe,
1105 .remove = zynqmp_qspi_remove,
1107 .name = "zynqmp-qspi",
1108 .of_match_table = zynqmp_qspi_of_match,
1109 .pm = &zynqmp_qspi_dev_pm_ops,
1113 module_platform_driver(zynqmp_qspi_driver);
1115 MODULE_AUTHOR("Xilinx, Inc.");
1116 MODULE_DESCRIPTION("Xilinx Zynqmp QSPI driver");
1117 MODULE_LICENSE("GPL");