drivers/spi/spi-topcliff-pch.c

   1 /*
   2  * SPI bus driver for the Topcliff PCH used by Intel SoCs
   3  *
   4  * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/pci.h>
  18 #include <linux/wait.h>
  19 #include <linux/spi/spi.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/sched.h>
  22 #include <linux/spi/spidev.h>
  23 #include <linux/module.h>
  24 #include <linux/device.h>
  25 #include <linux/platform_device.h>
  26
  27 #include <linux/dmaengine.h>
  28 #include <linux/pch_dma.h>
  29
  30 /* Register offsets */
  31 #define PCH_SPCR                0x00    /* SPI control register */
  32 #define PCH_SPBRR               0x04    /* SPI baud rate register */
  33 #define PCH_SPSR                0x08    /* SPI status register */
  34 #define PCH_SPDWR               0x0C    /* SPI write data register */
  35 #define PCH_SPDRR               0x10    /* SPI read data register */
  36 #define PCH_SSNXCR              0x18    /* SSN Expand Control Register */
  37 #define PCH_SRST                0x1C    /* SPI reset register */
  38 #define PCH_ADDRESS_SIZE        0x20
  39
  40 #define PCH_SPSR_TFD            0x000007C0
  41 #define PCH_SPSR_RFD            0x0000F800
  42
  43 #define PCH_READABLE(x)         (((x) & PCH_SPSR_RFD)>>11)
  44 #define PCH_WRITABLE(x)         (((x) & PCH_SPSR_TFD)>>6)
  45
  46 #define PCH_RX_THOLD            7
  47 #define PCH_RX_THOLD_MAX        15
  48
  49 #define PCH_TX_THOLD            2
  50
  51 #define PCH_MAX_BAUDRATE        5000000
  52 #define PCH_MAX_FIFO_DEPTH      16
  53
  54 #define STATUS_RUNNING          1
  55 #define STATUS_EXITING          2
  56 #define PCH_SLEEP_TIME          10
  57
  58 #define SSN_LOW                 0x02U
  59 #define SSN_HIGH                0x03U
  60 #define SSN_NO_CONTROL          0x00U
  61 #define PCH_MAX_CS              0xFF
  62 #define PCI_DEVICE_ID_GE_SPI    0x8816
  63
  64 #define SPCR_SPE_BIT            (1 << 0)
  65 #define SPCR_MSTR_BIT           (1 << 1)
  66 #define SPCR_LSBF_BIT           (1 << 4)
  67 #define SPCR_CPHA_BIT           (1 << 5)
  68 #define SPCR_CPOL_BIT           (1 << 6)
  69 #define SPCR_TFIE_BIT           (1 << 8)
  70 #define SPCR_RFIE_BIT           (1 << 9)
  71 #define SPCR_FIE_BIT            (1 << 10)
  72 #define SPCR_ORIE_BIT           (1 << 11)
  73 #define SPCR_MDFIE_BIT          (1 << 12)
  74 #define SPCR_FICLR_BIT          (1 << 24)
  75 #define SPSR_TFI_BIT            (1 << 0)
  76 #define SPSR_RFI_BIT            (1 << 1)
  77 #define SPSR_FI_BIT             (1 << 2)
  78 #define SPSR_ORF_BIT            (1 << 3)
  79 #define SPBRR_SIZE_BIT          (1 << 10)
  80
  81 #define PCH_ALL                 (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
  82                                 SPCR_ORIE_BIT|SPCR_MDFIE_BIT)
  83
  84 #define SPCR_RFIC_FIELD         20
  85 #define SPCR_TFIC_FIELD         16
  86
  87 #define MASK_SPBRR_SPBR_BITS    ((1 << 10) - 1)
  88 #define MASK_RFIC_SPCR_BITS     (0xf << SPCR_RFIC_FIELD)
  89 #define MASK_TFIC_SPCR_BITS     (0xf << SPCR_TFIC_FIELD)
  90
  91 #define PCH_CLOCK_HZ            50000000
  92 #define PCH_MAX_SPBR            1023
  93
  94 /* Definition for ML7213/ML7223/ML7831 by LAPIS Semiconductor */
  95 #define PCI_VENDOR_ID_ROHM              0x10DB
  96 #define PCI_DEVICE_ID_ML7213_SPI        0x802c
  97 #define PCI_DEVICE_ID_ML7223_SPI        0x800F
  98 #define PCI_DEVICE_ID_ML7831_SPI        0x8816
  99
 100 /*
 101  * Set the number of SPI instance max
 102  * Intel EG20T PCH :            1ch
 103  * LAPIS Semiconductor ML7213 IOH :     2ch
 104  * LAPIS Semiconductor ML7223 IOH :     1ch
 105  * LAPIS Semiconductor ML7831 IOH :     1ch
 106 */
 107 #define PCH_SPI_MAX_DEV                 2
 108
 109 #define PCH_BUF_SIZE            4096
 110 #define PCH_DMA_TRANS_SIZE      12
 111
 112 static int use_dma = 1;
 113
 114 struct pch_spi_dma_ctrl {
 115         struct dma_async_tx_descriptor  *desc_tx;
 116         struct dma_async_tx_descriptor  *desc_rx;
 117         struct pch_dma_slave            param_tx;
 118         struct pch_dma_slave            param_rx;
 119         struct dma_chan         *chan_tx;
 120         struct dma_chan         *chan_rx;
 121         struct scatterlist              *sg_tx_p;
 122         struct scatterlist              *sg_rx_p;
 123         struct scatterlist              sg_tx;
 124         struct scatterlist              sg_rx;
 125         int                             nent;
 126         void                            *tx_buf_virt;
 127         void                            *rx_buf_virt;
 128         dma_addr_t                      tx_buf_dma;
 129         dma_addr_t                      rx_buf_dma;
 130 };
 131 /**
 132  * struct pch_spi_data - Holds the SPI channel specific details
 133  * @io_remap_addr:              The remapped PCI base address
 134  * @master:                     Pointer to the SPI master structure
 135  * @work:                       Reference to work queue handler
 136  * @wait:                       Wait queue for waking up upon receiving an
 137  *                              interrupt.
 138  * @transfer_complete:          Status of SPI Transfer
 139  * @bcurrent_msg_processing:    Status flag for message processing
 140  * @lock:                       Lock for protecting this structure
 141  * @queue:                      SPI Message queue
 142  * @status:                     Status of the SPI driver
 143  * @bpw_len:                    Length of data to be transferred in bits per
 144  *                              word
 145  * @transfer_active:            Flag showing active transfer
 146  * @tx_index:                   Transmit data count; for bookkeeping during
 147  *                              transfer
 148  * @rx_index:                   Receive data count; for bookkeeping during
 149  *                              transfer
 150  * @tx_buff:                    Buffer for data to be transmitted
 151  * @rx_index:                   Buffer for Received data
 152  * @n_curnt_chip:               The chip number that this SPI driver currently
 153  *                              operates on
 154  * @current_chip:               Reference to the current chip that this SPI
 155  *                              driver currently operates on
 156  * @current_msg:                The current message that this SPI driver is
 157  *                              handling
 158  * @cur_trans:                  The current transfer that this SPI driver is
 159  *                              handling
 160  * @board_dat:                  Reference to the SPI device data structure
 161  * @plat_dev:                   platform_device structure
 162  * @ch:                         SPI channel number
 163  * @irq_reg_sts:                Status of IRQ registration
 164  */
 165 struct pch_spi_data {
 166         void __iomem *io_remap_addr;
 167         unsigned long io_base_addr;
 168         struct spi_master *master;
 169         struct work_struct work;
 170         wait_queue_head_t wait;
 171         u8 transfer_complete;
 172         u8 bcurrent_msg_processing;
 173         spinlock_t lock;
 174         struct list_head queue;
 175         u8 status;
 176         u32 bpw_len;
 177         u8 transfer_active;
 178         u32 tx_index;
 179         u32 rx_index;
 180         u16 *pkt_tx_buff;
 181         u16 *pkt_rx_buff;
 182         u8 n_curnt_chip;
 183         struct spi_device *current_chip;
 184         struct spi_message *current_msg;
 185         struct spi_transfer *cur_trans;
 186         struct pch_spi_board_data *board_dat;
 187         struct platform_device  *plat_dev;
 188         int ch;
 189         struct pch_spi_dma_ctrl dma;
 190         int use_dma;
 191         u8 irq_reg_sts;
 192         int save_total_len;
 193 };
 194
 195 /**
 196  * struct pch_spi_board_data - Holds the SPI device specific details
 197  * @pdev:               Pointer to the PCI device
 198  * @suspend_sts:        Status of suspend
 199  * @num:                The number of SPI device instance
 200  */
 201 struct pch_spi_board_data {
 202         struct pci_dev *pdev;
 203         u8 suspend_sts;
 204         int num;
 205 };
 206
 207 struct pch_pd_dev_save {
 208         int num;
 209         struct platform_device *pd_save[PCH_SPI_MAX_DEV];
 210         struct pch_spi_board_data *board_dat;
 211 };
 212
 213 static const struct pci_device_id pch_spi_pcidev_id[] = {
 214         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI),    1, },
 215         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
 216         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, },
 217         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_SPI), 1, },
 218         { }
 219 };
 220
 221 /**
 222  * pch_spi_writereg() - Performs  register writes
 223  * @master:     Pointer to struct spi_master.
 224  * @idx:        Register offset.
 225  * @val:        Value to be written to register.
 226  */
 227 static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val)
 228 {
 229         struct pch_spi_data *data = spi_master_get_devdata(master);
 230         iowrite32(val, (data->io_remap_addr + idx));
 231 }
 232
 233 /**
 234  * pch_spi_readreg() - Performs register reads
 235  * @master:     Pointer to struct spi_master.
 236  * @idx:        Register offset.
 237  */
 238 static inline u32 pch_spi_readreg(struct spi_master *master, int idx)
 239 {
 240         struct pch_spi_data *data = spi_master_get_devdata(master);
 241         return ioread32(data->io_remap_addr + idx);
 242 }
 243
 244 static inline void pch_spi_setclr_reg(struct spi_master *master, int idx,
 245                                       u32 set, u32 clr)
 246 {
 247         u32 tmp = pch_spi_readreg(master, idx);
 248         tmp = (tmp & ~clr) | set;
 249         pch_spi_writereg(master, idx, tmp);
 250 }
 251
 252 static void pch_spi_set_master_mode(struct spi_master *master)
 253 {
 254         pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0);
 255 }
 256
 257 /**
 258  * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs
 259  * @master:     Pointer to struct spi_master.
 260  */
 261 static void pch_spi_clear_fifo(struct spi_master *master)
 262 {
 263         pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0);
 264         pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT);
 265 }
 266
 267 static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
 268                                 void __iomem *io_remap_addr)
 269 {
 270         u32 n_read, tx_index, rx_index, bpw_len;
 271         u16 *pkt_rx_buffer, *pkt_tx_buff;
 272         int read_cnt;
 273         u32 reg_spcr_val;
 274         void __iomem *spsr;
 275         void __iomem *spdrr;
 276         void __iomem *spdwr;
 277
 278         spsr = io_remap_addr + PCH_SPSR;
 279         iowrite32(reg_spsr_val, spsr);
 280
 281         if (data->transfer_active) {
 282                 rx_index = data->rx_index;
 283                 tx_index = data->tx_index;
 284                 bpw_len = data->bpw_len;
 285                 pkt_rx_buffer = data->pkt_rx_buff;
 286                 pkt_tx_buff = data->pkt_tx_buff;
 287
 288                 spdrr = io_remap_addr + PCH_SPDRR;
 289                 spdwr = io_remap_addr + PCH_SPDWR;
 290
 291                 n_read = PCH_READABLE(reg_spsr_val);
 292
 293                 for (read_cnt = 0; (read_cnt < n_read); read_cnt++) {
 294                         pkt_rx_buffer[rx_index++] = ioread32(spdrr);
 295                         if (tx_index < bpw_len)
 296                                 iowrite32(pkt_tx_buff[tx_index++], spdwr);
 297                 }
 298
 299                 /* disable RFI if not needed */
 300                 if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) {
 301                         reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR);
 302                         reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */
 303
 304                         /* reset rx threshold */
 305                         reg_spcr_val &= ~MASK_RFIC_SPCR_BITS;
 306                         reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD);
 307
 308                         iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR));
 309                 }
 310
 311                 /* update counts */
 312                 data->tx_index = tx_index;
 313                 data->rx_index = rx_index;
 314
 315                 /* if transfer complete interrupt */
 316                 if (reg_spsr_val & SPSR_FI_BIT) {
 317                         if ((tx_index == bpw_len) && (rx_index == tx_index)) {
 318                                 /* disable interrupts */
 319                                 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
 320                                                    PCH_ALL);
 321
 322                                 /* transfer is completed;
 323                                    inform pch_spi_process_messages */
 324                                 data->transfer_complete = true;
 325                                 data->transfer_active = false;
 326                                 wake_up(&data->wait);
 327                         } else {
 328                                 dev_vdbg(&data->master->dev,
 329                                         "%s : Transfer is not completed",
 330                                         __func__);
 331                         }
 332                 }
 333         }
 334 }
 335
 336 /**
 337  * pch_spi_handler() - Interrupt handler
 338  * @irq:        The interrupt number.
 339  * @dev_id:     Pointer to struct pch_spi_board_data.
 340  */
 341 static irqreturn_t pch_spi_handler(int irq, void *dev_id)
 342 {
 343         u32 reg_spsr_val;
 344         void __iomem *spsr;
 345         void __iomem *io_remap_addr;
 346         irqreturn_t ret = IRQ_NONE;
 347         struct pch_spi_data *data = dev_id;
 348         struct pch_spi_board_data *board_dat = data->board_dat;
 349
 350         if (board_dat->suspend_sts) {
 351                 dev_dbg(&board_dat->pdev->dev,
 352                         "%s returning due to suspend\n", __func__);
 353                 return IRQ_NONE;
 354         }
 355
 356         io_remap_addr = data->io_remap_addr;
 357         spsr = io_remap_addr + PCH_SPSR;
 358
 359         reg_spsr_val = ioread32(spsr);
 360
 361         if (reg_spsr_val & SPSR_ORF_BIT) {
 362                 dev_err(&board_dat->pdev->dev, "%s Over run error\n", __func__);
 363                 if (data->current_msg->complete) {
 364                         data->transfer_complete = true;
 365                         data->current_msg->status = -EIO;
 366                         data->current_msg->complete(data->current_msg->context);
 367                         data->bcurrent_msg_processing = false;
 368                         data->current_msg = NULL;
 369                         data->cur_trans = NULL;
 370                 }
 371         }
 372
 373         if (data->use_dma)
 374                 return IRQ_NONE;
 375
 376         /* Check if the interrupt is for SPI device */
 377         if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) {
 378                 pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
 379                 ret = IRQ_HANDLED;
 380         }
 381
 382         dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n",
 383                 __func__, ret);
 384
 385         return ret;
 386 }
 387
 388 /**
 389  * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR
 390  * @master:     Pointer to struct spi_master.
 391  * @speed_hz:   Baud rate.
 392  */
 393 static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz)
 394 {
 395         u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2);
 396
 397         /* if baud rate is less than we can support limit it */
 398         if (n_spbr > PCH_MAX_SPBR)
 399                 n_spbr = PCH_MAX_SPBR;
 400
 401         pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS);
 402 }
 403
 404 /**
 405  * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR
 406  * @master:             Pointer to struct spi_master.
 407  * @bits_per_word:      Bits per word for SPI transfer.
 408  */
 409 static void pch_spi_set_bits_per_word(struct spi_master *master,
 410                                       u8 bits_per_word)
 411 {
 412         if (bits_per_word == 8)
 413                 pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT);
 414         else
 415                 pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0);
 416 }
 417
 418 /**
 419  * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer
 420  * @spi:        Pointer to struct spi_device.
 421  */
 422 static void pch_spi_setup_transfer(struct spi_device *spi)
 423 {
 424         u32 flags = 0;
 425
 426         dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n",
 427                 __func__, pch_spi_readreg(spi->master, PCH_SPBRR),
 428                 spi->max_speed_hz);
 429         pch_spi_set_baud_rate(spi->master, spi->max_speed_hz);
 430
 431         /* set bits per word */
 432         pch_spi_set_bits_per_word(spi->master, spi->bits_per_word);
 433
 434         if (!(spi->mode & SPI_LSB_FIRST))
 435                 flags |= SPCR_LSBF_BIT;
 436         if (spi->mode & SPI_CPOL)
 437                 flags |= SPCR_CPOL_BIT;
 438         if (spi->mode & SPI_CPHA)
 439                 flags |= SPCR_CPHA_BIT;
 440         pch_spi_setclr_reg(spi->master, PCH_SPCR, flags,
 441                            (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT));
 442
 443         /* Clear the FIFO by toggling  FICLR to 1 and back to 0 */
 444         pch_spi_clear_fifo(spi->master);
 445 }
 446
 447 /**
 448  * pch_spi_reset() - Clears SPI registers
 449  * @master:     Pointer to struct spi_master.
 450  */
 451 static void pch_spi_reset(struct spi_master *master)
 452 {
 453         /* write 1 to reset SPI */
 454         pch_spi_writereg(master, PCH_SRST, 0x1);
 455
 456         /* clear reset */
 457         pch_spi_writereg(master, PCH_SRST, 0x0);
 458 }
 459
 460 static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
 461 {
 462
 463         struct spi_transfer *transfer;
 464         struct pch_spi_data *data = spi_master_get_devdata(pspi->master);
 465         int retval;
 466         unsigned long flags;
 467
 468         spin_lock_irqsave(&data->lock, flags);
 469         /* validate Tx/Rx buffers and Transfer length */
 470         list_for_each_entry(transfer, &pmsg->transfers, transfer_list) {
 471                 if (!transfer->tx_buf && !transfer->rx_buf) {
 472                         dev_err(&pspi->dev,
 473                                 "%s Tx and Rx buffer NULL\n", __func__);
 474                         retval = -EINVAL;
 475                         goto err_return_spinlock;
 476                 }
 477
 478                 if (!transfer->len) {
 479                         dev_err(&pspi->dev, "%s Transfer length invalid\n",
 480                                 __func__);
 481                         retval = -EINVAL;
 482                         goto err_return_spinlock;
 483                 }
 484
 485                 dev_dbg(&pspi->dev,
 486                         "%s Tx/Rx buffer valid. Transfer length valid\n",
 487                         __func__);
 488         }
 489         spin_unlock_irqrestore(&data->lock, flags);
 490
 491         /* We won't process any messages if we have been asked to terminate */
 492         if (data->status == STATUS_EXITING) {
 493                 dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__);
 494                 retval = -ESHUTDOWN;
 495                 goto err_out;
 496         }
 497
 498         /* If suspended ,return -EINVAL */
 499         if (data->board_dat->suspend_sts) {
 500                 dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__);
 501                 retval = -EINVAL;
 502                 goto err_out;
 503         }
 504
 505         /* set status of message */
 506         pmsg->actual_length = 0;
 507         dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status);
 508
 509         pmsg->status = -EINPROGRESS;
 510         spin_lock_irqsave(&data->lock, flags);
 511         /* add message to queue */
 512         list_add_tail(&pmsg->queue, &data->queue);
 513         spin_unlock_irqrestore(&data->lock, flags);
 514
 515         dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__);
 516
 517         schedule_work(&data->work);
 518         dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__);
 519
 520         retval = 0;
 521
 522 err_out:
 523         dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
 524         return retval;
 525 err_return_spinlock:
 526         dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
 527         spin_unlock_irqrestore(&data->lock, flags);
 528         return retval;
 529 }
 530
 531 static inline void pch_spi_select_chip(struct pch_spi_data *data,
 532                                        struct spi_device *pspi)
 533 {
 534         if (data->current_chip != NULL) {
 535                 if (pspi->chip_select != data->n_curnt_chip) {
 536                         dev_dbg(&pspi->dev, "%s : different slave\n", __func__);
 537                         data->current_chip = NULL;
 538                 }
 539         }
 540
 541         data->current_chip = pspi;
 542
 543         data->n_curnt_chip = data->current_chip->chip_select;
 544
 545         dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__);
 546         pch_spi_setup_transfer(pspi);
 547 }
 548
 549 static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw)
 550 {
 551         int size;
 552         u32 n_writes;
 553         int j;
 554         struct spi_message *pmsg, *tmp;
 555         const u8 *tx_buf;
 556         const u16 *tx_sbuf;
 557
 558         /* set baud rate if needed */
 559         if (data->cur_trans->speed_hz) {
 560                 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
 561                 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
 562         }
 563
 564         /* set bits per word if needed */
 565         if (data->cur_trans->bits_per_word &&
 566             (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) {
 567                 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
 568                 pch_spi_set_bits_per_word(data->master,
 569                                           data->cur_trans->bits_per_word);
 570                 *bpw = data->cur_trans->bits_per_word;
 571         } else {
 572                 *bpw = data->current_msg->spi->bits_per_word;
 573         }
 574
 575         /* reset Tx/Rx index */
 576         data->tx_index = 0;
 577         data->rx_index = 0;
 578
 579         data->bpw_len = data->cur_trans->len / (*bpw / 8);
 580
 581         /* find alloc size */
 582         size = data->cur_trans->len * sizeof(*data->pkt_tx_buff);
 583
 584         /* allocate memory for pkt_tx_buff & pkt_rx_buffer */
 585         data->pkt_tx_buff = kzalloc(size, GFP_KERNEL);
 586         if (data->pkt_tx_buff != NULL) {
 587                 data->pkt_rx_buff = kzalloc(size, GFP_KERNEL);
 588                 if (!data->pkt_rx_buff) {
 589                         kfree(data->pkt_tx_buff);
 590                         data->pkt_tx_buff = NULL;
 591                 }
 592         }
 593
 594         if (!data->pkt_rx_buff) {
 595                 /* flush queue and set status of all transfers to -ENOMEM */
 596                 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
 597                         pmsg->status = -ENOMEM;
 598
 599                         if (pmsg->complete)
 600                                 pmsg->complete(pmsg->context);
 601
 602                         /* delete from queue */
 603                         list_del_init(&pmsg->queue);
 604                 }
 605                 return;
 606         }
 607
 608         /* copy Tx Data */
 609         if (data->cur_trans->tx_buf != NULL) {
 610                 if (*bpw == 8) {
 611                         tx_buf = data->cur_trans->tx_buf;
 612                         for (j = 0; j < data->bpw_len; j++)
 613                                 data->pkt_tx_buff[j] = *tx_buf++;
 614                 } else {
 615                         tx_sbuf = data->cur_trans->tx_buf;
 616                         for (j = 0; j < data->bpw_len; j++)
 617                                 data->pkt_tx_buff[j] = *tx_sbuf++;
 618                 }
 619         }
 620
 621         /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */
 622         n_writes = data->bpw_len;
 623         if (n_writes > PCH_MAX_FIFO_DEPTH)
 624                 n_writes = PCH_MAX_FIFO_DEPTH;
 625
 626         dev_dbg(&data->master->dev,
 627                 "\n%s:Pulling down SSN low - writing 0x2 to SSNXCR\n",
 628                 __func__);
 629         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
 630
 631         for (j = 0; j < n_writes; j++)
 632                 pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]);
 633
 634         /* update tx_index */
 635         data->tx_index = j;
 636
 637         /* reset transfer complete flag */
 638         data->transfer_complete = false;
 639         data->transfer_active = true;
 640 }
 641
 642 static void pch_spi_nomore_transfer(struct pch_spi_data *data)
 643 {
 644         struct spi_message *pmsg, *tmp;
 645         dev_dbg(&data->master->dev, "%s called\n", __func__);
 646         /* Invoke complete callback
 647          * [To the spi core..indicating end of transfer] */
 648         data->current_msg->status = 0;
 649
 650         if (data->current_msg->complete) {
 651                 dev_dbg(&data->master->dev,
 652                         "%s:Invoking callback of SPI core\n", __func__);
 653                 data->current_msg->complete(data->current_msg->context);
 654         }
 655
 656         /* update status in global variable */
 657         data->bcurrent_msg_processing = false;
 658
 659         dev_dbg(&data->master->dev,
 660                 "%s:data->bcurrent_msg_processing = false\n", __func__);
 661
 662         data->current_msg = NULL;
 663         data->cur_trans = NULL;
 664
 665         /* check if we have items in list and not suspending
 666          * return 1 if list empty */
 667         if ((list_empty(&data->queue) == 0) &&
 668             (!data->board_dat->suspend_sts) &&
 669             (data->status != STATUS_EXITING)) {
 670                 /* We have some more work to do (either there is more tranint
 671                  * bpw;sfer requests in the current message or there are
 672                  *more messages)
 673                  */
 674                 dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__);
 675                 schedule_work(&data->work);
 676         } else if (data->board_dat->suspend_sts ||
 677                    data->status == STATUS_EXITING) {
 678                 dev_dbg(&data->master->dev,
 679                         "%s suspend/remove initiated, flushing queue\n",
 680                         __func__);
 681                 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
 682                         pmsg->status = -EIO;
 683
 684                         if (pmsg->complete)
 685                                 pmsg->complete(pmsg->context);
 686
 687                         /* delete from queue */
 688                         list_del_init(&pmsg->queue);
 689                 }
 690         }
 691 }
 692
 693 static void pch_spi_set_ir(struct pch_spi_data *data)
 694 {
 695         /* enable interrupts, set threshold, enable SPI */
 696         if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH)
 697                 /* set receive threshold to PCH_RX_THOLD */
 698                 pch_spi_setclr_reg(data->master, PCH_SPCR,
 699                                    PCH_RX_THOLD << SPCR_RFIC_FIELD |
 700                                    SPCR_FIE_BIT | SPCR_RFIE_BIT |
 701                                    SPCR_ORIE_BIT | SPCR_SPE_BIT,
 702                                    MASK_RFIC_SPCR_BITS | PCH_ALL);
 703         else
 704                 /* set receive threshold to maximum */
 705                 pch_spi_setclr_reg(data->master, PCH_SPCR,
 706                                    PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD |
 707                                    SPCR_FIE_BIT | SPCR_ORIE_BIT |
 708                                    SPCR_SPE_BIT,
 709                                    MASK_RFIC_SPCR_BITS | PCH_ALL);
 710
 711         /* Wait until the transfer completes; go to sleep after
 712                                  initiating the transfer. */
 713         dev_dbg(&data->master->dev,
 714                 "%s:waiting for transfer to get over\n", __func__);
 715
 716         wait_event_interruptible(data->wait, data->transfer_complete);
 717
 718         /* clear all interrupts */
 719         pch_spi_writereg(data->master, PCH_SPSR,
 720                          pch_spi_readreg(data->master, PCH_SPSR));
 721         /* Disable interrupts and SPI transfer */
 722         pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT);
 723         /* clear FIFO */
 724         pch_spi_clear_fifo(data->master);
 725 }
 726
 727 static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw)
 728 {
 729         int j;
 730         u8 *rx_buf;
 731         u16 *rx_sbuf;
 732
 733         /* copy Rx Data */
 734         if (!data->cur_trans->rx_buf)
 735                 return;
 736
 737         if (bpw == 8) {
 738                 rx_buf = data->cur_trans->rx_buf;
 739                 for (j = 0; j < data->bpw_len; j++)
 740                         *rx_buf++ = data->pkt_rx_buff[j] & 0xFF;
 741         } else {
 742                 rx_sbuf = data->cur_trans->rx_buf;
 743                 for (j = 0; j < data->bpw_len; j++)
 744                         *rx_sbuf++ = data->pkt_rx_buff[j];
 745         }
 746 }
 747
 748 static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw)
 749 {
 750         int j;
 751         u8 *rx_buf;
 752         u16 *rx_sbuf;
 753         const u8 *rx_dma_buf;
 754         const u16 *rx_dma_sbuf;
 755
 756         /* copy Rx Data */
 757         if (!data->cur_trans->rx_buf)
 758                 return;
 759
 760         if (bpw == 8) {
 761                 rx_buf = data->cur_trans->rx_buf;
 762                 rx_dma_buf = data->dma.rx_buf_virt;
 763                 for (j = 0; j < data->bpw_len; j++)
 764                         *rx_buf++ = *rx_dma_buf++ & 0xFF;
 765                 data->cur_trans->rx_buf = rx_buf;
 766         } else {
 767                 rx_sbuf = data->cur_trans->rx_buf;
 768                 rx_dma_sbuf = data->dma.rx_buf_virt;
 769                 for (j = 0; j < data->bpw_len; j++)
 770                         *rx_sbuf++ = *rx_dma_sbuf++;
 771                 data->cur_trans->rx_buf = rx_sbuf;
 772         }
 773 }
 774
 775 static int pch_spi_start_transfer(struct pch_spi_data *data)
 776 {
 777         struct pch_spi_dma_ctrl *dma;
 778         unsigned long flags;
 779         int rtn;
 780
 781         dma = &data->dma;
 782
 783         spin_lock_irqsave(&data->lock, flags);
 784
 785         /* disable interrupts, SPI set enable */
 786         pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL);
 787
 788         spin_unlock_irqrestore(&data->lock, flags);
 789
 790         /* Wait until the transfer completes; go to sleep after
 791                                  initiating the transfer. */
 792         dev_dbg(&data->master->dev,
 793                 "%s:waiting for transfer to get over\n", __func__);
 794         rtn = wait_event_interruptible_timeout(data->wait,
 795                                                data->transfer_complete,
 796                                                msecs_to_jiffies(2 * HZ));
 797         if (!rtn)
 798                 dev_err(&data->master->dev,
 799                         "%s wait-event timeout\n", __func__);
 800
 801         dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent,
 802                             DMA_FROM_DEVICE);
 803
 804         dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent,
 805                             DMA_FROM_DEVICE);
 806         memset(data->dma.tx_buf_virt, 0, PAGE_SIZE);
 807
 808         async_tx_ack(dma->desc_rx);
 809         async_tx_ack(dma->desc_tx);
 810         kfree(dma->sg_tx_p);
 811         kfree(dma->sg_rx_p);
 812
 813         spin_lock_irqsave(&data->lock, flags);
 814
 815         /* clear fifo threshold, disable interrupts, disable SPI transfer */
 816         pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
 817                            MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL |
 818                            SPCR_SPE_BIT);
 819         /* clear all interrupts */
 820         pch_spi_writereg(data->master, PCH_SPSR,
 821                          pch_spi_readreg(data->master, PCH_SPSR));
 822         /* clear FIFO */
 823         pch_spi_clear_fifo(data->master);
 824
 825         spin_unlock_irqrestore(&data->lock, flags);
 826
 827         return rtn;
 828 }
 829
 830 static void pch_dma_rx_complete(void *arg)
 831 {
 832         struct pch_spi_data *data = arg;
 833
 834         /* transfer is completed;inform pch_spi_process_messages_dma */
 835         data->transfer_complete = true;
 836         wake_up_interruptible(&data->wait);
 837 }
 838
 839 static bool pch_spi_filter(struct dma_chan *chan, void *slave)
 840 {
 841         struct pch_dma_slave *param = slave;
 842
 843         if ((chan->chan_id == param->chan_id) &&
 844             (param->dma_dev == chan->device->dev)) {
 845                 chan->private = param;
 846                 return true;
 847         } else {
 848                 return false;
 849         }
 850 }
 851
 852 static void pch_spi_request_dma(struct pch_spi_data *data, int bpw)
 853 {
 854         dma_cap_mask_t mask;
 855         struct dma_chan *chan;
 856         struct pci_dev *dma_dev;
 857         struct pch_dma_slave *param;
 858         struct pch_spi_dma_ctrl *dma;
 859         unsigned int width;
 860
 861         if (bpw == 8)
 862                 width = PCH_DMA_WIDTH_1_BYTE;
 863         else
 864                 width = PCH_DMA_WIDTH_2_BYTES;
 865
 866         dma = &data->dma;
 867         dma_cap_zero(mask);
 868         dma_cap_set(DMA_SLAVE, mask);
 869
 870         /* Get DMA's dev information */
 871         dma_dev = pci_get_slot(data->board_dat->pdev->bus,
 872                         PCI_DEVFN(PCI_SLOT(data->board_dat->pdev->devfn), 0));
 873
 874         /* Set Tx DMA */
 875         param = &dma->param_tx;
 876         param->dma_dev = &dma_dev->dev;
 877         param->chan_id = data->ch * 2; /* Tx = 0, 2 */;
 878         param->tx_reg = data->io_base_addr + PCH_SPDWR;
 879         param->width = width;
 880         chan = dma_request_channel(mask, pch_spi_filter, param);
 881         if (!chan) {
 882                 dev_err(&data->master->dev,
 883                         "ERROR: dma_request_channel FAILS(Tx)\n");
 884                 data->use_dma = 0;
 885                 return;
 886         }
 887         dma->chan_tx = chan;
 888
 889         /* Set Rx DMA */
 890         param = &dma->param_rx;
 891         param->dma_dev = &dma_dev->dev;
 892         param->chan_id = data->ch * 2 + 1; /* Rx = Tx + 1 */;
 893         param->rx_reg = data->io_base_addr + PCH_SPDRR;
 894         param->width = width;
 895         chan = dma_request_channel(mask, pch_spi_filter, param);
 896         if (!chan) {
 897                 dev_err(&data->master->dev,
 898                         "ERROR: dma_request_channel FAILS(Rx)\n");
 899                 dma_release_channel(dma->chan_tx);
 900                 dma->chan_tx = NULL;
 901                 data->use_dma = 0;
 902                 return;
 903         }
 904         dma->chan_rx = chan;
 905 }
 906
 907 static void pch_spi_release_dma(struct pch_spi_data *data)
 908 {
 909         struct pch_spi_dma_ctrl *dma;
 910
 911         dma = &data->dma;
 912         if (dma->chan_tx) {
 913                 dma_release_channel(dma->chan_tx);
 914                 dma->chan_tx = NULL;
 915         }
 916         if (dma->chan_rx) {
 917                 dma_release_channel(dma->chan_rx);
 918                 dma->chan_rx = NULL;
 919         }
 920 }
 921
 922 static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
 923 {
 924         const u8 *tx_buf;
 925         const u16 *tx_sbuf;
 926         u8 *tx_dma_buf;
 927         u16 *tx_dma_sbuf;
 928         struct scatterlist *sg;
 929         struct dma_async_tx_descriptor *desc_tx;
 930         struct dma_async_tx_descriptor *desc_rx;
 931         int num;
 932         int i;
 933         int size;
 934         int rem;
 935         int head;
 936         unsigned long flags;
 937         struct pch_spi_dma_ctrl *dma;
 938
 939         dma = &data->dma;
 940
 941         /* set baud rate if needed */
 942         if (data->cur_trans->speed_hz) {
 943                 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
 944                 spin_lock_irqsave(&data->lock, flags);
 945                 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
 946                 spin_unlock_irqrestore(&data->lock, flags);
 947         }
 948
 949         /* set bits per word if needed */
 950         if (data->cur_trans->bits_per_word &&
 951             (data->current_msg->spi->bits_per_word !=
 952              data->cur_trans->bits_per_word)) {
 953                 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
 954                 spin_lock_irqsave(&data->lock, flags);
 955                 pch_spi_set_bits_per_word(data->master,
 956                                           data->cur_trans->bits_per_word);
 957                 spin_unlock_irqrestore(&data->lock, flags);
 958                 *bpw = data->cur_trans->bits_per_word;
 959         } else {
 960                 *bpw = data->current_msg->spi->bits_per_word;
 961         }
 962         data->bpw_len = data->cur_trans->len / (*bpw / 8);
 963
 964         if (data->bpw_len > PCH_BUF_SIZE) {
 965                 data->bpw_len = PCH_BUF_SIZE;
 966                 data->cur_trans->len -= PCH_BUF_SIZE;
 967         }
 968
 969         /* copy Tx Data */
 970         if (data->cur_trans->tx_buf != NULL) {
 971                 if (*bpw == 8) {
 972                         tx_buf = data->cur_trans->tx_buf;
 973                         tx_dma_buf = dma->tx_buf_virt;
 974                         for (i = 0; i < data->bpw_len; i++)
 975                                 *tx_dma_buf++ = *tx_buf++;
 976                 } else {
 977                         tx_sbuf = data->cur_trans->tx_buf;
 978                         tx_dma_sbuf = dma->tx_buf_virt;
 979                         for (i = 0; i < data->bpw_len; i++)
 980                                 *tx_dma_sbuf++ = *tx_sbuf++;
 981                 }
 982         }
 983
 984         /* Calculate Rx parameter for DMA transmitting */
 985         if (data->bpw_len > PCH_DMA_TRANS_SIZE) {
 986                 if (data->bpw_len % PCH_DMA_TRANS_SIZE) {
 987                         num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
 988                         rem = data->bpw_len % PCH_DMA_TRANS_SIZE;
 989                 } else {
 990                         num = data->bpw_len / PCH_DMA_TRANS_SIZE;
 991                         rem = PCH_DMA_TRANS_SIZE;
 992                 }
 993                 size = PCH_DMA_TRANS_SIZE;
 994         } else {
 995                 num = 1;
 996                 size = data->bpw_len;
 997                 rem = data->bpw_len;
 998         }
 999         dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n",
1000                 __func__, num, size, rem);
1001         spin_lock_irqsave(&data->lock, flags);
1002
1003         /* set receive fifo threshold and transmit fifo threshold */
1004         pch_spi_setclr_reg(data->master, PCH_SPCR,
1005                            ((size - 1) << SPCR_RFIC_FIELD) |
1006                            (PCH_TX_THOLD << SPCR_TFIC_FIELD),
1007                            MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS);
1008
1009         spin_unlock_irqrestore(&data->lock, flags);
1010
1011         /* RX */
1012         dma->sg_rx_p = kcalloc(num, sizeof(*dma->sg_rx_p), GFP_ATOMIC);
1013         if (!dma->sg_rx_p)
1014                 return;
1015
1016         sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */
1017         /* offset, length setting */
1018         sg = dma->sg_rx_p;
1019         for (i = 0; i < num; i++, sg++) {
1020                 if (i == (num - 2)) {
1021                         sg->offset = size * i;
1022                         sg->offset = sg->offset * (*bpw / 8);
1023                         sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem,
1024                                     sg->offset);
1025                         sg_dma_len(sg) = rem;
1026                 } else if (i == (num - 1)) {
1027                         sg->offset = size * (i - 1) + rem;
1028                         sg->offset = sg->offset * (*bpw / 8);
1029                         sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1030                                     sg->offset);
1031                         sg_dma_len(sg) = size;
1032                 } else {
1033                         sg->offset = size * i;
1034                         sg->offset = sg->offset * (*bpw / 8);
1035                         sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1036                                     sg->offset);
1037                         sg_dma_len(sg) = size;
1038                 }
1039                 sg_dma_address(sg) = dma->rx_buf_dma + sg->offset;
1040         }
1041         sg = dma->sg_rx_p;
1042         desc_rx = dmaengine_prep_slave_sg(dma->chan_rx, sg,
1043                                         num, DMA_DEV_TO_MEM,
1044                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1045         if (!desc_rx) {
1046                 dev_err(&data->master->dev,
1047                         "%s:dmaengine_prep_slave_sg Failed\n", __func__);
1048                 return;
1049         }
1050         dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE);
1051         desc_rx->callback = pch_dma_rx_complete;
1052         desc_rx->callback_param = data;
1053         dma->nent = num;
1054         dma->desc_rx = desc_rx;
1055
1056         /* Calculate Tx parameter for DMA transmitting */
1057         if (data->bpw_len > PCH_MAX_FIFO_DEPTH) {
1058                 head = PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE;
1059                 if (data->bpw_len % PCH_DMA_TRANS_SIZE > 4) {
1060                         num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
1061                         rem = data->bpw_len % PCH_DMA_TRANS_SIZE - head;
1062                 } else {
1063                         num = data->bpw_len / PCH_DMA_TRANS_SIZE;
1064                         rem = data->bpw_len % PCH_DMA_TRANS_SIZE +
1065                               PCH_DMA_TRANS_SIZE - head;
1066                 }
1067                 size = PCH_DMA_TRANS_SIZE;
1068         } else {
1069                 num = 1;
1070                 size = data->bpw_len;
1071                 rem = data->bpw_len;
1072                 head = 0;
1073         }
1074
1075         dma->sg_tx_p = kcalloc(num, sizeof(*dma->sg_tx_p), GFP_ATOMIC);
1076         if (!dma->sg_tx_p)
1077                 return;
1078
1079         sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */
1080         /* offset, length setting */
1081         sg = dma->sg_tx_p;
1082         for (i = 0; i < num; i++, sg++) {
1083                 if (i == 0) {
1084                         sg->offset = 0;
1085                         sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size + head,
1086                                     sg->offset);
1087                         sg_dma_len(sg) = size + head;
1088                 } else if (i == (num - 1)) {
1089                         sg->offset = head + size * i;
1090                         sg->offset = sg->offset * (*bpw / 8);
1091                         sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem,
1092                                     sg->offset);
1093                         sg_dma_len(sg) = rem;
1094                 } else {
1095                         sg->offset = head + size * i;
1096                         sg->offset = sg->offset * (*bpw / 8);
1097                         sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size,
1098                                     sg->offset);
1099                         sg_dma_len(sg) = size;
1100                 }
1101                 sg_dma_address(sg) = dma->tx_buf_dma + sg->offset;
1102         }
1103         sg = dma->sg_tx_p;
1104         desc_tx = dmaengine_prep_slave_sg(dma->chan_tx,
1105                                         sg, num, DMA_MEM_TO_DEV,
1106                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1107         if (!desc_tx) {
1108                 dev_err(&data->master->dev,
1109                         "%s:dmaengine_prep_slave_sg Failed\n", __func__);
1110                 return;
1111         }
1112         dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE);
1113         desc_tx->callback = NULL;
1114         desc_tx->callback_param = data;
1115         dma->nent = num;
1116         dma->desc_tx = desc_tx;
1117
1118         dev_dbg(&data->master->dev, "%s:Pulling down SSN low - writing 0x2 to SSNXCR\n", __func__);
1119
1120         spin_lock_irqsave(&data->lock, flags);
1121         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
1122         desc_rx->tx_submit(desc_rx);
1123         desc_tx->tx_submit(desc_tx);
1124         spin_unlock_irqrestore(&data->lock, flags);
1125
1126         /* reset transfer complete flag */
1127         data->transfer_complete = false;
1128 }
1129
1130 static void pch_spi_process_messages(struct work_struct *pwork)
1131 {
1132         struct spi_message *pmsg, *tmp;
1133         struct pch_spi_data *data;
1134         int bpw;
1135
1136         data = container_of(pwork, struct pch_spi_data, work);
1137         dev_dbg(&data->master->dev, "%s data initialized\n", __func__);
1138
1139         spin_lock(&data->lock);
1140         /* check if suspend has been initiated;if yes flush queue */
1141         if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) {
1142                 dev_dbg(&data->master->dev,
1143                         "%s suspend/remove initiated, flushing queue\n", __func__);
1144                 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
1145                         pmsg->status = -EIO;
1146
1147                         if (pmsg->complete) {
1148                                 spin_unlock(&data->lock);
1149                                 pmsg->complete(pmsg->context);
1150                                 spin_lock(&data->lock);
1151                         }
1152
1153                         /* delete from queue */
1154                         list_del_init(&pmsg->queue);
1155                 }
1156
1157                 spin_unlock(&data->lock);
1158                 return;
1159         }
1160
1161         data->bcurrent_msg_processing = true;
1162         dev_dbg(&data->master->dev,
1163                 "%s Set data->bcurrent_msg_processing= true\n", __func__);
1164
1165         /* Get the message from the queue and delete it from there. */
1166         data->current_msg = list_entry(data->queue.next, struct spi_message,
1167                                         queue);
1168
1169         list_del_init(&data->current_msg->queue);
1170
1171         data->current_msg->status = 0;
1172
1173         pch_spi_select_chip(data, data->current_msg->spi);
1174
1175         spin_unlock(&data->lock);
1176
1177         if (data->use_dma)
1178                 pch_spi_request_dma(data,
1179                                     data->current_msg->spi->bits_per_word);
1180         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
1181         do {
1182                 int cnt;
1183                 /* If we are already processing a message get the next
1184                 transfer structure from the message otherwise retrieve
1185                 the 1st transfer request from the message. */
1186                 spin_lock(&data->lock);
1187                 if (data->cur_trans == NULL) {
1188                         data->cur_trans =
1189                                 list_entry(data->current_msg->transfers.next,
1190                                            struct spi_transfer, transfer_list);
1191                         dev_dbg(&data->master->dev,
1192                                 "%s :Getting 1st transfer message\n",
1193                                 __func__);
1194                 } else {
1195                         data->cur_trans =
1196                                 list_entry(data->cur_trans->transfer_list.next,
1197                                            struct spi_transfer, transfer_list);
1198                         dev_dbg(&data->master->dev,
1199                                 "%s :Getting next transfer message\n",
1200                                 __func__);
1201                 }
1202                 spin_unlock(&data->lock);
1203
1204                 if (!data->cur_trans->len)
1205                         goto out;
1206                 cnt = (data->cur_trans->len - 1) / PCH_BUF_SIZE + 1;
1207                 data->save_total_len = data->cur_trans->len;
1208                 if (data->use_dma) {
1209                         int i;
1210                         char *save_rx_buf = data->cur_trans->rx_buf;
1211                         for (i = 0; i < cnt; i ++) {
1212                                 pch_spi_handle_dma(data, &bpw);
1213                                 if (!pch_spi_start_transfer(data)) {
1214                                         data->transfer_complete = true;
1215                                         data->current_msg->status = -EIO;
1216                                         data->current_msg->complete
1217                                                    (data->current_msg->context);
1218                                         data->bcurrent_msg_processing = false;
1219                                         data->current_msg = NULL;
1220                                         data->cur_trans = NULL;
1221                                         goto out;
1222                                 }
1223                                 pch_spi_copy_rx_data_for_dma(data, bpw);
1224                         }
1225                         data->cur_trans->rx_buf = save_rx_buf;
1226                 } else {
1227                         pch_spi_set_tx(data, &bpw);
1228                         pch_spi_set_ir(data);
1229                         pch_spi_copy_rx_data(data, bpw);
1230                         kfree(data->pkt_rx_buff);
1231                         data->pkt_rx_buff = NULL;
1232                         kfree(data->pkt_tx_buff);
1233                         data->pkt_tx_buff = NULL;
1234                 }
1235                 /* increment message count */
1236                 data->cur_trans->len = data->save_total_len;
1237                 data->current_msg->actual_length += data->cur_trans->len;
1238
1239                 dev_dbg(&data->master->dev,
1240                         "%s:data->current_msg->actual_length=%d\n",
1241                         __func__, data->current_msg->actual_length);
1242
1243                 /* check for delay */
1244                 if (data->cur_trans->delay_usecs) {
1245                         dev_dbg(&data->master->dev, "%s:delay in usec=%d\n",
1246                                 __func__, data->cur_trans->delay_usecs);
1247                         udelay(data->cur_trans->delay_usecs);
1248                 }
1249
1250                 spin_lock(&data->lock);
1251
1252                 /* No more transfer in this message. */
1253                 if ((data->cur_trans->transfer_list.next) ==
1254                     &(data->current_msg->transfers)) {
1255                         pch_spi_nomore_transfer(data);
1256                 }
1257
1258                 spin_unlock(&data->lock);
1259
1260         } while (data->cur_trans != NULL);
1261
1262 out:
1263         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_HIGH);
1264         if (data->use_dma)
1265                 pch_spi_release_dma(data);
1266 }
1267
1268 static void pch_spi_free_resources(struct pch_spi_board_data *board_dat,
1269                                    struct pch_spi_data *data)
1270 {
1271         dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1272
1273         flush_work(&data->work);
1274 }
1275
1276 static int pch_spi_get_resources(struct pch_spi_board_data *board_dat,
1277                                  struct pch_spi_data *data)
1278 {
1279         dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1280
1281         /* reset PCH SPI h/w */
1282         pch_spi_reset(data->master);
1283         dev_dbg(&board_dat->pdev->dev,
1284                 "%s pch_spi_reset invoked successfully\n", __func__);
1285
1286         dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__);
1287
1288         return 0;
1289 }
1290
1291 static void pch_free_dma_buf(struct pch_spi_board_data *board_dat,
1292                              struct pch_spi_data *data)
1293 {
1294         struct pch_spi_dma_ctrl *dma;
1295
1296         dma = &data->dma;
1297         if (dma->tx_buf_dma)
1298                 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1299                                   dma->tx_buf_virt, dma->tx_buf_dma);
1300         if (dma->rx_buf_dma)
1301                 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1302                                   dma->rx_buf_virt, dma->rx_buf_dma);
1303 }
1304
1305 static int pch_alloc_dma_buf(struct pch_spi_board_data *board_dat,
1306                               struct pch_spi_data *data)
1307 {
1308         struct pch_spi_dma_ctrl *dma;
1309         int ret;
1310
1311         dma = &data->dma;
1312         ret = 0;
1313         /* Get Consistent memory for Tx DMA */
1314         dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1315                                 PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL);
1316         if (!dma->tx_buf_virt)
1317                 ret = -ENOMEM;
1318
1319         /* Get Consistent memory for Rx DMA */
1320         dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1321                                 PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL);
1322         if (!dma->rx_buf_virt)
1323                 ret = -ENOMEM;
1324
1325         return ret;
1326 }
1327
1328 static int pch_spi_pd_probe(struct platform_device *plat_dev)
1329 {
1330         int ret;
1331         struct spi_master *master;
1332         struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1333         struct pch_spi_data *data;
1334
1335         dev_dbg(&plat_dev->dev, "%s:debug\n", __func__);
1336
1337         master = spi_alloc_master(&board_dat->pdev->dev,
1338                                   sizeof(struct pch_spi_data));
1339         if (!master) {
1340                 dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n",
1341                         plat_dev->id);
1342                 return -ENOMEM;
1343         }
1344
1345         data = spi_master_get_devdata(master);
1346         data->master = master;
1347
1348         platform_set_drvdata(plat_dev, data);
1349
1350         /* baseaddress + address offset) */
1351         data->io_base_addr = pci_resource_start(board_dat->pdev, 1) +
1352                                          PCH_ADDRESS_SIZE * plat_dev->id;
1353         data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0);
1354         if (!data->io_remap_addr) {
1355                 dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__);
1356                 ret = -ENOMEM;
1357                 goto err_pci_iomap;
1358         }
1359         data->io_remap_addr += PCH_ADDRESS_SIZE * plat_dev->id;
1360
1361         dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n",
1362                 plat_dev->id, data->io_remap_addr);
1363
1364         /* initialize members of SPI master */
1365         master->num_chipselect = PCH_MAX_CS;
1366         master->transfer = pch_spi_transfer;
1367         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1368         master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
1369         master->max_speed_hz = PCH_MAX_BAUDRATE;
1370
1371         data->board_dat = board_dat;
1372         data->plat_dev = plat_dev;
1373         data->n_curnt_chip = 255;
1374         data->status = STATUS_RUNNING;
1375         data->ch = plat_dev->id;
1376         data->use_dma = use_dma;
1377
1378         INIT_LIST_HEAD(&data->queue);
1379         spin_lock_init(&data->lock);
1380         INIT_WORK(&data->work, pch_spi_process_messages);
1381         init_waitqueue_head(&data->wait);
1382
1383         ret = pch_spi_get_resources(board_dat, data);
1384         if (ret) {
1385                 dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret);
1386                 goto err_spi_get_resources;
1387         }
1388
1389         ret = request_irq(board_dat->pdev->irq, pch_spi_handler,
1390                           IRQF_SHARED, KBUILD_MODNAME, data);
1391         if (ret) {
1392                 dev_err(&plat_dev->dev,
1393                         "%s request_irq failed\n", __func__);
1394                 goto err_request_irq;
1395         }
1396         data->irq_reg_sts = true;
1397
1398         pch_spi_set_master_mode(master);
1399
1400         if (use_dma) {
1401                 dev_info(&plat_dev->dev, "Use DMA for data transfers\n");
1402                 ret = pch_alloc_dma_buf(board_dat, data);
1403                 if (ret)
1404                         goto err_spi_register_master;
1405         }
1406
1407         ret = spi_register_master(master);
1408         if (ret != 0) {
1409                 dev_err(&plat_dev->dev,
1410                         "%s spi_register_master FAILED\n", __func__);
1411                 goto err_spi_register_master;
1412         }
1413
1414         return 0;
1415
1416 err_spi_register_master:
1417         pch_free_dma_buf(board_dat, data);
1418         free_irq(board_dat->pdev->irq, data);
1419 err_request_irq:
1420         pch_spi_free_resources(board_dat, data);
1421 err_spi_get_resources:
1422         pci_iounmap(board_dat->pdev, data->io_remap_addr);
1423 err_pci_iomap:
1424         spi_master_put(master);
1425
1426         return ret;
1427 }
1428
1429 static int pch_spi_pd_remove(struct platform_device *plat_dev)
1430 {
1431         struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1432         struct pch_spi_data *data = platform_get_drvdata(plat_dev);
1433         int count;
1434         unsigned long flags;
1435
1436         dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n",
1437                 __func__, plat_dev->id, board_dat->pdev->irq);
1438
1439         if (use_dma)
1440                 pch_free_dma_buf(board_dat, data);
1441
1442         /* check for any pending messages; no action is taken if the queue
1443          * is still full; but at least we tried.  Unload anyway */
1444         count = 500;
1445         spin_lock_irqsave(&data->lock, flags);
1446         data->status = STATUS_EXITING;
1447         while ((list_empty(&data->queue) == 0) && --count) {
1448                 dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n",
1449                         __func__);
1450                 spin_unlock_irqrestore(&data->lock, flags);
1451                 msleep(PCH_SLEEP_TIME);
1452                 spin_lock_irqsave(&data->lock, flags);
1453         }
1454         spin_unlock_irqrestore(&data->lock, flags);
1455
1456         pch_spi_free_resources(board_dat, data);
1457         /* disable interrupts & free IRQ */
1458         if (data->irq_reg_sts) {
1459                 /* disable interrupts */
1460                 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1461                 data->irq_reg_sts = false;
1462                 free_irq(board_dat->pdev->irq, data);
1463         }
1464
1465         pci_iounmap(board_dat->pdev, data->io_remap_addr);
1466         spi_unregister_master(data->master);
1467
1468         return 0;
1469 }
1470 #ifdef CONFIG_PM
1471 static int pch_spi_pd_suspend(struct platform_device *pd_dev,
1472                               pm_message_t state)
1473 {
1474         u8 count;
1475         struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1476         struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1477
1478         dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__);
1479
1480         if (!board_dat) {
1481                 dev_err(&pd_dev->dev,
1482                         "%s pci_get_drvdata returned NULL\n", __func__);
1483                 return -EFAULT;
1484         }
1485
1486         /* check if the current message is processed:
1487            Only after thats done the transfer will be suspended */
1488         count = 255;
1489         while ((--count) > 0) {
1490                 if (!(data->bcurrent_msg_processing))
1491                         break;
1492                 msleep(PCH_SLEEP_TIME);
1493         }
1494
1495         /* Free IRQ */
1496         if (data->irq_reg_sts) {
1497                 /* disable all interrupts */
1498                 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1499                 pch_spi_reset(data->master);
1500                 free_irq(board_dat->pdev->irq, data);
1501
1502                 data->irq_reg_sts = false;
1503                 dev_dbg(&pd_dev->dev,
1504                         "%s free_irq invoked successfully.\n", __func__);
1505         }
1506
1507         return 0;
1508 }
1509
1510 static int pch_spi_pd_resume(struct platform_device *pd_dev)
1511 {
1512         struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1513         struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1514         int retval;
1515
1516         if (!board_dat) {
1517                 dev_err(&pd_dev->dev,
1518                         "%s pci_get_drvdata returned NULL\n", __func__);
1519                 return -EFAULT;
1520         }
1521
1522         if (!data->irq_reg_sts) {
1523                 /* register IRQ */
1524                 retval = request_irq(board_dat->pdev->irq, pch_spi_handler,
1525                                      IRQF_SHARED, KBUILD_MODNAME, data);
1526                 if (retval < 0) {
1527                         dev_err(&pd_dev->dev,
1528                                 "%s request_irq failed\n", __func__);
1529                         return retval;
1530                 }
1531
1532                 /* reset PCH SPI h/w */
1533                 pch_spi_reset(data->master);
1534                 pch_spi_set_master_mode(data->master);
1535                 data->irq_reg_sts = true;
1536         }
1537         return 0;
1538 }
1539 #else
1540 #define pch_spi_pd_suspend NULL
1541 #define pch_spi_pd_resume NULL
1542 #endif
1543
1544 static struct platform_driver pch_spi_pd_driver = {
1545         .driver = {
1546                 .name = "pch-spi",
1547         },
1548         .probe = pch_spi_pd_probe,
1549         .remove = pch_spi_pd_remove,
1550         .suspend = pch_spi_pd_suspend,
1551         .resume = pch_spi_pd_resume
1552 };
1553
1554 static int pch_spi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1555 {
1556         struct pch_spi_board_data *board_dat;
1557         struct platform_device *pd_dev = NULL;
1558         int retval;
1559         int i;
1560         struct pch_pd_dev_save *pd_dev_save;
1561
1562         pd_dev_save = kzalloc(sizeof(*pd_dev_save), GFP_KERNEL);
1563         if (!pd_dev_save)
1564                 return -ENOMEM;
1565
1566         board_dat = kzalloc(sizeof(*board_dat), GFP_KERNEL);
1567         if (!board_dat) {
1568                 retval = -ENOMEM;
1569                 goto err_no_mem;
1570         }
1571
1572         retval = pci_request_regions(pdev, KBUILD_MODNAME);
1573         if (retval) {
1574                 dev_err(&pdev->dev, "%s request_region failed\n", __func__);
1575                 goto pci_request_regions;
1576         }
1577
1578         board_dat->pdev = pdev;
1579         board_dat->num = id->driver_data;
1580         pd_dev_save->num = id->driver_data;
1581         pd_dev_save->board_dat = board_dat;
1582
1583         retval = pci_enable_device(pdev);
1584         if (retval) {
1585                 dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__);
1586                 goto pci_enable_device;
1587         }
1588
1589         for (i = 0; i < board_dat->num; i++) {
1590                 pd_dev = platform_device_alloc("pch-spi", i);
1591                 if (!pd_dev) {
1592                         dev_err(&pdev->dev, "platform_device_alloc failed\n");
1593                         retval = -ENOMEM;
1594                         goto err_platform_device;
1595                 }
1596                 pd_dev_save->pd_save[i] = pd_dev;
1597                 pd_dev->dev.parent = &pdev->dev;
1598
1599                 retval = platform_device_add_data(pd_dev, board_dat,
1600                                                   sizeof(*board_dat));
1601                 if (retval) {
1602                         dev_err(&pdev->dev,
1603                                 "platform_device_add_data failed\n");
1604                         platform_device_put(pd_dev);
1605                         goto err_platform_device;
1606                 }
1607
1608                 retval = platform_device_add(pd_dev);
1609                 if (retval) {
1610                         dev_err(&pdev->dev, "platform_device_add failed\n");
1611                         platform_device_put(pd_dev);
1612                         goto err_platform_device;
1613                 }
1614         }
1615
1616         pci_set_drvdata(pdev, pd_dev_save);
1617
1618         return 0;
1619
1620 err_platform_device:
1621         while (--i >= 0)
1622                 platform_device_unregister(pd_dev_save->pd_save[i]);
1623         pci_disable_device(pdev);
1624 pci_enable_device:
1625         pci_release_regions(pdev);
1626 pci_request_regions:
1627         kfree(board_dat);
1628 err_no_mem:
1629         kfree(pd_dev_save);
1630
1631         return retval;
1632 }
1633
1634 static void pch_spi_remove(struct pci_dev *pdev)
1635 {
1636         int i;
1637         struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1638
1639         dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev);
1640
1641         for (i = 0; i < pd_dev_save->num; i++)
1642                 platform_device_unregister(pd_dev_save->pd_save[i]);
1643
1644         pci_disable_device(pdev);
1645         pci_release_regions(pdev);
1646         kfree(pd_dev_save->board_dat);
1647         kfree(pd_dev_save);
1648 }
1649
1650 #ifdef CONFIG_PM
1651 static int pch_spi_suspend(struct pci_dev *pdev, pm_message_t state)
1652 {
1653         int retval;
1654         struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1655
1656         dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1657
1658         pd_dev_save->board_dat->suspend_sts = true;
1659
1660         /* save config space */
1661         retval = pci_save_state(pdev);
1662         if (retval == 0) {
1663                 pci_enable_wake(pdev, PCI_D3hot, 0);
1664                 pci_disable_device(pdev);
1665                 pci_set_power_state(pdev, PCI_D3hot);
1666         } else {
1667                 dev_err(&pdev->dev, "%s pci_save_state failed\n", __func__);
1668         }
1669
1670         return retval;
1671 }
1672
1673 static int pch_spi_resume(struct pci_dev *pdev)
1674 {
1675         int retval;
1676         struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1677         dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1678
1679         pci_set_power_state(pdev, PCI_D0);
1680         pci_restore_state(pdev);
1681
1682         retval = pci_enable_device(pdev);
1683         if (retval < 0) {
1684                 dev_err(&pdev->dev,
1685                         "%s pci_enable_device failed\n", __func__);
1686         } else {
1687                 pci_enable_wake(pdev, PCI_D3hot, 0);
1688
1689                 /* set suspend status to false */
1690                 pd_dev_save->board_dat->suspend_sts = false;
1691         }
1692
1693         return retval;
1694 }
1695 #else
1696 #define pch_spi_suspend NULL
1697 #define pch_spi_resume NULL
1698
1699 #endif
1700
1701 static struct pci_driver pch_spi_pcidev_driver = {
1702         .name = "pch_spi",
1703         .id_table = pch_spi_pcidev_id,
1704         .probe = pch_spi_probe,
1705         .remove = pch_spi_remove,
1706         .suspend = pch_spi_suspend,
1707         .resume = pch_spi_resume,
1708 };
1709
1710 static int __init pch_spi_init(void)
1711 {
1712         int ret;
1713         ret = platform_driver_register(&pch_spi_pd_driver);
1714         if (ret)
1715                 return ret;
1716
1717         ret = pci_register_driver(&pch_spi_pcidev_driver);
1718         if (ret) {
1719                 platform_driver_unregister(&pch_spi_pd_driver);
1720                 return ret;
1721         }
1722
1723         return 0;
1724 }
1725 module_init(pch_spi_init);
1726
1727 static void __exit pch_spi_exit(void)
1728 {
1729         pci_unregister_driver(&pch_spi_pcidev_driver);
1730         platform_driver_unregister(&pch_spi_pd_driver);
1731 }
1732 module_exit(pch_spi_exit);
1733
1734 module_param(use_dma, int, 0644);
1735 MODULE_PARM_DESC(use_dma,
1736                  "to use DMA for data transfers pass 1 else 0; default 1");
1737
1738 MODULE_LICENSE("GPL");
1739 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor ML7xxx IOH SPI Driver");
1740 MODULE_DEVICE_TABLE(pci, pch_spi_pcidev_id);
1741