GNU Linux-libre 5.10.219-gnu1
[releases.git] / drivers / spi / spi-ti-qspi.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * TI QSPI driver
4  *
5  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
6  * Author: Sourav Poddar <sourav.poddar@ti.com>
7  */
8
9 #include <linux/kernel.h>
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
12 #include <linux/module.h>
13 #include <linux/device.h>
14 #include <linux/delay.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/dmaengine.h>
17 #include <linux/omap-dma.h>
18 #include <linux/platform_device.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22 #include <linux/slab.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/of.h>
25 #include <linux/of_device.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/regmap.h>
29 #include <linux/sizes.h>
30
31 #include <linux/spi/spi.h>
32 #include <linux/spi/spi-mem.h>
33
34 struct ti_qspi_regs {
35         u32 clkctrl;
36 };
37
38 struct ti_qspi {
39         struct completion       transfer_complete;
40
41         /* list synchronization */
42         struct mutex            list_lock;
43
44         struct spi_master       *master;
45         void __iomem            *base;
46         void __iomem            *mmap_base;
47         size_t                  mmap_size;
48         struct regmap           *ctrl_base;
49         unsigned int            ctrl_reg;
50         struct clk              *fclk;
51         struct device           *dev;
52
53         struct ti_qspi_regs     ctx_reg;
54
55         dma_addr_t              mmap_phys_base;
56         dma_addr_t              rx_bb_dma_addr;
57         void                    *rx_bb_addr;
58         struct dma_chan         *rx_chan;
59
60         u32 spi_max_frequency;
61         u32 cmd;
62         u32 dc;
63
64         bool mmap_enabled;
65         int current_cs;
66 };
67
68 #define QSPI_PID                        (0x0)
69 #define QSPI_SYSCONFIG                  (0x10)
70 #define QSPI_SPI_CLOCK_CNTRL_REG        (0x40)
71 #define QSPI_SPI_DC_REG                 (0x44)
72 #define QSPI_SPI_CMD_REG                (0x48)
73 #define QSPI_SPI_STATUS_REG             (0x4c)
74 #define QSPI_SPI_DATA_REG               (0x50)
75 #define QSPI_SPI_SETUP_REG(n)           ((0x54 + 4 * n))
76 #define QSPI_SPI_SWITCH_REG             (0x64)
77 #define QSPI_SPI_DATA_REG_1             (0x68)
78 #define QSPI_SPI_DATA_REG_2             (0x6c)
79 #define QSPI_SPI_DATA_REG_3             (0x70)
80
81 #define QSPI_COMPLETION_TIMEOUT         msecs_to_jiffies(2000)
82
83 /* Clock Control */
84 #define QSPI_CLK_EN                     (1 << 31)
85 #define QSPI_CLK_DIV_MAX                0xffff
86
87 /* Command */
88 #define QSPI_EN_CS(n)                   (n << 28)
89 #define QSPI_WLEN(n)                    ((n - 1) << 19)
90 #define QSPI_3_PIN                      (1 << 18)
91 #define QSPI_RD_SNGL                    (1 << 16)
92 #define QSPI_WR_SNGL                    (2 << 16)
93 #define QSPI_RD_DUAL                    (3 << 16)
94 #define QSPI_RD_QUAD                    (7 << 16)
95 #define QSPI_INVAL                      (4 << 16)
96 #define QSPI_FLEN(n)                    ((n - 1) << 0)
97 #define QSPI_WLEN_MAX_BITS              128
98 #define QSPI_WLEN_MAX_BYTES             16
99 #define QSPI_WLEN_MASK                  QSPI_WLEN(QSPI_WLEN_MAX_BITS)
100
101 /* STATUS REGISTER */
102 #define BUSY                            0x01
103 #define WC                              0x02
104
105 /* Device Control */
106 #define QSPI_DD(m, n)                   (m << (3 + n * 8))
107 #define QSPI_CKPHA(n)                   (1 << (2 + n * 8))
108 #define QSPI_CSPOL(n)                   (1 << (1 + n * 8))
109 #define QSPI_CKPOL(n)                   (1 << (n * 8))
110
111 #define QSPI_FRAME                      4096
112
113 #define QSPI_AUTOSUSPEND_TIMEOUT         2000
114
115 #define MEM_CS_EN(n)                    ((n + 1) << 8)
116 #define MEM_CS_MASK                     (7 << 8)
117
118 #define MM_SWITCH                       0x1
119
120 #define QSPI_SETUP_RD_NORMAL            (0x0 << 12)
121 #define QSPI_SETUP_RD_DUAL              (0x1 << 12)
122 #define QSPI_SETUP_RD_QUAD              (0x3 << 12)
123 #define QSPI_SETUP_ADDR_SHIFT           8
124 #define QSPI_SETUP_DUMMY_SHIFT          10
125
126 #define QSPI_DMA_BUFFER_SIZE            SZ_64K
127
128 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
129                 unsigned long reg)
130 {
131         return readl(qspi->base + reg);
132 }
133
134 static inline void ti_qspi_write(struct ti_qspi *qspi,
135                 unsigned long val, unsigned long reg)
136 {
137         writel(val, qspi->base + reg);
138 }
139
140 static int ti_qspi_setup(struct spi_device *spi)
141 {
142         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
143         struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
144         int clk_div = 0, ret;
145         u32 clk_ctrl_reg, clk_rate, clk_mask;
146
147         if (spi->master->busy) {
148                 dev_dbg(qspi->dev, "master busy doing other transfers\n");
149                 return -EBUSY;
150         }
151
152         if (!qspi->spi_max_frequency) {
153                 dev_err(qspi->dev, "spi max frequency not defined\n");
154                 return -EINVAL;
155         }
156
157         clk_rate = clk_get_rate(qspi->fclk);
158
159         clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
160
161         if (clk_div < 0) {
162                 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
163                 return -EINVAL;
164         }
165
166         if (clk_div > QSPI_CLK_DIV_MAX) {
167                 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
168                                 QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
169                 return -EINVAL;
170         }
171
172         dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
173                         qspi->spi_max_frequency, clk_div);
174
175         ret = pm_runtime_get_sync(qspi->dev);
176         if (ret < 0) {
177                 pm_runtime_put_noidle(qspi->dev);
178                 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
179                 return ret;
180         }
181
182         clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
183
184         clk_ctrl_reg &= ~QSPI_CLK_EN;
185
186         /* disable SCLK */
187         ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
188
189         /* enable SCLK */
190         clk_mask = QSPI_CLK_EN | clk_div;
191         ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
192         ctx_reg->clkctrl = clk_mask;
193
194         pm_runtime_mark_last_busy(qspi->dev);
195         ret = pm_runtime_put_autosuspend(qspi->dev);
196         if (ret < 0) {
197                 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
198                 return ret;
199         }
200
201         return 0;
202 }
203
204 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
205 {
206         struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
207
208         ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
209 }
210
211 static inline u32 qspi_is_busy(struct ti_qspi *qspi)
212 {
213         u32 stat;
214         unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
215
216         stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
217         while ((stat & BUSY) && time_after(timeout, jiffies)) {
218                 cpu_relax();
219                 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
220         }
221
222         WARN(stat & BUSY, "qspi busy\n");
223         return stat & BUSY;
224 }
225
226 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
227 {
228         u32 stat;
229         unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
230
231         do {
232                 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
233                 if (stat & WC)
234                         return 0;
235                 cpu_relax();
236         } while (time_after(timeout, jiffies));
237
238         stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
239         if (stat & WC)
240                 return 0;
241         return  -ETIMEDOUT;
242 }
243
244 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t,
245                           int count)
246 {
247         int wlen, xfer_len;
248         unsigned int cmd;
249         const u8 *txbuf;
250         u32 data;
251
252         txbuf = t->tx_buf;
253         cmd = qspi->cmd | QSPI_WR_SNGL;
254         wlen = t->bits_per_word >> 3;   /* in bytes */
255         xfer_len = wlen;
256
257         while (count) {
258                 if (qspi_is_busy(qspi))
259                         return -EBUSY;
260
261                 switch (wlen) {
262                 case 1:
263                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
264                                         cmd, qspi->dc, *txbuf);
265                         if (count >= QSPI_WLEN_MAX_BYTES) {
266                                 u32 *txp = (u32 *)txbuf;
267
268                                 data = cpu_to_be32(*txp++);
269                                 writel(data, qspi->base +
270                                        QSPI_SPI_DATA_REG_3);
271                                 data = cpu_to_be32(*txp++);
272                                 writel(data, qspi->base +
273                                        QSPI_SPI_DATA_REG_2);
274                                 data = cpu_to_be32(*txp++);
275                                 writel(data, qspi->base +
276                                        QSPI_SPI_DATA_REG_1);
277                                 data = cpu_to_be32(*txp++);
278                                 writel(data, qspi->base +
279                                        QSPI_SPI_DATA_REG);
280                                 xfer_len = QSPI_WLEN_MAX_BYTES;
281                                 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
282                         } else {
283                                 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
284                                 cmd = qspi->cmd | QSPI_WR_SNGL;
285                                 xfer_len = wlen;
286                                 cmd |= QSPI_WLEN(wlen);
287                         }
288                         break;
289                 case 2:
290                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
291                                         cmd, qspi->dc, *txbuf);
292                         writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
293                         break;
294                 case 4:
295                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
296                                         cmd, qspi->dc, *txbuf);
297                         writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
298                         break;
299                 }
300
301                 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
302                 if (ti_qspi_poll_wc(qspi)) {
303                         dev_err(qspi->dev, "write timed out\n");
304                         return -ETIMEDOUT;
305                 }
306                 txbuf += xfer_len;
307                 count -= xfer_len;
308         }
309
310         return 0;
311 }
312
313 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t,
314                          int count)
315 {
316         int wlen;
317         unsigned int cmd;
318         u32 rx;
319         u8 rxlen, rx_wlen;
320         u8 *rxbuf;
321
322         rxbuf = t->rx_buf;
323         cmd = qspi->cmd;
324         switch (t->rx_nbits) {
325         case SPI_NBITS_DUAL:
326                 cmd |= QSPI_RD_DUAL;
327                 break;
328         case SPI_NBITS_QUAD:
329                 cmd |= QSPI_RD_QUAD;
330                 break;
331         default:
332                 cmd |= QSPI_RD_SNGL;
333                 break;
334         }
335         wlen = t->bits_per_word >> 3;   /* in bytes */
336         rx_wlen = wlen;
337
338         while (count) {
339                 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
340                 if (qspi_is_busy(qspi))
341                         return -EBUSY;
342
343                 switch (wlen) {
344                 case 1:
345                         /*
346                          * Optimize the 8-bit words transfers, as used by
347                          * the SPI flash devices.
348                          */
349                         if (count >= QSPI_WLEN_MAX_BYTES) {
350                                 rxlen = QSPI_WLEN_MAX_BYTES;
351                         } else {
352                                 rxlen = min(count, 4);
353                         }
354                         rx_wlen = rxlen << 3;
355                         cmd &= ~QSPI_WLEN_MASK;
356                         cmd |= QSPI_WLEN(rx_wlen);
357                         break;
358                 default:
359                         rxlen = wlen;
360                         break;
361                 }
362
363                 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
364                 if (ti_qspi_poll_wc(qspi)) {
365                         dev_err(qspi->dev, "read timed out\n");
366                         return -ETIMEDOUT;
367                 }
368
369                 switch (wlen) {
370                 case 1:
371                         /*
372                          * Optimize the 8-bit words transfers, as used by
373                          * the SPI flash devices.
374                          */
375                         if (count >= QSPI_WLEN_MAX_BYTES) {
376                                 u32 *rxp = (u32 *) rxbuf;
377                                 rx = readl(qspi->base + QSPI_SPI_DATA_REG_3);
378                                 *rxp++ = be32_to_cpu(rx);
379                                 rx = readl(qspi->base + QSPI_SPI_DATA_REG_2);
380                                 *rxp++ = be32_to_cpu(rx);
381                                 rx = readl(qspi->base + QSPI_SPI_DATA_REG_1);
382                                 *rxp++ = be32_to_cpu(rx);
383                                 rx = readl(qspi->base + QSPI_SPI_DATA_REG);
384                                 *rxp++ = be32_to_cpu(rx);
385                         } else {
386                                 u8 *rxp = rxbuf;
387                                 rx = readl(qspi->base + QSPI_SPI_DATA_REG);
388                                 if (rx_wlen >= 8)
389                                         *rxp++ = rx >> (rx_wlen - 8);
390                                 if (rx_wlen >= 16)
391                                         *rxp++ = rx >> (rx_wlen - 16);
392                                 if (rx_wlen >= 24)
393                                         *rxp++ = rx >> (rx_wlen - 24);
394                                 if (rx_wlen >= 32)
395                                         *rxp++ = rx;
396                         }
397                         break;
398                 case 2:
399                         *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
400                         break;
401                 case 4:
402                         *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
403                         break;
404                 }
405                 rxbuf += rxlen;
406                 count -= rxlen;
407         }
408
409         return 0;
410 }
411
412 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
413                              int count)
414 {
415         int ret;
416
417         if (t->tx_buf) {
418                 ret = qspi_write_msg(qspi, t, count);
419                 if (ret) {
420                         dev_dbg(qspi->dev, "Error while writing\n");
421                         return ret;
422                 }
423         }
424
425         if (t->rx_buf) {
426                 ret = qspi_read_msg(qspi, t, count);
427                 if (ret) {
428                         dev_dbg(qspi->dev, "Error while reading\n");
429                         return ret;
430                 }
431         }
432
433         return 0;
434 }
435
436 static void ti_qspi_dma_callback(void *param)
437 {
438         struct ti_qspi *qspi = param;
439
440         complete(&qspi->transfer_complete);
441 }
442
443 static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst,
444                             dma_addr_t dma_src, size_t len)
445 {
446         struct dma_chan *chan = qspi->rx_chan;
447         dma_cookie_t cookie;
448         enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
449         struct dma_async_tx_descriptor *tx;
450         int ret;
451         unsigned long time_left;
452
453         tx = dmaengine_prep_dma_memcpy(chan, dma_dst, dma_src, len, flags);
454         if (!tx) {
455                 dev_err(qspi->dev, "device_prep_dma_memcpy error\n");
456                 return -EIO;
457         }
458
459         tx->callback = ti_qspi_dma_callback;
460         tx->callback_param = qspi;
461         cookie = tx->tx_submit(tx);
462         reinit_completion(&qspi->transfer_complete);
463
464         ret = dma_submit_error(cookie);
465         if (ret) {
466                 dev_err(qspi->dev, "dma_submit_error %d\n", cookie);
467                 return -EIO;
468         }
469
470         dma_async_issue_pending(chan);
471         time_left = wait_for_completion_timeout(&qspi->transfer_complete,
472                                           msecs_to_jiffies(len));
473         if (time_left == 0) {
474                 dmaengine_terminate_sync(chan);
475                 dev_err(qspi->dev, "DMA wait_for_completion_timeout\n");
476                 return -ETIMEDOUT;
477         }
478
479         return 0;
480 }
481
482 static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi, loff_t offs,
483                                      void *to, size_t readsize)
484 {
485         dma_addr_t dma_src = qspi->mmap_phys_base + offs;
486         int ret = 0;
487
488         /*
489          * Use bounce buffer as FS like jffs2, ubifs may pass
490          * buffers that does not belong to kernel lowmem region.
491          */
492         while (readsize != 0) {
493                 size_t xfer_len = min_t(size_t, QSPI_DMA_BUFFER_SIZE,
494                                         readsize);
495
496                 ret = ti_qspi_dma_xfer(qspi, qspi->rx_bb_dma_addr,
497                                        dma_src, xfer_len);
498                 if (ret != 0)
499                         return ret;
500                 memcpy(to, qspi->rx_bb_addr, xfer_len);
501                 readsize -= xfer_len;
502                 dma_src += xfer_len;
503                 to += xfer_len;
504         }
505
506         return ret;
507 }
508
509 static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg,
510                                loff_t from)
511 {
512         struct scatterlist *sg;
513         dma_addr_t dma_src = qspi->mmap_phys_base + from;
514         dma_addr_t dma_dst;
515         int i, len, ret;
516
517         for_each_sg(rx_sg.sgl, sg, rx_sg.nents, i) {
518                 dma_dst = sg_dma_address(sg);
519                 len = sg_dma_len(sg);
520                 ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len);
521                 if (ret)
522                         return ret;
523                 dma_src += len;
524         }
525
526         return 0;
527 }
528
529 static void ti_qspi_enable_memory_map(struct spi_device *spi)
530 {
531         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
532
533         ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
534         if (qspi->ctrl_base) {
535                 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
536                                    MEM_CS_MASK,
537                                    MEM_CS_EN(spi->chip_select));
538         }
539         qspi->mmap_enabled = true;
540         qspi->current_cs = spi->chip_select;
541 }
542
543 static void ti_qspi_disable_memory_map(struct spi_device *spi)
544 {
545         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
546
547         ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
548         if (qspi->ctrl_base)
549                 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
550                                    MEM_CS_MASK, 0);
551         qspi->mmap_enabled = false;
552         qspi->current_cs = -1;
553 }
554
555 static void ti_qspi_setup_mmap_read(struct spi_device *spi, u8 opcode,
556                                     u8 data_nbits, u8 addr_width,
557                                     u8 dummy_bytes)
558 {
559         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
560         u32 memval = opcode;
561
562         switch (data_nbits) {
563         case SPI_NBITS_QUAD:
564                 memval |= QSPI_SETUP_RD_QUAD;
565                 break;
566         case SPI_NBITS_DUAL:
567                 memval |= QSPI_SETUP_RD_DUAL;
568                 break;
569         default:
570                 memval |= QSPI_SETUP_RD_NORMAL;
571                 break;
572         }
573         memval |= ((addr_width - 1) << QSPI_SETUP_ADDR_SHIFT |
574                    dummy_bytes << QSPI_SETUP_DUMMY_SHIFT);
575         ti_qspi_write(qspi, memval,
576                       QSPI_SPI_SETUP_REG(spi->chip_select));
577 }
578
579 static int ti_qspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
580 {
581         struct ti_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
582         size_t max_len;
583
584         if (op->data.dir == SPI_MEM_DATA_IN) {
585                 if (op->addr.val < qspi->mmap_size) {
586                         /* Limit MMIO to the mmaped region */
587                         if (op->addr.val + op->data.nbytes > qspi->mmap_size) {
588                                 max_len = qspi->mmap_size - op->addr.val;
589                                 op->data.nbytes = min((size_t) op->data.nbytes,
590                                                       max_len);
591                         }
592                 } else {
593                         /*
594                          * Use fallback mode (SW generated transfers) above the
595                          * mmaped region.
596                          * Adjust size to comply with the QSPI max frame length.
597                          */
598                         max_len = QSPI_FRAME;
599                         max_len -= 1 + op->addr.nbytes + op->dummy.nbytes;
600                         op->data.nbytes = min((size_t) op->data.nbytes,
601                                               max_len);
602                 }
603         }
604
605         return 0;
606 }
607
608 static int ti_qspi_exec_mem_op(struct spi_mem *mem,
609                                const struct spi_mem_op *op)
610 {
611         struct ti_qspi *qspi = spi_master_get_devdata(mem->spi->master);
612         u32 from = 0;
613         int ret = 0;
614
615         /* Only optimize read path. */
616         if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
617             !op->addr.nbytes || op->addr.nbytes > 4)
618                 return -ENOTSUPP;
619
620         /* Address exceeds MMIO window size, fall back to regular mode. */
621         from = op->addr.val;
622         if (from + op->data.nbytes > qspi->mmap_size)
623                 return -ENOTSUPP;
624
625         mutex_lock(&qspi->list_lock);
626
627         if (!qspi->mmap_enabled || qspi->current_cs != mem->spi->chip_select)
628                 ti_qspi_enable_memory_map(mem->spi);
629         ti_qspi_setup_mmap_read(mem->spi, op->cmd.opcode, op->data.buswidth,
630                                 op->addr.nbytes, op->dummy.nbytes);
631
632         if (qspi->rx_chan) {
633                 struct sg_table sgt;
634
635                 if (virt_addr_valid(op->data.buf.in) &&
636                     !spi_controller_dma_map_mem_op_data(mem->spi->master, op,
637                                                         &sgt)) {
638                         ret = ti_qspi_dma_xfer_sg(qspi, sgt, from);
639                         spi_controller_dma_unmap_mem_op_data(mem->spi->master,
640                                                              op, &sgt);
641                 } else {
642                         ret = ti_qspi_dma_bounce_buffer(qspi, from,
643                                                         op->data.buf.in,
644                                                         op->data.nbytes);
645                 }
646         } else {
647                 memcpy_fromio(op->data.buf.in, qspi->mmap_base + from,
648                               op->data.nbytes);
649         }
650
651         mutex_unlock(&qspi->list_lock);
652
653         return ret;
654 }
655
656 static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
657         .exec_op = ti_qspi_exec_mem_op,
658         .adjust_op_size = ti_qspi_adjust_op_size,
659 };
660
661 static int ti_qspi_start_transfer_one(struct spi_master *master,
662                 struct spi_message *m)
663 {
664         struct ti_qspi *qspi = spi_master_get_devdata(master);
665         struct spi_device *spi = m->spi;
666         struct spi_transfer *t;
667         int status = 0, ret;
668         unsigned int frame_len_words, transfer_len_words;
669         int wlen;
670
671         /* setup device control reg */
672         qspi->dc = 0;
673
674         if (spi->mode & SPI_CPHA)
675                 qspi->dc |= QSPI_CKPHA(spi->chip_select);
676         if (spi->mode & SPI_CPOL)
677                 qspi->dc |= QSPI_CKPOL(spi->chip_select);
678         if (spi->mode & SPI_CS_HIGH)
679                 qspi->dc |= QSPI_CSPOL(spi->chip_select);
680
681         frame_len_words = 0;
682         list_for_each_entry(t, &m->transfers, transfer_list)
683                 frame_len_words += t->len / (t->bits_per_word >> 3);
684         frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME);
685
686         /* setup command reg */
687         qspi->cmd = 0;
688         qspi->cmd |= QSPI_EN_CS(spi->chip_select);
689         qspi->cmd |= QSPI_FLEN(frame_len_words);
690
691         ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
692
693         mutex_lock(&qspi->list_lock);
694
695         if (qspi->mmap_enabled)
696                 ti_qspi_disable_memory_map(spi);
697
698         list_for_each_entry(t, &m->transfers, transfer_list) {
699                 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
700                              QSPI_WLEN(t->bits_per_word));
701
702                 wlen = t->bits_per_word >> 3;
703                 transfer_len_words = min(t->len / wlen, frame_len_words);
704
705                 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
706                 if (ret) {
707                         dev_dbg(qspi->dev, "transfer message failed\n");
708                         mutex_unlock(&qspi->list_lock);
709                         return -EINVAL;
710                 }
711
712                 m->actual_length += transfer_len_words * wlen;
713                 frame_len_words -= transfer_len_words;
714                 if (frame_len_words == 0)
715                         break;
716         }
717
718         mutex_unlock(&qspi->list_lock);
719
720         ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
721         m->status = status;
722         spi_finalize_current_message(master);
723
724         return status;
725 }
726
727 static int ti_qspi_runtime_resume(struct device *dev)
728 {
729         struct ti_qspi      *qspi;
730
731         qspi = dev_get_drvdata(dev);
732         ti_qspi_restore_ctx(qspi);
733
734         return 0;
735 }
736
737 static void ti_qspi_dma_cleanup(struct ti_qspi *qspi)
738 {
739         if (qspi->rx_bb_addr)
740                 dma_free_coherent(qspi->dev, QSPI_DMA_BUFFER_SIZE,
741                                   qspi->rx_bb_addr,
742                                   qspi->rx_bb_dma_addr);
743
744         if (qspi->rx_chan)
745                 dma_release_channel(qspi->rx_chan);
746 }
747
748 static const struct of_device_id ti_qspi_match[] = {
749         {.compatible = "ti,dra7xxx-qspi" },
750         {.compatible = "ti,am4372-qspi" },
751         {},
752 };
753 MODULE_DEVICE_TABLE(of, ti_qspi_match);
754
755 static int ti_qspi_probe(struct platform_device *pdev)
756 {
757         struct  ti_qspi *qspi;
758         struct spi_master *master;
759         struct resource         *r, *res_mmap;
760         struct device_node *np = pdev->dev.of_node;
761         u32 max_freq;
762         int ret = 0, num_cs, irq;
763         dma_cap_mask_t mask;
764
765         master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
766         if (!master)
767                 return -ENOMEM;
768
769         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
770
771         master->flags = SPI_MASTER_HALF_DUPLEX;
772         master->setup = ti_qspi_setup;
773         master->auto_runtime_pm = true;
774         master->transfer_one_message = ti_qspi_start_transfer_one;
775         master->dev.of_node = pdev->dev.of_node;
776         master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
777                                      SPI_BPW_MASK(8);
778         master->mem_ops = &ti_qspi_mem_ops;
779
780         if (!of_property_read_u32(np, "num-cs", &num_cs))
781                 master->num_chipselect = num_cs;
782
783         qspi = spi_master_get_devdata(master);
784         qspi->master = master;
785         qspi->dev = &pdev->dev;
786         platform_set_drvdata(pdev, qspi);
787
788         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
789         if (r == NULL) {
790                 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
791                 if (r == NULL) {
792                         dev_err(&pdev->dev, "missing platform data\n");
793                         ret = -ENODEV;
794                         goto free_master;
795                 }
796         }
797
798         res_mmap = platform_get_resource_byname(pdev,
799                         IORESOURCE_MEM, "qspi_mmap");
800         if (res_mmap == NULL) {
801                 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
802                 if (res_mmap == NULL) {
803                         dev_err(&pdev->dev,
804                                 "memory mapped resource not required\n");
805                 }
806         }
807
808         if (res_mmap)
809                 qspi->mmap_size = resource_size(res_mmap);
810
811         irq = platform_get_irq(pdev, 0);
812         if (irq < 0) {
813                 ret = irq;
814                 goto free_master;
815         }
816
817         mutex_init(&qspi->list_lock);
818
819         qspi->base = devm_ioremap_resource(&pdev->dev, r);
820         if (IS_ERR(qspi->base)) {
821                 ret = PTR_ERR(qspi->base);
822                 goto free_master;
823         }
824
825
826         if (of_property_read_bool(np, "syscon-chipselects")) {
827                 qspi->ctrl_base =
828                 syscon_regmap_lookup_by_phandle(np,
829                                                 "syscon-chipselects");
830                 if (IS_ERR(qspi->ctrl_base)) {
831                         ret = PTR_ERR(qspi->ctrl_base);
832                         goto free_master;
833                 }
834                 ret = of_property_read_u32_index(np,
835                                                  "syscon-chipselects",
836                                                  1, &qspi->ctrl_reg);
837                 if (ret) {
838                         dev_err(&pdev->dev,
839                                 "couldn't get ctrl_mod reg index\n");
840                         goto free_master;
841                 }
842         }
843
844         qspi->fclk = devm_clk_get(&pdev->dev, "fck");
845         if (IS_ERR(qspi->fclk)) {
846                 ret = PTR_ERR(qspi->fclk);
847                 dev_err(&pdev->dev, "could not get clk: %d\n", ret);
848         }
849
850         pm_runtime_use_autosuspend(&pdev->dev);
851         pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
852         pm_runtime_enable(&pdev->dev);
853
854         if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
855                 qspi->spi_max_frequency = max_freq;
856
857         dma_cap_zero(mask);
858         dma_cap_set(DMA_MEMCPY, mask);
859
860         qspi->rx_chan = dma_request_chan_by_mask(&mask);
861         if (IS_ERR(qspi->rx_chan)) {
862                 dev_err(qspi->dev,
863                         "No Rx DMA available, trying mmap mode\n");
864                 qspi->rx_chan = NULL;
865                 ret = 0;
866                 goto no_dma;
867         }
868         qspi->rx_bb_addr = dma_alloc_coherent(qspi->dev,
869                                               QSPI_DMA_BUFFER_SIZE,
870                                               &qspi->rx_bb_dma_addr,
871                                               GFP_KERNEL | GFP_DMA);
872         if (!qspi->rx_bb_addr) {
873                 dev_err(qspi->dev,
874                         "dma_alloc_coherent failed, using PIO mode\n");
875                 dma_release_channel(qspi->rx_chan);
876                 goto no_dma;
877         }
878         master->dma_rx = qspi->rx_chan;
879         init_completion(&qspi->transfer_complete);
880         if (res_mmap)
881                 qspi->mmap_phys_base = (dma_addr_t)res_mmap->start;
882
883 no_dma:
884         if (!qspi->rx_chan && res_mmap) {
885                 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
886                 if (IS_ERR(qspi->mmap_base)) {
887                         dev_info(&pdev->dev,
888                                  "mmap failed with error %ld using PIO mode\n",
889                                  PTR_ERR(qspi->mmap_base));
890                         qspi->mmap_base = NULL;
891                         master->mem_ops = NULL;
892                 }
893         }
894         qspi->mmap_enabled = false;
895         qspi->current_cs = -1;
896
897         ret = devm_spi_register_master(&pdev->dev, master);
898         if (!ret)
899                 return 0;
900
901         ti_qspi_dma_cleanup(qspi);
902
903         pm_runtime_disable(&pdev->dev);
904 free_master:
905         spi_master_put(master);
906         return ret;
907 }
908
909 static int ti_qspi_remove(struct platform_device *pdev)
910 {
911         struct ti_qspi *qspi = platform_get_drvdata(pdev);
912         int rc;
913
914         rc = spi_master_suspend(qspi->master);
915         if (rc)
916                 return rc;
917
918         pm_runtime_put_sync(&pdev->dev);
919         pm_runtime_disable(&pdev->dev);
920
921         ti_qspi_dma_cleanup(qspi);
922
923         return 0;
924 }
925
926 static const struct dev_pm_ops ti_qspi_pm_ops = {
927         .runtime_resume = ti_qspi_runtime_resume,
928 };
929
930 static struct platform_driver ti_qspi_driver = {
931         .probe  = ti_qspi_probe,
932         .remove = ti_qspi_remove,
933         .driver = {
934                 .name   = "ti-qspi",
935                 .pm =   &ti_qspi_pm_ops,
936                 .of_match_table = ti_qspi_match,
937         }
938 };
939
940 module_platform_driver(ti_qspi_driver);
941
942 MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
943 MODULE_LICENSE("GPL v2");
944 MODULE_DESCRIPTION("TI QSPI controller driver");
945 MODULE_ALIAS("platform:ti-qspi");