drivers/spi/spi-ti-qspi.c

   1 /*
   2  * TI QSPI driver
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  * Author: Sourav Poddar <sourav.poddar@ti.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GPLv2.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/device.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/dmaengine.h>
  24 #include <linux/omap-dma.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/err.h>
  27 #include <linux/clk.h>
  28 #include <linux/io.h>
  29 #include <linux/slab.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/of.h>
  32 #include <linux/of_device.h>
  33 #include <linux/pinctrl/consumer.h>
  34 #include <linux/mfd/syscon.h>
  35 #include <linux/regmap.h>
  36 #include <linux/sizes.h>
  37
  38 #include <linux/spi/spi.h>
  39
  40 struct ti_qspi_regs {
  41         u32 clkctrl;
  42 };
  43
  44 struct ti_qspi {
  45         struct completion       transfer_complete;
  46
  47         /* list synchronization */
  48         struct mutex            list_lock;
  49
  50         struct spi_master       *master;
  51         void __iomem            *base;
  52         void __iomem            *mmap_base;
  53         struct regmap           *ctrl_base;
  54         unsigned int            ctrl_reg;
  55         struct clk              *fclk;
  56         struct device           *dev;
  57
  58         struct ti_qspi_regs     ctx_reg;
  59
  60         dma_addr_t              mmap_phys_base;
  61         dma_addr_t              rx_bb_dma_addr;
  62         void                    *rx_bb_addr;
  63         struct dma_chan         *rx_chan;
  64
  65         u32 spi_max_frequency;
  66         u32 cmd;
  67         u32 dc;
  68
  69         bool mmap_enabled;
  70 };
  71
  72 #define QSPI_PID                        (0x0)
  73 #define QSPI_SYSCONFIG                  (0x10)
  74 #define QSPI_SPI_CLOCK_CNTRL_REG        (0x40)
  75 #define QSPI_SPI_DC_REG                 (0x44)
  76 #define QSPI_SPI_CMD_REG                (0x48)
  77 #define QSPI_SPI_STATUS_REG             (0x4c)
  78 #define QSPI_SPI_DATA_REG               (0x50)
  79 #define QSPI_SPI_SETUP_REG(n)           ((0x54 + 4 * n))
  80 #define QSPI_SPI_SWITCH_REG             (0x64)
  81 #define QSPI_SPI_DATA_REG_1             (0x68)
  82 #define QSPI_SPI_DATA_REG_2             (0x6c)
  83 #define QSPI_SPI_DATA_REG_3             (0x70)
  84
  85 #define QSPI_COMPLETION_TIMEOUT         msecs_to_jiffies(2000)
  86
  87 #define QSPI_FCLK                       192000000
  88
  89 /* Clock Control */
  90 #define QSPI_CLK_EN                     (1 << 31)
  91 #define QSPI_CLK_DIV_MAX                0xffff
  92
  93 /* Command */
  94 #define QSPI_EN_CS(n)                   (n << 28)
  95 #define QSPI_WLEN(n)                    ((n - 1) << 19)
  96 #define QSPI_3_PIN                      (1 << 18)
  97 #define QSPI_RD_SNGL                    (1 << 16)
  98 #define QSPI_WR_SNGL                    (2 << 16)
  99 #define QSPI_RD_DUAL                    (3 << 16)
 100 #define QSPI_RD_QUAD                    (7 << 16)
 101 #define QSPI_INVAL                      (4 << 16)
 102 #define QSPI_FLEN(n)                    ((n - 1) << 0)
 103 #define QSPI_WLEN_MAX_BITS              128
 104 #define QSPI_WLEN_MAX_BYTES             16
 105 #define QSPI_WLEN_MASK                  QSPI_WLEN(QSPI_WLEN_MAX_BITS)
 106
 107 /* STATUS REGISTER */
 108 #define BUSY                            0x01
 109 #define WC                              0x02
 110
 111 /* Device Control */
 112 #define QSPI_DD(m, n)                   (m << (3 + n * 8))
 113 #define QSPI_CKPHA(n)                   (1 << (2 + n * 8))
 114 #define QSPI_CSPOL(n)                   (1 << (1 + n * 8))
 115 #define QSPI_CKPOL(n)                   (1 << (n * 8))
 116
 117 #define QSPI_FRAME                      4096
 118
 119 #define QSPI_AUTOSUSPEND_TIMEOUT         2000
 120
 121 #define MEM_CS_EN(n)                    ((n + 1) << 8)
 122 #define MEM_CS_MASK                     (7 << 8)
 123
 124 #define MM_SWITCH                       0x1
 125
 126 #define QSPI_SETUP_RD_NORMAL            (0x0 << 12)
 127 #define QSPI_SETUP_RD_DUAL              (0x1 << 12)
 128 #define QSPI_SETUP_RD_QUAD              (0x3 << 12)
 129 #define QSPI_SETUP_ADDR_SHIFT           8
 130 #define QSPI_SETUP_DUMMY_SHIFT          10
 131
 132 #define QSPI_DMA_BUFFER_SIZE            SZ_64K
 133
 134 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
 135                 unsigned long reg)
 136 {
 137         return readl(qspi->base + reg);
 138 }
 139
 140 static inline void ti_qspi_write(struct ti_qspi *qspi,
 141                 unsigned long val, unsigned long reg)
 142 {
 143         writel(val, qspi->base + reg);
 144 }
 145
 146 static int ti_qspi_setup(struct spi_device *spi)
 147 {
 148         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
 149         struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
 150         int clk_div = 0, ret;
 151         u32 clk_ctrl_reg, clk_rate, clk_mask;
 152
 153         if (spi->master->busy) {
 154                 dev_dbg(qspi->dev, "master busy doing other transfers\n");
 155                 return -EBUSY;
 156         }
 157
 158         if (!qspi->spi_max_frequency) {
 159                 dev_err(qspi->dev, "spi max frequency not defined\n");
 160                 return -EINVAL;
 161         }
 162
 163         clk_rate = clk_get_rate(qspi->fclk);
 164
 165         clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
 166
 167         if (clk_div < 0) {
 168                 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
 169                 return -EINVAL;
 170         }
 171
 172         if (clk_div > QSPI_CLK_DIV_MAX) {
 173                 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
 174                                 QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
 175                 return -EINVAL;
 176         }
 177
 178         dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
 179                         qspi->spi_max_frequency, clk_div);
 180
 181         ret = pm_runtime_get_sync(qspi->dev);
 182         if (ret < 0) {
 183                 pm_runtime_put_noidle(qspi->dev);
 184                 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
 185                 return ret;
 186         }
 187
 188         clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
 189
 190         clk_ctrl_reg &= ~QSPI_CLK_EN;
 191
 192         /* disable SCLK */
 193         ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
 194
 195         /* enable SCLK */
 196         clk_mask = QSPI_CLK_EN | clk_div;
 197         ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
 198         ctx_reg->clkctrl = clk_mask;
 199
 200         pm_runtime_mark_last_busy(qspi->dev);
 201         ret = pm_runtime_put_autosuspend(qspi->dev);
 202         if (ret < 0) {
 203                 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
 204                 return ret;
 205         }
 206
 207         return 0;
 208 }
 209
 210 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
 211 {
 212         struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
 213
 214         ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
 215 }
 216
 217 static inline u32 qspi_is_busy(struct ti_qspi *qspi)
 218 {
 219         u32 stat;
 220         unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
 221
 222         stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 223         while ((stat & BUSY) && time_after(timeout, jiffies)) {
 224                 cpu_relax();
 225                 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 226         }
 227
 228         WARN(stat & BUSY, "qspi busy\n");
 229         return stat & BUSY;
 230 }
 231
 232 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
 233 {
 234         u32 stat;
 235         unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
 236
 237         do {
 238                 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 239                 if (stat & WC)
 240                         return 0;
 241                 cpu_relax();
 242         } while (time_after(timeout, jiffies));
 243
 244         stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 245         if (stat & WC)
 246                 return 0;
 247         return  -ETIMEDOUT;
 248 }
 249
 250 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t,
 251                           int count)
 252 {
 253         int wlen, xfer_len;
 254         unsigned int cmd;
 255         const u8 *txbuf;
 256         u32 data;
 257
 258         txbuf = t->tx_buf;
 259         cmd = qspi->cmd | QSPI_WR_SNGL;
 260         wlen = t->bits_per_word >> 3;   /* in bytes */
 261         xfer_len = wlen;
 262
 263         while (count) {
 264                 if (qspi_is_busy(qspi))
 265                         return -EBUSY;
 266
 267                 switch (wlen) {
 268                 case 1:
 269                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
 270                                         cmd, qspi->dc, *txbuf);
 271                         if (count >= QSPI_WLEN_MAX_BYTES) {
 272                                 u32 *txp = (u32 *)txbuf;
 273
 274                                 data = cpu_to_be32(*txp++);
 275                                 writel(data, qspi->base +
 276                                        QSPI_SPI_DATA_REG_3);
 277                                 data = cpu_to_be32(*txp++);
 278                                 writel(data, qspi->base +
 279                                        QSPI_SPI_DATA_REG_2);
 280                                 data = cpu_to_be32(*txp++);
 281                                 writel(data, qspi->base +
 282                                        QSPI_SPI_DATA_REG_1);
 283                                 data = cpu_to_be32(*txp++);
 284                                 writel(data, qspi->base +
 285                                        QSPI_SPI_DATA_REG);
 286                                 xfer_len = QSPI_WLEN_MAX_BYTES;
 287                                 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
 288                         } else {
 289                                 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
 290                                 cmd = qspi->cmd | QSPI_WR_SNGL;
 291                                 xfer_len = wlen;
 292                                 cmd |= QSPI_WLEN(wlen);
 293                         }
 294                         break;
 295                 case 2:
 296                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
 297                                         cmd, qspi->dc, *txbuf);
 298                         writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
 299                         break;
 300                 case 4:
 301                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
 302                                         cmd, qspi->dc, *txbuf);
 303                         writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
 304                         break;
 305                 }
 306
 307                 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
 308                 if (ti_qspi_poll_wc(qspi)) {
 309                         dev_err(qspi->dev, "write timed out\n");
 310                         return -ETIMEDOUT;
 311                 }
 312                 txbuf += xfer_len;
 313                 count -= xfer_len;
 314         }
 315
 316         return 0;
 317 }
 318
 319 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t,
 320                          int count)
 321 {
 322         int wlen;
 323         unsigned int cmd;
 324         u8 *rxbuf;
 325
 326         rxbuf = t->rx_buf;
 327         cmd = qspi->cmd;
 328         switch (t->rx_nbits) {
 329         case SPI_NBITS_DUAL:
 330                 cmd |= QSPI_RD_DUAL;
 331                 break;
 332         case SPI_NBITS_QUAD:
 333                 cmd |= QSPI_RD_QUAD;
 334                 break;
 335         default:
 336                 cmd |= QSPI_RD_SNGL;
 337                 break;
 338         }
 339         wlen = t->bits_per_word >> 3;   /* in bytes */
 340
 341         while (count) {
 342                 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
 343                 if (qspi_is_busy(qspi))
 344                         return -EBUSY;
 345
 346                 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
 347                 if (ti_qspi_poll_wc(qspi)) {
 348                         dev_err(qspi->dev, "read timed out\n");
 349                         return -ETIMEDOUT;
 350                 }
 351                 switch (wlen) {
 352                 case 1:
 353                         *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
 354                         break;
 355                 case 2:
 356                         *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
 357                         break;
 358                 case 4:
 359                         *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
 360                         break;
 361                 }
 362                 rxbuf += wlen;
 363                 count -= wlen;
 364         }
 365
 366         return 0;
 367 }
 368
 369 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
 370                              int count)
 371 {
 372         int ret;
 373
 374         if (t->tx_buf) {
 375                 ret = qspi_write_msg(qspi, t, count);
 376                 if (ret) {
 377                         dev_dbg(qspi->dev, "Error while writing\n");
 378                         return ret;
 379                 }
 380         }
 381
 382         if (t->rx_buf) {
 383                 ret = qspi_read_msg(qspi, t, count);
 384                 if (ret) {
 385                         dev_dbg(qspi->dev, "Error while reading\n");
 386                         return ret;
 387                 }
 388         }
 389
 390         return 0;
 391 }
 392
 393 static void ti_qspi_dma_callback(void *param)
 394 {
 395         struct ti_qspi *qspi = param;
 396
 397         complete(&qspi->transfer_complete);
 398 }
 399
 400 static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst,
 401                             dma_addr_t dma_src, size_t len)
 402 {
 403         struct dma_chan *chan = qspi->rx_chan;
 404         dma_cookie_t cookie;
 405         enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 406         struct dma_async_tx_descriptor *tx;
 407         int ret;
 408
 409         tx = dmaengine_prep_dma_memcpy(chan, dma_dst, dma_src, len, flags);
 410         if (!tx) {
 411                 dev_err(qspi->dev, "device_prep_dma_memcpy error\n");
 412                 return -EIO;
 413         }
 414
 415         tx->callback = ti_qspi_dma_callback;
 416         tx->callback_param = qspi;
 417         cookie = tx->tx_submit(tx);
 418         reinit_completion(&qspi->transfer_complete);
 419
 420         ret = dma_submit_error(cookie);
 421         if (ret) {
 422                 dev_err(qspi->dev, "dma_submit_error %d\n", cookie);
 423                 return -EIO;
 424         }
 425
 426         dma_async_issue_pending(chan);
 427         ret = wait_for_completion_timeout(&qspi->transfer_complete,
 428                                           msecs_to_jiffies(len));
 429         if (ret <= 0) {
 430                 dmaengine_terminate_sync(chan);
 431                 dev_err(qspi->dev, "DMA wait_for_completion_timeout\n");
 432                 return -ETIMEDOUT;
 433         }
 434
 435         return 0;
 436 }
 437
 438 static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi,
 439                                      struct spi_flash_read_message *msg)
 440 {
 441         size_t readsize = msg->len;
 442         void *to = msg->buf;
 443         dma_addr_t dma_src = qspi->mmap_phys_base + msg->from;
 444         int ret = 0;
 445
 446         /*
 447          * Use bounce buffer as FS like jffs2, ubifs may pass
 448          * buffers that does not belong to kernel lowmem region.
 449          */
 450         while (readsize != 0) {
 451                 size_t xfer_len = min_t(size_t, QSPI_DMA_BUFFER_SIZE,
 452                                         readsize);
 453
 454                 ret = ti_qspi_dma_xfer(qspi, qspi->rx_bb_dma_addr,
 455                                        dma_src, xfer_len);
 456                 if (ret != 0)
 457                         return ret;
 458                 memcpy(to, qspi->rx_bb_addr, xfer_len);
 459                 readsize -= xfer_len;
 460                 dma_src += xfer_len;
 461                 to += xfer_len;
 462         }
 463
 464         return ret;
 465 }
 466
 467 static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg,
 468                                loff_t from)
 469 {
 470         struct scatterlist *sg;
 471         dma_addr_t dma_src = qspi->mmap_phys_base + from;
 472         dma_addr_t dma_dst;
 473         int i, len, ret;
 474
 475         for_each_sg(rx_sg.sgl, sg, rx_sg.nents, i) {
 476                 dma_dst = sg_dma_address(sg);
 477                 len = sg_dma_len(sg);
 478                 ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len);
 479                 if (ret)
 480                         return ret;
 481                 dma_src += len;
 482         }
 483
 484         return 0;
 485 }
 486
 487 static void ti_qspi_enable_memory_map(struct spi_device *spi)
 488 {
 489         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
 490
 491         ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
 492         if (qspi->ctrl_base) {
 493                 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
 494                                    MEM_CS_MASK,
 495                                    MEM_CS_EN(spi->chip_select));
 496         }
 497         qspi->mmap_enabled = true;
 498 }
 499
 500 static void ti_qspi_disable_memory_map(struct spi_device *spi)
 501 {
 502         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
 503
 504         ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
 505         if (qspi->ctrl_base)
 506                 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
 507                                    MEM_CS_MASK, 0);
 508         qspi->mmap_enabled = false;
 509 }
 510
 511 static void ti_qspi_setup_mmap_read(struct spi_device *spi,
 512                                     struct spi_flash_read_message *msg)
 513 {
 514         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
 515         u32 memval = msg->read_opcode;
 516
 517         switch (msg->data_nbits) {
 518         case SPI_NBITS_QUAD:
 519                 memval |= QSPI_SETUP_RD_QUAD;
 520                 break;
 521         case SPI_NBITS_DUAL:
 522                 memval |= QSPI_SETUP_RD_DUAL;
 523                 break;
 524         default:
 525                 memval |= QSPI_SETUP_RD_NORMAL;
 526                 break;
 527         }
 528         memval |= ((msg->addr_width - 1) << QSPI_SETUP_ADDR_SHIFT |
 529                    msg->dummy_bytes << QSPI_SETUP_DUMMY_SHIFT);
 530         ti_qspi_write(qspi, memval,
 531                       QSPI_SPI_SETUP_REG(spi->chip_select));
 532 }
 533
 534 static bool ti_qspi_spi_flash_can_dma(struct spi_device *spi,
 535                                       struct spi_flash_read_message *msg)
 536 {
 537         return virt_addr_valid(msg->buf);
 538 }
 539
 540 static int ti_qspi_spi_flash_read(struct spi_device *spi,
 541                                   struct spi_flash_read_message *msg)
 542 {
 543         struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
 544         int ret = 0;
 545
 546         mutex_lock(&qspi->list_lock);
 547
 548         if (!qspi->mmap_enabled)
 549                 ti_qspi_enable_memory_map(spi);
 550         ti_qspi_setup_mmap_read(spi, msg);
 551
 552         if (qspi->rx_chan) {
 553                 if (msg->cur_msg_mapped)
 554                         ret = ti_qspi_dma_xfer_sg(qspi, msg->rx_sg, msg->from);
 555                 else
 556                         ret = ti_qspi_dma_bounce_buffer(qspi, msg);
 557                 if (ret)
 558                         goto err_unlock;
 559         } else {
 560                 memcpy_fromio(msg->buf, qspi->mmap_base + msg->from, msg->len);
 561         }
 562         msg->retlen = msg->len;
 563
 564 err_unlock:
 565         mutex_unlock(&qspi->list_lock);
 566
 567         return ret;
 568 }
 569
 570 static int ti_qspi_start_transfer_one(struct spi_master *master,
 571                 struct spi_message *m)
 572 {
 573         struct ti_qspi *qspi = spi_master_get_devdata(master);
 574         struct spi_device *spi = m->spi;
 575         struct spi_transfer *t;
 576         int status = 0, ret;
 577         unsigned int frame_len_words, transfer_len_words;
 578         int wlen;
 579
 580         /* setup device control reg */
 581         qspi->dc = 0;
 582
 583         if (spi->mode & SPI_CPHA)
 584                 qspi->dc |= QSPI_CKPHA(spi->chip_select);
 585         if (spi->mode & SPI_CPOL)
 586                 qspi->dc |= QSPI_CKPOL(spi->chip_select);
 587         if (spi->mode & SPI_CS_HIGH)
 588                 qspi->dc |= QSPI_CSPOL(spi->chip_select);
 589
 590         frame_len_words = 0;
 591         list_for_each_entry(t, &m->transfers, transfer_list)
 592                 frame_len_words += t->len / (t->bits_per_word >> 3);
 593         frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME);
 594
 595         /* setup command reg */
 596         qspi->cmd = 0;
 597         qspi->cmd |= QSPI_EN_CS(spi->chip_select);
 598         qspi->cmd |= QSPI_FLEN(frame_len_words);
 599
 600         ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
 601
 602         mutex_lock(&qspi->list_lock);
 603
 604         if (qspi->mmap_enabled)
 605                 ti_qspi_disable_memory_map(spi);
 606
 607         list_for_each_entry(t, &m->transfers, transfer_list) {
 608                 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
 609                              QSPI_WLEN(t->bits_per_word));
 610
 611                 wlen = t->bits_per_word >> 3;
 612                 transfer_len_words = min(t->len / wlen, frame_len_words);
 613
 614                 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
 615                 if (ret) {
 616                         dev_dbg(qspi->dev, "transfer message failed\n");
 617                         mutex_unlock(&qspi->list_lock);
 618                         return -EINVAL;
 619                 }
 620
 621                 m->actual_length += transfer_len_words * wlen;
 622                 frame_len_words -= transfer_len_words;
 623                 if (frame_len_words == 0)
 624                         break;
 625         }
 626
 627         mutex_unlock(&qspi->list_lock);
 628
 629         ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
 630         m->status = status;
 631         spi_finalize_current_message(master);
 632
 633         return status;
 634 }
 635
 636 static int ti_qspi_runtime_resume(struct device *dev)
 637 {
 638         struct ti_qspi      *qspi;
 639
 640         qspi = dev_get_drvdata(dev);
 641         ti_qspi_restore_ctx(qspi);
 642
 643         return 0;
 644 }
 645
 646 static void ti_qspi_dma_cleanup(struct ti_qspi *qspi)
 647 {
 648         if (qspi->rx_bb_addr)
 649                 dma_free_coherent(qspi->dev, QSPI_DMA_BUFFER_SIZE,
 650                                   qspi->rx_bb_addr,
 651                                   qspi->rx_bb_dma_addr);
 652
 653         if (qspi->rx_chan)
 654                 dma_release_channel(qspi->rx_chan);
 655 }
 656
 657 static const struct of_device_id ti_qspi_match[] = {
 658         {.compatible = "ti,dra7xxx-qspi" },
 659         {.compatible = "ti,am4372-qspi" },
 660         {},
 661 };
 662 MODULE_DEVICE_TABLE(of, ti_qspi_match);
 663
 664 static int ti_qspi_probe(struct platform_device *pdev)
 665 {
 666         struct  ti_qspi *qspi;
 667         struct spi_master *master;
 668         struct resource         *r, *res_mmap;
 669         struct device_node *np = pdev->dev.of_node;
 670         u32 max_freq;
 671         int ret = 0, num_cs, irq;
 672         dma_cap_mask_t mask;
 673
 674         master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
 675         if (!master)
 676                 return -ENOMEM;
 677
 678         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
 679
 680         master->flags = SPI_MASTER_HALF_DUPLEX;
 681         master->setup = ti_qspi_setup;
 682         master->auto_runtime_pm = true;
 683         master->transfer_one_message = ti_qspi_start_transfer_one;
 684         master->dev.of_node = pdev->dev.of_node;
 685         master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
 686                                      SPI_BPW_MASK(8);
 687         master->spi_flash_read = ti_qspi_spi_flash_read;
 688
 689         if (!of_property_read_u32(np, "num-cs", &num_cs))
 690                 master->num_chipselect = num_cs;
 691
 692         qspi = spi_master_get_devdata(master);
 693         qspi->master = master;
 694         qspi->dev = &pdev->dev;
 695         platform_set_drvdata(pdev, qspi);
 696
 697         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
 698         if (r == NULL) {
 699                 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 700                 if (r == NULL) {
 701                         dev_err(&pdev->dev, "missing platform data\n");
 702                         ret = -ENODEV;
 703                         goto free_master;
 704                 }
 705         }
 706
 707         res_mmap = platform_get_resource_byname(pdev,
 708                         IORESOURCE_MEM, "qspi_mmap");
 709         if (res_mmap == NULL) {
 710                 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 711                 if (res_mmap == NULL) {
 712                         dev_err(&pdev->dev,
 713                                 "memory mapped resource not required\n");
 714                 }
 715         }
 716
 717         irq = platform_get_irq(pdev, 0);
 718         if (irq < 0) {
 719                 dev_err(&pdev->dev, "no irq resource?\n");
 720                 ret = irq;
 721                 goto free_master;
 722         }
 723
 724         mutex_init(&qspi->list_lock);
 725
 726         qspi->base = devm_ioremap_resource(&pdev->dev, r);
 727         if (IS_ERR(qspi->base)) {
 728                 ret = PTR_ERR(qspi->base);
 729                 goto free_master;
 730         }
 731
 732
 733         if (of_property_read_bool(np, "syscon-chipselects")) {
 734                 qspi->ctrl_base =
 735                 syscon_regmap_lookup_by_phandle(np,
 736                                                 "syscon-chipselects");
 737                 if (IS_ERR(qspi->ctrl_base)) {
 738                         ret = PTR_ERR(qspi->ctrl_base);
 739                         goto free_master;
 740                 }
 741                 ret = of_property_read_u32_index(np,
 742                                                  "syscon-chipselects",
 743                                                  1, &qspi->ctrl_reg);
 744                 if (ret) {
 745                         dev_err(&pdev->dev,
 746                                 "couldn't get ctrl_mod reg index\n");
 747                         goto free_master;
 748                 }
 749         }
 750
 751         qspi->fclk = devm_clk_get(&pdev->dev, "fck");
 752         if (IS_ERR(qspi->fclk)) {
 753                 ret = PTR_ERR(qspi->fclk);
 754                 dev_err(&pdev->dev, "could not get clk: %d\n", ret);
 755         }
 756
 757         pm_runtime_use_autosuspend(&pdev->dev);
 758         pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
 759         pm_runtime_enable(&pdev->dev);
 760
 761         if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
 762                 qspi->spi_max_frequency = max_freq;
 763
 764         dma_cap_zero(mask);
 765         dma_cap_set(DMA_MEMCPY, mask);
 766
 767         qspi->rx_chan = dma_request_chan_by_mask(&mask);
 768         if (IS_ERR(qspi->rx_chan)) {
 769                 dev_err(qspi->dev,
 770                         "No Rx DMA available, trying mmap mode\n");
 771                 qspi->rx_chan = NULL;
 772                 ret = 0;
 773                 goto no_dma;
 774         }
 775         qspi->rx_bb_addr = dma_alloc_coherent(qspi->dev,
 776                                               QSPI_DMA_BUFFER_SIZE,
 777                                               &qspi->rx_bb_dma_addr,
 778                                               GFP_KERNEL | GFP_DMA);
 779         if (!qspi->rx_bb_addr) {
 780                 dev_err(qspi->dev,
 781                         "dma_alloc_coherent failed, using PIO mode\n");
 782                 dma_release_channel(qspi->rx_chan);
 783                 goto no_dma;
 784         }
 785         master->spi_flash_can_dma = ti_qspi_spi_flash_can_dma;
 786         master->dma_rx = qspi->rx_chan;
 787         init_completion(&qspi->transfer_complete);
 788         if (res_mmap)
 789                 qspi->mmap_phys_base = (dma_addr_t)res_mmap->start;
 790
 791 no_dma:
 792         if (!qspi->rx_chan && res_mmap) {
 793                 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
 794                 if (IS_ERR(qspi->mmap_base)) {
 795                         dev_info(&pdev->dev,
 796                                  "mmap failed with error %ld using PIO mode\n",
 797                                  PTR_ERR(qspi->mmap_base));
 798                         qspi->mmap_base = NULL;
 799                         master->spi_flash_read = NULL;
 800                 }
 801         }
 802         qspi->mmap_enabled = false;
 803
 804         ret = devm_spi_register_master(&pdev->dev, master);
 805         if (!ret)
 806                 return 0;
 807
 808         ti_qspi_dma_cleanup(qspi);
 809
 810         pm_runtime_disable(&pdev->dev);
 811 free_master:
 812         spi_master_put(master);
 813         return ret;
 814 }
 815
 816 static int ti_qspi_remove(struct platform_device *pdev)
 817 {
 818         struct ti_qspi *qspi = platform_get_drvdata(pdev);
 819         int rc;
 820
 821         rc = spi_master_suspend(qspi->master);
 822         if (rc)
 823                 return rc;
 824
 825         pm_runtime_put_sync(&pdev->dev);
 826         pm_runtime_disable(&pdev->dev);
 827
 828         ti_qspi_dma_cleanup(qspi);
 829
 830         return 0;
 831 }
 832
 833 static const struct dev_pm_ops ti_qspi_pm_ops = {
 834         .runtime_resume = ti_qspi_runtime_resume,
 835 };
 836
 837 static struct platform_driver ti_qspi_driver = {
 838         .probe  = ti_qspi_probe,
 839         .remove = ti_qspi_remove,
 840         .driver = {
 841                 .name   = "ti-qspi",
 842                 .pm =   &ti_qspi_pm_ops,
 843                 .of_match_table = ti_qspi_match,
 844         }
 845 };
 846
 847 module_platform_driver(ti_qspi_driver);
 848
 849 MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
 850 MODULE_LICENSE("GPL v2");
 851 MODULE_DESCRIPTION("TI QSPI controller driver");
 852 MODULE_ALIAS("platform:ti-qspi");