drivers/spi/spi-ti-qspi.c

   1 /*
   2  * TI QSPI driver
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  * Author: Sourav Poddar <sourav.poddar@ti.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GPLv2.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/device.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/dmaengine.h>
  24 #include <linux/omap-dma.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/err.h>
  27 #include <linux/clk.h>
  28 #include <linux/io.h>
  29 #include <linux/slab.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/of.h>
  32 #include <linux/of_device.h>
  33 #include <linux/pinctrl/consumer.h>
  34 #include <linux/mfd/syscon.h>
  35 #include <linux/regmap.h>
  36 #include <linux/sizes.h>
  37
  38 #include <linux/spi/spi.h>
  39 #include <linux/spi/spi-mem.h>
  40
  41 struct ti_qspi_regs {
  42         u32 clkctrl;
  43 };
  44
  45 struct ti_qspi {
  46         struct completion       transfer_complete;
  47
  48         /* list synchronization */
  49         struct mutex            list_lock;
  50
  51         struct spi_master       *master;
  52         void __iomem            *base;
  53         void __iomem            *mmap_base;
  54         size_t                  mmap_size;
  55         struct regmap           *ctrl_base;
  56         unsigned int            ctrl_reg;
  57         struct clk              *fclk;
  58         struct device           *dev;
  59
  60         struct ti_qspi_regs     ctx_reg;
  61
  62         dma_addr_t              mmap_phys_base;
  63         dma_addr_t              rx_bb_dma_addr;
  64         void                    *rx_bb_addr;
  65         struct dma_chan         *rx_chan;
  66
  67         u32 spi_max_frequency;
  68         u32 cmd;
  69         u32 dc;
  70
  71         bool mmap_enabled;
  72         int current_cs;
  73 };
  74
  75 #define QSPI_PID                        (0x0)
  76 #define QSPI_SYSCONFIG                  (0x10)
  77 #define QSPI_SPI_CLOCK_CNTRL_REG        (0x40)
  78 #define QSPI_SPI_DC_REG                 (0x44)
  79 #define QSPI_SPI_CMD_REG                (0x48)
  80 #define QSPI_SPI_STATUS_REG             (0x4c)
  81 #define QSPI_SPI_DATA_REG               (0x50)
  82 #define QSPI_SPI_SETUP_REG(n)           ((0x54 + 4 * n))
  83 #define QSPI_SPI_SWITCH_REG             (0x64)
  84 #define QSPI_SPI_DATA_REG_1             (0x68)
  85 #define QSPI_SPI_DATA_REG_2             (0x6c)
  86 #define QSPI_SPI_DATA_REG_3             (0x70)
  87
  88 #define QSPI_COMPLETION_TIMEOUT         msecs_to_jiffies(2000)
  89
  90 #define QSPI_FCLK                       192000000
  91
  92 /* Clock Control */
  93 #define QSPI_CLK_EN                     (1 << 31)
  94 #define QSPI_CLK_DIV_MAX                0xffff
  95
  96 /* Command */
  97 #define QSPI_EN_CS(n)                   (n << 28)
  98 #define QSPI_WLEN(n)                    ((n - 1) << 19)
  99 #define QSPI_3_PIN                      (1 << 18)
 100 #define QSPI_RD_SNGL                    (1 << 16)
 101 #define QSPI_WR_SNGL                    (2 << 16)
 102 #define QSPI_RD_DUAL                    (3 << 16)
 103 #define QSPI_RD_QUAD                    (7 << 16)
 104 #define QSPI_INVAL                      (4 << 16)
 105 #define QSPI_FLEN(n)                    ((n - 1) << 0)
 106 #define QSPI_WLEN_MAX_BITS              128
 107 #define QSPI_WLEN_MAX_BYTES             16
 108 #define QSPI_WLEN_MASK                  QSPI_WLEN(QSPI_WLEN_MAX_BITS)
 109
 110 /* STATUS REGISTER */
 111 #define BUSY                            0x01
 112 #define WC                              0x02
 113
 114 /* Device Control */
 115 #define QSPI_DD(m, n)                   (m << (3 + n * 8))
 116 #define QSPI_CKPHA(n)                   (1 << (2 + n * 8))
 117 #define QSPI_CSPOL(n)                   (1 << (1 + n * 8))
 118 #define QSPI_CKPOL(n)                   (1 << (n * 8))
 119
 120 #define QSPI_FRAME                      4096
 121
 122 #define QSPI_AUTOSUSPEND_TIMEOUT         2000
 123
 124 #define MEM_CS_EN(n)                    ((n + 1) << 8)
 125 #define MEM_CS_MASK                     (7 << 8)
 126
 127 #define MM_SWITCH                       0x1
 128
 129 #define QSPI_SETUP_RD_NORMAL            (0x0 << 12)
 130 #define QSPI_SETUP_RD_DUAL              (0x1 << 12)
 131 #define QSPI_SETUP_RD_QUAD              (0x3 << 12)
 132 #define QSPI_SETUP_ADDR_SHIFT           8
 133 #define QSPI_SETUP_DUMMY_SHIFT          10
 134
 135 #define QSPI_DMA_BUFFER_SIZE            SZ_64K
 136
 137 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
 138                 unsigned long reg)
 139 {
 140         return readl(qspi->base + reg);
 141 }
 142
 143 static inline void ti_qspi_write(struct ti_qspi *qspi,
 144                 unsigned long val, unsigned long reg)
 145 {
 146         writel(val, qspi->base + reg);
 147 }
 148
 149 static int ti_qspi_setup(struct spi_device *spi)
 150 {
 151         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
 152         struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
 153         int clk_div = 0, ret;
 154         u32 clk_ctrl_reg, clk_rate, clk_mask;
 155
 156         if (spi->master->busy) {
 157                 dev_dbg(qspi->dev, "master busy doing other transfers\n");
 158                 return -EBUSY;
 159         }
 160
 161         if (!qspi->spi_max_frequency) {
 162                 dev_err(qspi->dev, "spi max frequency not defined\n");
 163                 return -EINVAL;
 164         }
 165
 166         clk_rate = clk_get_rate(qspi->fclk);
 167
 168         clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
 169
 170         if (clk_div < 0) {
 171                 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
 172                 return -EINVAL;
 173         }
 174
 175         if (clk_div > QSPI_CLK_DIV_MAX) {
 176                 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
 177                                 QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
 178                 return -EINVAL;
 179         }
 180
 181         dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
 182                         qspi->spi_max_frequency, clk_div);
 183
 184         ret = pm_runtime_get_sync(qspi->dev);
 185         if (ret < 0) {
 186                 pm_runtime_put_noidle(qspi->dev);
 187                 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
 188                 return ret;
 189         }
 190
 191         clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
 192
 193         clk_ctrl_reg &= ~QSPI_CLK_EN;
 194
 195         /* disable SCLK */
 196         ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
 197
 198         /* enable SCLK */
 199         clk_mask = QSPI_CLK_EN | clk_div;
 200         ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
 201         ctx_reg->clkctrl = clk_mask;
 202
 203         pm_runtime_mark_last_busy(qspi->dev);
 204         ret = pm_runtime_put_autosuspend(qspi->dev);
 205         if (ret < 0) {
 206                 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
 207                 return ret;
 208         }
 209
 210         return 0;
 211 }
 212
 213 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
 214 {
 215         struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
 216
 217         ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
 218 }
 219
 220 static inline u32 qspi_is_busy(struct ti_qspi *qspi)
 221 {
 222         u32 stat;
 223         unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
 224
 225         stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 226         while ((stat & BUSY) && time_after(timeout, jiffies)) {
 227                 cpu_relax();
 228                 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 229         }
 230
 231         WARN(stat & BUSY, "qspi busy\n");
 232         return stat & BUSY;
 233 }
 234
 235 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
 236 {
 237         u32 stat;
 238         unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
 239
 240         do {
 241                 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 242                 if (stat & WC)
 243                         return 0;
 244                 cpu_relax();
 245         } while (time_after(timeout, jiffies));
 246
 247         stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 248         if (stat & WC)
 249                 return 0;
 250         return  -ETIMEDOUT;
 251 }
 252
 253 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t,
 254                           int count)
 255 {
 256         int wlen, xfer_len;
 257         unsigned int cmd;
 258         const u8 *txbuf;
 259         u32 data;
 260
 261         txbuf = t->tx_buf;
 262         cmd = qspi->cmd | QSPI_WR_SNGL;
 263         wlen = t->bits_per_word >> 3;   /* in bytes */
 264         xfer_len = wlen;
 265
 266         while (count) {
 267                 if (qspi_is_busy(qspi))
 268                         return -EBUSY;
 269
 270                 switch (wlen) {
 271                 case 1:
 272                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
 273                                         cmd, qspi->dc, *txbuf);
 274                         if (count >= QSPI_WLEN_MAX_BYTES) {
 275                                 u32 *txp = (u32 *)txbuf;
 276
 277                                 data = cpu_to_be32(*txp++);
 278                                 writel(data, qspi->base +
 279                                        QSPI_SPI_DATA_REG_3);
 280                                 data = cpu_to_be32(*txp++);
 281                                 writel(data, qspi->base +
 282                                        QSPI_SPI_DATA_REG_2);
 283                                 data = cpu_to_be32(*txp++);
 284                                 writel(data, qspi->base +
 285                                        QSPI_SPI_DATA_REG_1);
 286                                 data = cpu_to_be32(*txp++);
 287                                 writel(data, qspi->base +
 288                                        QSPI_SPI_DATA_REG);
 289                                 xfer_len = QSPI_WLEN_MAX_BYTES;
 290                                 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
 291                         } else {
 292                                 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
 293                                 cmd = qspi->cmd | QSPI_WR_SNGL;
 294                                 xfer_len = wlen;
 295                                 cmd |= QSPI_WLEN(wlen);
 296                         }
 297                         break;
 298                 case 2:
 299                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
 300                                         cmd, qspi->dc, *txbuf);
 301                         writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
 302                         break;
 303                 case 4:
 304                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
 305                                         cmd, qspi->dc, *txbuf);
 306                         writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
 307                         break;
 308                 }
 309
 310                 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
 311                 if (ti_qspi_poll_wc(qspi)) {
 312                         dev_err(qspi->dev, "write timed out\n");
 313                         return -ETIMEDOUT;
 314                 }
 315                 txbuf += xfer_len;
 316                 count -= xfer_len;
 317         }
 318
 319         return 0;
 320 }
 321
 322 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t,
 323                          int count)
 324 {
 325         int wlen;
 326         unsigned int cmd;
 327         u8 *rxbuf;
 328
 329         rxbuf = t->rx_buf;
 330         cmd = qspi->cmd;
 331         switch (t->rx_nbits) {
 332         case SPI_NBITS_DUAL:
 333                 cmd |= QSPI_RD_DUAL;
 334                 break;
 335         case SPI_NBITS_QUAD:
 336                 cmd |= QSPI_RD_QUAD;
 337                 break;
 338         default:
 339                 cmd |= QSPI_RD_SNGL;
 340                 break;
 341         }
 342         wlen = t->bits_per_word >> 3;   /* in bytes */
 343
 344         while (count) {
 345                 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
 346                 if (qspi_is_busy(qspi))
 347                         return -EBUSY;
 348
 349                 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
 350                 if (ti_qspi_poll_wc(qspi)) {
 351                         dev_err(qspi->dev, "read timed out\n");
 352                         return -ETIMEDOUT;
 353                 }
 354                 switch (wlen) {
 355                 case 1:
 356                         *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
 357                         break;
 358                 case 2:
 359                         *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
 360                         break;
 361                 case 4:
 362                         *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
 363                         break;
 364                 }
 365                 rxbuf += wlen;
 366                 count -= wlen;
 367         }
 368
 369         return 0;
 370 }
 371
 372 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
 373                              int count)
 374 {
 375         int ret;
 376
 377         if (t->tx_buf) {
 378                 ret = qspi_write_msg(qspi, t, count);
 379                 if (ret) {
 380                         dev_dbg(qspi->dev, "Error while writing\n");
 381                         return ret;
 382                 }
 383         }
 384
 385         if (t->rx_buf) {
 386                 ret = qspi_read_msg(qspi, t, count);
 387                 if (ret) {
 388                         dev_dbg(qspi->dev, "Error while reading\n");
 389                         return ret;
 390                 }
 391         }
 392
 393         return 0;
 394 }
 395
 396 static void ti_qspi_dma_callback(void *param)
 397 {
 398         struct ti_qspi *qspi = param;
 399
 400         complete(&qspi->transfer_complete);
 401 }
 402
 403 static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst,
 404                             dma_addr_t dma_src, size_t len)
 405 {
 406         struct dma_chan *chan = qspi->rx_chan;
 407         dma_cookie_t cookie;
 408         enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 409         struct dma_async_tx_descriptor *tx;
 410         int ret;
 411
 412         tx = dmaengine_prep_dma_memcpy(chan, dma_dst, dma_src, len, flags);
 413         if (!tx) {
 414                 dev_err(qspi->dev, "device_prep_dma_memcpy error\n");
 415                 return -EIO;
 416         }
 417
 418         tx->callback = ti_qspi_dma_callback;
 419         tx->callback_param = qspi;
 420         cookie = tx->tx_submit(tx);
 421         reinit_completion(&qspi->transfer_complete);
 422
 423         ret = dma_submit_error(cookie);
 424         if (ret) {
 425                 dev_err(qspi->dev, "dma_submit_error %d\n", cookie);
 426                 return -EIO;
 427         }
 428
 429         dma_async_issue_pending(chan);
 430         ret = wait_for_completion_timeout(&qspi->transfer_complete,
 431                                           msecs_to_jiffies(len));
 432         if (ret <= 0) {
 433                 dmaengine_terminate_sync(chan);
 434                 dev_err(qspi->dev, "DMA wait_for_completion_timeout\n");
 435                 return -ETIMEDOUT;
 436         }
 437
 438         return 0;
 439 }
 440
 441 static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi, loff_t offs,
 442                                      void *to, size_t readsize)
 443 {
 444         dma_addr_t dma_src = qspi->mmap_phys_base + offs;
 445         int ret = 0;
 446
 447         /*
 448          * Use bounce buffer as FS like jffs2, ubifs may pass
 449          * buffers that does not belong to kernel lowmem region.
 450          */
 451         while (readsize != 0) {
 452                 size_t xfer_len = min_t(size_t, QSPI_DMA_BUFFER_SIZE,
 453                                         readsize);
 454
 455                 ret = ti_qspi_dma_xfer(qspi, qspi->rx_bb_dma_addr,
 456                                        dma_src, xfer_len);
 457                 if (ret != 0)
 458                         return ret;
 459                 memcpy(to, qspi->rx_bb_addr, xfer_len);
 460                 readsize -= xfer_len;
 461                 dma_src += xfer_len;
 462                 to += xfer_len;
 463         }
 464
 465         return ret;
 466 }
 467
 468 static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg,
 469                                loff_t from)
 470 {
 471         struct scatterlist *sg;
 472         dma_addr_t dma_src = qspi->mmap_phys_base + from;
 473         dma_addr_t dma_dst;
 474         int i, len, ret;
 475
 476         for_each_sg(rx_sg.sgl, sg, rx_sg.nents, i) {
 477                 dma_dst = sg_dma_address(sg);
 478                 len = sg_dma_len(sg);
 479                 ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len);
 480                 if (ret)
 481                         return ret;
 482                 dma_src += len;
 483         }
 484
 485         return 0;
 486 }
 487
 488 static void ti_qspi_enable_memory_map(struct spi_device *spi)
 489 {
 490         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
 491
 492         ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
 493         if (qspi->ctrl_base) {
 494                 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
 495                                    MEM_CS_MASK,
 496                                    MEM_CS_EN(spi->chip_select));
 497         }
 498         qspi->mmap_enabled = true;
 499         qspi->current_cs = spi->chip_select;
 500 }
 501
 502 static void ti_qspi_disable_memory_map(struct spi_device *spi)
 503 {
 504         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
 505
 506         ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
 507         if (qspi->ctrl_base)
 508                 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
 509                                    MEM_CS_MASK, 0);
 510         qspi->mmap_enabled = false;
 511         qspi->current_cs = -1;
 512 }
 513
 514 static void ti_qspi_setup_mmap_read(struct spi_device *spi, u8 opcode,
 515                                     u8 data_nbits, u8 addr_width,
 516                                     u8 dummy_bytes)
 517 {
 518         struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
 519         u32 memval = opcode;
 520
 521         switch (data_nbits) {
 522         case SPI_NBITS_QUAD:
 523                 memval |= QSPI_SETUP_RD_QUAD;
 524                 break;
 525         case SPI_NBITS_DUAL:
 526                 memval |= QSPI_SETUP_RD_DUAL;
 527                 break;
 528         default:
 529                 memval |= QSPI_SETUP_RD_NORMAL;
 530                 break;
 531         }
 532         memval |= ((addr_width - 1) << QSPI_SETUP_ADDR_SHIFT |
 533                    dummy_bytes << QSPI_SETUP_DUMMY_SHIFT);
 534         ti_qspi_write(qspi, memval,
 535                       QSPI_SPI_SETUP_REG(spi->chip_select));
 536 }
 537
 538 static int ti_qspi_exec_mem_op(struct spi_mem *mem,
 539                                const struct spi_mem_op *op)
 540 {
 541         struct ti_qspi *qspi = spi_master_get_devdata(mem->spi->master);
 542         u32 from = 0;
 543         int ret = 0;
 544
 545         /* Only optimize read path. */
 546         if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
 547             !op->addr.nbytes || op->addr.nbytes > 4)
 548                 return -ENOTSUPP;
 549
 550         /* Address exceeds MMIO window size, fall back to regular mode. */
 551         from = op->addr.val;
 552         if (from + op->data.nbytes > qspi->mmap_size)
 553                 return -ENOTSUPP;
 554
 555         mutex_lock(&qspi->list_lock);
 556
 557         if (!qspi->mmap_enabled || qspi->current_cs != mem->spi->chip_select)
 558                 ti_qspi_enable_memory_map(mem->spi);
 559         ti_qspi_setup_mmap_read(mem->spi, op->cmd.opcode, op->data.buswidth,
 560                                 op->addr.nbytes, op->dummy.nbytes);
 561
 562         if (qspi->rx_chan) {
 563                 struct sg_table sgt;
 564
 565                 if (virt_addr_valid(op->data.buf.in) &&
 566                     !spi_controller_dma_map_mem_op_data(mem->spi->master, op,
 567                                                         &sgt)) {
 568                         ret = ti_qspi_dma_xfer_sg(qspi, sgt, from);
 569                         spi_controller_dma_unmap_mem_op_data(mem->spi->master,
 570                                                              op, &sgt);
 571                 } else {
 572                         ret = ti_qspi_dma_bounce_buffer(qspi, from,
 573                                                         op->data.buf.in,
 574                                                         op->data.nbytes);
 575                 }
 576         } else {
 577                 memcpy_fromio(op->data.buf.in, qspi->mmap_base + from,
 578                               op->data.nbytes);
 579         }
 580
 581         mutex_unlock(&qspi->list_lock);
 582
 583         return ret;
 584 }
 585
 586 static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
 587         .exec_op = ti_qspi_exec_mem_op,
 588 };
 589
 590 static int ti_qspi_start_transfer_one(struct spi_master *master,
 591                 struct spi_message *m)
 592 {
 593         struct ti_qspi *qspi = spi_master_get_devdata(master);
 594         struct spi_device *spi = m->spi;
 595         struct spi_transfer *t;
 596         int status = 0, ret;
 597         unsigned int frame_len_words, transfer_len_words;
 598         int wlen;
 599
 600         /* setup device control reg */
 601         qspi->dc = 0;
 602
 603         if (spi->mode & SPI_CPHA)
 604                 qspi->dc |= QSPI_CKPHA(spi->chip_select);
 605         if (spi->mode & SPI_CPOL)
 606                 qspi->dc |= QSPI_CKPOL(spi->chip_select);
 607         if (spi->mode & SPI_CS_HIGH)
 608                 qspi->dc |= QSPI_CSPOL(spi->chip_select);
 609
 610         frame_len_words = 0;
 611         list_for_each_entry(t, &m->transfers, transfer_list)
 612                 frame_len_words += t->len / (t->bits_per_word >> 3);
 613         frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME);
 614
 615         /* setup command reg */
 616         qspi->cmd = 0;
 617         qspi->cmd |= QSPI_EN_CS(spi->chip_select);
 618         qspi->cmd |= QSPI_FLEN(frame_len_words);
 619
 620         ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
 621
 622         mutex_lock(&qspi->list_lock);
 623
 624         if (qspi->mmap_enabled)
 625                 ti_qspi_disable_memory_map(spi);
 626
 627         list_for_each_entry(t, &m->transfers, transfer_list) {
 628                 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
 629                              QSPI_WLEN(t->bits_per_word));
 630
 631                 wlen = t->bits_per_word >> 3;
 632                 transfer_len_words = min(t->len / wlen, frame_len_words);
 633
 634                 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
 635                 if (ret) {
 636                         dev_dbg(qspi->dev, "transfer message failed\n");
 637                         mutex_unlock(&qspi->list_lock);
 638                         return -EINVAL;
 639                 }
 640
 641                 m->actual_length += transfer_len_words * wlen;
 642                 frame_len_words -= transfer_len_words;
 643                 if (frame_len_words == 0)
 644                         break;
 645         }
 646
 647         mutex_unlock(&qspi->list_lock);
 648
 649         ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
 650         m->status = status;
 651         spi_finalize_current_message(master);
 652
 653         return status;
 654 }
 655
 656 static int ti_qspi_runtime_resume(struct device *dev)
 657 {
 658         struct ti_qspi      *qspi;
 659
 660         qspi = dev_get_drvdata(dev);
 661         ti_qspi_restore_ctx(qspi);
 662
 663         return 0;
 664 }
 665
 666 static void ti_qspi_dma_cleanup(struct ti_qspi *qspi)
 667 {
 668         if (qspi->rx_bb_addr)
 669                 dma_free_coherent(qspi->dev, QSPI_DMA_BUFFER_SIZE,
 670                                   qspi->rx_bb_addr,
 671                                   qspi->rx_bb_dma_addr);
 672
 673         if (qspi->rx_chan)
 674                 dma_release_channel(qspi->rx_chan);
 675 }
 676
 677 static const struct of_device_id ti_qspi_match[] = {
 678         {.compatible = "ti,dra7xxx-qspi" },
 679         {.compatible = "ti,am4372-qspi" },
 680         {},
 681 };
 682 MODULE_DEVICE_TABLE(of, ti_qspi_match);
 683
 684 static int ti_qspi_probe(struct platform_device *pdev)
 685 {
 686         struct  ti_qspi *qspi;
 687         struct spi_master *master;
 688         struct resource         *r, *res_mmap;
 689         struct device_node *np = pdev->dev.of_node;
 690         u32 max_freq;
 691         int ret = 0, num_cs, irq;
 692         dma_cap_mask_t mask;
 693
 694         master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
 695         if (!master)
 696                 return -ENOMEM;
 697
 698         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
 699
 700         master->flags = SPI_MASTER_HALF_DUPLEX;
 701         master->setup = ti_qspi_setup;
 702         master->auto_runtime_pm = true;
 703         master->transfer_one_message = ti_qspi_start_transfer_one;
 704         master->dev.of_node = pdev->dev.of_node;
 705         master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
 706                                      SPI_BPW_MASK(8);
 707         master->mem_ops = &ti_qspi_mem_ops;
 708
 709         if (!of_property_read_u32(np, "num-cs", &num_cs))
 710                 master->num_chipselect = num_cs;
 711
 712         qspi = spi_master_get_devdata(master);
 713         qspi->master = master;
 714         qspi->dev = &pdev->dev;
 715         platform_set_drvdata(pdev, qspi);
 716
 717         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
 718         if (r == NULL) {
 719                 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 720                 if (r == NULL) {
 721                         dev_err(&pdev->dev, "missing platform data\n");
 722                         ret = -ENODEV;
 723                         goto free_master;
 724                 }
 725         }
 726
 727         res_mmap = platform_get_resource_byname(pdev,
 728                         IORESOURCE_MEM, "qspi_mmap");
 729         if (res_mmap == NULL) {
 730                 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 731                 if (res_mmap == NULL) {
 732                         dev_err(&pdev->dev,
 733                                 "memory mapped resource not required\n");
 734                 }
 735         }
 736
 737         if (res_mmap)
 738                 qspi->mmap_size = resource_size(res_mmap);
 739
 740         irq = platform_get_irq(pdev, 0);
 741         if (irq < 0) {
 742                 dev_err(&pdev->dev, "no irq resource?\n");
 743                 ret = irq;
 744                 goto free_master;
 745         }
 746
 747         mutex_init(&qspi->list_lock);
 748
 749         qspi->base = devm_ioremap_resource(&pdev->dev, r);
 750         if (IS_ERR(qspi->base)) {
 751                 ret = PTR_ERR(qspi->base);
 752                 goto free_master;
 753         }
 754
 755
 756         if (of_property_read_bool(np, "syscon-chipselects")) {
 757                 qspi->ctrl_base =
 758                 syscon_regmap_lookup_by_phandle(np,
 759                                                 "syscon-chipselects");
 760                 if (IS_ERR(qspi->ctrl_base)) {
 761                         ret = PTR_ERR(qspi->ctrl_base);
 762                         goto free_master;
 763                 }
 764                 ret = of_property_read_u32_index(np,
 765                                                  "syscon-chipselects",
 766                                                  1, &qspi->ctrl_reg);
 767                 if (ret) {
 768                         dev_err(&pdev->dev,
 769                                 "couldn't get ctrl_mod reg index\n");
 770                         goto free_master;
 771                 }
 772         }
 773
 774         qspi->fclk = devm_clk_get(&pdev->dev, "fck");
 775         if (IS_ERR(qspi->fclk)) {
 776                 ret = PTR_ERR(qspi->fclk);
 777                 dev_err(&pdev->dev, "could not get clk: %d\n", ret);
 778         }
 779
 780         pm_runtime_use_autosuspend(&pdev->dev);
 781         pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
 782         pm_runtime_enable(&pdev->dev);
 783
 784         if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
 785                 qspi->spi_max_frequency = max_freq;
 786
 787         dma_cap_zero(mask);
 788         dma_cap_set(DMA_MEMCPY, mask);
 789
 790         qspi->rx_chan = dma_request_chan_by_mask(&mask);
 791         if (IS_ERR(qspi->rx_chan)) {
 792                 dev_err(qspi->dev,
 793                         "No Rx DMA available, trying mmap mode\n");
 794                 qspi->rx_chan = NULL;
 795                 ret = 0;
 796                 goto no_dma;
 797         }
 798         qspi->rx_bb_addr = dma_alloc_coherent(qspi->dev,
 799                                               QSPI_DMA_BUFFER_SIZE,
 800                                               &qspi->rx_bb_dma_addr,
 801                                               GFP_KERNEL | GFP_DMA);
 802         if (!qspi->rx_bb_addr) {
 803                 dev_err(qspi->dev,
 804                         "dma_alloc_coherent failed, using PIO mode\n");
 805                 dma_release_channel(qspi->rx_chan);
 806                 goto no_dma;
 807         }
 808         master->dma_rx = qspi->rx_chan;
 809         init_completion(&qspi->transfer_complete);
 810         if (res_mmap)
 811                 qspi->mmap_phys_base = (dma_addr_t)res_mmap->start;
 812
 813 no_dma:
 814         if (!qspi->rx_chan && res_mmap) {
 815                 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
 816                 if (IS_ERR(qspi->mmap_base)) {
 817                         dev_info(&pdev->dev,
 818                                  "mmap failed with error %ld using PIO mode\n",
 819                                  PTR_ERR(qspi->mmap_base));
 820                         qspi->mmap_base = NULL;
 821                         master->mem_ops = NULL;
 822                 }
 823         }
 824         qspi->mmap_enabled = false;
 825         qspi->current_cs = -1;
 826
 827         ret = devm_spi_register_master(&pdev->dev, master);
 828         if (!ret)
 829                 return 0;
 830
 831         ti_qspi_dma_cleanup(qspi);
 832
 833         pm_runtime_disable(&pdev->dev);
 834 free_master:
 835         spi_master_put(master);
 836         return ret;
 837 }
 838
 839 static int ti_qspi_remove(struct platform_device *pdev)
 840 {
 841         struct ti_qspi *qspi = platform_get_drvdata(pdev);
 842         int rc;
 843
 844         rc = spi_master_suspend(qspi->master);
 845         if (rc)
 846                 return rc;
 847
 848         pm_runtime_put_sync(&pdev->dev);
 849         pm_runtime_disable(&pdev->dev);
 850
 851         ti_qspi_dma_cleanup(qspi);
 852
 853         return 0;
 854 }
 855
 856 static const struct dev_pm_ops ti_qspi_pm_ops = {
 857         .runtime_resume = ti_qspi_runtime_resume,
 858 };
 859
 860 static struct platform_driver ti_qspi_driver = {
 861         .probe  = ti_qspi_probe,
 862         .remove = ti_qspi_remove,
 863         .driver = {
 864                 .name   = "ti-qspi",
 865                 .pm =   &ti_qspi_pm_ops,
 866                 .of_match_table = ti_qspi_match,
 867         }
 868 };
 869
 870 module_platform_driver(ti_qspi_driver);
 871
 872 MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
 873 MODULE_LICENSE("GPL v2");
 874 MODULE_DESCRIPTION("TI QSPI controller driver");
 875 MODULE_ALIAS("platform:ti-qspi");