4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Sourav Poddar <sourav.poddar@ti.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GPLv2.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/delay.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/omap-dma.h>
25 #include <linux/platform_device.h>
26 #include <linux/err.h>
27 #include <linux/clk.h>
29 #include <linux/slab.h>
30 #include <linux/pm_runtime.h>
32 #include <linux/of_device.h>
33 #include <linux/pinctrl/consumer.h>
34 #include <linux/mfd/syscon.h>
35 #include <linux/regmap.h>
37 #include <linux/spi/spi.h>
44 struct completion transfer_complete;
46 /* list synchronization */
47 struct mutex list_lock;
49 struct spi_master *master;
51 void __iomem *mmap_base;
52 struct regmap *ctrl_base;
53 unsigned int ctrl_reg;
57 struct ti_qspi_regs ctx_reg;
59 dma_addr_t mmap_phys_base;
60 struct dma_chan *rx_chan;
62 u32 spi_max_frequency;
69 #define QSPI_PID (0x0)
70 #define QSPI_SYSCONFIG (0x10)
71 #define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
72 #define QSPI_SPI_DC_REG (0x44)
73 #define QSPI_SPI_CMD_REG (0x48)
74 #define QSPI_SPI_STATUS_REG (0x4c)
75 #define QSPI_SPI_DATA_REG (0x50)
76 #define QSPI_SPI_SETUP_REG(n) ((0x54 + 4 * n))
77 #define QSPI_SPI_SWITCH_REG (0x64)
78 #define QSPI_SPI_DATA_REG_1 (0x68)
79 #define QSPI_SPI_DATA_REG_2 (0x6c)
80 #define QSPI_SPI_DATA_REG_3 (0x70)
82 #define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
84 #define QSPI_FCLK 192000000
87 #define QSPI_CLK_EN (1 << 31)
88 #define QSPI_CLK_DIV_MAX 0xffff
91 #define QSPI_EN_CS(n) (n << 28)
92 #define QSPI_WLEN(n) ((n - 1) << 19)
93 #define QSPI_3_PIN (1 << 18)
94 #define QSPI_RD_SNGL (1 << 16)
95 #define QSPI_WR_SNGL (2 << 16)
96 #define QSPI_RD_DUAL (3 << 16)
97 #define QSPI_RD_QUAD (7 << 16)
98 #define QSPI_INVAL (4 << 16)
99 #define QSPI_FLEN(n) ((n - 1) << 0)
100 #define QSPI_WLEN_MAX_BITS 128
101 #define QSPI_WLEN_MAX_BYTES 16
102 #define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
104 /* STATUS REGISTER */
109 #define QSPI_DD(m, n) (m << (3 + n * 8))
110 #define QSPI_CKPHA(n) (1 << (2 + n * 8))
111 #define QSPI_CSPOL(n) (1 << (1 + n * 8))
112 #define QSPI_CKPOL(n) (1 << (n * 8))
114 #define QSPI_FRAME 4096
116 #define QSPI_AUTOSUSPEND_TIMEOUT 2000
118 #define MEM_CS_EN(n) ((n + 1) << 8)
119 #define MEM_CS_MASK (7 << 8)
121 #define MM_SWITCH 0x1
123 #define QSPI_SETUP_RD_NORMAL (0x0 << 12)
124 #define QSPI_SETUP_RD_DUAL (0x1 << 12)
125 #define QSPI_SETUP_RD_QUAD (0x3 << 12)
126 #define QSPI_SETUP_ADDR_SHIFT 8
127 #define QSPI_SETUP_DUMMY_SHIFT 10
129 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
132 return readl(qspi->base + reg);
135 static inline void ti_qspi_write(struct ti_qspi *qspi,
136 unsigned long val, unsigned long reg)
138 writel(val, qspi->base + reg);
141 static int ti_qspi_setup(struct spi_device *spi)
143 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
144 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
145 int clk_div = 0, ret;
146 u32 clk_ctrl_reg, clk_rate, clk_mask;
148 if (spi->master->busy) {
149 dev_dbg(qspi->dev, "master busy doing other transfers\n");
153 if (!qspi->spi_max_frequency) {
154 dev_err(qspi->dev, "spi max frequency not defined\n");
158 clk_rate = clk_get_rate(qspi->fclk);
160 clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
163 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
167 if (clk_div > QSPI_CLK_DIV_MAX) {
168 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
169 QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
173 dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
174 qspi->spi_max_frequency, clk_div);
176 ret = pm_runtime_get_sync(qspi->dev);
178 pm_runtime_put_noidle(qspi->dev);
179 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
183 clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
185 clk_ctrl_reg &= ~QSPI_CLK_EN;
188 ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
191 clk_mask = QSPI_CLK_EN | clk_div;
192 ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
193 ctx_reg->clkctrl = clk_mask;
195 pm_runtime_mark_last_busy(qspi->dev);
196 ret = pm_runtime_put_autosuspend(qspi->dev);
198 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
205 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
207 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
209 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
212 static inline u32 qspi_is_busy(struct ti_qspi *qspi)
215 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
217 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
218 while ((stat & BUSY) && time_after(timeout, jiffies)) {
220 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
223 WARN(stat & BUSY, "qspi busy\n");
227 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
230 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
233 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
237 } while (time_after(timeout, jiffies));
239 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
245 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t,
254 cmd = qspi->cmd | QSPI_WR_SNGL;
255 wlen = t->bits_per_word >> 3; /* in bytes */
259 if (qspi_is_busy(qspi))
264 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
265 cmd, qspi->dc, *txbuf);
266 if (count >= QSPI_WLEN_MAX_BYTES) {
267 u32 *txp = (u32 *)txbuf;
269 data = cpu_to_be32(*txp++);
270 writel(data, qspi->base +
271 QSPI_SPI_DATA_REG_3);
272 data = cpu_to_be32(*txp++);
273 writel(data, qspi->base +
274 QSPI_SPI_DATA_REG_2);
275 data = cpu_to_be32(*txp++);
276 writel(data, qspi->base +
277 QSPI_SPI_DATA_REG_1);
278 data = cpu_to_be32(*txp++);
279 writel(data, qspi->base +
281 xfer_len = QSPI_WLEN_MAX_BYTES;
282 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
284 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
285 cmd = qspi->cmd | QSPI_WR_SNGL;
287 cmd |= QSPI_WLEN(wlen);
291 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
292 cmd, qspi->dc, *txbuf);
293 writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
296 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
297 cmd, qspi->dc, *txbuf);
298 writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
302 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
303 if (ti_qspi_poll_wc(qspi)) {
304 dev_err(qspi->dev, "write timed out\n");
314 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t,
323 switch (t->rx_nbits) {
334 wlen = t->bits_per_word >> 3; /* in bytes */
337 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
338 if (qspi_is_busy(qspi))
341 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
342 if (ti_qspi_poll_wc(qspi)) {
343 dev_err(qspi->dev, "read timed out\n");
348 *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
351 *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
354 *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
364 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
370 ret = qspi_write_msg(qspi, t, count);
372 dev_dbg(qspi->dev, "Error while writing\n");
378 ret = qspi_read_msg(qspi, t, count);
380 dev_dbg(qspi->dev, "Error while reading\n");
388 static void ti_qspi_dma_callback(void *param)
390 struct ti_qspi *qspi = param;
392 complete(&qspi->transfer_complete);
395 static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst,
396 dma_addr_t dma_src, size_t len)
398 struct dma_chan *chan = qspi->rx_chan;
399 struct dma_device *dma_dev = chan->device;
401 enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
402 struct dma_async_tx_descriptor *tx;
404 unsigned long time_left;
406 tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
409 dev_err(qspi->dev, "device_prep_dma_memcpy error\n");
413 tx->callback = ti_qspi_dma_callback;
414 tx->callback_param = qspi;
415 cookie = tx->tx_submit(tx);
417 ret = dma_submit_error(cookie);
419 dev_err(qspi->dev, "dma_submit_error %d\n", cookie);
423 dma_async_issue_pending(chan);
424 time_left = wait_for_completion_timeout(&qspi->transfer_complete,
425 msecs_to_jiffies(len));
426 if (time_left == 0) {
427 dmaengine_terminate_sync(chan);
428 dev_err(qspi->dev, "DMA wait_for_completion_timeout\n");
435 static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg,
438 struct scatterlist *sg;
439 dma_addr_t dma_src = qspi->mmap_phys_base + from;
443 for_each_sg(rx_sg.sgl, sg, rx_sg.nents, i) {
444 dma_dst = sg_dma_address(sg);
445 len = sg_dma_len(sg);
446 ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len);
455 static void ti_qspi_enable_memory_map(struct spi_device *spi)
457 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
459 ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
460 if (qspi->ctrl_base) {
461 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
463 MEM_CS_EN(spi->chip_select));
465 qspi->mmap_enabled = true;
468 static void ti_qspi_disable_memory_map(struct spi_device *spi)
470 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
472 ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
474 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
476 qspi->mmap_enabled = false;
479 static void ti_qspi_setup_mmap_read(struct spi_device *spi,
480 struct spi_flash_read_message *msg)
482 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
483 u32 memval = msg->read_opcode;
485 switch (msg->data_nbits) {
487 memval |= QSPI_SETUP_RD_QUAD;
490 memval |= QSPI_SETUP_RD_DUAL;
493 memval |= QSPI_SETUP_RD_NORMAL;
496 memval |= ((msg->addr_width - 1) << QSPI_SETUP_ADDR_SHIFT |
497 msg->dummy_bytes << QSPI_SETUP_DUMMY_SHIFT);
498 ti_qspi_write(qspi, memval,
499 QSPI_SPI_SETUP_REG(spi->chip_select));
502 static int ti_qspi_spi_flash_read(struct spi_device *spi,
503 struct spi_flash_read_message *msg)
505 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
508 mutex_lock(&qspi->list_lock);
510 if (!qspi->mmap_enabled)
511 ti_qspi_enable_memory_map(spi);
512 ti_qspi_setup_mmap_read(spi, msg);
515 if (msg->cur_msg_mapped) {
516 ret = ti_qspi_dma_xfer_sg(qspi, msg->rx_sg, msg->from);
520 dev_err(qspi->dev, "Invalid address for DMA\n");
525 memcpy_fromio(msg->buf, qspi->mmap_base + msg->from, msg->len);
527 msg->retlen = msg->len;
530 mutex_unlock(&qspi->list_lock);
535 static int ti_qspi_start_transfer_one(struct spi_master *master,
536 struct spi_message *m)
538 struct ti_qspi *qspi = spi_master_get_devdata(master);
539 struct spi_device *spi = m->spi;
540 struct spi_transfer *t;
542 unsigned int frame_len_words, transfer_len_words;
545 /* setup device control reg */
548 if (spi->mode & SPI_CPHA)
549 qspi->dc |= QSPI_CKPHA(spi->chip_select);
550 if (spi->mode & SPI_CPOL)
551 qspi->dc |= QSPI_CKPOL(spi->chip_select);
552 if (spi->mode & SPI_CS_HIGH)
553 qspi->dc |= QSPI_CSPOL(spi->chip_select);
556 list_for_each_entry(t, &m->transfers, transfer_list)
557 frame_len_words += t->len / (t->bits_per_word >> 3);
558 frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME);
560 /* setup command reg */
562 qspi->cmd |= QSPI_EN_CS(spi->chip_select);
563 qspi->cmd |= QSPI_FLEN(frame_len_words);
565 ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
567 mutex_lock(&qspi->list_lock);
569 if (qspi->mmap_enabled)
570 ti_qspi_disable_memory_map(spi);
572 list_for_each_entry(t, &m->transfers, transfer_list) {
573 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
574 QSPI_WLEN(t->bits_per_word));
576 wlen = t->bits_per_word >> 3;
577 transfer_len_words = min(t->len / wlen, frame_len_words);
579 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
581 dev_dbg(qspi->dev, "transfer message failed\n");
582 mutex_unlock(&qspi->list_lock);
586 m->actual_length += transfer_len_words * wlen;
587 frame_len_words -= transfer_len_words;
588 if (frame_len_words == 0)
592 mutex_unlock(&qspi->list_lock);
594 ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
596 spi_finalize_current_message(master);
601 static int ti_qspi_runtime_resume(struct device *dev)
603 struct ti_qspi *qspi;
605 qspi = dev_get_drvdata(dev);
606 ti_qspi_restore_ctx(qspi);
611 static const struct of_device_id ti_qspi_match[] = {
612 {.compatible = "ti,dra7xxx-qspi" },
613 {.compatible = "ti,am4372-qspi" },
616 MODULE_DEVICE_TABLE(of, ti_qspi_match);
618 static int ti_qspi_probe(struct platform_device *pdev)
620 struct ti_qspi *qspi;
621 struct spi_master *master;
622 struct resource *r, *res_mmap;
623 struct device_node *np = pdev->dev.of_node;
625 int ret = 0, num_cs, irq;
628 master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
632 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
634 master->flags = SPI_MASTER_HALF_DUPLEX;
635 master->setup = ti_qspi_setup;
636 master->auto_runtime_pm = true;
637 master->transfer_one_message = ti_qspi_start_transfer_one;
638 master->dev.of_node = pdev->dev.of_node;
639 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
641 master->spi_flash_read = ti_qspi_spi_flash_read;
643 if (!of_property_read_u32(np, "num-cs", &num_cs))
644 master->num_chipselect = num_cs;
646 qspi = spi_master_get_devdata(master);
647 qspi->master = master;
648 qspi->dev = &pdev->dev;
649 platform_set_drvdata(pdev, qspi);
651 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
653 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
655 dev_err(&pdev->dev, "missing platform data\n");
660 res_mmap = platform_get_resource_byname(pdev,
661 IORESOURCE_MEM, "qspi_mmap");
662 if (res_mmap == NULL) {
663 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
664 if (res_mmap == NULL) {
666 "memory mapped resource not required\n");
670 irq = platform_get_irq(pdev, 0);
672 dev_err(&pdev->dev, "no irq resource?\n");
676 mutex_init(&qspi->list_lock);
678 qspi->base = devm_ioremap_resource(&pdev->dev, r);
679 if (IS_ERR(qspi->base)) {
680 ret = PTR_ERR(qspi->base);
685 if (of_property_read_bool(np, "syscon-chipselects")) {
687 syscon_regmap_lookup_by_phandle(np,
688 "syscon-chipselects");
689 if (IS_ERR(qspi->ctrl_base))
690 return PTR_ERR(qspi->ctrl_base);
691 ret = of_property_read_u32_index(np,
692 "syscon-chipselects",
696 "couldn't get ctrl_mod reg index\n");
701 qspi->fclk = devm_clk_get(&pdev->dev, "fck");
702 if (IS_ERR(qspi->fclk)) {
703 ret = PTR_ERR(qspi->fclk);
704 dev_err(&pdev->dev, "could not get clk: %d\n", ret);
707 pm_runtime_use_autosuspend(&pdev->dev);
708 pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
709 pm_runtime_enable(&pdev->dev);
711 if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
712 qspi->spi_max_frequency = max_freq;
715 dma_cap_set(DMA_MEMCPY, mask);
717 qspi->rx_chan = dma_request_chan_by_mask(&mask);
718 if (!qspi->rx_chan) {
720 "No Rx DMA available, trying mmap mode\n");
724 master->dma_rx = qspi->rx_chan;
725 init_completion(&qspi->transfer_complete);
727 qspi->mmap_phys_base = (dma_addr_t)res_mmap->start;
730 if (!qspi->rx_chan && res_mmap) {
731 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
732 if (IS_ERR(qspi->mmap_base)) {
734 "mmap failed with error %ld using PIO mode\n",
735 PTR_ERR(qspi->mmap_base));
736 qspi->mmap_base = NULL;
737 master->spi_flash_read = NULL;
740 qspi->mmap_enabled = false;
742 ret = devm_spi_register_master(&pdev->dev, master);
747 spi_master_put(master);
751 static int ti_qspi_remove(struct platform_device *pdev)
753 struct ti_qspi *qspi = platform_get_drvdata(pdev);
756 rc = spi_master_suspend(qspi->master);
760 pm_runtime_put_sync(&pdev->dev);
761 pm_runtime_disable(&pdev->dev);
764 dma_release_channel(qspi->rx_chan);
769 static const struct dev_pm_ops ti_qspi_pm_ops = {
770 .runtime_resume = ti_qspi_runtime_resume,
773 static struct platform_driver ti_qspi_driver = {
774 .probe = ti_qspi_probe,
775 .remove = ti_qspi_remove,
778 .pm = &ti_qspi_pm_ops,
779 .of_match_table = ti_qspi_match,
783 module_platform_driver(ti_qspi_driver);
785 MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
786 MODULE_LICENSE("GPL v2");
787 MODULE_DESCRIPTION("TI QSPI controller driver");
788 MODULE_ALIAS("platform:ti-qspi");