2 * SPI driver for Nvidia's Tegra20/Tegra30 SLINK Controller.
4 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/delay.h>
22 #include <linux/dmaengine.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/dmapool.h>
25 #include <linux/err.h>
26 #include <linux/interrupt.h>
28 #include <linux/kernel.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/platform_device.h>
32 #include <linux/pm_runtime.h>
34 #include <linux/of_device.h>
35 #include <linux/reset.h>
36 #include <linux/spi/spi.h>
38 #define SLINK_COMMAND 0x000
39 #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0)
40 #define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5)
41 #define SLINK_BOTH_EN (1 << 10)
42 #define SLINK_CS_SW (1 << 11)
43 #define SLINK_CS_VALUE (1 << 12)
44 #define SLINK_CS_POLARITY (1 << 13)
45 #define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16)
46 #define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16)
47 #define SLINK_IDLE_SDA_PULL_LOW (2 << 16)
48 #define SLINK_IDLE_SDA_PULL_HIGH (3 << 16)
49 #define SLINK_IDLE_SDA_MASK (3 << 16)
50 #define SLINK_CS_POLARITY1 (1 << 20)
51 #define SLINK_CK_SDA (1 << 21)
52 #define SLINK_CS_POLARITY2 (1 << 22)
53 #define SLINK_CS_POLARITY3 (1 << 23)
54 #define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24)
55 #define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24)
56 #define SLINK_IDLE_SCLK_PULL_LOW (2 << 24)
57 #define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24)
58 #define SLINK_IDLE_SCLK_MASK (3 << 24)
59 #define SLINK_M_S (1 << 28)
60 #define SLINK_WAIT (1 << 29)
61 #define SLINK_GO (1 << 30)
62 #define SLINK_ENB (1 << 31)
64 #define SLINK_MODES (SLINK_IDLE_SCLK_MASK | SLINK_CK_SDA)
66 #define SLINK_COMMAND2 0x004
67 #define SLINK_LSBFE (1 << 0)
68 #define SLINK_SSOE (1 << 1)
69 #define SLINK_SPIE (1 << 4)
70 #define SLINK_BIDIROE (1 << 6)
71 #define SLINK_MODFEN (1 << 7)
72 #define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8)
73 #define SLINK_CS_ACTIVE_BETWEEN (1 << 17)
74 #define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18)
75 #define SLINK_SS_SETUP(x) (((x) & 0x3) << 20)
76 #define SLINK_FIFO_REFILLS_0 (0 << 22)
77 #define SLINK_FIFO_REFILLS_1 (1 << 22)
78 #define SLINK_FIFO_REFILLS_2 (2 << 22)
79 #define SLINK_FIFO_REFILLS_3 (3 << 22)
80 #define SLINK_FIFO_REFILLS_MASK (3 << 22)
81 #define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26)
82 #define SLINK_SPC0 (1 << 29)
83 #define SLINK_TXEN (1 << 30)
84 #define SLINK_RXEN (1 << 31)
86 #define SLINK_STATUS 0x008
87 #define SLINK_COUNT(val) (((val) >> 0) & 0x1f)
88 #define SLINK_WORD(val) (((val) >> 5) & 0x1f)
89 #define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff)
90 #define SLINK_MODF (1 << 16)
91 #define SLINK_RX_UNF (1 << 18)
92 #define SLINK_TX_OVF (1 << 19)
93 #define SLINK_TX_FULL (1 << 20)
94 #define SLINK_TX_EMPTY (1 << 21)
95 #define SLINK_RX_FULL (1 << 22)
96 #define SLINK_RX_EMPTY (1 << 23)
97 #define SLINK_TX_UNF (1 << 24)
98 #define SLINK_RX_OVF (1 << 25)
99 #define SLINK_TX_FLUSH (1 << 26)
100 #define SLINK_RX_FLUSH (1 << 27)
101 #define SLINK_SCLK (1 << 28)
102 #define SLINK_ERR (1 << 29)
103 #define SLINK_RDY (1 << 30)
104 #define SLINK_BSY (1 << 31)
105 #define SLINK_FIFO_ERROR (SLINK_TX_OVF | SLINK_RX_UNF | \
106 SLINK_TX_UNF | SLINK_RX_OVF)
108 #define SLINK_FIFO_EMPTY (SLINK_TX_EMPTY | SLINK_RX_EMPTY)
110 #define SLINK_MAS_DATA 0x010
111 #define SLINK_SLAVE_DATA 0x014
113 #define SLINK_DMA_CTL 0x018
114 #define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0)
115 #define SLINK_TX_TRIG_1 (0 << 16)
116 #define SLINK_TX_TRIG_4 (1 << 16)
117 #define SLINK_TX_TRIG_8 (2 << 16)
118 #define SLINK_TX_TRIG_16 (3 << 16)
119 #define SLINK_TX_TRIG_MASK (3 << 16)
120 #define SLINK_RX_TRIG_1 (0 << 18)
121 #define SLINK_RX_TRIG_4 (1 << 18)
122 #define SLINK_RX_TRIG_8 (2 << 18)
123 #define SLINK_RX_TRIG_16 (3 << 18)
124 #define SLINK_RX_TRIG_MASK (3 << 18)
125 #define SLINK_PACKED (1 << 20)
126 #define SLINK_PACK_SIZE_4 (0 << 21)
127 #define SLINK_PACK_SIZE_8 (1 << 21)
128 #define SLINK_PACK_SIZE_16 (2 << 21)
129 #define SLINK_PACK_SIZE_32 (3 << 21)
130 #define SLINK_PACK_SIZE_MASK (3 << 21)
131 #define SLINK_IE_TXC (1 << 26)
132 #define SLINK_IE_RXC (1 << 27)
133 #define SLINK_DMA_EN (1 << 31)
135 #define SLINK_STATUS2 0x01c
136 #define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0)
137 #define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f0000) >> 16)
138 #define SLINK_SS_HOLD_TIME(val) (((val) & 0xF) << 6)
140 #define SLINK_TX_FIFO 0x100
141 #define SLINK_RX_FIFO 0x180
143 #define DATA_DIR_TX (1 << 0)
144 #define DATA_DIR_RX (1 << 1)
146 #define SLINK_DMA_TIMEOUT (msecs_to_jiffies(1000))
148 #define DEFAULT_SPI_DMA_BUF_LEN (16*1024)
149 #define TX_FIFO_EMPTY_COUNT_MAX SLINK_TX_FIFO_EMPTY_COUNT(0x20)
150 #define RX_FIFO_FULL_COUNT_ZERO SLINK_RX_FIFO_FULL_COUNT(0)
152 #define SLINK_STATUS2_RESET \
153 (TX_FIFO_EMPTY_COUNT_MAX | RX_FIFO_FULL_COUNT_ZERO << 16)
155 #define MAX_CHIP_SELECT 4
156 #define SLINK_FIFO_DEPTH 32
158 struct tegra_slink_chip_data {
162 struct tegra_slink_data {
164 struct spi_master *master;
165 const struct tegra_slink_chip_data *chip_data;
169 struct reset_control *rst;
175 struct spi_device *cur_spi;
178 unsigned words_per_32bit;
179 unsigned bytes_per_word;
180 unsigned curr_dma_words;
181 unsigned cur_direction;
186 unsigned dma_buf_size;
187 unsigned max_buf_size;
188 bool is_curr_dma_xfer;
190 struct completion rx_dma_complete;
191 struct completion tx_dma_complete;
203 u32 def_command2_reg;
205 struct completion xfer_completion;
206 struct spi_transfer *curr_xfer;
207 struct dma_chan *rx_dma_chan;
209 dma_addr_t rx_dma_phys;
210 struct dma_async_tx_descriptor *rx_dma_desc;
212 struct dma_chan *tx_dma_chan;
214 dma_addr_t tx_dma_phys;
215 struct dma_async_tx_descriptor *tx_dma_desc;
218 static int tegra_slink_runtime_suspend(struct device *dev);
219 static int tegra_slink_runtime_resume(struct device *dev);
221 static inline u32 tegra_slink_readl(struct tegra_slink_data *tspi,
224 return readl(tspi->base + reg);
227 static inline void tegra_slink_writel(struct tegra_slink_data *tspi,
228 u32 val, unsigned long reg)
230 writel(val, tspi->base + reg);
232 /* Read back register to make sure that register writes completed */
233 if (reg != SLINK_TX_FIFO)
234 readl(tspi->base + SLINK_MAS_DATA);
237 static void tegra_slink_clear_status(struct tegra_slink_data *tspi)
241 tegra_slink_readl(tspi, SLINK_STATUS);
243 /* Write 1 to clear status register */
244 val_write = SLINK_RDY | SLINK_FIFO_ERROR;
245 tegra_slink_writel(tspi, val_write, SLINK_STATUS);
248 static u32 tegra_slink_get_packed_size(struct tegra_slink_data *tspi,
249 struct spi_transfer *t)
251 switch (tspi->bytes_per_word) {
253 return SLINK_PACK_SIZE_4;
255 return SLINK_PACK_SIZE_8;
257 return SLINK_PACK_SIZE_16;
259 return SLINK_PACK_SIZE_32;
265 static unsigned tegra_slink_calculate_curr_xfer_param(
266 struct spi_device *spi, struct tegra_slink_data *tspi,
267 struct spi_transfer *t)
269 unsigned remain_len = t->len - tspi->cur_pos;
271 unsigned bits_per_word;
273 unsigned total_fifo_words;
275 bits_per_word = t->bits_per_word;
276 tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8);
278 if (bits_per_word == 8 || bits_per_word == 16) {
280 tspi->words_per_32bit = 32/bits_per_word;
283 tspi->words_per_32bit = 1;
285 tspi->packed_size = tegra_slink_get_packed_size(tspi, t);
287 if (tspi->is_packed) {
288 max_len = min(remain_len, tspi->max_buf_size);
289 tspi->curr_dma_words = max_len/tspi->bytes_per_word;
290 total_fifo_words = max_len/4;
292 max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
293 max_word = min(max_word, tspi->max_buf_size/4);
294 tspi->curr_dma_words = max_word;
295 total_fifo_words = max_word;
297 return total_fifo_words;
300 static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf(
301 struct tegra_slink_data *tspi, struct spi_transfer *t)
304 unsigned tx_empty_count;
306 unsigned max_n_32bit;
308 unsigned int written_words;
309 unsigned fifo_words_left;
310 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
312 fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2);
313 tx_empty_count = SLINK_TX_FIFO_EMPTY_COUNT(fifo_status);
315 if (tspi->is_packed) {
316 fifo_words_left = tx_empty_count * tspi->words_per_32bit;
317 written_words = min(fifo_words_left, tspi->curr_dma_words);
318 nbytes = written_words * tspi->bytes_per_word;
319 max_n_32bit = DIV_ROUND_UP(nbytes, 4);
320 for (count = 0; count < max_n_32bit; count++) {
322 for (i = 0; (i < 4) && nbytes; i++, nbytes--)
323 x |= (u32)(*tx_buf++) << (i * 8);
324 tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
327 max_n_32bit = min(tspi->curr_dma_words, tx_empty_count);
328 written_words = max_n_32bit;
329 nbytes = written_words * tspi->bytes_per_word;
330 for (count = 0; count < max_n_32bit; count++) {
332 for (i = 0; nbytes && (i < tspi->bytes_per_word);
334 x |= (u32)(*tx_buf++) << (i * 8);
335 tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
338 tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
339 return written_words;
342 static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf(
343 struct tegra_slink_data *tspi, struct spi_transfer *t)
345 unsigned rx_full_count;
348 unsigned int read_words = 0;
350 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
352 fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2);
353 rx_full_count = SLINK_RX_FIFO_FULL_COUNT(fifo_status);
354 if (tspi->is_packed) {
355 len = tspi->curr_dma_words * tspi->bytes_per_word;
356 for (count = 0; count < rx_full_count; count++) {
357 u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
358 for (i = 0; len && (i < 4); i++, len--)
359 *rx_buf++ = (x >> i*8) & 0xFF;
361 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
362 read_words += tspi->curr_dma_words;
364 for (count = 0; count < rx_full_count; count++) {
365 u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
366 for (i = 0; (i < tspi->bytes_per_word); i++)
367 *rx_buf++ = (x >> (i*8)) & 0xFF;
369 tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word;
370 read_words += rx_full_count;
375 static void tegra_slink_copy_client_txbuf_to_spi_txbuf(
376 struct tegra_slink_data *tspi, struct spi_transfer *t)
378 /* Make the dma buffer to read by cpu */
379 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
380 tspi->dma_buf_size, DMA_TO_DEVICE);
382 if (tspi->is_packed) {
383 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
384 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
388 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
389 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
391 for (count = 0; count < tspi->curr_dma_words; count++) {
393 for (i = 0; consume && (i < tspi->bytes_per_word);
395 x |= (u32)(*tx_buf++) << (i * 8);
396 tspi->tx_dma_buf[count] = x;
399 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
401 /* Make the dma buffer to read by dma */
402 dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
403 tspi->dma_buf_size, DMA_TO_DEVICE);
406 static void tegra_slink_copy_spi_rxbuf_to_client_rxbuf(
407 struct tegra_slink_data *tspi, struct spi_transfer *t)
411 /* Make the dma buffer to read by cpu */
412 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
413 tspi->dma_buf_size, DMA_FROM_DEVICE);
415 if (tspi->is_packed) {
416 len = tspi->curr_dma_words * tspi->bytes_per_word;
417 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
421 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
422 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
424 for (count = 0; count < tspi->curr_dma_words; count++) {
425 u32 x = tspi->rx_dma_buf[count] & rx_mask;
426 for (i = 0; (i < tspi->bytes_per_word); i++)
427 *rx_buf++ = (x >> (i*8)) & 0xFF;
430 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
432 /* Make the dma buffer to read by dma */
433 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
434 tspi->dma_buf_size, DMA_FROM_DEVICE);
437 static void tegra_slink_dma_complete(void *args)
439 struct completion *dma_complete = args;
441 complete(dma_complete);
444 static int tegra_slink_start_tx_dma(struct tegra_slink_data *tspi, int len)
446 reinit_completion(&tspi->tx_dma_complete);
447 tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
448 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
449 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
450 if (!tspi->tx_dma_desc) {
451 dev_err(tspi->dev, "Not able to get desc for Tx\n");
455 tspi->tx_dma_desc->callback = tegra_slink_dma_complete;
456 tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
458 dmaengine_submit(tspi->tx_dma_desc);
459 dma_async_issue_pending(tspi->tx_dma_chan);
463 static int tegra_slink_start_rx_dma(struct tegra_slink_data *tspi, int len)
465 reinit_completion(&tspi->rx_dma_complete);
466 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
467 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
468 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
469 if (!tspi->rx_dma_desc) {
470 dev_err(tspi->dev, "Not able to get desc for Rx\n");
474 tspi->rx_dma_desc->callback = tegra_slink_dma_complete;
475 tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
477 dmaengine_submit(tspi->rx_dma_desc);
478 dma_async_issue_pending(tspi->rx_dma_chan);
482 static int tegra_slink_start_dma_based_transfer(
483 struct tegra_slink_data *tspi, struct spi_transfer *t)
490 /* Make sure that Rx and Tx fifo are empty */
491 status = tegra_slink_readl(tspi, SLINK_STATUS);
492 if ((status & SLINK_FIFO_EMPTY) != SLINK_FIFO_EMPTY) {
493 dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n",
498 val = SLINK_DMA_BLOCK_SIZE(tspi->curr_dma_words - 1);
499 val |= tspi->packed_size;
501 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
504 len = tspi->curr_dma_words * 4;
506 /* Set attention level based on length of transfer */
508 val |= SLINK_TX_TRIG_1 | SLINK_RX_TRIG_1;
509 else if (((len) >> 4) & 0x1)
510 val |= SLINK_TX_TRIG_4 | SLINK_RX_TRIG_4;
512 val |= SLINK_TX_TRIG_8 | SLINK_RX_TRIG_8;
514 if (tspi->cur_direction & DATA_DIR_TX)
517 if (tspi->cur_direction & DATA_DIR_RX)
520 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
521 tspi->dma_control_reg = val;
523 if (tspi->cur_direction & DATA_DIR_TX) {
524 tegra_slink_copy_client_txbuf_to_spi_txbuf(tspi, t);
526 ret = tegra_slink_start_tx_dma(tspi, len);
529 "Starting tx dma failed, err %d\n", ret);
533 /* Wait for tx fifo to be fill before starting slink */
534 status = tegra_slink_readl(tspi, SLINK_STATUS);
535 while (!(status & SLINK_TX_FULL))
536 status = tegra_slink_readl(tspi, SLINK_STATUS);
539 if (tspi->cur_direction & DATA_DIR_RX) {
540 /* Make the dma buffer to read by dma */
541 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
542 tspi->dma_buf_size, DMA_FROM_DEVICE);
544 ret = tegra_slink_start_rx_dma(tspi, len);
547 "Starting rx dma failed, err %d\n", ret);
548 if (tspi->cur_direction & DATA_DIR_TX)
549 dmaengine_terminate_all(tspi->tx_dma_chan);
553 tspi->is_curr_dma_xfer = true;
554 if (tspi->is_packed) {
556 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
557 /* HW need small delay after settign Packed mode */
560 tspi->dma_control_reg = val;
563 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
567 static int tegra_slink_start_cpu_based_transfer(
568 struct tegra_slink_data *tspi, struct spi_transfer *t)
573 val = tspi->packed_size;
574 if (tspi->cur_direction & DATA_DIR_TX)
577 if (tspi->cur_direction & DATA_DIR_RX)
580 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
581 tspi->dma_control_reg = val;
583 if (tspi->cur_direction & DATA_DIR_TX)
584 cur_words = tegra_slink_fill_tx_fifo_from_client_txbuf(tspi, t);
586 cur_words = tspi->curr_dma_words;
587 val |= SLINK_DMA_BLOCK_SIZE(cur_words - 1);
588 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
589 tspi->dma_control_reg = val;
591 tspi->is_curr_dma_xfer = false;
592 if (tspi->is_packed) {
594 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
598 tspi->dma_control_reg = val;
600 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
604 static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi,
607 struct dma_chan *dma_chan;
611 struct dma_slave_config dma_sconfig;
613 dma_chan = dma_request_slave_channel_reason(tspi->dev,
614 dma_to_memory ? "rx" : "tx");
615 if (IS_ERR(dma_chan)) {
616 ret = PTR_ERR(dma_chan);
617 if (ret != -EPROBE_DEFER)
619 "Dma channel is not available: %d\n", ret);
623 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
624 &dma_phys, GFP_KERNEL);
626 dev_err(tspi->dev, " Not able to allocate the dma buffer\n");
627 dma_release_channel(dma_chan);
632 dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO;
633 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
634 dma_sconfig.src_maxburst = 0;
636 dma_sconfig.dst_addr = tspi->phys + SLINK_TX_FIFO;
637 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
638 dma_sconfig.dst_maxburst = 0;
641 ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
645 tspi->rx_dma_chan = dma_chan;
646 tspi->rx_dma_buf = dma_buf;
647 tspi->rx_dma_phys = dma_phys;
649 tspi->tx_dma_chan = dma_chan;
650 tspi->tx_dma_buf = dma_buf;
651 tspi->tx_dma_phys = dma_phys;
656 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
657 dma_release_channel(dma_chan);
661 static void tegra_slink_deinit_dma_param(struct tegra_slink_data *tspi,
666 struct dma_chan *dma_chan;
669 dma_buf = tspi->rx_dma_buf;
670 dma_chan = tspi->rx_dma_chan;
671 dma_phys = tspi->rx_dma_phys;
672 tspi->rx_dma_chan = NULL;
673 tspi->rx_dma_buf = NULL;
675 dma_buf = tspi->tx_dma_buf;
676 dma_chan = tspi->tx_dma_chan;
677 dma_phys = tspi->tx_dma_phys;
678 tspi->tx_dma_buf = NULL;
679 tspi->tx_dma_chan = NULL;
684 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
685 dma_release_channel(dma_chan);
688 static int tegra_slink_start_transfer_one(struct spi_device *spi,
689 struct spi_transfer *t)
691 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
694 unsigned total_fifo_words;
699 bits_per_word = t->bits_per_word;
701 if (speed != tspi->cur_speed) {
702 clk_set_rate(tspi->clk, speed * 4);
703 tspi->cur_speed = speed;
708 tspi->cur_rx_pos = 0;
709 tspi->cur_tx_pos = 0;
711 total_fifo_words = tegra_slink_calculate_curr_xfer_param(spi, tspi, t);
713 command = tspi->command_reg;
714 command &= ~SLINK_BIT_LENGTH(~0);
715 command |= SLINK_BIT_LENGTH(bits_per_word - 1);
717 command2 = tspi->command2_reg;
718 command2 &= ~(SLINK_RXEN | SLINK_TXEN);
720 tegra_slink_writel(tspi, command, SLINK_COMMAND);
721 tspi->command_reg = command;
723 tspi->cur_direction = 0;
725 command2 |= SLINK_RXEN;
726 tspi->cur_direction |= DATA_DIR_RX;
729 command2 |= SLINK_TXEN;
730 tspi->cur_direction |= DATA_DIR_TX;
732 tegra_slink_writel(tspi, command2, SLINK_COMMAND2);
733 tspi->command2_reg = command2;
735 if (total_fifo_words > SLINK_FIFO_DEPTH)
736 ret = tegra_slink_start_dma_based_transfer(tspi, t);
738 ret = tegra_slink_start_cpu_based_transfer(tspi, t);
742 static int tegra_slink_setup(struct spi_device *spi)
744 static const u32 cs_pol_bit[MAX_CHIP_SELECT] = {
751 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
756 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
758 spi->mode & SPI_CPOL ? "" : "~",
759 spi->mode & SPI_CPHA ? "" : "~",
762 ret = pm_runtime_get_sync(tspi->dev);
764 pm_runtime_put_noidle(tspi->dev);
765 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
769 spin_lock_irqsave(&tspi->lock, flags);
770 val = tspi->def_command_reg;
771 if (spi->mode & SPI_CS_HIGH)
772 val |= cs_pol_bit[spi->chip_select];
774 val &= ~cs_pol_bit[spi->chip_select];
775 tspi->def_command_reg = val;
776 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
777 spin_unlock_irqrestore(&tspi->lock, flags);
779 pm_runtime_put(tspi->dev);
783 static int tegra_slink_prepare_message(struct spi_master *master,
784 struct spi_message *msg)
786 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
787 struct spi_device *spi = msg->spi;
789 tegra_slink_clear_status(tspi);
791 tspi->command_reg = tspi->def_command_reg;
792 tspi->command_reg |= SLINK_CS_SW | SLINK_CS_VALUE;
794 tspi->command2_reg = tspi->def_command2_reg;
795 tspi->command2_reg |= SLINK_SS_EN_CS(spi->chip_select);
797 tspi->command_reg &= ~SLINK_MODES;
798 if (spi->mode & SPI_CPHA)
799 tspi->command_reg |= SLINK_CK_SDA;
801 if (spi->mode & SPI_CPOL)
802 tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_HIGH;
804 tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_LOW;
809 static int tegra_slink_transfer_one(struct spi_master *master,
810 struct spi_device *spi,
811 struct spi_transfer *xfer)
813 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
816 reinit_completion(&tspi->xfer_completion);
817 ret = tegra_slink_start_transfer_one(spi, xfer);
820 "spi can not start transfer, err %d\n", ret);
824 ret = wait_for_completion_timeout(&tspi->xfer_completion,
826 if (WARN_ON(ret == 0)) {
828 "spi transfer timeout, err %d\n", ret);
833 return tspi->tx_status;
835 return tspi->rx_status;
840 static int tegra_slink_unprepare_message(struct spi_master *master,
841 struct spi_message *msg)
843 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
845 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
846 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
851 static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi)
853 struct spi_transfer *t = tspi->curr_xfer;
856 spin_lock_irqsave(&tspi->lock, flags);
857 if (tspi->tx_status || tspi->rx_status ||
858 (tspi->status_reg & SLINK_BSY)) {
860 "CpuXfer ERROR bit set 0x%x\n", tspi->status_reg);
862 "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
863 tspi->command2_reg, tspi->dma_control_reg);
864 reset_control_assert(tspi->rst);
866 reset_control_deassert(tspi->rst);
867 complete(&tspi->xfer_completion);
871 if (tspi->cur_direction & DATA_DIR_RX)
872 tegra_slink_read_rx_fifo_to_client_rxbuf(tspi, t);
874 if (tspi->cur_direction & DATA_DIR_TX)
875 tspi->cur_pos = tspi->cur_tx_pos;
877 tspi->cur_pos = tspi->cur_rx_pos;
879 if (tspi->cur_pos == t->len) {
880 complete(&tspi->xfer_completion);
884 tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, tspi, t);
885 tegra_slink_start_cpu_based_transfer(tspi, t);
887 spin_unlock_irqrestore(&tspi->lock, flags);
891 static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi)
893 struct spi_transfer *t = tspi->curr_xfer;
896 unsigned total_fifo_words;
899 /* Abort dmas if any error */
900 if (tspi->cur_direction & DATA_DIR_TX) {
901 if (tspi->tx_status) {
902 dmaengine_terminate_all(tspi->tx_dma_chan);
905 wait_status = wait_for_completion_interruptible_timeout(
906 &tspi->tx_dma_complete, SLINK_DMA_TIMEOUT);
907 if (wait_status <= 0) {
908 dmaengine_terminate_all(tspi->tx_dma_chan);
909 dev_err(tspi->dev, "TxDma Xfer failed\n");
915 if (tspi->cur_direction & DATA_DIR_RX) {
916 if (tspi->rx_status) {
917 dmaengine_terminate_all(tspi->rx_dma_chan);
920 wait_status = wait_for_completion_interruptible_timeout(
921 &tspi->rx_dma_complete, SLINK_DMA_TIMEOUT);
922 if (wait_status <= 0) {
923 dmaengine_terminate_all(tspi->rx_dma_chan);
924 dev_err(tspi->dev, "RxDma Xfer failed\n");
930 spin_lock_irqsave(&tspi->lock, flags);
933 "DmaXfer: ERROR bit set 0x%x\n", tspi->status_reg);
935 "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
936 tspi->command2_reg, tspi->dma_control_reg);
937 reset_control_assert(tspi->rst);
939 reset_control_assert(tspi->rst);
940 complete(&tspi->xfer_completion);
941 spin_unlock_irqrestore(&tspi->lock, flags);
945 if (tspi->cur_direction & DATA_DIR_RX)
946 tegra_slink_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
948 if (tspi->cur_direction & DATA_DIR_TX)
949 tspi->cur_pos = tspi->cur_tx_pos;
951 tspi->cur_pos = tspi->cur_rx_pos;
953 if (tspi->cur_pos == t->len) {
954 complete(&tspi->xfer_completion);
958 /* Continue transfer in current message */
959 total_fifo_words = tegra_slink_calculate_curr_xfer_param(tspi->cur_spi,
961 if (total_fifo_words > SLINK_FIFO_DEPTH)
962 err = tegra_slink_start_dma_based_transfer(tspi, t);
964 err = tegra_slink_start_cpu_based_transfer(tspi, t);
967 spin_unlock_irqrestore(&tspi->lock, flags);
971 static irqreturn_t tegra_slink_isr_thread(int irq, void *context_data)
973 struct tegra_slink_data *tspi = context_data;
975 if (!tspi->is_curr_dma_xfer)
976 return handle_cpu_based_xfer(tspi);
977 return handle_dma_based_xfer(tspi);
980 static irqreturn_t tegra_slink_isr(int irq, void *context_data)
982 struct tegra_slink_data *tspi = context_data;
984 tspi->status_reg = tegra_slink_readl(tspi, SLINK_STATUS);
985 if (tspi->cur_direction & DATA_DIR_TX)
986 tspi->tx_status = tspi->status_reg &
987 (SLINK_TX_OVF | SLINK_TX_UNF);
989 if (tspi->cur_direction & DATA_DIR_RX)
990 tspi->rx_status = tspi->status_reg &
991 (SLINK_RX_OVF | SLINK_RX_UNF);
992 tegra_slink_clear_status(tspi);
994 return IRQ_WAKE_THREAD;
997 static const struct tegra_slink_chip_data tegra30_spi_cdata = {
998 .cs_hold_time = true,
1001 static const struct tegra_slink_chip_data tegra20_spi_cdata = {
1002 .cs_hold_time = false,
1005 static const struct of_device_id tegra_slink_of_match[] = {
1006 { .compatible = "nvidia,tegra30-slink", .data = &tegra30_spi_cdata, },
1007 { .compatible = "nvidia,tegra20-slink", .data = &tegra20_spi_cdata, },
1010 MODULE_DEVICE_TABLE(of, tegra_slink_of_match);
1012 static int tegra_slink_probe(struct platform_device *pdev)
1014 struct spi_master *master;
1015 struct tegra_slink_data *tspi;
1018 const struct tegra_slink_chip_data *cdata = NULL;
1019 const struct of_device_id *match;
1021 match = of_match_device(tegra_slink_of_match, &pdev->dev);
1023 dev_err(&pdev->dev, "Error: No device match found\n");
1026 cdata = match->data;
1028 master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
1030 dev_err(&pdev->dev, "master allocation failed\n");
1034 /* the spi->mode bits understood by this driver: */
1035 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1036 master->setup = tegra_slink_setup;
1037 master->prepare_message = tegra_slink_prepare_message;
1038 master->transfer_one = tegra_slink_transfer_one;
1039 master->unprepare_message = tegra_slink_unprepare_message;
1040 master->auto_runtime_pm = true;
1041 master->num_chipselect = MAX_CHIP_SELECT;
1043 platform_set_drvdata(pdev, master);
1044 tspi = spi_master_get_devdata(master);
1045 tspi->master = master;
1046 tspi->dev = &pdev->dev;
1047 tspi->chip_data = cdata;
1048 spin_lock_init(&tspi->lock);
1050 if (of_property_read_u32(tspi->dev->of_node, "spi-max-frequency",
1051 &master->max_speed_hz))
1052 master->max_speed_hz = 25000000; /* 25MHz */
1054 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1056 dev_err(&pdev->dev, "No IO memory resource\n");
1058 goto exit_free_master;
1060 tspi->phys = r->start;
1061 tspi->base = devm_ioremap_resource(&pdev->dev, r);
1062 if (IS_ERR(tspi->base)) {
1063 ret = PTR_ERR(tspi->base);
1064 goto exit_free_master;
1067 /* disabled clock may cause interrupt storm upon request */
1068 tspi->clk = devm_clk_get(&pdev->dev, NULL);
1069 if (IS_ERR(tspi->clk)) {
1070 ret = PTR_ERR(tspi->clk);
1071 dev_err(&pdev->dev, "Can not get clock %d\n", ret);
1072 goto exit_free_master;
1074 ret = clk_prepare(tspi->clk);
1076 dev_err(&pdev->dev, "Clock prepare failed %d\n", ret);
1077 goto exit_free_master;
1079 ret = clk_enable(tspi->clk);
1081 dev_err(&pdev->dev, "Clock enable failed %d\n", ret);
1082 goto exit_clk_unprepare;
1085 spi_irq = platform_get_irq(pdev, 0);
1086 tspi->irq = spi_irq;
1087 ret = request_threaded_irq(tspi->irq, tegra_slink_isr,
1088 tegra_slink_isr_thread, IRQF_ONESHOT,
1089 dev_name(&pdev->dev), tspi);
1091 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1093 goto exit_clk_disable;
1096 tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi");
1097 if (IS_ERR(tspi->rst)) {
1098 dev_err(&pdev->dev, "can not get reset\n");
1099 ret = PTR_ERR(tspi->rst);
1103 tspi->max_buf_size = SLINK_FIFO_DEPTH << 2;
1104 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1106 ret = tegra_slink_init_dma_param(tspi, true);
1109 ret = tegra_slink_init_dma_param(tspi, false);
1111 goto exit_rx_dma_free;
1112 tspi->max_buf_size = tspi->dma_buf_size;
1113 init_completion(&tspi->tx_dma_complete);
1114 init_completion(&tspi->rx_dma_complete);
1116 init_completion(&tspi->xfer_completion);
1118 pm_runtime_enable(&pdev->dev);
1119 if (!pm_runtime_enabled(&pdev->dev)) {
1120 ret = tegra_slink_runtime_resume(&pdev->dev);
1122 goto exit_pm_disable;
1125 ret = pm_runtime_get_sync(&pdev->dev);
1127 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
1128 goto exit_pm_disable;
1130 tspi->def_command_reg = SLINK_M_S;
1131 tspi->def_command2_reg = SLINK_CS_ACTIVE_BETWEEN;
1132 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
1133 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
1134 pm_runtime_put(&pdev->dev);
1136 master->dev.of_node = pdev->dev.of_node;
1137 ret = devm_spi_register_master(&pdev->dev, master);
1139 dev_err(&pdev->dev, "can not register to master err %d\n", ret);
1140 goto exit_pm_disable;
1145 pm_runtime_disable(&pdev->dev);
1146 if (!pm_runtime_status_suspended(&pdev->dev))
1147 tegra_slink_runtime_suspend(&pdev->dev);
1148 tegra_slink_deinit_dma_param(tspi, false);
1150 tegra_slink_deinit_dma_param(tspi, true);
1152 free_irq(spi_irq, tspi);
1154 clk_disable(tspi->clk);
1156 clk_unprepare(tspi->clk);
1158 spi_master_put(master);
1162 static int tegra_slink_remove(struct platform_device *pdev)
1164 struct spi_master *master = platform_get_drvdata(pdev);
1165 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1167 free_irq(tspi->irq, tspi);
1169 clk_disable(tspi->clk);
1170 clk_unprepare(tspi->clk);
1172 if (tspi->tx_dma_chan)
1173 tegra_slink_deinit_dma_param(tspi, false);
1175 if (tspi->rx_dma_chan)
1176 tegra_slink_deinit_dma_param(tspi, true);
1178 pm_runtime_disable(&pdev->dev);
1179 if (!pm_runtime_status_suspended(&pdev->dev))
1180 tegra_slink_runtime_suspend(&pdev->dev);
1185 #ifdef CONFIG_PM_SLEEP
1186 static int tegra_slink_suspend(struct device *dev)
1188 struct spi_master *master = dev_get_drvdata(dev);
1190 return spi_master_suspend(master);
1193 static int tegra_slink_resume(struct device *dev)
1195 struct spi_master *master = dev_get_drvdata(dev);
1196 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1199 ret = pm_runtime_get_sync(dev);
1201 pm_runtime_put_noidle(dev);
1202 dev_err(dev, "pm runtime failed, e = %d\n", ret);
1205 tegra_slink_writel(tspi, tspi->command_reg, SLINK_COMMAND);
1206 tegra_slink_writel(tspi, tspi->command2_reg, SLINK_COMMAND2);
1207 pm_runtime_put(dev);
1209 return spi_master_resume(master);
1213 static int __maybe_unused tegra_slink_runtime_suspend(struct device *dev)
1215 struct spi_master *master = dev_get_drvdata(dev);
1216 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1218 /* Flush all write which are in PPSB queue by reading back */
1219 tegra_slink_readl(tspi, SLINK_MAS_DATA);
1221 clk_disable_unprepare(tspi->clk);
1225 static int __maybe_unused tegra_slink_runtime_resume(struct device *dev)
1227 struct spi_master *master = dev_get_drvdata(dev);
1228 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1231 ret = clk_prepare_enable(tspi->clk);
1233 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1239 static const struct dev_pm_ops slink_pm_ops = {
1240 SET_RUNTIME_PM_OPS(tegra_slink_runtime_suspend,
1241 tegra_slink_runtime_resume, NULL)
1242 SET_SYSTEM_SLEEP_PM_OPS(tegra_slink_suspend, tegra_slink_resume)
1244 static struct platform_driver tegra_slink_driver = {
1246 .name = "spi-tegra-slink",
1247 .pm = &slink_pm_ops,
1248 .of_match_table = tegra_slink_of_match,
1250 .probe = tegra_slink_probe,
1251 .remove = tegra_slink_remove,
1253 module_platform_driver(tegra_slink_driver);
1255 MODULE_ALIAS("platform:spi-tegra-slink");
1256 MODULE_DESCRIPTION("NVIDIA Tegra20/Tegra30 SLINK Controller Driver");
1257 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1258 MODULE_LICENSE("GPL v2");