2 * Copyright (C) 2012 - 2014 Allwinner Tech
3 * Pan Nan <pannan@allwinnertech.com>
5 * Copyright (C) 2014 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/device.h>
17 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/reset.h>
25 #include <linux/spi/spi.h>
27 #define SUN6I_FIFO_DEPTH 128
28 #define SUN8I_FIFO_DEPTH 64
30 #define SUN6I_GBL_CTL_REG 0x04
31 #define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
32 #define SUN6I_GBL_CTL_MASTER BIT(1)
33 #define SUN6I_GBL_CTL_TP BIT(7)
34 #define SUN6I_GBL_CTL_RST BIT(31)
36 #define SUN6I_TFR_CTL_REG 0x08
37 #define SUN6I_TFR_CTL_CPHA BIT(0)
38 #define SUN6I_TFR_CTL_CPOL BIT(1)
39 #define SUN6I_TFR_CTL_SPOL BIT(2)
40 #define SUN6I_TFR_CTL_CS_MASK 0x30
41 #define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK)
42 #define SUN6I_TFR_CTL_CS_MANUAL BIT(6)
43 #define SUN6I_TFR_CTL_CS_LEVEL BIT(7)
44 #define SUN6I_TFR_CTL_DHB BIT(8)
45 #define SUN6I_TFR_CTL_FBS BIT(12)
46 #define SUN6I_TFR_CTL_XCH BIT(31)
48 #define SUN6I_INT_CTL_REG 0x10
49 #define SUN6I_INT_CTL_RF_RDY BIT(0)
50 #define SUN6I_INT_CTL_TF_ERQ BIT(4)
51 #define SUN6I_INT_CTL_RF_OVF BIT(8)
52 #define SUN6I_INT_CTL_TC BIT(12)
54 #define SUN6I_INT_STA_REG 0x14
56 #define SUN6I_FIFO_CTL_REG 0x18
57 #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff
58 #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0
59 #define SUN6I_FIFO_CTL_RF_RST BIT(15)
60 #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff
61 #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16
62 #define SUN6I_FIFO_CTL_TF_RST BIT(31)
64 #define SUN6I_FIFO_STA_REG 0x1c
65 #define SUN6I_FIFO_STA_RF_CNT_MASK 0x7f
66 #define SUN6I_FIFO_STA_RF_CNT_BITS 0
67 #define SUN6I_FIFO_STA_TF_CNT_MASK 0x7f
68 #define SUN6I_FIFO_STA_TF_CNT_BITS 16
70 #define SUN6I_CLK_CTL_REG 0x24
71 #define SUN6I_CLK_CTL_CDR2_MASK 0xff
72 #define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
73 #define SUN6I_CLK_CTL_CDR1_MASK 0xf
74 #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
75 #define SUN6I_CLK_CTL_DRS BIT(12)
77 #define SUN6I_MAX_XFER_SIZE 0xffffff
79 #define SUN6I_BURST_CNT_REG 0x30
80 #define SUN6I_BURST_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE)
82 #define SUN6I_XMIT_CNT_REG 0x34
83 #define SUN6I_XMIT_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE)
85 #define SUN6I_BURST_CTL_CNT_REG 0x38
86 #define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE)
88 #define SUN6I_TXDATA_REG 0x200
89 #define SUN6I_RXDATA_REG 0x300
92 struct spi_master *master;
93 void __iomem *base_addr;
96 struct reset_control *rstc;
98 struct completion done;
103 unsigned long fifo_depth;
106 static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
108 return readl(sspi->base_addr + reg);
111 static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
113 writel(value, sspi->base_addr + reg);
116 static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi)
118 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
120 reg >>= SUN6I_FIFO_STA_TF_CNT_BITS;
122 return reg & SUN6I_FIFO_STA_TF_CNT_MASK;
125 static inline void sun6i_spi_enable_interrupt(struct sun6i_spi *sspi, u32 mask)
127 u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
130 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
133 static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
135 u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
138 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
141 static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
146 /* See how much data is available */
147 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
148 reg &= SUN6I_FIFO_STA_RF_CNT_MASK;
149 cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS;
155 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
157 *sspi->rx_buf++ = byte;
161 static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
166 /* See how much data we can fit */
167 cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
169 len = min3(len, (int)cnt, sspi->len);
172 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
173 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
178 static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
180 struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
183 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
184 reg &= ~SUN6I_TFR_CTL_CS_MASK;
185 reg |= SUN6I_TFR_CTL_CS(spi->chip_select);
188 reg |= SUN6I_TFR_CTL_CS_LEVEL;
190 reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
192 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
195 static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
197 return SUN6I_MAX_XFER_SIZE - 1;
200 static int sun6i_spi_transfer_one(struct spi_master *master,
201 struct spi_device *spi,
202 struct spi_transfer *tfr)
204 struct sun6i_spi *sspi = spi_master_get_devdata(master);
205 unsigned int mclk_rate, div, div_cdr1, div_cdr2, timeout;
206 unsigned int start, end, tx_time;
207 unsigned int trig_level;
208 unsigned int tx_len = 0;
212 if (tfr->len > SUN6I_MAX_XFER_SIZE)
215 reinit_completion(&sspi->done);
216 sspi->tx_buf = tfr->tx_buf;
217 sspi->rx_buf = tfr->rx_buf;
218 sspi->len = tfr->len;
220 /* Clear pending interrupts */
221 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
224 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
225 SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
228 * Setup FIFO interrupt trigger level
229 * Here we choose 3/4 of the full fifo depth, as it's the hardcoded
230 * value used in old generation of Allwinner SPI controller.
233 trig_level = sspi->fifo_depth / 4 * 3;
234 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
235 (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) |
236 (trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS));
239 * Setup the transfer control register: Chip Select,
242 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
244 if (spi->mode & SPI_CPOL)
245 reg |= SUN6I_TFR_CTL_CPOL;
247 reg &= ~SUN6I_TFR_CTL_CPOL;
249 if (spi->mode & SPI_CPHA)
250 reg |= SUN6I_TFR_CTL_CPHA;
252 reg &= ~SUN6I_TFR_CTL_CPHA;
254 if (spi->mode & SPI_LSB_FIRST)
255 reg |= SUN6I_TFR_CTL_FBS;
257 reg &= ~SUN6I_TFR_CTL_FBS;
260 * If it's a TX only transfer, we don't want to fill the RX
261 * FIFO with bogus data
264 reg &= ~SUN6I_TFR_CTL_DHB;
266 reg |= SUN6I_TFR_CTL_DHB;
268 /* We want to control the chip select manually */
269 reg |= SUN6I_TFR_CTL_CS_MANUAL;
271 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
273 /* Ensure that we have a parent clock fast enough */
274 mclk_rate = clk_get_rate(sspi->mclk);
275 if (mclk_rate < (2 * tfr->speed_hz)) {
276 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
277 mclk_rate = clk_get_rate(sspi->mclk);
281 * Setup clock divider.
283 * We have two choices there. Either we can use the clock
284 * divide rate 1, which is calculated thanks to this formula:
285 * SPI_CLK = MOD_CLK / (2 ^ cdr)
286 * Or we can use CDR2, which is calculated with the formula:
287 * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
288 * Wether we use the former or the latter is set through the
291 * First try CDR2, and if we can't reach the expected
292 * frequency, fall back to CDR1.
294 div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz);
295 div_cdr2 = DIV_ROUND_UP(div_cdr1, 2);
296 if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
297 reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS;
299 div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1));
300 reg = SUN6I_CLK_CTL_CDR1(div);
303 sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
304 /* Finally enable the bus - doing so before might raise SCK to HIGH */
305 reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG);
306 reg |= SUN6I_GBL_CTL_BUS_ENABLE;
307 sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg);
309 /* Setup the transfer now... */
313 /* Setup the counters */
314 sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len));
315 sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len));
316 sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG,
317 SUN6I_BURST_CTL_CNT_STC(tx_len));
319 /* Fill the TX FIFO */
320 sun6i_spi_fill_fifo(sspi, sspi->fifo_depth);
322 /* Enable the interrupts */
323 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
324 sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TC |
325 SUN6I_INT_CTL_RF_RDY);
326 if (tx_len > sspi->fifo_depth)
327 sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
329 /* Start the transfer */
330 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
331 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
333 tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
335 timeout = wait_for_completion_timeout(&sspi->done,
336 msecs_to_jiffies(tx_time));
339 dev_warn(&master->dev,
340 "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
341 dev_name(&spi->dev), tfr->len, tfr->speed_hz,
342 jiffies_to_msecs(end - start), tx_time);
348 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
353 static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
355 struct sun6i_spi *sspi = dev_id;
356 u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
358 /* Transfer complete */
359 if (status & SUN6I_INT_CTL_TC) {
360 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
361 sun6i_spi_drain_fifo(sspi, sspi->fifo_depth);
362 complete(&sspi->done);
366 /* Receive FIFO 3/4 full */
367 if (status & SUN6I_INT_CTL_RF_RDY) {
368 sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
369 /* Only clear the interrupt _after_ draining the FIFO */
370 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY);
374 /* Transmit FIFO 3/4 empty */
375 if (status & SUN6I_INT_CTL_TF_ERQ) {
376 sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);
379 /* nothing left to transmit */
380 sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
382 /* Only clear the interrupt _after_ re-seeding the FIFO */
383 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ);
391 static int sun6i_spi_runtime_resume(struct device *dev)
393 struct spi_master *master = dev_get_drvdata(dev);
394 struct sun6i_spi *sspi = spi_master_get_devdata(master);
397 ret = clk_prepare_enable(sspi->hclk);
399 dev_err(dev, "Couldn't enable AHB clock\n");
403 ret = clk_prepare_enable(sspi->mclk);
405 dev_err(dev, "Couldn't enable module clock\n");
409 ret = reset_control_deassert(sspi->rstc);
411 dev_err(dev, "Couldn't deassert the device from reset\n");
415 sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
416 SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
421 clk_disable_unprepare(sspi->mclk);
423 clk_disable_unprepare(sspi->hclk);
428 static int sun6i_spi_runtime_suspend(struct device *dev)
430 struct spi_master *master = dev_get_drvdata(dev);
431 struct sun6i_spi *sspi = spi_master_get_devdata(master);
433 reset_control_assert(sspi->rstc);
434 clk_disable_unprepare(sspi->mclk);
435 clk_disable_unprepare(sspi->hclk);
440 static int sun6i_spi_probe(struct platform_device *pdev)
442 struct spi_master *master;
443 struct sun6i_spi *sspi;
444 struct resource *res;
447 master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
449 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
453 platform_set_drvdata(pdev, master);
454 sspi = spi_master_get_devdata(master);
456 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
457 sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
458 if (IS_ERR(sspi->base_addr)) {
459 ret = PTR_ERR(sspi->base_addr);
460 goto err_free_master;
463 irq = platform_get_irq(pdev, 0);
465 dev_err(&pdev->dev, "No spi IRQ specified\n");
467 goto err_free_master;
470 ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
471 0, "sun6i-spi", sspi);
473 dev_err(&pdev->dev, "Cannot request IRQ\n");
474 goto err_free_master;
477 sspi->master = master;
478 sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev);
480 master->max_speed_hz = 100 * 1000 * 1000;
481 master->min_speed_hz = 3 * 1000;
482 master->set_cs = sun6i_spi_set_cs;
483 master->transfer_one = sun6i_spi_transfer_one;
484 master->num_chipselect = 4;
485 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
486 master->bits_per_word_mask = SPI_BPW_MASK(8);
487 master->dev.of_node = pdev->dev.of_node;
488 master->auto_runtime_pm = true;
489 master->max_transfer_size = sun6i_spi_max_transfer_size;
491 sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
492 if (IS_ERR(sspi->hclk)) {
493 dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
494 ret = PTR_ERR(sspi->hclk);
495 goto err_free_master;
498 sspi->mclk = devm_clk_get(&pdev->dev, "mod");
499 if (IS_ERR(sspi->mclk)) {
500 dev_err(&pdev->dev, "Unable to acquire module clock\n");
501 ret = PTR_ERR(sspi->mclk);
502 goto err_free_master;
505 init_completion(&sspi->done);
507 sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
508 if (IS_ERR(sspi->rstc)) {
509 dev_err(&pdev->dev, "Couldn't get reset controller\n");
510 ret = PTR_ERR(sspi->rstc);
511 goto err_free_master;
515 * This wake-up/shutdown pattern is to be able to have the
516 * device woken up, even if runtime_pm is disabled
518 ret = sun6i_spi_runtime_resume(&pdev->dev);
520 dev_err(&pdev->dev, "Couldn't resume the device\n");
521 goto err_free_master;
524 pm_runtime_set_active(&pdev->dev);
525 pm_runtime_enable(&pdev->dev);
526 pm_runtime_idle(&pdev->dev);
528 ret = devm_spi_register_master(&pdev->dev, master);
530 dev_err(&pdev->dev, "cannot register SPI master\n");
537 pm_runtime_disable(&pdev->dev);
538 sun6i_spi_runtime_suspend(&pdev->dev);
540 spi_master_put(master);
544 static int sun6i_spi_remove(struct platform_device *pdev)
546 pm_runtime_force_suspend(&pdev->dev);
551 static const struct of_device_id sun6i_spi_match[] = {
552 { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH },
553 { .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH },
556 MODULE_DEVICE_TABLE(of, sun6i_spi_match);
558 static const struct dev_pm_ops sun6i_spi_pm_ops = {
559 .runtime_resume = sun6i_spi_runtime_resume,
560 .runtime_suspend = sun6i_spi_runtime_suspend,
563 static struct platform_driver sun6i_spi_driver = {
564 .probe = sun6i_spi_probe,
565 .remove = sun6i_spi_remove,
568 .of_match_table = sun6i_spi_match,
569 .pm = &sun6i_spi_pm_ops,
572 module_platform_driver(sun6i_spi_driver);
574 MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
575 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
576 MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
577 MODULE_LICENSE("GPL");