1 // SPDX-License-Identifier: GPL-2.0
3 // STMicroelectronics STM32 SPI Controller driver
5 // Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 // Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics.
8 #include <linux/bitfield.h>
9 #include <linux/debugfs.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/dmaengine.h>
13 #include <linux/interrupt.h>
14 #include <linux/iopoll.h>
15 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/reset.h>
21 #include <linux/spi/spi.h>
23 #define DRIVER_NAME "spi_stm32"
25 /* STM32F4 SPI registers */
26 #define STM32F4_SPI_CR1 0x00
27 #define STM32F4_SPI_CR2 0x04
28 #define STM32F4_SPI_SR 0x08
29 #define STM32F4_SPI_DR 0x0C
30 #define STM32F4_SPI_I2SCFGR 0x1C
32 /* STM32F4_SPI_CR1 bit fields */
33 #define STM32F4_SPI_CR1_CPHA BIT(0)
34 #define STM32F4_SPI_CR1_CPOL BIT(1)
35 #define STM32F4_SPI_CR1_MSTR BIT(2)
36 #define STM32F4_SPI_CR1_BR_SHIFT 3
37 #define STM32F4_SPI_CR1_BR GENMASK(5, 3)
38 #define STM32F4_SPI_CR1_SPE BIT(6)
39 #define STM32F4_SPI_CR1_LSBFRST BIT(7)
40 #define STM32F4_SPI_CR1_SSI BIT(8)
41 #define STM32F4_SPI_CR1_SSM BIT(9)
42 #define STM32F4_SPI_CR1_RXONLY BIT(10)
43 #define STM32F4_SPI_CR1_DFF BIT(11)
44 #define STM32F4_SPI_CR1_CRCNEXT BIT(12)
45 #define STM32F4_SPI_CR1_CRCEN BIT(13)
46 #define STM32F4_SPI_CR1_BIDIOE BIT(14)
47 #define STM32F4_SPI_CR1_BIDIMODE BIT(15)
48 #define STM32F4_SPI_CR1_BR_MIN 0
49 #define STM32F4_SPI_CR1_BR_MAX (GENMASK(5, 3) >> 3)
51 /* STM32F4_SPI_CR2 bit fields */
52 #define STM32F4_SPI_CR2_RXDMAEN BIT(0)
53 #define STM32F4_SPI_CR2_TXDMAEN BIT(1)
54 #define STM32F4_SPI_CR2_SSOE BIT(2)
55 #define STM32F4_SPI_CR2_FRF BIT(4)
56 #define STM32F4_SPI_CR2_ERRIE BIT(5)
57 #define STM32F4_SPI_CR2_RXNEIE BIT(6)
58 #define STM32F4_SPI_CR2_TXEIE BIT(7)
60 /* STM32F4_SPI_SR bit fields */
61 #define STM32F4_SPI_SR_RXNE BIT(0)
62 #define STM32F4_SPI_SR_TXE BIT(1)
63 #define STM32F4_SPI_SR_CHSIDE BIT(2)
64 #define STM32F4_SPI_SR_UDR BIT(3)
65 #define STM32F4_SPI_SR_CRCERR BIT(4)
66 #define STM32F4_SPI_SR_MODF BIT(5)
67 #define STM32F4_SPI_SR_OVR BIT(6)
68 #define STM32F4_SPI_SR_BSY BIT(7)
69 #define STM32F4_SPI_SR_FRE BIT(8)
71 /* STM32F4_SPI_I2SCFGR bit fields */
72 #define STM32F4_SPI_I2SCFGR_I2SMOD BIT(11)
74 /* STM32F4 SPI Baud Rate min/max divisor */
75 #define STM32F4_SPI_BR_DIV_MIN (2 << STM32F4_SPI_CR1_BR_MIN)
76 #define STM32F4_SPI_BR_DIV_MAX (2 << STM32F4_SPI_CR1_BR_MAX)
78 /* STM32H7 SPI registers */
79 #define STM32H7_SPI_CR1 0x00
80 #define STM32H7_SPI_CR2 0x04
81 #define STM32H7_SPI_CFG1 0x08
82 #define STM32H7_SPI_CFG2 0x0C
83 #define STM32H7_SPI_IER 0x10
84 #define STM32H7_SPI_SR 0x14
85 #define STM32H7_SPI_IFCR 0x18
86 #define STM32H7_SPI_TXDR 0x20
87 #define STM32H7_SPI_RXDR 0x30
88 #define STM32H7_SPI_I2SCFGR 0x50
90 /* STM32H7_SPI_CR1 bit fields */
91 #define STM32H7_SPI_CR1_SPE BIT(0)
92 #define STM32H7_SPI_CR1_MASRX BIT(8)
93 #define STM32H7_SPI_CR1_CSTART BIT(9)
94 #define STM32H7_SPI_CR1_CSUSP BIT(10)
95 #define STM32H7_SPI_CR1_HDDIR BIT(11)
96 #define STM32H7_SPI_CR1_SSI BIT(12)
98 /* STM32H7_SPI_CR2 bit fields */
99 #define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0)
100 #define STM32H7_SPI_TSIZE_MAX GENMASK(15, 0)
102 /* STM32H7_SPI_CFG1 bit fields */
103 #define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0)
104 #define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5)
105 #define STM32H7_SPI_CFG1_RXDMAEN BIT(14)
106 #define STM32H7_SPI_CFG1_TXDMAEN BIT(15)
107 #define STM32H7_SPI_CFG1_MBR GENMASK(30, 28)
108 #define STM32H7_SPI_CFG1_MBR_SHIFT 28
109 #define STM32H7_SPI_CFG1_MBR_MIN 0
110 #define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
112 /* STM32H7_SPI_CFG2 bit fields */
113 #define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4)
114 #define STM32H7_SPI_CFG2_COMM GENMASK(18, 17)
115 #define STM32H7_SPI_CFG2_SP GENMASK(21, 19)
116 #define STM32H7_SPI_CFG2_MASTER BIT(22)
117 #define STM32H7_SPI_CFG2_LSBFRST BIT(23)
118 #define STM32H7_SPI_CFG2_CPHA BIT(24)
119 #define STM32H7_SPI_CFG2_CPOL BIT(25)
120 #define STM32H7_SPI_CFG2_SSM BIT(26)
121 #define STM32H7_SPI_CFG2_SSIOP BIT(28)
122 #define STM32H7_SPI_CFG2_AFCNTR BIT(31)
124 /* STM32H7_SPI_IER bit fields */
125 #define STM32H7_SPI_IER_RXPIE BIT(0)
126 #define STM32H7_SPI_IER_TXPIE BIT(1)
127 #define STM32H7_SPI_IER_DXPIE BIT(2)
128 #define STM32H7_SPI_IER_EOTIE BIT(3)
129 #define STM32H7_SPI_IER_TXTFIE BIT(4)
130 #define STM32H7_SPI_IER_OVRIE BIT(6)
131 #define STM32H7_SPI_IER_MODFIE BIT(9)
132 #define STM32H7_SPI_IER_ALL GENMASK(10, 0)
134 /* STM32H7_SPI_SR bit fields */
135 #define STM32H7_SPI_SR_RXP BIT(0)
136 #define STM32H7_SPI_SR_TXP BIT(1)
137 #define STM32H7_SPI_SR_EOT BIT(3)
138 #define STM32H7_SPI_SR_OVR BIT(6)
139 #define STM32H7_SPI_SR_MODF BIT(9)
140 #define STM32H7_SPI_SR_SUSP BIT(11)
141 #define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13)
142 #define STM32H7_SPI_SR_RXWNE BIT(15)
144 /* STM32H7_SPI_IFCR bit fields */
145 #define STM32H7_SPI_IFCR_ALL GENMASK(11, 3)
147 /* STM32H7_SPI_I2SCFGR bit fields */
148 #define STM32H7_SPI_I2SCFGR_I2SMOD BIT(0)
150 /* STM32H7 SPI Master Baud Rate min/max divisor */
151 #define STM32H7_SPI_MBR_DIV_MIN (2 << STM32H7_SPI_CFG1_MBR_MIN)
152 #define STM32H7_SPI_MBR_DIV_MAX (2 << STM32H7_SPI_CFG1_MBR_MAX)
154 /* STM32H7 SPI Communication mode */
155 #define STM32H7_SPI_FULL_DUPLEX 0
156 #define STM32H7_SPI_SIMPLEX_TX 1
157 #define STM32H7_SPI_SIMPLEX_RX 2
158 #define STM32H7_SPI_HALF_DUPLEX 3
160 /* SPI Communication type */
161 #define SPI_FULL_DUPLEX 0
162 #define SPI_SIMPLEX_TX 1
163 #define SPI_SIMPLEX_RX 2
164 #define SPI_3WIRE_TX 3
165 #define SPI_3WIRE_RX 4
167 #define STM32_SPI_AUTOSUSPEND_DELAY 1 /* 1 ms */
170 * use PIO for small transfers, avoiding DMA setup/teardown overhead for drivers
171 * without fifo buffers.
173 #define SPI_DMA_MIN_BYTES 16
175 /* STM32 SPI driver helpers */
176 #define STM32_SPI_MASTER_MODE(stm32_spi) (!(stm32_spi)->device_mode)
177 #define STM32_SPI_DEVICE_MODE(stm32_spi) ((stm32_spi)->device_mode)
180 * struct stm32_spi_reg - stm32 SPI register & bitfield desc
181 * @reg: register offset
182 * @mask: bitfield mask
185 struct stm32_spi_reg {
192 * struct stm32_spi_regspec - stm32 registers definition, compatible dependent data
193 * @en: enable register and SPI enable bit
194 * @dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit
195 * @dma_tx_en: SPI DMA TX enable register end SPI DMA TX enable bit
196 * @cpol: clock polarity register and polarity bit
197 * @cpha: clock phase register and phase bit
198 * @lsb_first: LSB transmitted first register and bit
199 * @cs_high: chips select active value
200 * @br: baud rate register and bitfields
201 * @rx: SPI RX data register
202 * @tx: SPI TX data register
204 struct stm32_spi_regspec {
205 const struct stm32_spi_reg en;
206 const struct stm32_spi_reg dma_rx_en;
207 const struct stm32_spi_reg dma_tx_en;
208 const struct stm32_spi_reg cpol;
209 const struct stm32_spi_reg cpha;
210 const struct stm32_spi_reg lsb_first;
211 const struct stm32_spi_reg cs_high;
212 const struct stm32_spi_reg br;
213 const struct stm32_spi_reg rx;
214 const struct stm32_spi_reg tx;
220 * struct stm32_spi_cfg - stm32 compatible configuration data
221 * @regs: registers descriptions
222 * @get_fifo_size: routine to get fifo size
223 * @get_bpw_mask: routine to get bits per word mask
224 * @disable: routine to disable controller
225 * @config: routine to configure controller as SPI Master
226 * @set_bpw: routine to configure registers to for bits per word
227 * @set_mode: routine to configure registers to desired mode
228 * @set_data_idleness: optional routine to configure registers to desired idle
229 * time between frames (if driver has this functionality)
230 * @set_number_of_data: optional routine to configure registers to desired
231 * number of data (if driver has this functionality)
232 * @transfer_one_dma_start: routine to start transfer a single spi_transfer
234 * @dma_rx_cb: routine to call after DMA RX channel operation is complete
235 * @dma_tx_cb: routine to call after DMA TX channel operation is complete
236 * @transfer_one_irq: routine to configure interrupts for driver
237 * @irq_handler_event: Interrupt handler for SPI controller events
238 * @irq_handler_thread: thread of interrupt handler for SPI controller
239 * @baud_rate_div_min: minimum baud rate divisor
240 * @baud_rate_div_max: maximum baud rate divisor
241 * @has_fifo: boolean to know if fifo is used for driver
242 * @has_device_mode: is this compatible capable to switch on device mode
243 * @flags: compatible specific SPI controller flags used at registration time
245 struct stm32_spi_cfg {
246 const struct stm32_spi_regspec *regs;
247 int (*get_fifo_size)(struct stm32_spi *spi);
248 int (*get_bpw_mask)(struct stm32_spi *spi);
249 void (*disable)(struct stm32_spi *spi);
250 int (*config)(struct stm32_spi *spi);
251 void (*set_bpw)(struct stm32_spi *spi);
252 int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type);
253 void (*set_data_idleness)(struct stm32_spi *spi, u32 length);
254 int (*set_number_of_data)(struct stm32_spi *spi, u32 length);
255 void (*transfer_one_dma_start)(struct stm32_spi *spi);
256 void (*dma_rx_cb)(void *data);
257 void (*dma_tx_cb)(void *data);
258 int (*transfer_one_irq)(struct stm32_spi *spi);
259 irqreturn_t (*irq_handler_event)(int irq, void *dev_id);
260 irqreturn_t (*irq_handler_thread)(int irq, void *dev_id);
261 unsigned int baud_rate_div_min;
262 unsigned int baud_rate_div_max;
264 bool has_device_mode;
269 * struct stm32_spi - private data of the SPI controller
270 * @dev: driver model representation of the controller
271 * @ctrl: controller interface
272 * @cfg: compatible configuration data
273 * @base: virtual memory area
274 * @clk: hw kernel clock feeding the SPI clock generator
275 * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
276 * @lock: prevent I/O concurrent access
277 * @irq: SPI controller interrupt line
278 * @fifo_size: size of the embedded fifo in bytes
279 * @cur_midi: master inter-data idleness in ns
280 * @cur_speed: speed configured in Hz
281 * @cur_half_period: time of a half bit in us
282 * @cur_bpw: number of bits in a single SPI data frame
283 * @cur_fthlv: fifo threshold level (data frames in a single data packet)
284 * @cur_comm: SPI communication mode
285 * @cur_xferlen: current transfer length in bytes
286 * @cur_usedma: boolean to know if dma is used in current transfer
287 * @tx_buf: data to be written, or NULL
288 * @rx_buf: data to be read, or NULL
289 * @tx_len: number of data to be written in bytes
290 * @rx_len: number of data to be read in bytes
291 * @dma_tx: dma channel for TX transfer
292 * @dma_rx: dma channel for RX transfer
293 * @phys_addr: SPI registers physical base address
294 * @device_mode: the controller is configured as SPI device
298 struct spi_controller *ctrl;
299 const struct stm32_spi_cfg *cfg;
303 spinlock_t lock; /* prevent I/O concurrent access */
305 unsigned int fifo_size;
307 unsigned int cur_midi;
308 unsigned int cur_speed;
309 unsigned int cur_half_period;
310 unsigned int cur_bpw;
311 unsigned int cur_fthlv;
312 unsigned int cur_comm;
313 unsigned int cur_xferlen;
320 struct dma_chan *dma_tx;
321 struct dma_chan *dma_rx;
322 dma_addr_t phys_addr;
327 static const struct stm32_spi_regspec stm32f4_spi_regspec = {
328 .en = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE },
330 .dma_rx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_RXDMAEN },
331 .dma_tx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN },
333 .cpol = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPOL },
334 .cpha = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPHA },
335 .lsb_first = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_LSBFRST },
337 .br = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_BR, STM32F4_SPI_CR1_BR_SHIFT },
339 .rx = { STM32F4_SPI_DR },
340 .tx = { STM32F4_SPI_DR },
343 static const struct stm32_spi_regspec stm32h7_spi_regspec = {
344 /* SPI data transfer is enabled but spi_ker_ck is idle.
345 * CFG1 and CFG2 registers are write protected when SPE is enabled.
347 .en = { STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE },
349 .dma_rx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN },
350 .dma_tx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN },
352 .cpol = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPOL },
353 .cpha = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPHA },
354 .lsb_first = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_LSBFRST },
355 .cs_high = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_SSIOP },
356 .br = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_MBR,
357 STM32H7_SPI_CFG1_MBR_SHIFT },
359 .rx = { STM32H7_SPI_RXDR },
360 .tx = { STM32H7_SPI_TXDR },
363 static inline void stm32_spi_set_bits(struct stm32_spi *spi,
364 u32 offset, u32 bits)
366 writel_relaxed(readl_relaxed(spi->base + offset) | bits,
370 static inline void stm32_spi_clr_bits(struct stm32_spi *spi,
371 u32 offset, u32 bits)
373 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits,
378 * stm32h7_spi_get_fifo_size - Return fifo size
379 * @spi: pointer to the spi controller data structure
381 static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi)
386 spin_lock_irqsave(&spi->lock, flags);
388 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
390 while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP)
391 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR);
393 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
395 spin_unlock_irqrestore(&spi->lock, flags);
397 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count);
403 * stm32f4_spi_get_bpw_mask - Return bits per word mask
404 * @spi: pointer to the spi controller data structure
406 static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi)
408 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n");
409 return SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
413 * stm32h7_spi_get_bpw_mask - Return bits per word mask
414 * @spi: pointer to the spi controller data structure
416 static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi)
421 spin_lock_irqsave(&spi->lock, flags);
424 * The most significant bit at DSIZE bit field is reserved when the
425 * maximum data size of periperal instances is limited to 16-bit
427 stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
429 cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
430 max_bpw = FIELD_GET(STM32H7_SPI_CFG1_DSIZE, cfg1) + 1;
432 spin_unlock_irqrestore(&spi->lock, flags);
434 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw);
436 return SPI_BPW_RANGE_MASK(4, max_bpw);
440 * stm32_spi_prepare_mbr - Determine baud rate divisor value
441 * @spi: pointer to the spi controller data structure
442 * @speed_hz: requested speed
443 * @min_div: minimum baud rate divisor
444 * @max_div: maximum baud rate divisor
446 * Return baud rate divisor value in case of success or -EINVAL
448 static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
449 u32 min_div, u32 max_div)
453 /* Ensure spi->clk_rate is even */
454 div = DIV_ROUND_CLOSEST(spi->clk_rate & ~0x1, speed_hz);
457 * SPI framework set xfer->speed_hz to ctrl->max_speed_hz if
458 * xfer->speed_hz is greater than ctrl->max_speed_hz, and it returns
459 * an error when xfer->speed_hz is lower than ctrl->min_speed_hz, so
460 * no need to check it there.
461 * However, we need to ensure the following calculations.
463 if ((div < min_div) || (div > max_div))
466 /* Determine the first power of 2 greater than or equal to div */
470 mbrdiv = fls(div) - 1;
472 spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
474 spi->cur_half_period = DIV_ROUND_CLOSEST(USEC_PER_SEC, 2 * spi->cur_speed);
480 * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
481 * @spi: pointer to the spi controller data structure
482 * @xfer_len: length of the message to be transferred
484 static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
488 /* data packet should not exceed 1/2 of fifo space */
489 packet = clamp(xfer_len, 1U, spi->fifo_size / 2);
491 /* align packet size with data registers access */
492 bpw = DIV_ROUND_UP(spi->cur_bpw, 8);
493 return DIV_ROUND_UP(packet, bpw);
497 * stm32f4_spi_write_tx - Write bytes to Transmit Data Register
498 * @spi: pointer to the spi controller data structure
500 * Read from tx_buf depends on remaining bytes to avoid to read beyond
503 static void stm32f4_spi_write_tx(struct stm32_spi *spi)
505 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
506 STM32F4_SPI_SR_TXE)) {
507 u32 offs = spi->cur_xferlen - spi->tx_len;
509 if (spi->cur_bpw == 16) {
510 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
512 writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR);
513 spi->tx_len -= sizeof(u16);
515 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
517 writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR);
518 spi->tx_len -= sizeof(u8);
522 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
526 * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register
527 * @spi: pointer to the spi controller data structure
529 * Read from tx_buf depends on remaining bytes to avoid to read beyond
532 static void stm32h7_spi_write_txfifo(struct stm32_spi *spi)
534 while ((spi->tx_len > 0) &&
535 (readl_relaxed(spi->base + STM32H7_SPI_SR) &
536 STM32H7_SPI_SR_TXP)) {
537 u32 offs = spi->cur_xferlen - spi->tx_len;
539 if (spi->tx_len >= sizeof(u32)) {
540 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs);
542 writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR);
543 spi->tx_len -= sizeof(u32);
544 } else if (spi->tx_len >= sizeof(u16)) {
545 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
547 writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR);
548 spi->tx_len -= sizeof(u16);
550 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
552 writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR);
553 spi->tx_len -= sizeof(u8);
557 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
561 * stm32f4_spi_read_rx - Read bytes from Receive Data Register
562 * @spi: pointer to the spi controller data structure
564 * Write in rx_buf depends on remaining bytes to avoid to write beyond
567 static void stm32f4_spi_read_rx(struct stm32_spi *spi)
569 if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
570 STM32F4_SPI_SR_RXNE)) {
571 u32 offs = spi->cur_xferlen - spi->rx_len;
573 if (spi->cur_bpw == 16) {
574 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
576 *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR);
577 spi->rx_len -= sizeof(u16);
579 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
581 *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR);
582 spi->rx_len -= sizeof(u8);
586 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len);
590 * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register
591 * @spi: pointer to the spi controller data structure
593 * Write in rx_buf depends on remaining bytes to avoid to write beyond
596 static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi)
598 u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
599 u32 rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
601 while ((spi->rx_len > 0) &&
602 ((sr & STM32H7_SPI_SR_RXP) ||
603 ((sr & STM32H7_SPI_SR_EOT) &&
604 ((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) {
605 u32 offs = spi->cur_xferlen - spi->rx_len;
607 if ((spi->rx_len >= sizeof(u32)) ||
608 (sr & STM32H7_SPI_SR_RXWNE)) {
609 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs);
611 *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR);
612 spi->rx_len -= sizeof(u32);
613 } else if ((spi->rx_len >= sizeof(u16)) ||
614 (!(sr & STM32H7_SPI_SR_RXWNE) &&
615 (rxplvl >= 2 || spi->cur_bpw > 8))) {
616 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
618 *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR);
619 spi->rx_len -= sizeof(u16);
621 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
623 *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR);
624 spi->rx_len -= sizeof(u8);
627 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
628 rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
631 dev_dbg(spi->dev, "%s: %d bytes left (sr=%08x)\n",
632 __func__, spi->rx_len, sr);
636 * stm32_spi_enable - Enable SPI controller
637 * @spi: pointer to the spi controller data structure
639 static void stm32_spi_enable(struct stm32_spi *spi)
641 dev_dbg(spi->dev, "enable controller\n");
643 stm32_spi_set_bits(spi, spi->cfg->regs->en.reg,
644 spi->cfg->regs->en.mask);
648 * stm32f4_spi_disable - Disable SPI controller
649 * @spi: pointer to the spi controller data structure
651 static void stm32f4_spi_disable(struct stm32_spi *spi)
656 dev_dbg(spi->dev, "disable controller\n");
658 spin_lock_irqsave(&spi->lock, flags);
660 if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) &
661 STM32F4_SPI_CR1_SPE)) {
662 spin_unlock_irqrestore(&spi->lock, flags);
666 /* Disable interrupts */
667 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXEIE |
668 STM32F4_SPI_CR2_RXNEIE |
669 STM32F4_SPI_CR2_ERRIE);
671 /* Wait until BSY = 0 */
672 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR,
673 sr, !(sr & STM32F4_SPI_SR_BSY),
675 dev_warn(spi->dev, "disabling condition timeout\n");
678 if (spi->cur_usedma && spi->dma_tx)
679 dmaengine_terminate_async(spi->dma_tx);
680 if (spi->cur_usedma && spi->dma_rx)
681 dmaengine_terminate_async(spi->dma_rx);
683 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE);
685 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN |
686 STM32F4_SPI_CR2_RXDMAEN);
688 /* Sequence to clear OVR flag */
689 readl_relaxed(spi->base + STM32F4_SPI_DR);
690 readl_relaxed(spi->base + STM32F4_SPI_SR);
692 spin_unlock_irqrestore(&spi->lock, flags);
696 * stm32h7_spi_disable - Disable SPI controller
697 * @spi: pointer to the spi controller data structure
699 * RX-Fifo is flushed when SPI controller is disabled.
701 static void stm32h7_spi_disable(struct stm32_spi *spi)
706 dev_dbg(spi->dev, "disable controller\n");
708 spin_lock_irqsave(&spi->lock, flags);
710 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1);
712 if (!(cr1 & STM32H7_SPI_CR1_SPE)) {
713 spin_unlock_irqrestore(&spi->lock, flags);
717 /* Add a delay to make sure that transmission is ended. */
718 if (spi->cur_half_period)
719 udelay(spi->cur_half_period);
721 if (spi->cur_usedma && spi->dma_tx)
722 dmaengine_terminate_async(spi->dma_tx);
723 if (spi->cur_usedma && spi->dma_rx)
724 dmaengine_terminate_async(spi->dma_rx);
726 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
728 stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN |
729 STM32H7_SPI_CFG1_RXDMAEN);
731 /* Disable interrupts and clear status flags */
732 writel_relaxed(0, spi->base + STM32H7_SPI_IER);
733 writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR);
735 spin_unlock_irqrestore(&spi->lock, flags);
739 * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
740 * @ctrl: controller interface
741 * @spi_dev: pointer to the spi device
742 * @transfer: pointer to spi transfer
744 * If driver has fifo and the current transfer size is greater than fifo size,
745 * use DMA. Otherwise use DMA for transfer longer than defined DMA min bytes.
747 static bool stm32_spi_can_dma(struct spi_controller *ctrl,
748 struct spi_device *spi_dev,
749 struct spi_transfer *transfer)
751 unsigned int dma_size;
752 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
754 if (spi->cfg->has_fifo)
755 dma_size = spi->fifo_size;
757 dma_size = SPI_DMA_MIN_BYTES;
759 dev_dbg(spi->dev, "%s: %s\n", __func__,
760 (transfer->len > dma_size) ? "true" : "false");
762 return (transfer->len > dma_size);
766 * stm32f4_spi_irq_event - Interrupt handler for SPI controller events
767 * @irq: interrupt line
768 * @dev_id: SPI controller ctrl interface
770 static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id)
772 struct spi_controller *ctrl = dev_id;
773 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
777 spin_lock(&spi->lock);
779 sr = readl_relaxed(spi->base + STM32F4_SPI_SR);
781 * BSY flag is not handled in interrupt but it is normal behavior when
784 sr &= ~STM32F4_SPI_SR_BSY;
786 if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX ||
787 spi->cur_comm == SPI_3WIRE_TX)) {
788 /* OVR flag shouldn't be handled for TX only mode */
789 sr &= ~(STM32F4_SPI_SR_OVR | STM32F4_SPI_SR_RXNE);
790 mask |= STM32F4_SPI_SR_TXE;
793 if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX ||
794 spi->cur_comm == SPI_SIMPLEX_RX ||
795 spi->cur_comm == SPI_3WIRE_RX)) {
796 /* TXE flag is set and is handled when RXNE flag occurs */
797 sr &= ~STM32F4_SPI_SR_TXE;
798 mask |= STM32F4_SPI_SR_RXNE | STM32F4_SPI_SR_OVR;
802 dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr);
803 spin_unlock(&spi->lock);
807 if (sr & STM32F4_SPI_SR_OVR) {
808 dev_warn(spi->dev, "Overrun: received value discarded\n");
810 /* Sequence to clear OVR flag */
811 readl_relaxed(spi->base + STM32F4_SPI_DR);
812 readl_relaxed(spi->base + STM32F4_SPI_SR);
815 * If overrun is detected, it means that something went wrong,
816 * so stop the current transfer. Transfer can wait for next
817 * RXNE but DR is already read and end never happens.
823 if (sr & STM32F4_SPI_SR_TXE) {
825 stm32f4_spi_write_tx(spi);
826 if (spi->tx_len == 0)
830 if (sr & STM32F4_SPI_SR_RXNE) {
831 stm32f4_spi_read_rx(spi);
832 if (spi->rx_len == 0)
834 else if (spi->tx_buf)/* Load data for discontinuous mode */
835 stm32f4_spi_write_tx(spi);
840 /* Immediately disable interrupts to do not generate new one */
841 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2,
842 STM32F4_SPI_CR2_TXEIE |
843 STM32F4_SPI_CR2_RXNEIE |
844 STM32F4_SPI_CR2_ERRIE);
845 spin_unlock(&spi->lock);
846 return IRQ_WAKE_THREAD;
849 spin_unlock(&spi->lock);
854 * stm32f4_spi_irq_thread - Thread of interrupt handler for SPI controller
855 * @irq: interrupt line
856 * @dev_id: SPI controller interface
858 static irqreturn_t stm32f4_spi_irq_thread(int irq, void *dev_id)
860 struct spi_controller *ctrl = dev_id;
861 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
863 spi_finalize_current_transfer(ctrl);
864 stm32f4_spi_disable(spi);
870 * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller
871 * @irq: interrupt line
872 * @dev_id: SPI controller interface
874 static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
876 struct spi_controller *ctrl = dev_id;
877 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
882 spin_lock_irqsave(&spi->lock, flags);
884 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
885 ier = readl_relaxed(spi->base + STM32H7_SPI_IER);
889 * EOTIE enables irq from EOT, SUSP and TXC events. We need to set
890 * SUSP to acknowledge it later. TXC is automatically cleared
893 mask |= STM32H7_SPI_SR_SUSP;
895 * DXPIE is set in Full-Duplex, one IT will be raised if TXP and RXP
896 * are set. So in case of Full-Duplex, need to poll TXP and RXP event.
898 if ((spi->cur_comm == SPI_FULL_DUPLEX) && !spi->cur_usedma)
899 mask |= STM32H7_SPI_SR_TXP | STM32H7_SPI_SR_RXP;
902 dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
904 spin_unlock_irqrestore(&spi->lock, flags);
908 if (sr & STM32H7_SPI_SR_SUSP) {
909 static DEFINE_RATELIMIT_STATE(rs,
910 DEFAULT_RATELIMIT_INTERVAL * 10,
912 ratelimit_set_flags(&rs, RATELIMIT_MSG_ON_RELEASE);
913 if (__ratelimit(&rs))
914 dev_dbg_ratelimited(spi->dev, "Communication suspended\n");
915 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
916 stm32h7_spi_read_rxfifo(spi);
918 * If communication is suspended while using DMA, it means
919 * that something went wrong, so stop the current transfer
925 if (sr & STM32H7_SPI_SR_MODF) {
926 dev_warn(spi->dev, "Mode fault: transfer aborted\n");
930 if (sr & STM32H7_SPI_SR_OVR) {
931 dev_err(spi->dev, "Overrun: RX data lost\n");
935 if (sr & STM32H7_SPI_SR_EOT) {
936 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
937 stm32h7_spi_read_rxfifo(spi);
938 if (!spi->cur_usedma ||
939 (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX))
943 if (sr & STM32H7_SPI_SR_TXP)
944 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0)))
945 stm32h7_spi_write_txfifo(spi);
947 if (sr & STM32H7_SPI_SR_RXP)
948 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
949 stm32h7_spi_read_rxfifo(spi);
951 writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR);
953 spin_unlock_irqrestore(&spi->lock, flags);
956 stm32h7_spi_disable(spi);
957 spi_finalize_current_transfer(ctrl);
964 * stm32_spi_prepare_msg - set up the controller to transfer a single message
965 * @ctrl: controller interface
966 * @msg: pointer to spi message
968 static int stm32_spi_prepare_msg(struct spi_controller *ctrl,
969 struct spi_message *msg)
971 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
972 struct spi_device *spi_dev = msg->spi;
973 struct device_node *np = spi_dev->dev.of_node;
975 u32 clrb = 0, setb = 0;
977 /* SPI slave device may need time between data frames */
979 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi))
980 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
982 if (spi_dev->mode & SPI_CPOL)
983 setb |= spi->cfg->regs->cpol.mask;
985 clrb |= spi->cfg->regs->cpol.mask;
987 if (spi_dev->mode & SPI_CPHA)
988 setb |= spi->cfg->regs->cpha.mask;
990 clrb |= spi->cfg->regs->cpha.mask;
992 if (spi_dev->mode & SPI_LSB_FIRST)
993 setb |= spi->cfg->regs->lsb_first.mask;
995 clrb |= spi->cfg->regs->lsb_first.mask;
997 if (STM32_SPI_DEVICE_MODE(spi) && spi_dev->mode & SPI_CS_HIGH)
998 setb |= spi->cfg->regs->cs_high.mask;
1000 clrb |= spi->cfg->regs->cs_high.mask;
1002 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
1003 !!(spi_dev->mode & SPI_CPOL),
1004 !!(spi_dev->mode & SPI_CPHA),
1005 !!(spi_dev->mode & SPI_LSB_FIRST),
1006 !!(spi_dev->mode & SPI_CS_HIGH));
1008 /* On STM32H7, messages should not exceed a maximum size setted
1009 * afterward via the set_number_of_data function. In order to
1010 * ensure that, split large messages into several messages
1012 if (spi->cfg->set_number_of_data) {
1015 ret = spi_split_transfers_maxwords(ctrl, msg,
1016 STM32H7_SPI_TSIZE_MAX,
1017 GFP_KERNEL | GFP_DMA);
1022 spin_lock_irqsave(&spi->lock, flags);
1024 /* CPOL, CPHA and LSB FIRST bits have common register */
1027 (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) &
1029 spi->base + spi->cfg->regs->cpol.reg);
1031 spin_unlock_irqrestore(&spi->lock, flags);
1037 * stm32f4_spi_dma_tx_cb - dma callback
1038 * @data: pointer to the spi controller data structure
1040 * DMA callback is called when the transfer is complete for DMA TX channel.
1042 static void stm32f4_spi_dma_tx_cb(void *data)
1044 struct stm32_spi *spi = data;
1046 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1047 spi_finalize_current_transfer(spi->ctrl);
1048 stm32f4_spi_disable(spi);
1053 * stm32_spi_dma_rx_cb - dma callback
1054 * @data: pointer to the spi controller data structure
1056 * DMA callback is called when the transfer is complete for DMA RX channel.
1058 static void stm32_spi_dma_rx_cb(void *data)
1060 struct stm32_spi *spi = data;
1062 spi_finalize_current_transfer(spi->ctrl);
1063 spi->cfg->disable(spi);
1067 * stm32_spi_dma_config - configure dma slave channel depending on current
1068 * transfer bits_per_word.
1069 * @spi: pointer to the spi controller data structure
1070 * @dma_conf: pointer to the dma_slave_config structure
1071 * @dir: direction of the dma transfer
1073 static void stm32_spi_dma_config(struct stm32_spi *spi,
1074 struct dma_slave_config *dma_conf,
1075 enum dma_transfer_direction dir)
1077 enum dma_slave_buswidth buswidth;
1080 if (spi->cur_bpw <= 8)
1081 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1082 else if (spi->cur_bpw <= 16)
1083 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1085 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1087 if (spi->cfg->has_fifo) {
1088 /* Valid for DMA Half or Full Fifo threshold */
1089 if (spi->cur_fthlv == 2)
1092 maxburst = spi->cur_fthlv;
1097 memset(dma_conf, 0, sizeof(struct dma_slave_config));
1098 dma_conf->direction = dir;
1099 if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */
1100 dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg;
1101 dma_conf->src_addr_width = buswidth;
1102 dma_conf->src_maxburst = maxburst;
1104 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
1105 buswidth, maxburst);
1106 } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */
1107 dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg;
1108 dma_conf->dst_addr_width = buswidth;
1109 dma_conf->dst_maxburst = maxburst;
1111 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n",
1112 buswidth, maxburst);
1117 * stm32f4_spi_transfer_one_irq - transfer a single spi_transfer using
1119 * @spi: pointer to the spi controller data structure
1121 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1124 static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi)
1126 unsigned long flags;
1129 /* Enable the interrupts relative to the current communication mode */
1130 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1131 cr2 |= STM32F4_SPI_CR2_TXEIE;
1132 } else if (spi->cur_comm == SPI_FULL_DUPLEX ||
1133 spi->cur_comm == SPI_SIMPLEX_RX ||
1134 spi->cur_comm == SPI_3WIRE_RX) {
1135 /* In transmit-only mode, the OVR flag is set in the SR register
1136 * since the received data are never read. Therefore set OVR
1137 * interrupt only when rx buffer is available.
1139 cr2 |= STM32F4_SPI_CR2_RXNEIE | STM32F4_SPI_CR2_ERRIE;
1144 spin_lock_irqsave(&spi->lock, flags);
1146 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, cr2);
1148 stm32_spi_enable(spi);
1150 /* starting data transfer when buffer is loaded */
1152 stm32f4_spi_write_tx(spi);
1154 spin_unlock_irqrestore(&spi->lock, flags);
1160 * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using
1162 * @spi: pointer to the spi controller data structure
1164 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1167 static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi)
1169 unsigned long flags;
1172 /* Enable the interrupts relative to the current communication mode */
1173 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */
1174 ier |= STM32H7_SPI_IER_DXPIE;
1175 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */
1176 ier |= STM32H7_SPI_IER_TXPIE;
1177 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */
1178 ier |= STM32H7_SPI_IER_RXPIE;
1180 /* Enable the interrupts relative to the end of transfer */
1181 ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE |
1182 STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
1184 spin_lock_irqsave(&spi->lock, flags);
1186 stm32_spi_enable(spi);
1188 /* Be sure to have data in fifo before starting data transfer */
1190 stm32h7_spi_write_txfifo(spi);
1192 if (STM32_SPI_MASTER_MODE(spi))
1193 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1195 writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
1197 spin_unlock_irqrestore(&spi->lock, flags);
1203 * stm32f4_spi_transfer_one_dma_start - Set SPI driver registers to start
1204 * transfer using DMA
1205 * @spi: pointer to the spi controller data structure
1207 static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi)
1209 /* In DMA mode end of transfer is handled by DMA TX or RX callback. */
1210 if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX ||
1211 spi->cur_comm == SPI_FULL_DUPLEX) {
1213 * In transmit-only mode, the OVR flag is set in the SR register
1214 * since the received data are never read. Therefore set OVR
1215 * interrupt only when rx buffer is available.
1217 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_ERRIE);
1220 stm32_spi_enable(spi);
1224 * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start
1225 * transfer using DMA
1226 * @spi: pointer to the spi controller data structure
1228 static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi)
1230 uint32_t ier = STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
1232 /* Enable the interrupts */
1233 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX)
1234 ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE;
1236 stm32_spi_set_bits(spi, STM32H7_SPI_IER, ier);
1238 stm32_spi_enable(spi);
1240 if (STM32_SPI_MASTER_MODE(spi))
1241 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1245 * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA
1246 * @spi: pointer to the spi controller data structure
1247 * @xfer: pointer to the spi_transfer structure
1249 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1252 static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
1253 struct spi_transfer *xfer)
1255 struct dma_slave_config tx_dma_conf, rx_dma_conf;
1256 struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc;
1257 unsigned long flags;
1259 spin_lock_irqsave(&spi->lock, flags);
1262 if (spi->rx_buf && spi->dma_rx) {
1263 stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM);
1264 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
1266 /* Enable Rx DMA request */
1267 stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1268 spi->cfg->regs->dma_rx_en.mask);
1270 rx_dma_desc = dmaengine_prep_slave_sg(
1271 spi->dma_rx, xfer->rx_sg.sgl,
1273 rx_dma_conf.direction,
1274 DMA_PREP_INTERRUPT);
1278 if (spi->tx_buf && spi->dma_tx) {
1279 stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV);
1280 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf);
1282 tx_dma_desc = dmaengine_prep_slave_sg(
1283 spi->dma_tx, xfer->tx_sg.sgl,
1285 tx_dma_conf.direction,
1286 DMA_PREP_INTERRUPT);
1289 if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) ||
1290 (spi->rx_buf && spi->dma_rx && !rx_dma_desc))
1291 goto dma_desc_error;
1293 if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc))
1294 goto dma_desc_error;
1297 rx_dma_desc->callback = spi->cfg->dma_rx_cb;
1298 rx_dma_desc->callback_param = spi;
1300 if (dma_submit_error(dmaengine_submit(rx_dma_desc))) {
1301 dev_err(spi->dev, "Rx DMA submit failed\n");
1302 goto dma_desc_error;
1304 /* Enable Rx DMA channel */
1305 dma_async_issue_pending(spi->dma_rx);
1309 if (spi->cur_comm == SPI_SIMPLEX_TX ||
1310 spi->cur_comm == SPI_3WIRE_TX) {
1311 tx_dma_desc->callback = spi->cfg->dma_tx_cb;
1312 tx_dma_desc->callback_param = spi;
1315 if (dma_submit_error(dmaengine_submit(tx_dma_desc))) {
1316 dev_err(spi->dev, "Tx DMA submit failed\n");
1317 goto dma_submit_error;
1319 /* Enable Tx DMA channel */
1320 dma_async_issue_pending(spi->dma_tx);
1322 /* Enable Tx DMA request */
1323 stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg,
1324 spi->cfg->regs->dma_tx_en.mask);
1327 spi->cfg->transfer_one_dma_start(spi);
1329 spin_unlock_irqrestore(&spi->lock, flags);
1335 dmaengine_terminate_sync(spi->dma_rx);
1338 stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1339 spi->cfg->regs->dma_rx_en.mask);
1341 spin_unlock_irqrestore(&spi->lock, flags);
1343 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n");
1345 spi->cur_usedma = false;
1346 return spi->cfg->transfer_one_irq(spi);
1350 * stm32f4_spi_set_bpw - Configure bits per word
1351 * @spi: pointer to the spi controller data structure
1353 static void stm32f4_spi_set_bpw(struct stm32_spi *spi)
1355 if (spi->cur_bpw == 16)
1356 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
1358 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
1362 * stm32h7_spi_set_bpw - configure bits per word
1363 * @spi: pointer to the spi controller data structure
1365 static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
1368 u32 cfg1_clrb = 0, cfg1_setb = 0;
1370 bpw = spi->cur_bpw - 1;
1372 cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
1373 cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_DSIZE, bpw);
1375 spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
1376 fthlv = spi->cur_fthlv - 1;
1378 cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
1379 cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_FTHLV, fthlv);
1382 (readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
1383 ~cfg1_clrb) | cfg1_setb,
1384 spi->base + STM32H7_SPI_CFG1);
1388 * stm32_spi_set_mbr - Configure baud rate divisor in master mode
1389 * @spi: pointer to the spi controller data structure
1390 * @mbrdiv: baud rate divisor value
1392 static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv)
1394 u32 clrb = 0, setb = 0;
1396 clrb |= spi->cfg->regs->br.mask;
1397 setb |= (mbrdiv << spi->cfg->regs->br.shift) & spi->cfg->regs->br.mask;
1399 writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) &
1401 spi->base + spi->cfg->regs->br.reg);
1405 * stm32_spi_communication_type - return transfer communication type
1406 * @spi_dev: pointer to the spi device
1407 * @transfer: pointer to spi transfer
1409 static unsigned int stm32_spi_communication_type(struct spi_device *spi_dev,
1410 struct spi_transfer *transfer)
1412 unsigned int type = SPI_FULL_DUPLEX;
1414 if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */
1416 * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL
1417 * is forbidden and unvalidated by SPI subsystem so depending
1418 * on the valid buffer, we can determine the direction of the
1421 if (!transfer->tx_buf)
1422 type = SPI_3WIRE_RX;
1424 type = SPI_3WIRE_TX;
1426 if (!transfer->tx_buf)
1427 type = SPI_SIMPLEX_RX;
1428 else if (!transfer->rx_buf)
1429 type = SPI_SIMPLEX_TX;
1436 * stm32f4_spi_set_mode - configure communication mode
1437 * @spi: pointer to the spi controller data structure
1438 * @comm_type: type of communication to configure
1440 static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1442 if (comm_type == SPI_3WIRE_TX || comm_type == SPI_SIMPLEX_TX) {
1443 stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
1444 STM32F4_SPI_CR1_BIDIMODE |
1445 STM32F4_SPI_CR1_BIDIOE);
1446 } else if (comm_type == SPI_FULL_DUPLEX ||
1447 comm_type == SPI_SIMPLEX_RX) {
1448 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
1449 STM32F4_SPI_CR1_BIDIMODE |
1450 STM32F4_SPI_CR1_BIDIOE);
1451 } else if (comm_type == SPI_3WIRE_RX) {
1452 stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
1453 STM32F4_SPI_CR1_BIDIMODE);
1454 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
1455 STM32F4_SPI_CR1_BIDIOE);
1464 * stm32h7_spi_set_mode - configure communication mode
1465 * @spi: pointer to the spi controller data structure
1466 * @comm_type: type of communication to configure
1468 static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1471 u32 cfg2_clrb = 0, cfg2_setb = 0;
1473 if (comm_type == SPI_3WIRE_RX) {
1474 mode = STM32H7_SPI_HALF_DUPLEX;
1475 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1476 } else if (comm_type == SPI_3WIRE_TX) {
1477 mode = STM32H7_SPI_HALF_DUPLEX;
1478 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1479 } else if (comm_type == SPI_SIMPLEX_RX) {
1480 mode = STM32H7_SPI_SIMPLEX_RX;
1481 } else if (comm_type == SPI_SIMPLEX_TX) {
1482 mode = STM32H7_SPI_SIMPLEX_TX;
1484 mode = STM32H7_SPI_FULL_DUPLEX;
1487 cfg2_clrb |= STM32H7_SPI_CFG2_COMM;
1488 cfg2_setb |= FIELD_PREP(STM32H7_SPI_CFG2_COMM, mode);
1491 (readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1492 ~cfg2_clrb) | cfg2_setb,
1493 spi->base + STM32H7_SPI_CFG2);
1499 * stm32h7_spi_data_idleness - configure minimum time delay inserted between two
1500 * consecutive data frames in master mode
1501 * @spi: pointer to the spi controller data structure
1502 * @len: transfer len
1504 static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len)
1506 u32 cfg2_clrb = 0, cfg2_setb = 0;
1508 cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
1509 if ((len > 1) && (spi->cur_midi > 0)) {
1510 u32 sck_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->cur_speed);
1511 u32 midi = min_t(u32,
1512 DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
1513 FIELD_GET(STM32H7_SPI_CFG2_MIDI,
1514 STM32H7_SPI_CFG2_MIDI));
1517 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
1518 sck_period_ns, midi, midi * sck_period_ns);
1519 cfg2_setb |= FIELD_PREP(STM32H7_SPI_CFG2_MIDI, midi);
1522 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1523 ~cfg2_clrb) | cfg2_setb,
1524 spi->base + STM32H7_SPI_CFG2);
1528 * stm32h7_spi_number_of_data - configure number of data at current transfer
1529 * @spi: pointer to the spi controller data structure
1530 * @nb_words: transfer length (in words)
1532 static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words)
1534 if (nb_words <= STM32H7_SPI_TSIZE_MAX) {
1535 writel_relaxed(FIELD_PREP(STM32H7_SPI_CR2_TSIZE, nb_words),
1536 spi->base + STM32H7_SPI_CR2);
1545 * stm32_spi_transfer_one_setup - common setup to transfer a single
1546 * spi_transfer either using DMA or
1548 * @spi: pointer to the spi controller data structure
1549 * @spi_dev: pointer to the spi device
1550 * @transfer: pointer to spi transfer
1552 static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
1553 struct spi_device *spi_dev,
1554 struct spi_transfer *transfer)
1556 unsigned long flags;
1557 unsigned int comm_type;
1558 int nb_words, ret = 0;
1561 spin_lock_irqsave(&spi->lock, flags);
1563 spi->cur_xferlen = transfer->len;
1565 spi->cur_bpw = transfer->bits_per_word;
1566 spi->cfg->set_bpw(spi);
1568 /* Update spi->cur_speed with real clock speed */
1569 if (STM32_SPI_MASTER_MODE(spi)) {
1570 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz,
1571 spi->cfg->baud_rate_div_min,
1572 spi->cfg->baud_rate_div_max);
1578 transfer->speed_hz = spi->cur_speed;
1579 stm32_spi_set_mbr(spi, mbr);
1582 comm_type = stm32_spi_communication_type(spi_dev, transfer);
1583 ret = spi->cfg->set_mode(spi, comm_type);
1587 spi->cur_comm = comm_type;
1589 if (STM32_SPI_MASTER_MODE(spi) && spi->cfg->set_data_idleness)
1590 spi->cfg->set_data_idleness(spi, transfer->len);
1592 if (spi->cur_bpw <= 8)
1593 nb_words = transfer->len;
1594 else if (spi->cur_bpw <= 16)
1595 nb_words = DIV_ROUND_UP(transfer->len * 8, 16);
1597 nb_words = DIV_ROUND_UP(transfer->len * 8, 32);
1599 if (spi->cfg->set_number_of_data) {
1600 ret = spi->cfg->set_number_of_data(spi, nb_words);
1605 dev_dbg(spi->dev, "transfer communication mode set to %d\n",
1608 "data frame of %d-bit, data packet of %d data frames\n",
1609 spi->cur_bpw, spi->cur_fthlv);
1610 if (STM32_SPI_MASTER_MODE(spi))
1611 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed);
1612 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n",
1613 spi->cur_xferlen, nb_words);
1614 dev_dbg(spi->dev, "dma %s\n",
1615 (spi->cur_usedma) ? "enabled" : "disabled");
1618 spin_unlock_irqrestore(&spi->lock, flags);
1624 * stm32_spi_transfer_one - transfer a single spi_transfer
1625 * @ctrl: controller interface
1626 * @spi_dev: pointer to the spi device
1627 * @transfer: pointer to spi transfer
1629 * It must return 0 if the transfer is finished or 1 if the transfer is still
1632 static int stm32_spi_transfer_one(struct spi_controller *ctrl,
1633 struct spi_device *spi_dev,
1634 struct spi_transfer *transfer)
1636 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
1639 spi->tx_buf = transfer->tx_buf;
1640 spi->rx_buf = transfer->rx_buf;
1641 spi->tx_len = spi->tx_buf ? transfer->len : 0;
1642 spi->rx_len = spi->rx_buf ? transfer->len : 0;
1644 spi->cur_usedma = (ctrl->can_dma &&
1645 ctrl->can_dma(ctrl, spi_dev, transfer));
1647 ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer);
1649 dev_err(spi->dev, "SPI transfer setup failed\n");
1653 if (spi->cur_usedma)
1654 return stm32_spi_transfer_one_dma(spi, transfer);
1656 return spi->cfg->transfer_one_irq(spi);
1660 * stm32_spi_unprepare_msg - relax the hardware
1661 * @ctrl: controller interface
1662 * @msg: pointer to the spi message
1664 static int stm32_spi_unprepare_msg(struct spi_controller *ctrl,
1665 struct spi_message *msg)
1667 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
1669 spi->cfg->disable(spi);
1675 * stm32f4_spi_config - Configure SPI controller as SPI master
1676 * @spi: pointer to the spi controller data structure
1678 static int stm32f4_spi_config(struct stm32_spi *spi)
1680 unsigned long flags;
1682 spin_lock_irqsave(&spi->lock, flags);
1684 /* Ensure I2SMOD bit is kept cleared */
1685 stm32_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR,
1686 STM32F4_SPI_I2SCFGR_I2SMOD);
1689 * - SS input value high
1690 * - transmitter half duplex direction
1691 * - Set the master mode (default Motorola mode)
1692 * - Consider 1 master/n slaves configuration and
1693 * SS input value is determined by the SSI bit
1695 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SSI |
1696 STM32F4_SPI_CR1_BIDIOE |
1697 STM32F4_SPI_CR1_MSTR |
1698 STM32F4_SPI_CR1_SSM);
1700 spin_unlock_irqrestore(&spi->lock, flags);
1706 * stm32h7_spi_config - Configure SPI controller
1707 * @spi: pointer to the spi controller data structure
1709 static int stm32h7_spi_config(struct stm32_spi *spi)
1711 unsigned long flags;
1712 u32 cr1 = 0, cfg2 = 0;
1714 spin_lock_irqsave(&spi->lock, flags);
1716 /* Ensure I2SMOD bit is kept cleared */
1717 stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR,
1718 STM32H7_SPI_I2SCFGR_I2SMOD);
1720 if (STM32_SPI_DEVICE_MODE(spi)) {
1721 /* Use native device select */
1722 cfg2 &= ~STM32H7_SPI_CFG2_SSM;
1725 * - Transmitter half duplex direction
1726 * - Automatic communication suspend when RX-Fifo is full
1727 * - SS input value high
1729 cr1 |= STM32H7_SPI_CR1_HDDIR | STM32H7_SPI_CR1_MASRX | STM32H7_SPI_CR1_SSI;
1732 * - Set the master mode (default Motorola mode)
1733 * - Consider 1 master/n devices configuration and
1734 * SS input value is determined by the SSI bit
1735 * - keep control of all associated GPIOs
1737 cfg2 |= STM32H7_SPI_CFG2_MASTER | STM32H7_SPI_CFG2_SSM | STM32H7_SPI_CFG2_AFCNTR;
1740 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, cr1);
1741 stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, cfg2);
1743 spin_unlock_irqrestore(&spi->lock, flags);
1748 static const struct stm32_spi_cfg stm32f4_spi_cfg = {
1749 .regs = &stm32f4_spi_regspec,
1750 .get_bpw_mask = stm32f4_spi_get_bpw_mask,
1751 .disable = stm32f4_spi_disable,
1752 .config = stm32f4_spi_config,
1753 .set_bpw = stm32f4_spi_set_bpw,
1754 .set_mode = stm32f4_spi_set_mode,
1755 .transfer_one_dma_start = stm32f4_spi_transfer_one_dma_start,
1756 .dma_tx_cb = stm32f4_spi_dma_tx_cb,
1757 .dma_rx_cb = stm32_spi_dma_rx_cb,
1758 .transfer_one_irq = stm32f4_spi_transfer_one_irq,
1759 .irq_handler_event = stm32f4_spi_irq_event,
1760 .irq_handler_thread = stm32f4_spi_irq_thread,
1761 .baud_rate_div_min = STM32F4_SPI_BR_DIV_MIN,
1762 .baud_rate_div_max = STM32F4_SPI_BR_DIV_MAX,
1764 .has_device_mode = false,
1765 .flags = SPI_CONTROLLER_MUST_TX,
1768 static const struct stm32_spi_cfg stm32h7_spi_cfg = {
1769 .regs = &stm32h7_spi_regspec,
1770 .get_fifo_size = stm32h7_spi_get_fifo_size,
1771 .get_bpw_mask = stm32h7_spi_get_bpw_mask,
1772 .disable = stm32h7_spi_disable,
1773 .config = stm32h7_spi_config,
1774 .set_bpw = stm32h7_spi_set_bpw,
1775 .set_mode = stm32h7_spi_set_mode,
1776 .set_data_idleness = stm32h7_spi_data_idleness,
1777 .set_number_of_data = stm32h7_spi_number_of_data,
1778 .transfer_one_dma_start = stm32h7_spi_transfer_one_dma_start,
1779 .dma_rx_cb = stm32_spi_dma_rx_cb,
1781 * dma_tx_cb is not necessary since in case of TX, dma is followed by
1782 * SPI access hence handling is performed within the SPI interrupt
1784 .transfer_one_irq = stm32h7_spi_transfer_one_irq,
1785 .irq_handler_thread = stm32h7_spi_irq_thread,
1786 .baud_rate_div_min = STM32H7_SPI_MBR_DIV_MIN,
1787 .baud_rate_div_max = STM32H7_SPI_MBR_DIV_MAX,
1789 .has_device_mode = true,
1792 static const struct of_device_id stm32_spi_of_match[] = {
1793 { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
1794 { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
1797 MODULE_DEVICE_TABLE(of, stm32_spi_of_match);
1799 static int stm32h7_spi_device_abort(struct spi_controller *ctrl)
1801 spi_finalize_current_transfer(ctrl);
1805 static int stm32_spi_probe(struct platform_device *pdev)
1807 struct spi_controller *ctrl;
1808 struct stm32_spi *spi;
1809 struct resource *res;
1810 struct reset_control *rst;
1811 struct device_node *np = pdev->dev.of_node;
1814 const struct stm32_spi_cfg *cfg = of_device_get_match_data(&pdev->dev);
1816 device_mode = of_property_read_bool(np, "spi-slave");
1817 if (!cfg->has_device_mode && device_mode) {
1818 dev_err(&pdev->dev, "spi-slave not supported\n");
1823 ctrl = devm_spi_alloc_slave(&pdev->dev, sizeof(struct stm32_spi));
1825 ctrl = devm_spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi));
1827 dev_err(&pdev->dev, "spi controller allocation failed\n");
1830 platform_set_drvdata(pdev, ctrl);
1832 spi = spi_controller_get_devdata(ctrl);
1833 spi->dev = &pdev->dev;
1835 spi->device_mode = device_mode;
1836 spin_lock_init(&spi->lock);
1840 spi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1841 if (IS_ERR(spi->base))
1842 return PTR_ERR(spi->base);
1844 spi->phys_addr = (dma_addr_t)res->start;
1846 spi->irq = platform_get_irq(pdev, 0);
1850 ret = devm_request_threaded_irq(&pdev->dev, spi->irq,
1851 spi->cfg->irq_handler_event,
1852 spi->cfg->irq_handler_thread,
1853 IRQF_ONESHOT, pdev->name, ctrl);
1855 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq,
1860 spi->clk = devm_clk_get(&pdev->dev, NULL);
1861 if (IS_ERR(spi->clk)) {
1862 ret = PTR_ERR(spi->clk);
1863 dev_err(&pdev->dev, "clk get failed: %d\n", ret);
1867 ret = clk_prepare_enable(spi->clk);
1869 dev_err(&pdev->dev, "clk enable failed: %d\n", ret);
1872 spi->clk_rate = clk_get_rate(spi->clk);
1873 if (!spi->clk_rate) {
1874 dev_err(&pdev->dev, "clk rate = 0\n");
1876 goto err_clk_disable;
1879 rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
1882 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst),
1883 "failed to get reset\n");
1884 goto err_clk_disable;
1887 reset_control_assert(rst);
1889 reset_control_deassert(rst);
1892 if (spi->cfg->has_fifo)
1893 spi->fifo_size = spi->cfg->get_fifo_size(spi);
1895 ret = spi->cfg->config(spi);
1897 dev_err(&pdev->dev, "controller configuration failed: %d\n",
1899 goto err_clk_disable;
1902 ctrl->dev.of_node = pdev->dev.of_node;
1903 ctrl->auto_runtime_pm = true;
1904 ctrl->bus_num = pdev->id;
1905 ctrl->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST |
1907 ctrl->bits_per_word_mask = spi->cfg->get_bpw_mask(spi);
1908 ctrl->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min;
1909 ctrl->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max;
1910 ctrl->use_gpio_descriptors = true;
1911 ctrl->prepare_message = stm32_spi_prepare_msg;
1912 ctrl->transfer_one = stm32_spi_transfer_one;
1913 ctrl->unprepare_message = stm32_spi_unprepare_msg;
1914 ctrl->flags = spi->cfg->flags;
1915 if (STM32_SPI_DEVICE_MODE(spi))
1916 ctrl->slave_abort = stm32h7_spi_device_abort;
1918 spi->dma_tx = dma_request_chan(spi->dev, "tx");
1919 if (IS_ERR(spi->dma_tx)) {
1920 ret = PTR_ERR(spi->dma_tx);
1922 if (ret == -EPROBE_DEFER)
1923 goto err_clk_disable;
1925 dev_warn(&pdev->dev, "failed to request tx dma channel\n");
1927 ctrl->dma_tx = spi->dma_tx;
1930 spi->dma_rx = dma_request_chan(spi->dev, "rx");
1931 if (IS_ERR(spi->dma_rx)) {
1932 ret = PTR_ERR(spi->dma_rx);
1934 if (ret == -EPROBE_DEFER)
1935 goto err_dma_release;
1937 dev_warn(&pdev->dev, "failed to request rx dma channel\n");
1939 ctrl->dma_rx = spi->dma_rx;
1942 if (spi->dma_tx || spi->dma_rx)
1943 ctrl->can_dma = stm32_spi_can_dma;
1945 pm_runtime_set_autosuspend_delay(&pdev->dev,
1946 STM32_SPI_AUTOSUSPEND_DELAY);
1947 pm_runtime_use_autosuspend(&pdev->dev);
1948 pm_runtime_set_active(&pdev->dev);
1949 pm_runtime_get_noresume(&pdev->dev);
1950 pm_runtime_enable(&pdev->dev);
1952 ret = spi_register_controller(ctrl);
1954 dev_err(&pdev->dev, "spi controller registration failed: %d\n",
1956 goto err_pm_disable;
1959 pm_runtime_mark_last_busy(&pdev->dev);
1960 pm_runtime_put_autosuspend(&pdev->dev);
1962 dev_info(&pdev->dev, "driver initialized (%s mode)\n",
1963 STM32_SPI_MASTER_MODE(spi) ? "master" : "device");
1968 pm_runtime_disable(&pdev->dev);
1969 pm_runtime_put_noidle(&pdev->dev);
1970 pm_runtime_set_suspended(&pdev->dev);
1971 pm_runtime_dont_use_autosuspend(&pdev->dev);
1974 dma_release_channel(spi->dma_tx);
1976 dma_release_channel(spi->dma_rx);
1978 clk_disable_unprepare(spi->clk);
1983 static void stm32_spi_remove(struct platform_device *pdev)
1985 struct spi_controller *ctrl = platform_get_drvdata(pdev);
1986 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
1988 pm_runtime_get_sync(&pdev->dev);
1990 spi_unregister_controller(ctrl);
1991 spi->cfg->disable(spi);
1993 pm_runtime_disable(&pdev->dev);
1994 pm_runtime_put_noidle(&pdev->dev);
1995 pm_runtime_set_suspended(&pdev->dev);
1996 pm_runtime_dont_use_autosuspend(&pdev->dev);
1999 dma_release_channel(ctrl->dma_tx);
2001 dma_release_channel(ctrl->dma_rx);
2003 clk_disable_unprepare(spi->clk);
2006 pinctrl_pm_select_sleep_state(&pdev->dev);
2009 static int __maybe_unused stm32_spi_runtime_suspend(struct device *dev)
2011 struct spi_controller *ctrl = dev_get_drvdata(dev);
2012 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
2014 clk_disable_unprepare(spi->clk);
2016 return pinctrl_pm_select_sleep_state(dev);
2019 static int __maybe_unused stm32_spi_runtime_resume(struct device *dev)
2021 struct spi_controller *ctrl = dev_get_drvdata(dev);
2022 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
2025 ret = pinctrl_pm_select_default_state(dev);
2029 return clk_prepare_enable(spi->clk);
2032 static int __maybe_unused stm32_spi_suspend(struct device *dev)
2034 struct spi_controller *ctrl = dev_get_drvdata(dev);
2037 ret = spi_controller_suspend(ctrl);
2041 return pm_runtime_force_suspend(dev);
2044 static int __maybe_unused stm32_spi_resume(struct device *dev)
2046 struct spi_controller *ctrl = dev_get_drvdata(dev);
2047 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
2050 ret = pm_runtime_force_resume(dev);
2054 ret = spi_controller_resume(ctrl);
2056 clk_disable_unprepare(spi->clk);
2060 ret = pm_runtime_resume_and_get(dev);
2062 dev_err(dev, "Unable to power device:%d\n", ret);
2066 spi->cfg->config(spi);
2068 pm_runtime_mark_last_busy(dev);
2069 pm_runtime_put_autosuspend(dev);
2074 static const struct dev_pm_ops stm32_spi_pm_ops = {
2075 SET_SYSTEM_SLEEP_PM_OPS(stm32_spi_suspend, stm32_spi_resume)
2076 SET_RUNTIME_PM_OPS(stm32_spi_runtime_suspend,
2077 stm32_spi_runtime_resume, NULL)
2080 static struct platform_driver stm32_spi_driver = {
2081 .probe = stm32_spi_probe,
2082 .remove_new = stm32_spi_remove,
2084 .name = DRIVER_NAME,
2085 .pm = &stm32_spi_pm_ops,
2086 .of_match_table = stm32_spi_of_match,
2090 module_platform_driver(stm32_spi_driver);
2092 MODULE_ALIAS("platform:" DRIVER_NAME);
2093 MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver");
2094 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
2095 MODULE_LICENSE("GPL v2");