2 * STMicroelectronics STM32 SPI Controller driver (master mode only)
4 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
5 * Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics.
7 * License terms: GPL V2.0.
9 * spi_stm32 driver is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
13 * spi_stm32 driver is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
18 * You should have received a copy of the GNU General Public License along with
19 * spi_stm32 driver. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/debugfs.h>
22 #include <linux/clk.h>
23 #include <linux/delay.h>
24 #include <linux/dmaengine.h>
25 #include <linux/gpio.h>
26 #include <linux/interrupt.h>
27 #include <linux/iopoll.h>
28 #include <linux/module.h>
29 #include <linux/of_platform.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/reset.h>
32 #include <linux/spi/spi.h>
34 #define DRIVER_NAME "spi_stm32"
36 /* STM32 SPI registers */
37 #define STM32_SPI_CR1 0x00
38 #define STM32_SPI_CR2 0x04
39 #define STM32_SPI_CFG1 0x08
40 #define STM32_SPI_CFG2 0x0C
41 #define STM32_SPI_IER 0x10
42 #define STM32_SPI_SR 0x14
43 #define STM32_SPI_IFCR 0x18
44 #define STM32_SPI_TXDR 0x20
45 #define STM32_SPI_RXDR 0x30
46 #define STM32_SPI_I2SCFGR 0x50
48 /* STM32_SPI_CR1 bit fields */
49 #define SPI_CR1_SPE BIT(0)
50 #define SPI_CR1_MASRX BIT(8)
51 #define SPI_CR1_CSTART BIT(9)
52 #define SPI_CR1_CSUSP BIT(10)
53 #define SPI_CR1_HDDIR BIT(11)
54 #define SPI_CR1_SSI BIT(12)
56 /* STM32_SPI_CR2 bit fields */
57 #define SPI_CR2_TSIZE_SHIFT 0
58 #define SPI_CR2_TSIZE GENMASK(15, 0)
60 /* STM32_SPI_CFG1 bit fields */
61 #define SPI_CFG1_DSIZE_SHIFT 0
62 #define SPI_CFG1_DSIZE GENMASK(4, 0)
63 #define SPI_CFG1_FTHLV_SHIFT 5
64 #define SPI_CFG1_FTHLV GENMASK(8, 5)
65 #define SPI_CFG1_RXDMAEN BIT(14)
66 #define SPI_CFG1_TXDMAEN BIT(15)
67 #define SPI_CFG1_MBR_SHIFT 28
68 #define SPI_CFG1_MBR GENMASK(30, 28)
69 #define SPI_CFG1_MBR_MIN 0
70 #define SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
72 /* STM32_SPI_CFG2 bit fields */
73 #define SPI_CFG2_MIDI_SHIFT 4
74 #define SPI_CFG2_MIDI GENMASK(7, 4)
75 #define SPI_CFG2_COMM_SHIFT 17
76 #define SPI_CFG2_COMM GENMASK(18, 17)
77 #define SPI_CFG2_SP_SHIFT 19
78 #define SPI_CFG2_SP GENMASK(21, 19)
79 #define SPI_CFG2_MASTER BIT(22)
80 #define SPI_CFG2_LSBFRST BIT(23)
81 #define SPI_CFG2_CPHA BIT(24)
82 #define SPI_CFG2_CPOL BIT(25)
83 #define SPI_CFG2_SSM BIT(26)
84 #define SPI_CFG2_AFCNTR BIT(31)
86 /* STM32_SPI_IER bit fields */
87 #define SPI_IER_RXPIE BIT(0)
88 #define SPI_IER_TXPIE BIT(1)
89 #define SPI_IER_DXPIE BIT(2)
90 #define SPI_IER_EOTIE BIT(3)
91 #define SPI_IER_TXTFIE BIT(4)
92 #define SPI_IER_OVRIE BIT(6)
93 #define SPI_IER_MODFIE BIT(9)
94 #define SPI_IER_ALL GENMASK(10, 0)
96 /* STM32_SPI_SR bit fields */
97 #define SPI_SR_RXP BIT(0)
98 #define SPI_SR_TXP BIT(1)
99 #define SPI_SR_EOT BIT(3)
100 #define SPI_SR_OVR BIT(6)
101 #define SPI_SR_MODF BIT(9)
102 #define SPI_SR_SUSP BIT(11)
103 #define SPI_SR_RXPLVL_SHIFT 13
104 #define SPI_SR_RXPLVL GENMASK(14, 13)
105 #define SPI_SR_RXWNE BIT(15)
107 /* STM32_SPI_IFCR bit fields */
108 #define SPI_IFCR_ALL GENMASK(11, 3)
110 /* STM32_SPI_I2SCFGR bit fields */
111 #define SPI_I2SCFGR_I2SMOD BIT(0)
113 /* SPI Master Baud Rate min/max divisor */
114 #define SPI_MBR_DIV_MIN (2 << SPI_CFG1_MBR_MIN)
115 #define SPI_MBR_DIV_MAX (2 << SPI_CFG1_MBR_MAX)
117 /* SPI Communication mode */
118 #define SPI_FULL_DUPLEX 0
119 #define SPI_SIMPLEX_TX 1
120 #define SPI_SIMPLEX_RX 2
121 #define SPI_HALF_DUPLEX 3
123 #define SPI_1HZ_NS 1000000000
126 * struct stm32_spi - private data of the SPI controller
127 * @dev: driver model representation of the controller
128 * @master: controller master interface
129 * @base: virtual memory area
130 * @clk: hw kernel clock feeding the SPI clock generator
131 * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
132 * @rst: SPI controller reset line
133 * @lock: prevent I/O concurrent access
134 * @irq: SPI controller interrupt line
135 * @fifo_size: size of the embedded fifo in bytes
136 * @cur_midi: master inter-data idleness in ns
137 * @cur_speed: speed configured in Hz
138 * @cur_bpw: number of bits in a single SPI data frame
139 * @cur_fthlv: fifo threshold level (data frames in a single data packet)
140 * @cur_comm: SPI communication mode
141 * @cur_xferlen: current transfer length in bytes
142 * @cur_usedma: boolean to know if dma is used in current transfer
143 * @tx_buf: data to be written, or NULL
144 * @rx_buf: data to be read, or NULL
145 * @tx_len: number of data to be written in bytes
146 * @rx_len: number of data to be read in bytes
147 * @dma_tx: dma channel for TX transfer
148 * @dma_rx: dma channel for RX transfer
149 * @phys_addr: SPI registers physical base address
153 struct spi_master *master;
157 struct reset_control *rst;
158 spinlock_t lock; /* prevent I/O concurrent access */
160 unsigned int fifo_size;
162 unsigned int cur_midi;
163 unsigned int cur_speed;
164 unsigned int cur_bpw;
165 unsigned int cur_fthlv;
166 unsigned int cur_comm;
167 unsigned int cur_xferlen;
174 struct dma_chan *dma_tx;
175 struct dma_chan *dma_rx;
176 dma_addr_t phys_addr;
179 static inline void stm32_spi_set_bits(struct stm32_spi *spi,
180 u32 offset, u32 bits)
182 writel_relaxed(readl_relaxed(spi->base + offset) | bits,
186 static inline void stm32_spi_clr_bits(struct stm32_spi *spi,
187 u32 offset, u32 bits)
189 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits,
194 * stm32_spi_get_fifo_size - Return fifo size
195 * @spi: pointer to the spi controller data structure
197 static int stm32_spi_get_fifo_size(struct stm32_spi *spi)
202 spin_lock_irqsave(&spi->lock, flags);
204 stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE);
206 while (readl_relaxed(spi->base + STM32_SPI_SR) & SPI_SR_TXP)
207 writeb_relaxed(++count, spi->base + STM32_SPI_TXDR);
209 stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE);
211 spin_unlock_irqrestore(&spi->lock, flags);
213 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count);
219 * stm32_spi_get_bpw_mask - Return bits per word mask
220 * @spi: pointer to the spi controller data structure
222 static int stm32_spi_get_bpw_mask(struct stm32_spi *spi)
227 spin_lock_irqsave(&spi->lock, flags);
230 * The most significant bit at DSIZE bit field is reserved when the
231 * maximum data size of periperal instances is limited to 16-bit
233 stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_DSIZE);
235 cfg1 = readl_relaxed(spi->base + STM32_SPI_CFG1);
236 max_bpw = (cfg1 & SPI_CFG1_DSIZE) >> SPI_CFG1_DSIZE_SHIFT;
239 spin_unlock_irqrestore(&spi->lock, flags);
241 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw);
243 return SPI_BPW_RANGE_MASK(4, max_bpw);
247 * stm32_spi_prepare_mbr - Determine SPI_CFG1.MBR value
248 * @spi: pointer to the spi controller data structure
249 * @speed_hz: requested speed
251 * Return SPI_CFG1.MBR value in case of success or -EINVAL
253 static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz)
257 /* Ensure spi->clk_rate is even */
258 div = DIV_ROUND_UP(spi->clk_rate & ~0x1, speed_hz);
261 * SPI framework set xfer->speed_hz to master->max_speed_hz if
262 * xfer->speed_hz is greater than master->max_speed_hz, and it returns
263 * an error when xfer->speed_hz is lower than master->min_speed_hz, so
264 * no need to check it there.
265 * However, we need to ensure the following calculations.
267 if (div < SPI_MBR_DIV_MIN ||
268 div > SPI_MBR_DIV_MAX)
271 /* Determine the first power of 2 greater than or equal to div */
275 mbrdiv = fls(div) - 1;
277 spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
283 * stm32_spi_prepare_fthlv - Determine FIFO threshold level
284 * @spi: pointer to the spi controller data structure
286 static u32 stm32_spi_prepare_fthlv(struct stm32_spi *spi)
288 u32 fthlv, half_fifo;
290 /* data packet should not exceed 1/2 of fifo space */
291 half_fifo = (spi->fifo_size / 2);
293 if (spi->cur_bpw <= 8)
295 else if (spi->cur_bpw <= 16)
296 fthlv = half_fifo / 2;
298 fthlv = half_fifo / 4;
300 /* align packet size with data registers access */
301 if (spi->cur_bpw > 8)
302 fthlv += (fthlv % 2) ? 1 : 0;
304 fthlv += (fthlv % 4) ? (4 - (fthlv % 4)) : 0;
310 * stm32_spi_write_txfifo - Write bytes in Transmit Data Register
311 * @spi: pointer to the spi controller data structure
313 * Read from tx_buf depends on remaining bytes to avoid to read beyond
316 static void stm32_spi_write_txfifo(struct stm32_spi *spi)
318 while ((spi->tx_len > 0) &&
319 (readl_relaxed(spi->base + STM32_SPI_SR) & SPI_SR_TXP)) {
320 u32 offs = spi->cur_xferlen - spi->tx_len;
322 if (spi->tx_len >= sizeof(u32)) {
323 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs);
325 writel_relaxed(*tx_buf32, spi->base + STM32_SPI_TXDR);
326 spi->tx_len -= sizeof(u32);
327 } else if (spi->tx_len >= sizeof(u16)) {
328 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
330 writew_relaxed(*tx_buf16, spi->base + STM32_SPI_TXDR);
331 spi->tx_len -= sizeof(u16);
333 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
335 writeb_relaxed(*tx_buf8, spi->base + STM32_SPI_TXDR);
336 spi->tx_len -= sizeof(u8);
340 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
344 * stm32_spi_read_rxfifo - Read bytes in Receive Data Register
345 * @spi: pointer to the spi controller data structure
347 * Write in rx_buf depends on remaining bytes to avoid to write beyond
350 static void stm32_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
352 u32 sr = readl_relaxed(spi->base + STM32_SPI_SR);
353 u32 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
355 while ((spi->rx_len > 0) &&
356 ((sr & SPI_SR_RXP) ||
357 (flush && ((sr & SPI_SR_RXWNE) || (rxplvl > 0))))) {
358 u32 offs = spi->cur_xferlen - spi->rx_len;
360 if ((spi->rx_len >= sizeof(u32)) ||
361 (flush && (sr & SPI_SR_RXWNE))) {
362 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs);
364 *rx_buf32 = readl_relaxed(spi->base + STM32_SPI_RXDR);
365 spi->rx_len -= sizeof(u32);
366 } else if ((spi->rx_len >= sizeof(u16)) ||
367 (flush && (rxplvl >= 2 || spi->cur_bpw > 8))) {
368 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
370 *rx_buf16 = readw_relaxed(spi->base + STM32_SPI_RXDR);
371 spi->rx_len -= sizeof(u16);
373 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
375 *rx_buf8 = readb_relaxed(spi->base + STM32_SPI_RXDR);
376 spi->rx_len -= sizeof(u8);
379 sr = readl_relaxed(spi->base + STM32_SPI_SR);
380 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
383 dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
384 flush ? "(flush)" : "", spi->rx_len);
388 * stm32_spi_enable - Enable SPI controller
389 * @spi: pointer to the spi controller data structure
391 * SPI data transfer is enabled but spi_ker_ck is idle.
392 * SPI_CFG1 and SPI_CFG2 are now write protected.
394 static void stm32_spi_enable(struct stm32_spi *spi)
396 dev_dbg(spi->dev, "enable controller\n");
398 stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE);
402 * stm32_spi_disable - Disable SPI controller
403 * @spi: pointer to the spi controller data structure
405 * RX-Fifo is flushed when SPI controller is disabled. To prevent any data
406 * loss, use stm32_spi_read_rxfifo(flush) to read the remaining bytes in
409 static void stm32_spi_disable(struct stm32_spi *spi)
414 dev_dbg(spi->dev, "disable controller\n");
416 spin_lock_irqsave(&spi->lock, flags);
418 cr1 = readl_relaxed(spi->base + STM32_SPI_CR1);
420 if (!(cr1 & SPI_CR1_SPE)) {
421 spin_unlock_irqrestore(&spi->lock, flags);
425 /* Wait on EOT or suspend the flow */
426 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32_SPI_SR,
427 sr, !(sr & SPI_SR_EOT),
429 if (cr1 & SPI_CR1_CSTART) {
430 writel_relaxed(cr1 | SPI_CR1_CSUSP,
431 spi->base + STM32_SPI_CR1);
432 if (readl_relaxed_poll_timeout_atomic(
433 spi->base + STM32_SPI_SR,
434 sr, !(sr & SPI_SR_SUSP),
437 "Suspend request timeout\n");
441 if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0))
442 stm32_spi_read_rxfifo(spi, true);
444 if (spi->cur_usedma && spi->tx_buf)
445 dmaengine_terminate_all(spi->dma_tx);
446 if (spi->cur_usedma && spi->rx_buf)
447 dmaengine_terminate_all(spi->dma_rx);
449 stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE);
451 stm32_spi_clr_bits(spi, STM32_SPI_CFG1, SPI_CFG1_TXDMAEN |
454 /* Disable interrupts and clear status flags */
455 writel_relaxed(0, spi->base + STM32_SPI_IER);
456 writel_relaxed(SPI_IFCR_ALL, spi->base + STM32_SPI_IFCR);
458 spin_unlock_irqrestore(&spi->lock, flags);
462 * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
464 * If the current transfer size is greater than fifo size, use DMA.
466 static bool stm32_spi_can_dma(struct spi_master *master,
467 struct spi_device *spi_dev,
468 struct spi_transfer *transfer)
470 struct stm32_spi *spi = spi_master_get_devdata(master);
472 dev_dbg(spi->dev, "%s: %s\n", __func__,
473 (transfer->len > spi->fifo_size) ? "true" : "false");
475 return (transfer->len > spi->fifo_size);
479 * stm32_spi_irq - Interrupt handler for SPI controller events
480 * @irq: interrupt line
481 * @dev_id: SPI controller master interface
483 static irqreturn_t stm32_spi_irq(int irq, void *dev_id)
485 struct spi_master *master = dev_id;
486 struct stm32_spi *spi = spi_master_get_devdata(master);
491 spin_lock_irqsave(&spi->lock, flags);
493 sr = readl_relaxed(spi->base + STM32_SPI_SR);
494 ier = readl_relaxed(spi->base + STM32_SPI_IER);
497 /* EOTIE is triggered on EOT, SUSP and TXC events. */
500 * When TXTF is set, DXPIE and TXPIE are cleared. So in case of
501 * Full-Duplex, need to poll RXP event to know if there are remaining
502 * data, before disabling SPI.
504 if (spi->rx_buf && !spi->cur_usedma)
508 dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
510 spin_unlock_irqrestore(&spi->lock, flags);
514 if (sr & SPI_SR_SUSP) {
515 dev_warn(spi->dev, "Communication suspended\n");
516 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
517 stm32_spi_read_rxfifo(spi, false);
519 * If communication is suspended while using DMA, it means
520 * that something went wrong, so stop the current transfer
526 if (sr & SPI_SR_MODF) {
527 dev_warn(spi->dev, "Mode fault: transfer aborted\n");
531 if (sr & SPI_SR_OVR) {
532 dev_warn(spi->dev, "Overrun: received value discarded\n");
533 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
534 stm32_spi_read_rxfifo(spi, false);
536 * If overrun is detected while using DMA, it means that
537 * something went wrong, so stop the current transfer
543 if (sr & SPI_SR_EOT) {
544 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
545 stm32_spi_read_rxfifo(spi, true);
550 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0)))
551 stm32_spi_write_txfifo(spi);
554 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
555 stm32_spi_read_rxfifo(spi, false);
557 writel_relaxed(mask, spi->base + STM32_SPI_IFCR);
559 spin_unlock_irqrestore(&spi->lock, flags);
562 spi_finalize_current_transfer(master);
563 stm32_spi_disable(spi);
570 * stm32_spi_setup - setup device chip select
572 static int stm32_spi_setup(struct spi_device *spi_dev)
576 if (!gpio_is_valid(spi_dev->cs_gpio)) {
577 dev_err(&spi_dev->dev, "%d is not a valid gpio\n",
582 dev_dbg(&spi_dev->dev, "%s: set gpio%d output %s\n", __func__,
584 (spi_dev->mode & SPI_CS_HIGH) ? "low" : "high");
586 ret = gpio_direction_output(spi_dev->cs_gpio,
587 !(spi_dev->mode & SPI_CS_HIGH));
593 * stm32_spi_prepare_msg - set up the controller to transfer a single message
595 static int stm32_spi_prepare_msg(struct spi_master *master,
596 struct spi_message *msg)
598 struct stm32_spi *spi = spi_master_get_devdata(master);
599 struct spi_device *spi_dev = msg->spi;
600 struct device_node *np = spi_dev->dev.of_node;
602 u32 cfg2_clrb = 0, cfg2_setb = 0;
604 /* SPI slave device may need time between data frames */
606 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi))
607 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
609 if (spi_dev->mode & SPI_CPOL)
610 cfg2_setb |= SPI_CFG2_CPOL;
612 cfg2_clrb |= SPI_CFG2_CPOL;
614 if (spi_dev->mode & SPI_CPHA)
615 cfg2_setb |= SPI_CFG2_CPHA;
617 cfg2_clrb |= SPI_CFG2_CPHA;
619 if (spi_dev->mode & SPI_LSB_FIRST)
620 cfg2_setb |= SPI_CFG2_LSBFRST;
622 cfg2_clrb |= SPI_CFG2_LSBFRST;
624 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
625 spi_dev->mode & SPI_CPOL,
626 spi_dev->mode & SPI_CPHA,
627 spi_dev->mode & SPI_LSB_FIRST,
628 spi_dev->mode & SPI_CS_HIGH);
630 spin_lock_irqsave(&spi->lock, flags);
632 if (cfg2_clrb || cfg2_setb)
634 (readl_relaxed(spi->base + STM32_SPI_CFG2) &
635 ~cfg2_clrb) | cfg2_setb,
636 spi->base + STM32_SPI_CFG2);
638 spin_unlock_irqrestore(&spi->lock, flags);
644 * stm32_spi_dma_cb - dma callback
646 * DMA callback is called when the transfer is complete or when an error
647 * occurs. If the transfer is complete, EOT flag is raised.
649 static void stm32_spi_dma_cb(void *data)
651 struct stm32_spi *spi = data;
655 spin_lock_irqsave(&spi->lock, flags);
657 sr = readl_relaxed(spi->base + STM32_SPI_SR);
659 spin_unlock_irqrestore(&spi->lock, flags);
661 if (!(sr & SPI_SR_EOT))
662 dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr);
664 /* Now wait for EOT, or SUSP or OVR in case of error */
668 * stm32_spi_dma_config - configure dma slave channel depending on current
669 * transfer bits_per_word.
671 static void stm32_spi_dma_config(struct stm32_spi *spi,
672 struct dma_slave_config *dma_conf,
673 enum dma_transfer_direction dir)
675 enum dma_slave_buswidth buswidth;
678 if (spi->cur_bpw <= 8)
679 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
680 else if (spi->cur_bpw <= 16)
681 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
683 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
685 /* Valid for DMA Half or Full Fifo threshold */
686 if (spi->cur_fthlv == 2)
689 maxburst = spi->cur_fthlv;
691 memset(dma_conf, 0, sizeof(struct dma_slave_config));
692 dma_conf->direction = dir;
693 if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */
694 dma_conf->src_addr = spi->phys_addr + STM32_SPI_RXDR;
695 dma_conf->src_addr_width = buswidth;
696 dma_conf->src_maxburst = maxburst;
698 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
700 } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */
701 dma_conf->dst_addr = spi->phys_addr + STM32_SPI_TXDR;
702 dma_conf->dst_addr_width = buswidth;
703 dma_conf->dst_maxburst = maxburst;
705 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n",
711 * stm32_spi_transfer_one_irq - transfer a single spi_transfer using
714 * It must returns 0 if the transfer is finished or 1 if the transfer is still
717 static int stm32_spi_transfer_one_irq(struct stm32_spi *spi)
722 /* Enable the interrupts relative to the current communication mode */
723 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */
724 ier |= SPI_IER_DXPIE;
725 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */
726 ier |= SPI_IER_TXPIE;
727 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */
728 ier |= SPI_IER_RXPIE;
730 /* Enable the interrupts relative to the end of transfer */
731 ier |= SPI_IER_EOTIE | SPI_IER_TXTFIE | SPI_IER_OVRIE | SPI_IER_MODFIE;
733 spin_lock_irqsave(&spi->lock, flags);
735 stm32_spi_enable(spi);
737 /* Be sure to have data in fifo before starting data transfer */
739 stm32_spi_write_txfifo(spi);
741 stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_CSTART);
743 writel_relaxed(ier, spi->base + STM32_SPI_IER);
745 spin_unlock_irqrestore(&spi->lock, flags);
751 * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA
753 * It must returns 0 if the transfer is finished or 1 if the transfer is still
756 static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
757 struct spi_transfer *xfer)
759 struct dma_slave_config tx_dma_conf, rx_dma_conf;
760 struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc;
764 spin_lock_irqsave(&spi->lock, flags);
768 stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM);
769 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
771 /* Enable Rx DMA request */
772 stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_RXDMAEN);
774 rx_dma_desc = dmaengine_prep_slave_sg(
775 spi->dma_rx, xfer->rx_sg.sgl,
777 rx_dma_conf.direction,
783 stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV);
784 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf);
786 tx_dma_desc = dmaengine_prep_slave_sg(
787 spi->dma_tx, xfer->tx_sg.sgl,
789 tx_dma_conf.direction,
793 if ((spi->tx_buf && !tx_dma_desc) ||
794 (spi->rx_buf && !rx_dma_desc))
798 rx_dma_desc->callback = stm32_spi_dma_cb;
799 rx_dma_desc->callback_param = spi;
801 if (dma_submit_error(dmaengine_submit(rx_dma_desc))) {
802 dev_err(spi->dev, "Rx DMA submit failed\n");
805 /* Enable Rx DMA channel */
806 dma_async_issue_pending(spi->dma_rx);
810 if (spi->cur_comm == SPI_SIMPLEX_TX) {
811 tx_dma_desc->callback = stm32_spi_dma_cb;
812 tx_dma_desc->callback_param = spi;
815 if (dma_submit_error(dmaengine_submit(tx_dma_desc))) {
816 dev_err(spi->dev, "Tx DMA submit failed\n");
817 goto dma_submit_error;
819 /* Enable Tx DMA channel */
820 dma_async_issue_pending(spi->dma_tx);
822 /* Enable Tx DMA request */
823 stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_TXDMAEN);
826 /* Enable the interrupts relative to the end of transfer */
827 ier |= SPI_IER_EOTIE | SPI_IER_TXTFIE | SPI_IER_OVRIE | SPI_IER_MODFIE;
828 writel_relaxed(ier, spi->base + STM32_SPI_IER);
830 stm32_spi_enable(spi);
832 stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_CSTART);
834 spin_unlock_irqrestore(&spi->lock, flags);
840 dmaengine_terminate_all(spi->dma_rx);
843 stm32_spi_clr_bits(spi, STM32_SPI_CFG1, SPI_CFG1_RXDMAEN);
845 spin_unlock_irqrestore(&spi->lock, flags);
847 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n");
849 return stm32_spi_transfer_one_irq(spi);
853 * stm32_spi_transfer_one_setup - common setup to transfer a single
854 * spi_transfer either using DMA or
857 static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
858 struct spi_device *spi_dev,
859 struct spi_transfer *transfer)
862 u32 cfg1_clrb = 0, cfg1_setb = 0, cfg2_clrb = 0, cfg2_setb = 0;
866 spin_lock_irqsave(&spi->lock, flags);
868 if (spi->cur_bpw != transfer->bits_per_word) {
871 spi->cur_bpw = transfer->bits_per_word;
872 bpw = spi->cur_bpw - 1;
874 cfg1_clrb |= SPI_CFG1_DSIZE;
875 cfg1_setb |= (bpw << SPI_CFG1_DSIZE_SHIFT) & SPI_CFG1_DSIZE;
877 spi->cur_fthlv = stm32_spi_prepare_fthlv(spi);
878 fthlv = spi->cur_fthlv - 1;
880 cfg1_clrb |= SPI_CFG1_FTHLV;
881 cfg1_setb |= (fthlv << SPI_CFG1_FTHLV_SHIFT) & SPI_CFG1_FTHLV;
884 if (spi->cur_speed != transfer->speed_hz) {
887 /* Update spi->cur_speed with real clock speed */
888 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz);
894 transfer->speed_hz = spi->cur_speed;
896 cfg1_clrb |= SPI_CFG1_MBR;
897 cfg1_setb |= ((u32)mbr << SPI_CFG1_MBR_SHIFT) & SPI_CFG1_MBR;
900 if (cfg1_clrb || cfg1_setb)
901 writel_relaxed((readl_relaxed(spi->base + STM32_SPI_CFG1) &
902 ~cfg1_clrb) | cfg1_setb,
903 spi->base + STM32_SPI_CFG1);
905 mode = SPI_FULL_DUPLEX;
906 if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */
908 * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL
909 * is forbidden und unvalidated by SPI subsystem so depending
910 * on the valid buffer, we can determine the direction of the
913 mode = SPI_HALF_DUPLEX;
914 if (!transfer->tx_buf)
915 stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_HDDIR);
916 else if (!transfer->rx_buf)
917 stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_HDDIR);
919 if (!transfer->tx_buf)
920 mode = SPI_SIMPLEX_RX;
921 else if (!transfer->rx_buf)
922 mode = SPI_SIMPLEX_TX;
924 if (spi->cur_comm != mode) {
925 spi->cur_comm = mode;
927 cfg2_clrb |= SPI_CFG2_COMM;
928 cfg2_setb |= (mode << SPI_CFG2_COMM_SHIFT) & SPI_CFG2_COMM;
931 cfg2_clrb |= SPI_CFG2_MIDI;
932 if ((transfer->len > 1) && (spi->cur_midi > 0)) {
933 u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed);
934 u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
935 (u32)SPI_CFG2_MIDI >> SPI_CFG2_MIDI_SHIFT);
937 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
938 sck_period_ns, midi, midi * sck_period_ns);
940 cfg2_setb |= (midi << SPI_CFG2_MIDI_SHIFT) & SPI_CFG2_MIDI;
943 if (cfg2_clrb || cfg2_setb)
944 writel_relaxed((readl_relaxed(spi->base + STM32_SPI_CFG2) &
945 ~cfg2_clrb) | cfg2_setb,
946 spi->base + STM32_SPI_CFG2);
948 if (spi->cur_bpw <= 8)
949 nb_words = transfer->len;
950 else if (spi->cur_bpw <= 16)
951 nb_words = DIV_ROUND_UP(transfer->len * 8, 16);
953 nb_words = DIV_ROUND_UP(transfer->len * 8, 32);
954 nb_words <<= SPI_CR2_TSIZE_SHIFT;
956 if (nb_words <= SPI_CR2_TSIZE) {
957 writel_relaxed(nb_words, spi->base + STM32_SPI_CR2);
963 spi->cur_xferlen = transfer->len;
965 dev_dbg(spi->dev, "transfer communication mode set to %d\n",
968 "data frame of %d-bit, data packet of %d data frames\n",
969 spi->cur_bpw, spi->cur_fthlv);
970 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed);
971 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n",
972 spi->cur_xferlen, nb_words);
973 dev_dbg(spi->dev, "dma %s\n",
974 (spi->cur_usedma) ? "enabled" : "disabled");
977 spin_unlock_irqrestore(&spi->lock, flags);
983 * stm32_spi_transfer_one - transfer a single spi_transfer
985 * It must return 0 if the transfer is finished or 1 if the transfer is still
988 static int stm32_spi_transfer_one(struct spi_master *master,
989 struct spi_device *spi_dev,
990 struct spi_transfer *transfer)
992 struct stm32_spi *spi = spi_master_get_devdata(master);
995 /* Don't do anything on 0 bytes transfers */
996 if (transfer->len == 0)
999 spi->tx_buf = transfer->tx_buf;
1000 spi->rx_buf = transfer->rx_buf;
1001 spi->tx_len = spi->tx_buf ? transfer->len : 0;
1002 spi->rx_len = spi->rx_buf ? transfer->len : 0;
1004 spi->cur_usedma = (master->can_dma &&
1005 stm32_spi_can_dma(master, spi_dev, transfer));
1007 ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer);
1009 dev_err(spi->dev, "SPI transfer setup failed\n");
1013 if (spi->cur_usedma)
1014 return stm32_spi_transfer_one_dma(spi, transfer);
1016 return stm32_spi_transfer_one_irq(spi);
1020 * stm32_spi_unprepare_msg - relax the hardware
1022 * Normally, if TSIZE has been configured, we should relax the hardware at the
1023 * reception of the EOT interrupt. But in case of error, EOT will not be
1024 * raised. So the subsystem unprepare_message call allows us to properly
1025 * complete the transfer from an hardware point of view.
1027 static int stm32_spi_unprepare_msg(struct spi_master *master,
1028 struct spi_message *msg)
1030 struct stm32_spi *spi = spi_master_get_devdata(master);
1032 stm32_spi_disable(spi);
1038 * stm32_spi_config - Configure SPI controller as SPI master
1040 static int stm32_spi_config(struct stm32_spi *spi)
1042 unsigned long flags;
1044 spin_lock_irqsave(&spi->lock, flags);
1046 /* Ensure I2SMOD bit is kept cleared */
1047 stm32_spi_clr_bits(spi, STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD);
1050 * - SS input value high
1051 * - transmitter half duplex direction
1052 * - automatic communication suspend when RX-Fifo is full
1054 stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SSI |
1059 * - Set the master mode (default Motorola mode)
1060 * - Consider 1 master/n slaves configuration and
1061 * SS input value is determined by the SSI bit
1062 * - keep control of all associated GPIOs
1064 stm32_spi_set_bits(spi, STM32_SPI_CFG2, SPI_CFG2_MASTER |
1068 spin_unlock_irqrestore(&spi->lock, flags);
1073 static const struct of_device_id stm32_spi_of_match[] = {
1074 { .compatible = "st,stm32h7-spi", },
1077 MODULE_DEVICE_TABLE(of, stm32_spi_of_match);
1079 static int stm32_spi_probe(struct platform_device *pdev)
1081 struct spi_master *master;
1082 struct stm32_spi *spi;
1083 struct resource *res;
1086 master = spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi));
1088 dev_err(&pdev->dev, "spi master allocation failed\n");
1091 platform_set_drvdata(pdev, master);
1093 spi = spi_master_get_devdata(master);
1094 spi->dev = &pdev->dev;
1095 spi->master = master;
1096 spin_lock_init(&spi->lock);
1098 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1099 spi->base = devm_ioremap_resource(&pdev->dev, res);
1100 if (IS_ERR(spi->base)) {
1101 ret = PTR_ERR(spi->base);
1102 goto err_master_put;
1104 spi->phys_addr = (dma_addr_t)res->start;
1106 spi->irq = platform_get_irq(pdev, 0);
1107 if (spi->irq <= 0) {
1108 dev_err(&pdev->dev, "no irq: %d\n", spi->irq);
1110 goto err_master_put;
1112 ret = devm_request_threaded_irq(&pdev->dev, spi->irq, NULL,
1113 stm32_spi_irq, IRQF_ONESHOT,
1114 pdev->name, master);
1116 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq,
1118 goto err_master_put;
1121 spi->clk = devm_clk_get(&pdev->dev, 0);
1122 if (IS_ERR(spi->clk)) {
1123 ret = PTR_ERR(spi->clk);
1124 dev_err(&pdev->dev, "clk get failed: %d\n", ret);
1125 goto err_master_put;
1128 ret = clk_prepare_enable(spi->clk);
1130 dev_err(&pdev->dev, "clk enable failed: %d\n", ret);
1131 goto err_master_put;
1133 spi->clk_rate = clk_get_rate(spi->clk);
1134 if (!spi->clk_rate) {
1135 dev_err(&pdev->dev, "clk rate = 0\n");
1137 goto err_master_put;
1140 spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1141 if (!IS_ERR(spi->rst)) {
1142 reset_control_assert(spi->rst);
1144 reset_control_deassert(spi->rst);
1147 spi->fifo_size = stm32_spi_get_fifo_size(spi);
1149 ret = stm32_spi_config(spi);
1151 dev_err(&pdev->dev, "controller configuration failed: %d\n",
1153 goto err_clk_disable;
1156 master->dev.of_node = pdev->dev.of_node;
1157 master->auto_runtime_pm = true;
1158 master->bus_num = pdev->id;
1159 master->mode_bits = SPI_MODE_3 | SPI_CS_HIGH | SPI_LSB_FIRST |
1160 SPI_3WIRE | SPI_LOOP;
1161 master->bits_per_word_mask = stm32_spi_get_bpw_mask(spi);
1162 master->max_speed_hz = spi->clk_rate / SPI_MBR_DIV_MIN;
1163 master->min_speed_hz = spi->clk_rate / SPI_MBR_DIV_MAX;
1164 master->setup = stm32_spi_setup;
1165 master->prepare_message = stm32_spi_prepare_msg;
1166 master->transfer_one = stm32_spi_transfer_one;
1167 master->unprepare_message = stm32_spi_unprepare_msg;
1169 spi->dma_tx = dma_request_slave_channel(spi->dev, "tx");
1171 dev_warn(&pdev->dev, "failed to request tx dma channel\n");
1173 master->dma_tx = spi->dma_tx;
1175 spi->dma_rx = dma_request_slave_channel(spi->dev, "rx");
1177 dev_warn(&pdev->dev, "failed to request rx dma channel\n");
1179 master->dma_rx = spi->dma_rx;
1181 if (spi->dma_tx || spi->dma_rx)
1182 master->can_dma = stm32_spi_can_dma;
1184 pm_runtime_set_active(&pdev->dev);
1185 pm_runtime_enable(&pdev->dev);
1187 ret = devm_spi_register_master(&pdev->dev, master);
1189 dev_err(&pdev->dev, "spi master registration failed: %d\n",
1191 goto err_dma_release;
1194 if (!master->cs_gpios) {
1195 dev_err(&pdev->dev, "no CS gpios available\n");
1197 goto err_dma_release;
1200 for (i = 0; i < master->num_chipselect; i++) {
1201 if (!gpio_is_valid(master->cs_gpios[i])) {
1202 dev_err(&pdev->dev, "%i is not a valid gpio\n",
1203 master->cs_gpios[i]);
1205 goto err_dma_release;
1208 ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i],
1211 dev_err(&pdev->dev, "can't get CS gpio %i\n",
1212 master->cs_gpios[i]);
1213 goto err_dma_release;
1217 dev_info(&pdev->dev, "driver initialized\n");
1223 dma_release_channel(spi->dma_tx);
1225 dma_release_channel(spi->dma_rx);
1227 pm_runtime_disable(&pdev->dev);
1229 clk_disable_unprepare(spi->clk);
1231 spi_master_put(master);
1236 static int stm32_spi_remove(struct platform_device *pdev)
1238 struct spi_master *master = platform_get_drvdata(pdev);
1239 struct stm32_spi *spi = spi_master_get_devdata(master);
1241 stm32_spi_disable(spi);
1244 dma_release_channel(master->dma_tx);
1246 dma_release_channel(master->dma_rx);
1248 clk_disable_unprepare(spi->clk);
1250 pm_runtime_disable(&pdev->dev);
1256 static int stm32_spi_runtime_suspend(struct device *dev)
1258 struct spi_master *master = dev_get_drvdata(dev);
1259 struct stm32_spi *spi = spi_master_get_devdata(master);
1261 clk_disable_unprepare(spi->clk);
1266 static int stm32_spi_runtime_resume(struct device *dev)
1268 struct spi_master *master = dev_get_drvdata(dev);
1269 struct stm32_spi *spi = spi_master_get_devdata(master);
1271 return clk_prepare_enable(spi->clk);
1275 #ifdef CONFIG_PM_SLEEP
1276 static int stm32_spi_suspend(struct device *dev)
1278 struct spi_master *master = dev_get_drvdata(dev);
1281 ret = spi_master_suspend(master);
1285 return pm_runtime_force_suspend(dev);
1288 static int stm32_spi_resume(struct device *dev)
1290 struct spi_master *master = dev_get_drvdata(dev);
1291 struct stm32_spi *spi = spi_master_get_devdata(master);
1294 ret = pm_runtime_force_resume(dev);
1298 ret = spi_master_resume(master);
1300 clk_disable_unprepare(spi->clk);
1306 static const struct dev_pm_ops stm32_spi_pm_ops = {
1307 SET_SYSTEM_SLEEP_PM_OPS(stm32_spi_suspend, stm32_spi_resume)
1308 SET_RUNTIME_PM_OPS(stm32_spi_runtime_suspend,
1309 stm32_spi_runtime_resume, NULL)
1312 static struct platform_driver stm32_spi_driver = {
1313 .probe = stm32_spi_probe,
1314 .remove = stm32_spi_remove,
1316 .name = DRIVER_NAME,
1317 .pm = &stm32_spi_pm_ops,
1318 .of_match_table = stm32_spi_of_match,
1322 module_platform_driver(stm32_spi_driver);
1324 MODULE_ALIAS("platform:" DRIVER_NAME);
1325 MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver");
1326 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
1327 MODULE_LICENSE("GPL v2");