drivers/spi/spi-stm32-qspi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
   4  * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
   5  */
   6 #include <linux/bitfield.h>
   7 #include <linux/clk.h>
   8 #include <linux/dmaengine.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/errno.h>
  11 #include <linux/io.h>
  12 #include <linux/iopoll.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/module.h>
  15 #include <linux/mutex.h>
  16 #include <linux/of.h>
  17 #include <linux/of_device.h>
  18 #include <linux/pinctrl/consumer.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/reset.h>
  22 #include <linux/sizes.h>
  23 #include <linux/spi/spi-mem.h>
  24
  25 #define QSPI_CR                 0x00
  26 #define CR_EN                   BIT(0)
  27 #define CR_ABORT                BIT(1)
  28 #define CR_DMAEN                BIT(2)
  29 #define CR_TCEN                 BIT(3)
  30 #define CR_SSHIFT               BIT(4)
  31 #define CR_DFM                  BIT(6)
  32 #define CR_FSEL                 BIT(7)
  33 #define CR_FTHRES_SHIFT         8
  34 #define CR_TEIE                 BIT(16)
  35 #define CR_TCIE                 BIT(17)
  36 #define CR_FTIE                 BIT(18)
  37 #define CR_SMIE                 BIT(19)
  38 #define CR_TOIE                 BIT(20)
  39 #define CR_PRESC_MASK           GENMASK(31, 24)
  40
  41 #define QSPI_DCR                0x04
  42 #define DCR_FSIZE_MASK          GENMASK(20, 16)
  43
  44 #define QSPI_SR                 0x08
  45 #define SR_TEF                  BIT(0)
  46 #define SR_TCF                  BIT(1)
  47 #define SR_FTF                  BIT(2)
  48 #define SR_SMF                  BIT(3)
  49 #define SR_TOF                  BIT(4)
  50 #define SR_BUSY                 BIT(5)
  51 #define SR_FLEVEL_MASK          GENMASK(13, 8)
  52
  53 #define QSPI_FCR                0x0c
  54 #define FCR_CTEF                BIT(0)
  55 #define FCR_CTCF                BIT(1)
  56
  57 #define QSPI_DLR                0x10
  58
  59 #define QSPI_CCR                0x14
  60 #define CCR_INST_MASK           GENMASK(7, 0)
  61 #define CCR_IMODE_MASK          GENMASK(9, 8)
  62 #define CCR_ADMODE_MASK         GENMASK(11, 10)
  63 #define CCR_ADSIZE_MASK         GENMASK(13, 12)
  64 #define CCR_DCYC_MASK           GENMASK(22, 18)
  65 #define CCR_DMODE_MASK          GENMASK(25, 24)
  66 #define CCR_FMODE_MASK          GENMASK(27, 26)
  67 #define CCR_FMODE_INDW          (0U << 26)
  68 #define CCR_FMODE_INDR          (1U << 26)
  69 #define CCR_FMODE_APM           (2U << 26)
  70 #define CCR_FMODE_MM            (3U << 26)
  71 #define CCR_BUSWIDTH_0          0x0
  72 #define CCR_BUSWIDTH_1          0x1
  73 #define CCR_BUSWIDTH_2          0x2
  74 #define CCR_BUSWIDTH_4          0x3
  75
  76 #define QSPI_AR                 0x18
  77 #define QSPI_ABR                0x1c
  78 #define QSPI_DR                 0x20
  79 #define QSPI_PSMKR              0x24
  80 #define QSPI_PSMAR              0x28
  81 #define QSPI_PIR                0x2c
  82 #define QSPI_LPTR               0x30
  83
  84 #define STM32_QSPI_MAX_MMAP_SZ  SZ_256M
  85 #define STM32_QSPI_MAX_NORCHIP  2
  86
  87 #define STM32_FIFO_TIMEOUT_US 30000
  88 #define STM32_BUSY_TIMEOUT_US 100000
  89 #define STM32_ABT_TIMEOUT_US 100000
  90 #define STM32_COMP_TIMEOUT_MS 1000
  91 #define STM32_AUTOSUSPEND_DELAY -1
  92
  93 struct stm32_qspi_flash {
  94         struct stm32_qspi *qspi;
  95         u32 cs;
  96         u32 presc;
  97 };
  98
  99 struct stm32_qspi {
 100         struct device *dev;
 101         struct spi_controller *ctrl;
 102         phys_addr_t phys_base;
 103         void __iomem *io_base;
 104         void __iomem *mm_base;
 105         resource_size_t mm_size;
 106         struct clk *clk;
 107         u32 clk_rate;
 108         struct stm32_qspi_flash flash[STM32_QSPI_MAX_NORCHIP];
 109         struct completion data_completion;
 110         u32 fmode;
 111
 112         struct dma_chan *dma_chtx;
 113         struct dma_chan *dma_chrx;
 114         struct completion dma_completion;
 115
 116         u32 cr_reg;
 117         u32 dcr_reg;
 118
 119         /*
 120          * to protect device configuration, could be different between
 121          * 2 flash access (bk1, bk2)
 122          */
 123         struct mutex lock;
 124 };
 125
 126 static irqreturn_t stm32_qspi_irq(int irq, void *dev_id)
 127 {
 128         struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id;
 129         u32 cr, sr;
 130
 131         sr = readl_relaxed(qspi->io_base + QSPI_SR);
 132
 133         if (sr & (SR_TEF | SR_TCF)) {
 134                 /* disable irq */
 135                 cr = readl_relaxed(qspi->io_base + QSPI_CR);
 136                 cr &= ~CR_TCIE & ~CR_TEIE;
 137                 writel_relaxed(cr, qspi->io_base + QSPI_CR);
 138                 complete(&qspi->data_completion);
 139         }
 140
 141         return IRQ_HANDLED;
 142 }
 143
 144 static void stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
 145 {
 146         *val = readb_relaxed(addr);
 147 }
 148
 149 static void stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
 150 {
 151         writeb_relaxed(*val, addr);
 152 }
 153
 154 static int stm32_qspi_tx_poll(struct stm32_qspi *qspi,
 155                               const struct spi_mem_op *op)
 156 {
 157         void (*tx_fifo)(u8 *val, void __iomem *addr);
 158         u32 len = op->data.nbytes, sr;
 159         u8 *buf;
 160         int ret;
 161
 162         if (op->data.dir == SPI_MEM_DATA_IN) {
 163                 tx_fifo = stm32_qspi_read_fifo;
 164                 buf = op->data.buf.in;
 165
 166         } else {
 167                 tx_fifo = stm32_qspi_write_fifo;
 168                 buf = (u8 *)op->data.buf.out;
 169         }
 170
 171         while (len--) {
 172                 ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR,
 173                                                         sr, (sr & SR_FTF), 1,
 174                                                         STM32_FIFO_TIMEOUT_US);
 175                 if (ret) {
 176                         dev_err(qspi->dev, "fifo timeout (len:%d stat:%#x)\n",
 177                                 len, sr);
 178                         return ret;
 179                 }
 180                 tx_fifo(buf++, qspi->io_base + QSPI_DR);
 181         }
 182
 183         return 0;
 184 }
 185
 186 static int stm32_qspi_tx_mm(struct stm32_qspi *qspi,
 187                             const struct spi_mem_op *op)
 188 {
 189         memcpy_fromio(op->data.buf.in, qspi->mm_base + op->addr.val,
 190                       op->data.nbytes);
 191         return 0;
 192 }
 193
 194 static void stm32_qspi_dma_callback(void *arg)
 195 {
 196         struct completion *dma_completion = arg;
 197
 198         complete(dma_completion);
 199 }
 200
 201 static int stm32_qspi_tx_dma(struct stm32_qspi *qspi,
 202                              const struct spi_mem_op *op)
 203 {
 204         struct dma_async_tx_descriptor *desc;
 205         enum dma_transfer_direction dma_dir;
 206         struct dma_chan *dma_ch;
 207         struct sg_table sgt;
 208         dma_cookie_t cookie;
 209         u32 cr, t_out;
 210         int err;
 211
 212         if (op->data.dir == SPI_MEM_DATA_IN) {
 213                 dma_dir = DMA_DEV_TO_MEM;
 214                 dma_ch = qspi->dma_chrx;
 215         } else {
 216                 dma_dir = DMA_MEM_TO_DEV;
 217                 dma_ch = qspi->dma_chtx;
 218         }
 219
 220         /*
 221          * spi_map_buf return -EINVAL if the buffer is not DMA-able
 222          * (DMA-able: in vmalloc | kmap | virt_addr_valid)
 223          */
 224         err = spi_controller_dma_map_mem_op_data(qspi->ctrl, op, &sgt);
 225         if (err)
 226                 return err;
 227
 228         desc = dmaengine_prep_slave_sg(dma_ch, sgt.sgl, sgt.nents,
 229                                        dma_dir, DMA_PREP_INTERRUPT);
 230         if (!desc) {
 231                 err = -ENOMEM;
 232                 goto out_unmap;
 233         }
 234
 235         cr = readl_relaxed(qspi->io_base + QSPI_CR);
 236
 237         reinit_completion(&qspi->dma_completion);
 238         desc->callback = stm32_qspi_dma_callback;
 239         desc->callback_param = &qspi->dma_completion;
 240         cookie = dmaengine_submit(desc);
 241         err = dma_submit_error(cookie);
 242         if (err)
 243                 goto out;
 244
 245         dma_async_issue_pending(dma_ch);
 246
 247         writel_relaxed(cr | CR_DMAEN, qspi->io_base + QSPI_CR);
 248
 249         t_out = sgt.nents * STM32_COMP_TIMEOUT_MS;
 250         if (!wait_for_completion_timeout(&qspi->dma_completion,
 251                                          msecs_to_jiffies(t_out)))
 252                 err = -ETIMEDOUT;
 253
 254         if (err)
 255                 dmaengine_terminate_all(dma_ch);
 256
 257 out:
 258         writel_relaxed(cr & ~CR_DMAEN, qspi->io_base + QSPI_CR);
 259 out_unmap:
 260         spi_controller_dma_unmap_mem_op_data(qspi->ctrl, op, &sgt);
 261
 262         return err;
 263 }
 264
 265 static int stm32_qspi_tx(struct stm32_qspi *qspi, const struct spi_mem_op *op)
 266 {
 267         if (!op->data.nbytes)
 268                 return 0;
 269
 270         if (qspi->fmode == CCR_FMODE_MM)
 271                 return stm32_qspi_tx_mm(qspi, op);
 272         else if ((op->data.dir == SPI_MEM_DATA_IN && qspi->dma_chrx) ||
 273                  (op->data.dir == SPI_MEM_DATA_OUT && qspi->dma_chtx))
 274                 if (!stm32_qspi_tx_dma(qspi, op))
 275                         return 0;
 276
 277         return stm32_qspi_tx_poll(qspi, op);
 278 }
 279
 280 static int stm32_qspi_wait_nobusy(struct stm32_qspi *qspi)
 281 {
 282         u32 sr;
 283
 284         return readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, sr,
 285                                                  !(sr & SR_BUSY), 1,
 286                                                  STM32_BUSY_TIMEOUT_US);
 287 }
 288
 289 static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi,
 290                                const struct spi_mem_op *op)
 291 {
 292         u32 cr, sr;
 293         int err = 0;
 294
 295         if (!op->data.nbytes)
 296                 goto wait_nobusy;
 297
 298         if ((readl_relaxed(qspi->io_base + QSPI_SR) & SR_TCF) ||
 299             qspi->fmode == CCR_FMODE_APM)
 300                 goto out;
 301
 302         reinit_completion(&qspi->data_completion);
 303         cr = readl_relaxed(qspi->io_base + QSPI_CR);
 304         writel_relaxed(cr | CR_TCIE | CR_TEIE, qspi->io_base + QSPI_CR);
 305
 306         if (!wait_for_completion_timeout(&qspi->data_completion,
 307                                 msecs_to_jiffies(STM32_COMP_TIMEOUT_MS))) {
 308                 err = -ETIMEDOUT;
 309         } else {
 310                 sr = readl_relaxed(qspi->io_base + QSPI_SR);
 311                 if (sr & SR_TEF)
 312                         err = -EIO;
 313         }
 314
 315 out:
 316         /* clear flags */
 317         writel_relaxed(FCR_CTCF | FCR_CTEF, qspi->io_base + QSPI_FCR);
 318 wait_nobusy:
 319         if (!err)
 320                 err = stm32_qspi_wait_nobusy(qspi);
 321
 322         return err;
 323 }
 324
 325 static int stm32_qspi_get_mode(struct stm32_qspi *qspi, u8 buswidth)
 326 {
 327         if (buswidth == 4)
 328                 return CCR_BUSWIDTH_4;
 329
 330         return buswidth;
 331 }
 332
 333 static int stm32_qspi_send(struct spi_mem *mem, const struct spi_mem_op *op)
 334 {
 335         struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
 336         struct stm32_qspi_flash *flash = &qspi->flash[mem->spi->chip_select];
 337         u32 ccr, cr, addr_max;
 338         int timeout, err = 0;
 339
 340         dev_dbg(qspi->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
 341                 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
 342                 op->dummy.buswidth, op->data.buswidth,
 343                 op->addr.val, op->data.nbytes);
 344
 345         err = stm32_qspi_wait_nobusy(qspi);
 346         if (err)
 347                 goto abort;
 348
 349         addr_max = op->addr.val + op->data.nbytes + 1;
 350
 351         if (op->data.dir == SPI_MEM_DATA_IN) {
 352                 if (addr_max < qspi->mm_size &&
 353                     op->addr.buswidth)
 354                         qspi->fmode = CCR_FMODE_MM;
 355                 else
 356                         qspi->fmode = CCR_FMODE_INDR;
 357         } else {
 358                 qspi->fmode = CCR_FMODE_INDW;
 359         }
 360
 361         cr = readl_relaxed(qspi->io_base + QSPI_CR);
 362         cr &= ~CR_PRESC_MASK & ~CR_FSEL;
 363         cr |= FIELD_PREP(CR_PRESC_MASK, flash->presc);
 364         cr |= FIELD_PREP(CR_FSEL, flash->cs);
 365         writel_relaxed(cr, qspi->io_base + QSPI_CR);
 366
 367         if (op->data.nbytes)
 368                 writel_relaxed(op->data.nbytes - 1,
 369                                qspi->io_base + QSPI_DLR);
 370         else
 371                 qspi->fmode = CCR_FMODE_INDW;
 372
 373         ccr = qspi->fmode;
 374         ccr |= FIELD_PREP(CCR_INST_MASK, op->cmd.opcode);
 375         ccr |= FIELD_PREP(CCR_IMODE_MASK,
 376                           stm32_qspi_get_mode(qspi, op->cmd.buswidth));
 377
 378         if (op->addr.nbytes) {
 379                 ccr |= FIELD_PREP(CCR_ADMODE_MASK,
 380                                   stm32_qspi_get_mode(qspi, op->addr.buswidth));
 381                 ccr |= FIELD_PREP(CCR_ADSIZE_MASK, op->addr.nbytes - 1);
 382         }
 383
 384         if (op->dummy.buswidth && op->dummy.nbytes)
 385                 ccr |= FIELD_PREP(CCR_DCYC_MASK,
 386                                   op->dummy.nbytes * 8 / op->dummy.buswidth);
 387
 388         if (op->data.nbytes) {
 389                 ccr |= FIELD_PREP(CCR_DMODE_MASK,
 390                                   stm32_qspi_get_mode(qspi, op->data.buswidth));
 391         }
 392
 393         writel_relaxed(ccr, qspi->io_base + QSPI_CCR);
 394
 395         if (op->addr.nbytes && qspi->fmode != CCR_FMODE_MM)
 396                 writel_relaxed(op->addr.val, qspi->io_base + QSPI_AR);
 397
 398         err = stm32_qspi_tx(qspi, op);
 399
 400         /*
 401          * Abort in:
 402          * -error case
 403          * -read memory map: prefetching must be stopped if we read the last
 404          *  byte of device (device size - fifo size). like device size is not
 405          *  knows, the prefetching is always stop.
 406          */
 407         if (err || qspi->fmode == CCR_FMODE_MM)
 408                 goto abort;
 409
 410         /* wait end of tx in indirect mode */
 411         err = stm32_qspi_wait_cmd(qspi, op);
 412         if (err)
 413                 goto abort;
 414
 415         return 0;
 416
 417 abort:
 418         cr = readl_relaxed(qspi->io_base + QSPI_CR) | CR_ABORT;
 419         writel_relaxed(cr, qspi->io_base + QSPI_CR);
 420
 421         /* wait clear of abort bit by hw */
 422         timeout = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_CR,
 423                                                     cr, !(cr & CR_ABORT), 1,
 424                                                     STM32_ABT_TIMEOUT_US);
 425
 426         writel_relaxed(FCR_CTCF, qspi->io_base + QSPI_FCR);
 427
 428         if (err || timeout)
 429                 dev_err(qspi->dev, "%s err:%d abort timeout:%d\n",
 430                         __func__, err, timeout);
 431
 432         return err;
 433 }
 434
 435 static int stm32_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
 436 {
 437         struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
 438         int ret;
 439
 440         ret = pm_runtime_get_sync(qspi->dev);
 441         if (ret < 0) {
 442                 pm_runtime_put_noidle(qspi->dev);
 443                 return ret;
 444         }
 445
 446         mutex_lock(&qspi->lock);
 447         ret = stm32_qspi_send(mem, op);
 448         mutex_unlock(&qspi->lock);
 449
 450         pm_runtime_mark_last_busy(qspi->dev);
 451         pm_runtime_put_autosuspend(qspi->dev);
 452
 453         return ret;
 454 }
 455
 456 static int stm32_qspi_setup(struct spi_device *spi)
 457 {
 458         struct spi_controller *ctrl = spi->master;
 459         struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl);
 460         struct stm32_qspi_flash *flash;
 461         u32 presc;
 462         int ret;
 463
 464         if (ctrl->busy)
 465                 return -EBUSY;
 466
 467         if (!spi->max_speed_hz)
 468                 return -EINVAL;
 469
 470         ret = pm_runtime_get_sync(qspi->dev);
 471         if (ret < 0) {
 472                 pm_runtime_put_noidle(qspi->dev);
 473                 return ret;
 474         }
 475
 476         presc = DIV_ROUND_UP(qspi->clk_rate, spi->max_speed_hz) - 1;
 477
 478         flash = &qspi->flash[spi->chip_select];
 479         flash->qspi = qspi;
 480         flash->cs = spi->chip_select;
 481         flash->presc = presc;
 482
 483         mutex_lock(&qspi->lock);
 484         qspi->cr_reg = 3 << CR_FTHRES_SHIFT | CR_SSHIFT | CR_EN;
 485         writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
 486
 487         /* set dcr fsize to max address */
 488         qspi->dcr_reg = DCR_FSIZE_MASK;
 489         writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
 490         mutex_unlock(&qspi->lock);
 491
 492         pm_runtime_mark_last_busy(qspi->dev);
 493         pm_runtime_put_autosuspend(qspi->dev);
 494
 495         return 0;
 496 }
 497
 498 static int stm32_qspi_dma_setup(struct stm32_qspi *qspi)
 499 {
 500         struct dma_slave_config dma_cfg;
 501         struct device *dev = qspi->dev;
 502         int ret = 0;
 503
 504         memset(&dma_cfg, 0, sizeof(dma_cfg));
 505
 506         dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 507         dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 508         dma_cfg.src_addr = qspi->phys_base + QSPI_DR;
 509         dma_cfg.dst_addr = qspi->phys_base + QSPI_DR;
 510         dma_cfg.src_maxburst = 4;
 511         dma_cfg.dst_maxburst = 4;
 512
 513         qspi->dma_chrx = dma_request_chan(dev, "rx");
 514         if (IS_ERR(qspi->dma_chrx)) {
 515                 ret = PTR_ERR(qspi->dma_chrx);
 516                 qspi->dma_chrx = NULL;
 517                 if (ret == -EPROBE_DEFER)
 518                         goto out;
 519         } else {
 520                 if (dmaengine_slave_config(qspi->dma_chrx, &dma_cfg)) {
 521                         dev_err(dev, "dma rx config failed\n");
 522                         dma_release_channel(qspi->dma_chrx);
 523                         qspi->dma_chrx = NULL;
 524                 }
 525         }
 526
 527         qspi->dma_chtx = dma_request_chan(dev, "tx");
 528         if (IS_ERR(qspi->dma_chtx)) {
 529                 ret = PTR_ERR(qspi->dma_chtx);
 530                 qspi->dma_chtx = NULL;
 531         } else {
 532                 if (dmaengine_slave_config(qspi->dma_chtx, &dma_cfg)) {
 533                         dev_err(dev, "dma tx config failed\n");
 534                         dma_release_channel(qspi->dma_chtx);
 535                         qspi->dma_chtx = NULL;
 536                 }
 537         }
 538
 539 out:
 540         init_completion(&qspi->dma_completion);
 541
 542         if (ret != -EPROBE_DEFER)
 543                 ret = 0;
 544
 545         return ret;
 546 }
 547
 548 static void stm32_qspi_dma_free(struct stm32_qspi *qspi)
 549 {
 550         if (qspi->dma_chtx)
 551                 dma_release_channel(qspi->dma_chtx);
 552         if (qspi->dma_chrx)
 553                 dma_release_channel(qspi->dma_chrx);
 554 }
 555
 556 /*
 557  * no special host constraint, so use default spi_mem_default_supports_op
 558  * to check supported mode.
 559  */
 560 static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
 561         .exec_op = stm32_qspi_exec_op,
 562 };
 563
 564 static int stm32_qspi_probe(struct platform_device *pdev)
 565 {
 566         struct device *dev = &pdev->dev;
 567         struct spi_controller *ctrl;
 568         struct reset_control *rstc;
 569         struct stm32_qspi *qspi;
 570         struct resource *res;
 571         int ret, irq;
 572
 573         ctrl = spi_alloc_master(dev, sizeof(*qspi));
 574         if (!ctrl)
 575                 return -ENOMEM;
 576
 577         qspi = spi_controller_get_devdata(ctrl);
 578         qspi->ctrl = ctrl;
 579
 580         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi");
 581         qspi->io_base = devm_ioremap_resource(dev, res);
 582         if (IS_ERR(qspi->io_base)) {
 583                 ret = PTR_ERR(qspi->io_base);
 584                 goto err_master_put;
 585         }
 586
 587         qspi->phys_base = res->start;
 588
 589         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm");
 590         qspi->mm_base = devm_ioremap_resource(dev, res);
 591         if (IS_ERR(qspi->mm_base)) {
 592                 ret = PTR_ERR(qspi->mm_base);
 593                 goto err_master_put;
 594         }
 595
 596         qspi->mm_size = resource_size(res);
 597         if (qspi->mm_size > STM32_QSPI_MAX_MMAP_SZ) {
 598                 ret = -EINVAL;
 599                 goto err_master_put;
 600         }
 601
 602         irq = platform_get_irq(pdev, 0);
 603         if (irq < 0) {
 604                 ret = irq;
 605                 goto err_master_put;
 606         }
 607
 608         ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0,
 609                                dev_name(dev), qspi);
 610         if (ret) {
 611                 dev_err(dev, "failed to request irq\n");
 612                 goto err_master_put;
 613         }
 614
 615         init_completion(&qspi->data_completion);
 616
 617         qspi->clk = devm_clk_get(dev, NULL);
 618         if (IS_ERR(qspi->clk)) {
 619                 ret = PTR_ERR(qspi->clk);
 620                 goto err_master_put;
 621         }
 622
 623         qspi->clk_rate = clk_get_rate(qspi->clk);
 624         if (!qspi->clk_rate) {
 625                 ret = -EINVAL;
 626                 goto err_master_put;
 627         }
 628
 629         ret = clk_prepare_enable(qspi->clk);
 630         if (ret) {
 631                 dev_err(dev, "can not enable the clock\n");
 632                 goto err_master_put;
 633         }
 634
 635         rstc = devm_reset_control_get_exclusive(dev, NULL);
 636         if (IS_ERR(rstc)) {
 637                 ret = PTR_ERR(rstc);
 638                 if (ret == -EPROBE_DEFER)
 639                         goto err_clk_disable;
 640         } else {
 641                 reset_control_assert(rstc);
 642                 udelay(2);
 643                 reset_control_deassert(rstc);
 644         }
 645
 646         qspi->dev = dev;
 647         platform_set_drvdata(pdev, qspi);
 648         ret = stm32_qspi_dma_setup(qspi);
 649         if (ret)
 650                 goto err_dma_free;
 651
 652         mutex_init(&qspi->lock);
 653
 654         ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD
 655                 | SPI_TX_DUAL | SPI_TX_QUAD;
 656         ctrl->setup = stm32_qspi_setup;
 657         ctrl->bus_num = -1;
 658         ctrl->mem_ops = &stm32_qspi_mem_ops;
 659         ctrl->num_chipselect = STM32_QSPI_MAX_NORCHIP;
 660         ctrl->dev.of_node = dev->of_node;
 661
 662         pm_runtime_set_autosuspend_delay(dev, STM32_AUTOSUSPEND_DELAY);
 663         pm_runtime_use_autosuspend(dev);
 664         pm_runtime_set_active(dev);
 665         pm_runtime_enable(dev);
 666         pm_runtime_get_noresume(dev);
 667
 668         ret = devm_spi_register_master(dev, ctrl);
 669         if (ret)
 670                 goto err_pm_runtime_free;
 671
 672         pm_runtime_mark_last_busy(dev);
 673         pm_runtime_put_autosuspend(dev);
 674
 675         return 0;
 676
 677 err_pm_runtime_free:
 678         pm_runtime_get_sync(qspi->dev);
 679         /* disable qspi */
 680         writel_relaxed(0, qspi->io_base + QSPI_CR);
 681         mutex_destroy(&qspi->lock);
 682         pm_runtime_put_noidle(qspi->dev);
 683         pm_runtime_disable(qspi->dev);
 684         pm_runtime_set_suspended(qspi->dev);
 685         pm_runtime_dont_use_autosuspend(qspi->dev);
 686 err_dma_free:
 687         stm32_qspi_dma_free(qspi);
 688 err_clk_disable:
 689         clk_disable_unprepare(qspi->clk);
 690 err_master_put:
 691         spi_master_put(qspi->ctrl);
 692
 693         return ret;
 694 }
 695
 696 static int stm32_qspi_remove(struct platform_device *pdev)
 697 {
 698         struct stm32_qspi *qspi = platform_get_drvdata(pdev);
 699
 700         pm_runtime_get_sync(qspi->dev);
 701         /* disable qspi */
 702         writel_relaxed(0, qspi->io_base + QSPI_CR);
 703         stm32_qspi_dma_free(qspi);
 704         mutex_destroy(&qspi->lock);
 705         pm_runtime_put_noidle(qspi->dev);
 706         pm_runtime_disable(qspi->dev);
 707         pm_runtime_set_suspended(qspi->dev);
 708         pm_runtime_dont_use_autosuspend(qspi->dev);
 709         clk_disable_unprepare(qspi->clk);
 710
 711         return 0;
 712 }
 713
 714 static int __maybe_unused stm32_qspi_runtime_suspend(struct device *dev)
 715 {
 716         struct stm32_qspi *qspi = dev_get_drvdata(dev);
 717
 718         clk_disable_unprepare(qspi->clk);
 719
 720         return 0;
 721 }
 722
 723 static int __maybe_unused stm32_qspi_runtime_resume(struct device *dev)
 724 {
 725         struct stm32_qspi *qspi = dev_get_drvdata(dev);
 726
 727         return clk_prepare_enable(qspi->clk);
 728 }
 729
 730 static int __maybe_unused stm32_qspi_suspend(struct device *dev)
 731 {
 732         pinctrl_pm_select_sleep_state(dev);
 733
 734         return pm_runtime_force_suspend(dev);
 735 }
 736
 737 static int __maybe_unused stm32_qspi_resume(struct device *dev)
 738 {
 739         struct stm32_qspi *qspi = dev_get_drvdata(dev);
 740         int ret;
 741
 742         ret = pm_runtime_force_resume(dev);
 743         if (ret < 0)
 744                 return ret;
 745
 746         pinctrl_pm_select_default_state(dev);
 747
 748         ret = pm_runtime_get_sync(dev);
 749         if (ret < 0) {
 750                 pm_runtime_put_noidle(dev);
 751                 return ret;
 752         }
 753
 754         writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
 755         writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
 756
 757         pm_runtime_mark_last_busy(dev);
 758         pm_runtime_put_autosuspend(dev);
 759
 760         return 0;
 761 }
 762
 763 static const struct dev_pm_ops stm32_qspi_pm_ops = {
 764         SET_RUNTIME_PM_OPS(stm32_qspi_runtime_suspend,
 765                            stm32_qspi_runtime_resume, NULL)
 766         SET_SYSTEM_SLEEP_PM_OPS(stm32_qspi_suspend, stm32_qspi_resume)
 767 };
 768
 769 static const struct of_device_id stm32_qspi_match[] = {
 770         {.compatible = "st,stm32f469-qspi"},
 771         {}
 772 };
 773 MODULE_DEVICE_TABLE(of, stm32_qspi_match);
 774
 775 static struct platform_driver stm32_qspi_driver = {
 776         .probe  = stm32_qspi_probe,
 777         .remove = stm32_qspi_remove,
 778         .driver = {
 779                 .name = "stm32-qspi",
 780                 .of_match_table = stm32_qspi_match,
 781                 .pm = &stm32_qspi_pm_ops,
 782         },
 783 };
 784 module_platform_driver(stm32_qspi_driver);
 785
 786 MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
 787 MODULE_DESCRIPTION("STMicroelectronics STM32 quad spi driver");
 788 MODULE_LICENSE("GPL v2");