2 * SuperH MSIOF SPI Master Interface
4 * Copyright (c) 2009 Magnus Damm
5 * Copyright (C) 2014 Renesas Electronics Corporation
6 * Copyright (C) 2014-2017 Glider bvba
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 #include <linux/bitmap.h>
15 #include <linux/clk.h>
16 #include <linux/completion.h>
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/dmaengine.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
27 #include <linux/of_device.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/sh_dma.h>
32 #include <linux/spi/sh_msiof.h>
33 #include <linux/spi/spi.h>
35 #include <asm/unaligned.h>
37 struct sh_msiof_chipdata {
44 struct sh_msiof_spi_priv {
45 struct spi_master *master;
46 void __iomem *mapbase;
48 struct platform_device *pdev;
49 struct sh_msiof_spi_info *info;
50 struct completion done;
51 unsigned int tx_fifo_size;
52 unsigned int rx_fifo_size;
56 dma_addr_t tx_dma_addr;
57 dma_addr_t rx_dma_addr;
58 bool native_cs_inited;
63 #define TMDR1 0x00 /* Transmit Mode Register 1 */
64 #define TMDR2 0x04 /* Transmit Mode Register 2 */
65 #define TMDR3 0x08 /* Transmit Mode Register 3 */
66 #define RMDR1 0x10 /* Receive Mode Register 1 */
67 #define RMDR2 0x14 /* Receive Mode Register 2 */
68 #define RMDR3 0x18 /* Receive Mode Register 3 */
69 #define TSCR 0x20 /* Transmit Clock Select Register */
70 #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
71 #define CTR 0x28 /* Control Register */
72 #define FCTR 0x30 /* FIFO Control Register */
73 #define STR 0x40 /* Status Register */
74 #define IER 0x44 /* Interrupt Enable Register */
75 #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
76 #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
77 #define TFDR 0x50 /* Transmit FIFO Data Register */
78 #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
79 #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
80 #define RFDR 0x60 /* Receive FIFO Data Register */
83 #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */
84 #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */
85 #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */
86 #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */
87 #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
88 #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
89 #define MDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
90 #define MDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
91 #define MDR1_FLD_MASK 0x0000000c /* Frame Sync Signal Interval (0-3) */
92 #define MDR1_FLD_SHIFT 2
93 #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */
95 #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */
98 #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
99 #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
100 #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */
103 #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */
104 #define SCR_BRPS(i) (((i) - 1) << 8)
105 #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */
106 #define SCR_BRDV_DIV_2 0x0000
107 #define SCR_BRDV_DIV_4 0x0001
108 #define SCR_BRDV_DIV_8 0x0002
109 #define SCR_BRDV_DIV_16 0x0003
110 #define SCR_BRDV_DIV_32 0x0004
111 #define SCR_BRDV_DIV_1 0x0007
114 #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */
115 #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */
116 #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
117 #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */
118 #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */
119 #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
120 #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
121 #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
122 #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */
123 #define CTR_TXDIZ_LOW 0x00000000 /* 0 */
124 #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */
125 #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */
126 #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */
127 #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */
128 #define CTR_TXE 0x00000200 /* Transmit Enable */
129 #define CTR_RXE 0x00000100 /* Receive Enable */
132 #define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */
133 #define FCTR_TFWM_64 0x00000000 /* Transfer Request when 64 empty stages */
134 #define FCTR_TFWM_32 0x20000000 /* Transfer Request when 32 empty stages */
135 #define FCTR_TFWM_24 0x40000000 /* Transfer Request when 24 empty stages */
136 #define FCTR_TFWM_16 0x60000000 /* Transfer Request when 16 empty stages */
137 #define FCTR_TFWM_12 0x80000000 /* Transfer Request when 12 empty stages */
138 #define FCTR_TFWM_8 0xa0000000 /* Transfer Request when 8 empty stages */
139 #define FCTR_TFWM_4 0xc0000000 /* Transfer Request when 4 empty stages */
140 #define FCTR_TFWM_1 0xe0000000 /* Transfer Request when 1 empty stage */
141 #define FCTR_TFUA_MASK 0x07f00000 /* Transmit FIFO Usable Area */
142 #define FCTR_TFUA_SHIFT 20
143 #define FCTR_TFUA(i) ((i) << FCTR_TFUA_SHIFT)
144 #define FCTR_RFWM_MASK 0x0000e000 /* Receive FIFO Watermark */
145 #define FCTR_RFWM_1 0x00000000 /* Transfer Request when 1 valid stages */
146 #define FCTR_RFWM_4 0x00002000 /* Transfer Request when 4 valid stages */
147 #define FCTR_RFWM_8 0x00004000 /* Transfer Request when 8 valid stages */
148 #define FCTR_RFWM_16 0x00006000 /* Transfer Request when 16 valid stages */
149 #define FCTR_RFWM_32 0x00008000 /* Transfer Request when 32 valid stages */
150 #define FCTR_RFWM_64 0x0000a000 /* Transfer Request when 64 valid stages */
151 #define FCTR_RFWM_128 0x0000c000 /* Transfer Request when 128 valid stages */
152 #define FCTR_RFWM_256 0x0000e000 /* Transfer Request when 256 valid stages */
153 #define FCTR_RFUA_MASK 0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */
154 #define FCTR_RFUA_SHIFT 4
155 #define FCTR_RFUA(i) ((i) << FCTR_RFUA_SHIFT)
158 #define STR_TFEMP 0x20000000 /* Transmit FIFO Empty */
159 #define STR_TDREQ 0x10000000 /* Transmit Data Transfer Request */
160 #define STR_TEOF 0x00800000 /* Frame Transmission End */
161 #define STR_TFSERR 0x00200000 /* Transmit Frame Synchronization Error */
162 #define STR_TFOVF 0x00100000 /* Transmit FIFO Overflow */
163 #define STR_TFUDF 0x00080000 /* Transmit FIFO Underflow */
164 #define STR_RFFUL 0x00002000 /* Receive FIFO Full */
165 #define STR_RDREQ 0x00001000 /* Receive Data Transfer Request */
166 #define STR_REOF 0x00000080 /* Frame Reception End */
167 #define STR_RFSERR 0x00000020 /* Receive Frame Synchronization Error */
168 #define STR_RFUDF 0x00000010 /* Receive FIFO Underflow */
169 #define STR_RFOVF 0x00000008 /* Receive FIFO Overflow */
172 #define IER_TDMAE 0x80000000 /* Transmit Data DMA Transfer Req. Enable */
173 #define IER_TFEMPE 0x20000000 /* Transmit FIFO Empty Enable */
174 #define IER_TDREQE 0x10000000 /* Transmit Data Transfer Request Enable */
175 #define IER_TEOFE 0x00800000 /* Frame Transmission End Enable */
176 #define IER_TFSERRE 0x00200000 /* Transmit Frame Sync Error Enable */
177 #define IER_TFOVFE 0x00100000 /* Transmit FIFO Overflow Enable */
178 #define IER_TFUDFE 0x00080000 /* Transmit FIFO Underflow Enable */
179 #define IER_RDMAE 0x00008000 /* Receive Data DMA Transfer Req. Enable */
180 #define IER_RFFULE 0x00002000 /* Receive FIFO Full Enable */
181 #define IER_RDREQE 0x00001000 /* Receive Data Transfer Request Enable */
182 #define IER_REOFE 0x00000080 /* Frame Reception End Enable */
183 #define IER_RFSERRE 0x00000020 /* Receive Frame Sync Error Enable */
184 #define IER_RFUDFE 0x00000010 /* Receive FIFO Underflow Enable */
185 #define IER_RFOVFE 0x00000008 /* Receive FIFO Overflow Enable */
188 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
193 return ioread16(p->mapbase + reg_offs);
195 return ioread32(p->mapbase + reg_offs);
199 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
205 iowrite16(value, p->mapbase + reg_offs);
208 iowrite32(value, p->mapbase + reg_offs);
213 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
216 u32 mask = clr | set;
220 data = sh_msiof_read(p, CTR);
223 sh_msiof_write(p, CTR, data);
225 for (k = 100; k > 0; k--) {
226 if ((sh_msiof_read(p, CTR) & mask) == set)
232 return k > 0 ? 0 : -ETIMEDOUT;
235 static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
237 struct sh_msiof_spi_priv *p = data;
239 /* just disable the interrupt and wake up */
240 sh_msiof_write(p, IER, 0);
249 } const sh_msiof_spi_div_table[] = {
250 { 1, SCR_BRDV_DIV_1 },
251 { 2, SCR_BRDV_DIV_2 },
252 { 4, SCR_BRDV_DIV_4 },
253 { 8, SCR_BRDV_DIV_8 },
254 { 16, SCR_BRDV_DIV_16 },
255 { 32, SCR_BRDV_DIV_32 },
258 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
259 unsigned long parent_rate, u32 spi_hz)
261 unsigned long div = 1024;
265 if (!WARN_ON(!spi_hz || !parent_rate))
266 div = DIV_ROUND_UP(parent_rate, spi_hz);
268 div = max_t(unsigned long, div, p->min_div);
270 for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_div_table); k++) {
271 brps = DIV_ROUND_UP(div, sh_msiof_spi_div_table[k].div);
272 /* SCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
273 if (sh_msiof_spi_div_table[k].div == 1 && brps > 2)
275 if (brps <= 32) /* max of brdv is 32 */
279 k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_div_table) - 1);
280 brps = min_t(int, brps, 32);
282 scr = sh_msiof_spi_div_table[k].brdv | SCR_BRPS(brps);
283 sh_msiof_write(p, TSCR, scr);
284 if (!(p->master->flags & SPI_MASTER_MUST_TX))
285 sh_msiof_write(p, RSCR, scr);
288 static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)
291 * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl
295 * b'011 (SYNCDL only) : 300
299 if (dtdl_or_syncdl % 100)
300 return dtdl_or_syncdl / 100 + 5;
302 return dtdl_or_syncdl / 100;
305 static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p)
312 /* check if DTDL and SYNCDL is allowed value */
313 if (p->info->dtdl > 200 || p->info->syncdl > 300) {
314 dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n");
318 /* check if the sum of DTDL and SYNCDL becomes an integer value */
319 if ((p->info->dtdl + p->info->syncdl) % 100) {
320 dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n");
324 val = sh_msiof_get_delay_bit(p->info->dtdl) << MDR1_DTDL_SHIFT;
325 val |= sh_msiof_get_delay_bit(p->info->syncdl) << MDR1_SYNCDL_SHIFT;
330 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
332 u32 tx_hi_z, u32 lsb_first, u32 cs_high)
338 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
344 tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
345 tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
346 tmp |= lsb_first << MDR1_BITLSB_SHIFT;
347 tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
348 if (spi_controller_is_slave(p->master))
349 sh_msiof_write(p, TMDR1, tmp | TMDR1_PCON);
351 sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON);
352 if (p->master->flags & SPI_MASTER_MUST_TX) {
353 /* These bits are reserved if RX needs TX */
356 sh_msiof_write(p, RMDR1, tmp);
359 tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT;
360 tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT;
364 tmp |= edge << CTR_TEDG_SHIFT;
365 tmp |= edge << CTR_REDG_SHIFT;
366 tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW;
367 sh_msiof_write(p, CTR, tmp);
370 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
371 const void *tx_buf, void *rx_buf,
374 u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words);
376 if (tx_buf || (p->master->flags & SPI_MASTER_MUST_TX))
377 sh_msiof_write(p, TMDR2, dr2);
379 sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1);
382 sh_msiof_write(p, RMDR2, dr2);
385 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
387 sh_msiof_write(p, STR,
388 sh_msiof_read(p, STR) & ~(STR_TDREQ | STR_RDREQ));
391 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
392 const void *tx_buf, int words, int fs)
394 const u8 *buf_8 = tx_buf;
397 for (k = 0; k < words; k++)
398 sh_msiof_write(p, TFDR, buf_8[k] << fs);
401 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
402 const void *tx_buf, int words, int fs)
404 const u16 *buf_16 = tx_buf;
407 for (k = 0; k < words; k++)
408 sh_msiof_write(p, TFDR, buf_16[k] << fs);
411 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
412 const void *tx_buf, int words, int fs)
414 const u16 *buf_16 = tx_buf;
417 for (k = 0; k < words; k++)
418 sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
421 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
422 const void *tx_buf, int words, int fs)
424 const u32 *buf_32 = tx_buf;
427 for (k = 0; k < words; k++)
428 sh_msiof_write(p, TFDR, buf_32[k] << fs);
431 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
432 const void *tx_buf, int words, int fs)
434 const u32 *buf_32 = tx_buf;
437 for (k = 0; k < words; k++)
438 sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
441 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
442 const void *tx_buf, int words, int fs)
444 const u32 *buf_32 = tx_buf;
447 for (k = 0; k < words; k++)
448 sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs));
451 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
452 const void *tx_buf, int words, int fs)
454 const u32 *buf_32 = tx_buf;
457 for (k = 0; k < words; k++)
458 sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs));
461 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
462 void *rx_buf, int words, int fs)
467 for (k = 0; k < words; k++)
468 buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
471 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
472 void *rx_buf, int words, int fs)
474 u16 *buf_16 = rx_buf;
477 for (k = 0; k < words; k++)
478 buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
481 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
482 void *rx_buf, int words, int fs)
484 u16 *buf_16 = rx_buf;
487 for (k = 0; k < words; k++)
488 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
491 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
492 void *rx_buf, int words, int fs)
494 u32 *buf_32 = rx_buf;
497 for (k = 0; k < words; k++)
498 buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
501 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
502 void *rx_buf, int words, int fs)
504 u32 *buf_32 = rx_buf;
507 for (k = 0; k < words; k++)
508 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
511 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
512 void *rx_buf, int words, int fs)
514 u32 *buf_32 = rx_buf;
517 for (k = 0; k < words; k++)
518 buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs);
521 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
522 void *rx_buf, int words, int fs)
524 u32 *buf_32 = rx_buf;
527 for (k = 0; k < words; k++)
528 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
531 static int sh_msiof_spi_setup(struct spi_device *spi)
533 struct device_node *np = spi->master->dev.of_node;
534 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
539 * Use spi->controller_data for CS (same strategy as spi_gpio),
540 * if any. otherwise let HW control CS
542 spi->cs_gpio = (uintptr_t)spi->controller_data;
545 if (spi->cs_gpio >= 0) {
546 gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
550 if (spi_controller_is_slave(p->master))
553 if (p->native_cs_inited &&
554 (p->native_cs_high == !!(spi->mode & SPI_CS_HIGH)))
557 /* Configure native chip select mode/polarity early */
558 clr = MDR1_SYNCMD_MASK;
559 set = MDR1_SYNCMD_SPI;
560 if (spi->mode & SPI_CS_HIGH)
561 clr |= BIT(MDR1_SYNCAC_SHIFT);
563 set |= BIT(MDR1_SYNCAC_SHIFT);
564 pm_runtime_get_sync(&p->pdev->dev);
565 tmp = sh_msiof_read(p, TMDR1) & ~clr;
566 sh_msiof_write(p, TMDR1, tmp | set | MDR1_TRMD | TMDR1_PCON);
567 tmp = sh_msiof_read(p, RMDR1) & ~clr;
568 sh_msiof_write(p, RMDR1, tmp | set);
569 pm_runtime_put(&p->pdev->dev);
570 p->native_cs_high = spi->mode & SPI_CS_HIGH;
571 p->native_cs_inited = true;
575 static int sh_msiof_prepare_message(struct spi_master *master,
576 struct spi_message *msg)
578 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
579 const struct spi_device *spi = msg->spi;
581 /* Configure pins before asserting CS */
582 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
583 !!(spi->mode & SPI_CPHA),
584 !!(spi->mode & SPI_3WIRE),
585 !!(spi->mode & SPI_LSB_FIRST),
586 !!(spi->mode & SPI_CS_HIGH));
590 static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
592 bool slave = spi_controller_is_slave(p->master);
595 /* setup clock and rx/tx signals */
597 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
599 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
601 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
603 /* start by setting frame bit */
605 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
610 static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
612 bool slave = spi_controller_is_slave(p->master);
615 /* shut down frame, rx/tx and clock signals */
617 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
619 ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
621 ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
623 ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
628 static int sh_msiof_slave_abort(struct spi_master *master)
630 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
632 p->slave_aborted = true;
637 static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p)
639 if (spi_controller_is_slave(p->master)) {
640 if (wait_for_completion_interruptible(&p->done) ||
642 dev_dbg(&p->pdev->dev, "interrupted\n");
646 if (!wait_for_completion_timeout(&p->done, HZ)) {
647 dev_err(&p->pdev->dev, "timeout\n");
655 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
656 void (*tx_fifo)(struct sh_msiof_spi_priv *,
657 const void *, int, int),
658 void (*rx_fifo)(struct sh_msiof_spi_priv *,
660 const void *tx_buf, void *rx_buf,
666 /* limit maximum word transfer to rx/tx fifo size */
668 words = min_t(int, words, p->tx_fifo_size);
670 words = min_t(int, words, p->rx_fifo_size);
672 /* the fifo contents need shifting */
673 fifo_shift = 32 - bits;
675 /* default FIFO watermarks for PIO */
676 sh_msiof_write(p, FCTR, 0);
678 /* setup msiof transfer mode registers */
679 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
680 sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE);
684 tx_fifo(p, tx_buf, words, fifo_shift);
686 reinit_completion(&p->done);
687 p->slave_aborted = false;
689 ret = sh_msiof_spi_start(p, rx_buf);
691 dev_err(&p->pdev->dev, "failed to start hardware\n");
695 /* wait for tx fifo to be emptied / rx fifo to be filled */
696 ret = sh_msiof_wait_for_completion(p);
702 rx_fifo(p, rx_buf, words, fifo_shift);
704 /* clear status bits */
705 sh_msiof_reset_str(p);
707 ret = sh_msiof_spi_stop(p, rx_buf);
709 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
716 sh_msiof_reset_str(p);
717 sh_msiof_spi_stop(p, rx_buf);
719 sh_msiof_write(p, IER, 0);
723 static void sh_msiof_dma_complete(void *arg)
725 struct sh_msiof_spi_priv *p = arg;
727 sh_msiof_write(p, IER, 0);
731 static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
732 void *rx, unsigned int len)
735 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
739 /* First prepare and submit the DMA request(s), as this may fail */
741 ier_bits |= IER_RDREQE | IER_RDMAE;
742 desc_rx = dmaengine_prep_slave_single(p->master->dma_rx,
743 p->rx_dma_addr, len, DMA_FROM_DEVICE,
744 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
748 desc_rx->callback = sh_msiof_dma_complete;
749 desc_rx->callback_param = p;
750 cookie = dmaengine_submit(desc_rx);
751 if (dma_submit_error(cookie))
756 ier_bits |= IER_TDREQE | IER_TDMAE;
757 dma_sync_single_for_device(p->master->dma_tx->device->dev,
758 p->tx_dma_addr, len, DMA_TO_DEVICE);
759 desc_tx = dmaengine_prep_slave_single(p->master->dma_tx,
760 p->tx_dma_addr, len, DMA_TO_DEVICE,
761 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
769 desc_tx->callback = NULL;
771 desc_tx->callback = sh_msiof_dma_complete;
772 desc_tx->callback_param = p;
774 cookie = dmaengine_submit(desc_tx);
775 if (dma_submit_error(cookie)) {
781 /* 1 stage FIFO watermarks for DMA */
782 sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1);
784 /* setup msiof transfer mode registers (32-bit words) */
785 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
787 sh_msiof_write(p, IER, ier_bits);
789 reinit_completion(&p->done);
790 p->slave_aborted = false;
794 dma_async_issue_pending(p->master->dma_rx);
796 dma_async_issue_pending(p->master->dma_tx);
798 ret = sh_msiof_spi_start(p, rx);
800 dev_err(&p->pdev->dev, "failed to start hardware\n");
804 /* wait for tx/rx DMA completion */
805 ret = sh_msiof_wait_for_completion(p);
810 reinit_completion(&p->done);
811 sh_msiof_write(p, IER, IER_TEOFE);
813 /* wait for tx fifo to be emptied */
814 ret = sh_msiof_wait_for_completion(p);
819 /* clear status bits */
820 sh_msiof_reset_str(p);
822 ret = sh_msiof_spi_stop(p, rx);
824 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
829 dma_sync_single_for_cpu(p->master->dma_rx->device->dev,
836 sh_msiof_reset_str(p);
837 sh_msiof_spi_stop(p, rx);
840 dmaengine_terminate_all(p->master->dma_tx);
843 dmaengine_terminate_all(p->master->dma_rx);
844 sh_msiof_write(p, IER, 0);
848 static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words)
850 /* src or dst can be unaligned, but not both */
851 if ((unsigned long)src & 3) {
853 *dst++ = swab32(get_unaligned(src));
856 } else if ((unsigned long)dst & 3) {
858 put_unaligned(swab32(*src++), dst);
863 *dst++ = swab32(*src++);
867 static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words)
869 /* src or dst can be unaligned, but not both */
870 if ((unsigned long)src & 3) {
872 *dst++ = swahw32(get_unaligned(src));
875 } else if ((unsigned long)dst & 3) {
877 put_unaligned(swahw32(*src++), dst);
882 *dst++ = swahw32(*src++);
886 static void copy_plain32(u32 *dst, const u32 *src, unsigned int words)
888 memcpy(dst, src, words * 4);
891 static int sh_msiof_transfer_one(struct spi_master *master,
892 struct spi_device *spi,
893 struct spi_transfer *t)
895 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
896 void (*copy32)(u32 *, const u32 *, unsigned int);
897 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
898 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
899 const void *tx_buf = t->tx_buf;
900 void *rx_buf = t->rx_buf;
901 unsigned int len = t->len;
902 unsigned int bits = t->bits_per_word;
903 unsigned int bytes_per_word;
909 /* setup clocks (clock already enabled in chipselect()) */
910 if (!spi_controller_is_slave(p->master))
911 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
913 while (master->dma_tx && len > 15) {
915 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit
916 * words, with byte resp. word swapping.
921 l = min(len, p->tx_fifo_size * 4);
923 l = min(len, p->rx_fifo_size * 4);
928 copy32 = copy_bswap32;
929 } else if (bits <= 16) {
932 copy32 = copy_wswap32;
934 copy32 = copy_plain32;
938 copy32(p->tx_dma_page, tx_buf, l / 4);
940 ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l);
941 if (ret == -EAGAIN) {
942 pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
943 dev_driver_string(&p->pdev->dev),
944 dev_name(&p->pdev->dev));
951 copy32(rx_buf, p->rx_dma_page, l / 4);
962 if (bits <= 8 && len > 15 && !(len & 3)) {
969 /* setup bytes per word and fifo read/write functions */
972 tx_fifo = sh_msiof_spi_write_fifo_8;
973 rx_fifo = sh_msiof_spi_read_fifo_8;
974 } else if (bits <= 16) {
976 if ((unsigned long)tx_buf & 0x01)
977 tx_fifo = sh_msiof_spi_write_fifo_16u;
979 tx_fifo = sh_msiof_spi_write_fifo_16;
981 if ((unsigned long)rx_buf & 0x01)
982 rx_fifo = sh_msiof_spi_read_fifo_16u;
984 rx_fifo = sh_msiof_spi_read_fifo_16;
987 if ((unsigned long)tx_buf & 0x03)
988 tx_fifo = sh_msiof_spi_write_fifo_s32u;
990 tx_fifo = sh_msiof_spi_write_fifo_s32;
992 if ((unsigned long)rx_buf & 0x03)
993 rx_fifo = sh_msiof_spi_read_fifo_s32u;
995 rx_fifo = sh_msiof_spi_read_fifo_s32;
998 if ((unsigned long)tx_buf & 0x03)
999 tx_fifo = sh_msiof_spi_write_fifo_32u;
1001 tx_fifo = sh_msiof_spi_write_fifo_32;
1003 if ((unsigned long)rx_buf & 0x03)
1004 rx_fifo = sh_msiof_spi_read_fifo_32u;
1006 rx_fifo = sh_msiof_spi_read_fifo_32;
1009 /* transfer in fifo sized chunks */
1010 words = len / bytes_per_word;
1013 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf,
1019 tx_buf += n * bytes_per_word;
1021 rx_buf += n * bytes_per_word;
1028 static const struct sh_msiof_chipdata sh_data = {
1035 static const struct sh_msiof_chipdata rcar_gen2_data = {
1038 .master_flags = SPI_MASTER_MUST_TX,
1042 static const struct sh_msiof_chipdata rcar_gen3_data = {
1045 .master_flags = SPI_MASTER_MUST_TX,
1049 static const struct of_device_id sh_msiof_match[] = {
1050 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
1051 { .compatible = "renesas,msiof-r8a7790", .data = &rcar_gen2_data },
1052 { .compatible = "renesas,msiof-r8a7791", .data = &rcar_gen2_data },
1053 { .compatible = "renesas,msiof-r8a7792", .data = &rcar_gen2_data },
1054 { .compatible = "renesas,msiof-r8a7793", .data = &rcar_gen2_data },
1055 { .compatible = "renesas,msiof-r8a7794", .data = &rcar_gen2_data },
1056 { .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data },
1057 { .compatible = "renesas,msiof-r8a7796", .data = &rcar_gen3_data },
1058 { .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data },
1059 { .compatible = "renesas,sh-msiof", .data = &sh_data }, /* Deprecated */
1062 MODULE_DEVICE_TABLE(of, sh_msiof_match);
1065 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1067 struct sh_msiof_spi_info *info;
1068 struct device_node *np = dev->of_node;
1071 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
1075 info->mode = of_property_read_bool(np, "spi-slave") ? MSIOF_SPI_SLAVE
1078 /* Parse the MSIOF properties */
1079 if (info->mode == MSIOF_SPI_MASTER)
1080 of_property_read_u32(np, "num-cs", &num_cs);
1081 of_property_read_u32(np, "renesas,tx-fifo-size",
1082 &info->tx_fifo_override);
1083 of_property_read_u32(np, "renesas,rx-fifo-size",
1084 &info->rx_fifo_override);
1085 of_property_read_u32(np, "renesas,dtdl", &info->dtdl);
1086 of_property_read_u32(np, "renesas,syncdl", &info->syncdl);
1088 info->num_chipselect = num_cs;
1093 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1099 static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev,
1100 enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr)
1102 dma_cap_mask_t mask;
1103 struct dma_chan *chan;
1104 struct dma_slave_config cfg;
1108 dma_cap_set(DMA_SLAVE, mask);
1110 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1111 (void *)(unsigned long)id, dev,
1112 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1114 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1118 memset(&cfg, 0, sizeof(cfg));
1119 cfg.direction = dir;
1120 if (dir == DMA_MEM_TO_DEV) {
1121 cfg.dst_addr = port_addr;
1122 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1124 cfg.src_addr = port_addr;
1125 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1128 ret = dmaengine_slave_config(chan, &cfg);
1130 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1131 dma_release_channel(chan);
1138 static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
1140 struct platform_device *pdev = p->pdev;
1141 struct device *dev = &pdev->dev;
1142 const struct sh_msiof_spi_info *info = dev_get_platdata(dev);
1143 unsigned int dma_tx_id, dma_rx_id;
1144 const struct resource *res;
1145 struct spi_master *master;
1146 struct device *tx_dev, *rx_dev;
1149 /* In the OF case we will get the slave IDs from the DT */
1152 } else if (info && info->dma_tx_id && info->dma_rx_id) {
1153 dma_tx_id = info->dma_tx_id;
1154 dma_rx_id = info->dma_rx_id;
1156 /* The driver assumes no error */
1160 /* The DMA engine uses the second register set, if present */
1161 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1163 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1166 master->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,
1169 if (!master->dma_tx)
1172 master->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,
1175 if (!master->dma_rx)
1178 p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1179 if (!p->tx_dma_page)
1182 p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1183 if (!p->rx_dma_page)
1186 tx_dev = master->dma_tx->device->dev;
1187 p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE,
1189 if (dma_mapping_error(tx_dev, p->tx_dma_addr))
1192 rx_dev = master->dma_rx->device->dev;
1193 p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE,
1195 if (dma_mapping_error(rx_dev, p->rx_dma_addr))
1198 dev_info(dev, "DMA available");
1202 dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE);
1204 free_page((unsigned long)p->rx_dma_page);
1206 free_page((unsigned long)p->tx_dma_page);
1208 dma_release_channel(master->dma_rx);
1210 dma_release_channel(master->dma_tx);
1211 master->dma_tx = NULL;
1215 static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p)
1217 struct spi_master *master = p->master;
1220 if (!master->dma_tx)
1223 dev = &p->pdev->dev;
1224 dma_unmap_single(master->dma_rx->device->dev, p->rx_dma_addr,
1225 PAGE_SIZE, DMA_FROM_DEVICE);
1226 dma_unmap_single(master->dma_tx->device->dev, p->tx_dma_addr,
1227 PAGE_SIZE, DMA_TO_DEVICE);
1228 free_page((unsigned long)p->rx_dma_page);
1229 free_page((unsigned long)p->tx_dma_page);
1230 dma_release_channel(master->dma_rx);
1231 dma_release_channel(master->dma_tx);
1234 static int sh_msiof_spi_probe(struct platform_device *pdev)
1237 struct spi_master *master;
1238 const struct sh_msiof_chipdata *chipdata;
1239 const struct of_device_id *of_id;
1240 struct sh_msiof_spi_info *info;
1241 struct sh_msiof_spi_priv *p;
1245 of_id = of_match_device(sh_msiof_match, &pdev->dev);
1247 chipdata = of_id->data;
1248 info = sh_msiof_spi_parse_dt(&pdev->dev);
1250 chipdata = (const void *)pdev->id_entry->driver_data;
1251 info = dev_get_platdata(&pdev->dev);
1255 dev_err(&pdev->dev, "failed to obtain device info\n");
1259 if (info->mode == MSIOF_SPI_SLAVE)
1260 master = spi_alloc_slave(&pdev->dev,
1261 sizeof(struct sh_msiof_spi_priv));
1263 master = spi_alloc_master(&pdev->dev,
1264 sizeof(struct sh_msiof_spi_priv));
1268 p = spi_master_get_devdata(master);
1270 platform_set_drvdata(pdev, p);
1273 p->min_div = chipdata->min_div;
1275 init_completion(&p->done);
1277 p->clk = devm_clk_get(&pdev->dev, NULL);
1278 if (IS_ERR(p->clk)) {
1279 dev_err(&pdev->dev, "cannot get clock\n");
1280 ret = PTR_ERR(p->clk);
1284 i = platform_get_irq(pdev, 0);
1286 dev_err(&pdev->dev, "cannot get IRQ\n");
1291 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1292 p->mapbase = devm_ioremap_resource(&pdev->dev, r);
1293 if (IS_ERR(p->mapbase)) {
1294 ret = PTR_ERR(p->mapbase);
1298 ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
1299 dev_name(&pdev->dev), p);
1301 dev_err(&pdev->dev, "unable to request irq\n");
1306 pm_runtime_enable(&pdev->dev);
1308 /* Platform data may override FIFO sizes */
1309 p->tx_fifo_size = chipdata->tx_fifo_size;
1310 p->rx_fifo_size = chipdata->rx_fifo_size;
1311 if (p->info->tx_fifo_override)
1312 p->tx_fifo_size = p->info->tx_fifo_override;
1313 if (p->info->rx_fifo_override)
1314 p->rx_fifo_size = p->info->rx_fifo_override;
1316 /* init master code */
1317 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1318 master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
1319 master->flags = chipdata->master_flags;
1320 master->bus_num = pdev->id;
1321 master->dev.of_node = pdev->dev.of_node;
1322 master->num_chipselect = p->info->num_chipselect;
1323 master->setup = sh_msiof_spi_setup;
1324 master->prepare_message = sh_msiof_prepare_message;
1325 master->slave_abort = sh_msiof_slave_abort;
1326 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
1327 master->auto_runtime_pm = true;
1328 master->transfer_one = sh_msiof_transfer_one;
1330 ret = sh_msiof_request_dma(p);
1332 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1334 ret = devm_spi_register_master(&pdev->dev, master);
1336 dev_err(&pdev->dev, "spi_register_master error.\n");
1343 sh_msiof_release_dma(p);
1344 pm_runtime_disable(&pdev->dev);
1346 spi_master_put(master);
1350 static int sh_msiof_spi_remove(struct platform_device *pdev)
1352 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1354 sh_msiof_release_dma(p);
1355 pm_runtime_disable(&pdev->dev);
1359 static const struct platform_device_id spi_driver_ids[] = {
1360 { "spi_sh_msiof", (kernel_ulong_t)&sh_data },
1363 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1365 #ifdef CONFIG_PM_SLEEP
1366 static int sh_msiof_spi_suspend(struct device *dev)
1368 struct platform_device *pdev = to_platform_device(dev);
1369 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1371 return spi_master_suspend(p->master);
1374 static int sh_msiof_spi_resume(struct device *dev)
1376 struct platform_device *pdev = to_platform_device(dev);
1377 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1379 return spi_master_resume(p->master);
1382 static SIMPLE_DEV_PM_OPS(sh_msiof_spi_pm_ops, sh_msiof_spi_suspend,
1383 sh_msiof_spi_resume);
1384 #define DEV_PM_OPS &sh_msiof_spi_pm_ops
1386 #define DEV_PM_OPS NULL
1387 #endif /* CONFIG_PM_SLEEP */
1389 static struct platform_driver sh_msiof_spi_drv = {
1390 .probe = sh_msiof_spi_probe,
1391 .remove = sh_msiof_spi_remove,
1392 .id_table = spi_driver_ids,
1394 .name = "spi_sh_msiof",
1396 .of_match_table = of_match_ptr(sh_msiof_match),
1399 module_platform_driver(sh_msiof_spi_drv);
1401 MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver");
1402 MODULE_AUTHOR("Magnus Damm");
1403 MODULE_LICENSE("GPL v2");
1404 MODULE_ALIAS("platform:spi_sh_msiof");