2 * SuperH MSIOF SPI Master Interface
4 * Copyright (c) 2009 Magnus Damm
5 * Copyright (C) 2014 Glider bvba
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
13 #include <linux/bitmap.h>
14 #include <linux/clk.h>
15 #include <linux/completion.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/dmaengine.h>
19 #include <linux/err.h>
20 #include <linux/gpio.h>
21 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
26 #include <linux/of_device.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/sh_dma.h>
31 #include <linux/spi/sh_msiof.h>
32 #include <linux/spi/spi.h>
34 #include <asm/unaligned.h>
37 struct sh_msiof_chipdata {
43 struct sh_msiof_spi_priv {
44 struct spi_master *master;
45 void __iomem *mapbase;
47 struct platform_device *pdev;
48 struct sh_msiof_spi_info *info;
49 struct completion done;
50 unsigned int tx_fifo_size;
51 unsigned int rx_fifo_size;
54 dma_addr_t tx_dma_addr;
55 dma_addr_t rx_dma_addr;
58 #define TMDR1 0x00 /* Transmit Mode Register 1 */
59 #define TMDR2 0x04 /* Transmit Mode Register 2 */
60 #define TMDR3 0x08 /* Transmit Mode Register 3 */
61 #define RMDR1 0x10 /* Receive Mode Register 1 */
62 #define RMDR2 0x14 /* Receive Mode Register 2 */
63 #define RMDR3 0x18 /* Receive Mode Register 3 */
64 #define TSCR 0x20 /* Transmit Clock Select Register */
65 #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
66 #define CTR 0x28 /* Control Register */
67 #define FCTR 0x30 /* FIFO Control Register */
68 #define STR 0x40 /* Status Register */
69 #define IER 0x44 /* Interrupt Enable Register */
70 #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
71 #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
72 #define TFDR 0x50 /* Transmit FIFO Data Register */
73 #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
74 #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
75 #define RFDR 0x60 /* Receive FIFO Data Register */
78 #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */
79 #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */
80 #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */
81 #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */
82 #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
83 #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
84 #define MDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
85 #define MDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
86 #define MDR1_FLD_MASK 0x0000000c /* Frame Sync Signal Interval (0-3) */
87 #define MDR1_FLD_SHIFT 2
88 #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */
90 #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */
93 #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
94 #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
95 #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */
98 #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */
99 #define SCR_BRPS(i) (((i) - 1) << 8)
100 #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */
101 #define SCR_BRDV_DIV_2 0x0000
102 #define SCR_BRDV_DIV_4 0x0001
103 #define SCR_BRDV_DIV_8 0x0002
104 #define SCR_BRDV_DIV_16 0x0003
105 #define SCR_BRDV_DIV_32 0x0004
106 #define SCR_BRDV_DIV_1 0x0007
109 #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */
110 #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */
111 #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
112 #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */
113 #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */
114 #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
115 #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
116 #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
117 #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */
118 #define CTR_TXDIZ_LOW 0x00000000 /* 0 */
119 #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */
120 #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */
121 #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */
122 #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */
123 #define CTR_TXE 0x00000200 /* Transmit Enable */
124 #define CTR_RXE 0x00000100 /* Receive Enable */
127 #define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */
128 #define FCTR_TFWM_64 0x00000000 /* Transfer Request when 64 empty stages */
129 #define FCTR_TFWM_32 0x20000000 /* Transfer Request when 32 empty stages */
130 #define FCTR_TFWM_24 0x40000000 /* Transfer Request when 24 empty stages */
131 #define FCTR_TFWM_16 0x60000000 /* Transfer Request when 16 empty stages */
132 #define FCTR_TFWM_12 0x80000000 /* Transfer Request when 12 empty stages */
133 #define FCTR_TFWM_8 0xa0000000 /* Transfer Request when 8 empty stages */
134 #define FCTR_TFWM_4 0xc0000000 /* Transfer Request when 4 empty stages */
135 #define FCTR_TFWM_1 0xe0000000 /* Transfer Request when 1 empty stage */
136 #define FCTR_TFUA_MASK 0x07f00000 /* Transmit FIFO Usable Area */
137 #define FCTR_TFUA_SHIFT 20
138 #define FCTR_TFUA(i) ((i) << FCTR_TFUA_SHIFT)
139 #define FCTR_RFWM_MASK 0x0000e000 /* Receive FIFO Watermark */
140 #define FCTR_RFWM_1 0x00000000 /* Transfer Request when 1 valid stages */
141 #define FCTR_RFWM_4 0x00002000 /* Transfer Request when 4 valid stages */
142 #define FCTR_RFWM_8 0x00004000 /* Transfer Request when 8 valid stages */
143 #define FCTR_RFWM_16 0x00006000 /* Transfer Request when 16 valid stages */
144 #define FCTR_RFWM_32 0x00008000 /* Transfer Request when 32 valid stages */
145 #define FCTR_RFWM_64 0x0000a000 /* Transfer Request when 64 valid stages */
146 #define FCTR_RFWM_128 0x0000c000 /* Transfer Request when 128 valid stages */
147 #define FCTR_RFWM_256 0x0000e000 /* Transfer Request when 256 valid stages */
148 #define FCTR_RFUA_MASK 0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */
149 #define FCTR_RFUA_SHIFT 4
150 #define FCTR_RFUA(i) ((i) << FCTR_RFUA_SHIFT)
153 #define STR_TFEMP 0x20000000 /* Transmit FIFO Empty */
154 #define STR_TDREQ 0x10000000 /* Transmit Data Transfer Request */
155 #define STR_TEOF 0x00800000 /* Frame Transmission End */
156 #define STR_TFSERR 0x00200000 /* Transmit Frame Synchronization Error */
157 #define STR_TFOVF 0x00100000 /* Transmit FIFO Overflow */
158 #define STR_TFUDF 0x00080000 /* Transmit FIFO Underflow */
159 #define STR_RFFUL 0x00002000 /* Receive FIFO Full */
160 #define STR_RDREQ 0x00001000 /* Receive Data Transfer Request */
161 #define STR_REOF 0x00000080 /* Frame Reception End */
162 #define STR_RFSERR 0x00000020 /* Receive Frame Synchronization Error */
163 #define STR_RFUDF 0x00000010 /* Receive FIFO Underflow */
164 #define STR_RFOVF 0x00000008 /* Receive FIFO Overflow */
167 #define IER_TDMAE 0x80000000 /* Transmit Data DMA Transfer Req. Enable */
168 #define IER_TFEMPE 0x20000000 /* Transmit FIFO Empty Enable */
169 #define IER_TDREQE 0x10000000 /* Transmit Data Transfer Request Enable */
170 #define IER_TEOFE 0x00800000 /* Frame Transmission End Enable */
171 #define IER_TFSERRE 0x00200000 /* Transmit Frame Sync Error Enable */
172 #define IER_TFOVFE 0x00100000 /* Transmit FIFO Overflow Enable */
173 #define IER_TFUDFE 0x00080000 /* Transmit FIFO Underflow Enable */
174 #define IER_RDMAE 0x00008000 /* Receive Data DMA Transfer Req. Enable */
175 #define IER_RFFULE 0x00002000 /* Receive FIFO Full Enable */
176 #define IER_RDREQE 0x00001000 /* Receive Data Transfer Request Enable */
177 #define IER_REOFE 0x00000080 /* Frame Reception End Enable */
178 #define IER_RFSERRE 0x00000020 /* Receive Frame Sync Error Enable */
179 #define IER_RFUDFE 0x00000010 /* Receive FIFO Underflow Enable */
180 #define IER_RFOVFE 0x00000008 /* Receive FIFO Overflow Enable */
183 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
188 return ioread16(p->mapbase + reg_offs);
190 return ioread32(p->mapbase + reg_offs);
194 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
200 iowrite16(value, p->mapbase + reg_offs);
203 iowrite32(value, p->mapbase + reg_offs);
208 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
211 u32 mask = clr | set;
215 data = sh_msiof_read(p, CTR);
218 sh_msiof_write(p, CTR, data);
220 for (k = 100; k > 0; k--) {
221 if ((sh_msiof_read(p, CTR) & mask) == set)
227 return k > 0 ? 0 : -ETIMEDOUT;
230 static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
232 struct sh_msiof_spi_priv *p = data;
234 /* just disable the interrupt and wake up */
235 sh_msiof_write(p, IER, 0);
244 } const sh_msiof_spi_div_table[] = {
245 { 1, SCR_BRDV_DIV_1 },
246 { 2, SCR_BRDV_DIV_2 },
247 { 4, SCR_BRDV_DIV_4 },
248 { 8, SCR_BRDV_DIV_8 },
249 { 16, SCR_BRDV_DIV_16 },
250 { 32, SCR_BRDV_DIV_32 },
253 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
254 unsigned long parent_rate, u32 spi_hz)
256 unsigned long div = 1024;
260 if (!WARN_ON(!spi_hz || !parent_rate))
261 div = DIV_ROUND_UP(parent_rate, spi_hz);
263 for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_div_table); k++) {
264 brps = DIV_ROUND_UP(div, sh_msiof_spi_div_table[k].div);
265 /* SCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
266 if (sh_msiof_spi_div_table[k].div == 1 && brps > 2)
268 if (brps <= 32) /* max of brdv is 32 */
272 k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_div_table) - 1);
274 scr = sh_msiof_spi_div_table[k].brdv | SCR_BRPS(brps);
275 sh_msiof_write(p, TSCR, scr);
276 if (!(p->master->flags & SPI_MASTER_MUST_TX))
277 sh_msiof_write(p, RSCR, scr);
280 static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)
283 * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl
287 * b'011 (SYNCDL only) : 300
291 if (dtdl_or_syncdl % 100)
292 return dtdl_or_syncdl / 100 + 5;
294 return dtdl_or_syncdl / 100;
297 static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p)
304 /* check if DTDL and SYNCDL is allowed value */
305 if (p->info->dtdl > 200 || p->info->syncdl > 300) {
306 dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n");
310 /* check if the sum of DTDL and SYNCDL becomes an integer value */
311 if ((p->info->dtdl + p->info->syncdl) % 100) {
312 dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n");
316 val = sh_msiof_get_delay_bit(p->info->dtdl) << MDR1_DTDL_SHIFT;
317 val |= sh_msiof_get_delay_bit(p->info->syncdl) << MDR1_SYNCDL_SHIFT;
322 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
324 u32 tx_hi_z, u32 lsb_first, u32 cs_high)
330 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
336 tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
337 tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
338 tmp |= lsb_first << MDR1_BITLSB_SHIFT;
339 tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
340 sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON);
341 if (p->master->flags & SPI_MASTER_MUST_TX) {
342 /* These bits are reserved if RX needs TX */
345 sh_msiof_write(p, RMDR1, tmp);
348 tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT;
349 tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT;
353 tmp |= edge << CTR_TEDG_SHIFT;
354 tmp |= edge << CTR_REDG_SHIFT;
355 tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW;
356 sh_msiof_write(p, CTR, tmp);
359 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
360 const void *tx_buf, void *rx_buf,
363 u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words);
365 if (tx_buf || (p->master->flags & SPI_MASTER_MUST_TX))
366 sh_msiof_write(p, TMDR2, dr2);
368 sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1);
371 sh_msiof_write(p, RMDR2, dr2);
374 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
376 sh_msiof_write(p, STR,
377 sh_msiof_read(p, STR) & ~(STR_TDREQ | STR_RDREQ));
380 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
381 const void *tx_buf, int words, int fs)
383 const u8 *buf_8 = tx_buf;
386 for (k = 0; k < words; k++)
387 sh_msiof_write(p, TFDR, buf_8[k] << fs);
390 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
391 const void *tx_buf, int words, int fs)
393 const u16 *buf_16 = tx_buf;
396 for (k = 0; k < words; k++)
397 sh_msiof_write(p, TFDR, buf_16[k] << fs);
400 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
401 const void *tx_buf, int words, int fs)
403 const u16 *buf_16 = tx_buf;
406 for (k = 0; k < words; k++)
407 sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
410 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
411 const void *tx_buf, int words, int fs)
413 const u32 *buf_32 = tx_buf;
416 for (k = 0; k < words; k++)
417 sh_msiof_write(p, TFDR, buf_32[k] << fs);
420 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
421 const void *tx_buf, int words, int fs)
423 const u32 *buf_32 = tx_buf;
426 for (k = 0; k < words; k++)
427 sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
430 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
431 const void *tx_buf, int words, int fs)
433 const u32 *buf_32 = tx_buf;
436 for (k = 0; k < words; k++)
437 sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs));
440 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
441 const void *tx_buf, int words, int fs)
443 const u32 *buf_32 = tx_buf;
446 for (k = 0; k < words; k++)
447 sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs));
450 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
451 void *rx_buf, int words, int fs)
456 for (k = 0; k < words; k++)
457 buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
460 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
461 void *rx_buf, int words, int fs)
463 u16 *buf_16 = rx_buf;
466 for (k = 0; k < words; k++)
467 buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
470 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
471 void *rx_buf, int words, int fs)
473 u16 *buf_16 = rx_buf;
476 for (k = 0; k < words; k++)
477 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
480 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
481 void *rx_buf, int words, int fs)
483 u32 *buf_32 = rx_buf;
486 for (k = 0; k < words; k++)
487 buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
490 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
491 void *rx_buf, int words, int fs)
493 u32 *buf_32 = rx_buf;
496 for (k = 0; k < words; k++)
497 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
500 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
501 void *rx_buf, int words, int fs)
503 u32 *buf_32 = rx_buf;
506 for (k = 0; k < words; k++)
507 buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs);
510 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
511 void *rx_buf, int words, int fs)
513 u32 *buf_32 = rx_buf;
516 for (k = 0; k < words; k++)
517 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
520 static int sh_msiof_spi_setup(struct spi_device *spi)
522 struct device_node *np = spi->master->dev.of_node;
523 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
525 pm_runtime_get_sync(&p->pdev->dev);
529 * Use spi->controller_data for CS (same strategy as spi_gpio),
530 * if any. otherwise let HW control CS
532 spi->cs_gpio = (uintptr_t)spi->controller_data;
535 /* Configure pins before deasserting CS */
536 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
537 !!(spi->mode & SPI_CPHA),
538 !!(spi->mode & SPI_3WIRE),
539 !!(spi->mode & SPI_LSB_FIRST),
540 !!(spi->mode & SPI_CS_HIGH));
542 if (spi->cs_gpio >= 0)
543 gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
546 pm_runtime_put(&p->pdev->dev);
551 static int sh_msiof_prepare_message(struct spi_master *master,
552 struct spi_message *msg)
554 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
555 const struct spi_device *spi = msg->spi;
557 /* Configure pins before asserting CS */
558 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
559 !!(spi->mode & SPI_CPHA),
560 !!(spi->mode & SPI_3WIRE),
561 !!(spi->mode & SPI_LSB_FIRST),
562 !!(spi->mode & SPI_CS_HIGH));
566 static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
570 /* setup clock and rx/tx signals */
571 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
573 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
575 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
577 /* start by setting frame bit */
579 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
584 static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
588 /* shut down frame, rx/tx and clock signals */
589 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
591 ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
593 ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
595 ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
600 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
601 void (*tx_fifo)(struct sh_msiof_spi_priv *,
602 const void *, int, int),
603 void (*rx_fifo)(struct sh_msiof_spi_priv *,
605 const void *tx_buf, void *rx_buf,
611 /* limit maximum word transfer to rx/tx fifo size */
613 words = min_t(int, words, p->tx_fifo_size);
615 words = min_t(int, words, p->rx_fifo_size);
617 /* the fifo contents need shifting */
618 fifo_shift = 32 - bits;
620 /* default FIFO watermarks for PIO */
621 sh_msiof_write(p, FCTR, 0);
623 /* setup msiof transfer mode registers */
624 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
625 sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE);
629 tx_fifo(p, tx_buf, words, fifo_shift);
631 reinit_completion(&p->done);
633 ret = sh_msiof_spi_start(p, rx_buf);
635 dev_err(&p->pdev->dev, "failed to start hardware\n");
639 /* wait for tx fifo to be emptied / rx fifo to be filled */
640 if (!wait_for_completion_timeout(&p->done, HZ)) {
641 dev_err(&p->pdev->dev, "PIO timeout\n");
648 rx_fifo(p, rx_buf, words, fifo_shift);
650 /* clear status bits */
651 sh_msiof_reset_str(p);
653 ret = sh_msiof_spi_stop(p, rx_buf);
655 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
662 sh_msiof_reset_str(p);
663 sh_msiof_spi_stop(p, rx_buf);
665 sh_msiof_write(p, IER, 0);
669 static void sh_msiof_dma_complete(void *arg)
671 struct sh_msiof_spi_priv *p = arg;
673 sh_msiof_write(p, IER, 0);
677 static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
678 void *rx, unsigned int len)
681 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
685 /* First prepare and submit the DMA request(s), as this may fail */
687 ier_bits |= IER_RDREQE | IER_RDMAE;
688 desc_rx = dmaengine_prep_slave_single(p->master->dma_rx,
689 p->rx_dma_addr, len, DMA_FROM_DEVICE,
690 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
694 desc_rx->callback = sh_msiof_dma_complete;
695 desc_rx->callback_param = p;
696 cookie = dmaengine_submit(desc_rx);
697 if (dma_submit_error(cookie))
702 ier_bits |= IER_TDREQE | IER_TDMAE;
703 dma_sync_single_for_device(p->master->dma_tx->device->dev,
704 p->tx_dma_addr, len, DMA_TO_DEVICE);
705 desc_tx = dmaengine_prep_slave_single(p->master->dma_tx,
706 p->tx_dma_addr, len, DMA_TO_DEVICE,
707 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
715 desc_tx->callback = NULL;
717 desc_tx->callback = sh_msiof_dma_complete;
718 desc_tx->callback_param = p;
720 cookie = dmaengine_submit(desc_tx);
721 if (dma_submit_error(cookie)) {
727 /* 1 stage FIFO watermarks for DMA */
728 sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1);
730 /* setup msiof transfer mode registers (32-bit words) */
731 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
733 sh_msiof_write(p, IER, ier_bits);
735 reinit_completion(&p->done);
739 dma_async_issue_pending(p->master->dma_rx);
741 dma_async_issue_pending(p->master->dma_tx);
743 ret = sh_msiof_spi_start(p, rx);
745 dev_err(&p->pdev->dev, "failed to start hardware\n");
749 /* wait for tx fifo to be emptied / rx fifo to be filled */
750 if (!wait_for_completion_timeout(&p->done, HZ)) {
751 dev_err(&p->pdev->dev, "DMA timeout\n");
756 /* clear status bits */
757 sh_msiof_reset_str(p);
759 ret = sh_msiof_spi_stop(p, rx);
761 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
766 dma_sync_single_for_cpu(p->master->dma_rx->device->dev,
773 sh_msiof_reset_str(p);
774 sh_msiof_spi_stop(p, rx);
777 dmaengine_terminate_all(p->master->dma_tx);
780 dmaengine_terminate_all(p->master->dma_rx);
781 sh_msiof_write(p, IER, 0);
785 static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words)
787 /* src or dst can be unaligned, but not both */
788 if ((unsigned long)src & 3) {
790 *dst++ = swab32(get_unaligned(src));
793 } else if ((unsigned long)dst & 3) {
795 put_unaligned(swab32(*src++), dst);
800 *dst++ = swab32(*src++);
804 static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words)
806 /* src or dst can be unaligned, but not both */
807 if ((unsigned long)src & 3) {
809 *dst++ = swahw32(get_unaligned(src));
812 } else if ((unsigned long)dst & 3) {
814 put_unaligned(swahw32(*src++), dst);
819 *dst++ = swahw32(*src++);
823 static void copy_plain32(u32 *dst, const u32 *src, unsigned int words)
825 memcpy(dst, src, words * 4);
828 static int sh_msiof_transfer_one(struct spi_master *master,
829 struct spi_device *spi,
830 struct spi_transfer *t)
832 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
833 void (*copy32)(u32 *, const u32 *, unsigned int);
834 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
835 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
836 const void *tx_buf = t->tx_buf;
837 void *rx_buf = t->rx_buf;
838 unsigned int len = t->len;
839 unsigned int bits = t->bits_per_word;
840 unsigned int bytes_per_word;
846 /* setup clocks (clock already enabled in chipselect()) */
847 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
849 while (master->dma_tx && len > 15) {
851 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit
852 * words, with byte resp. word swapping.
857 l = min(len, p->tx_fifo_size * 4);
859 l = min(len, p->rx_fifo_size * 4);
864 copy32 = copy_bswap32;
865 } else if (bits <= 16) {
868 copy32 = copy_wswap32;
870 copy32 = copy_plain32;
874 copy32(p->tx_dma_page, tx_buf, l / 4);
876 ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l);
877 if (ret == -EAGAIN) {
878 pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
879 dev_driver_string(&p->pdev->dev),
880 dev_name(&p->pdev->dev));
887 copy32(rx_buf, p->rx_dma_page, l / 4);
898 if (bits <= 8 && len > 15 && !(len & 3)) {
905 /* setup bytes per word and fifo read/write functions */
908 tx_fifo = sh_msiof_spi_write_fifo_8;
909 rx_fifo = sh_msiof_spi_read_fifo_8;
910 } else if (bits <= 16) {
912 if ((unsigned long)tx_buf & 0x01)
913 tx_fifo = sh_msiof_spi_write_fifo_16u;
915 tx_fifo = sh_msiof_spi_write_fifo_16;
917 if ((unsigned long)rx_buf & 0x01)
918 rx_fifo = sh_msiof_spi_read_fifo_16u;
920 rx_fifo = sh_msiof_spi_read_fifo_16;
923 if ((unsigned long)tx_buf & 0x03)
924 tx_fifo = sh_msiof_spi_write_fifo_s32u;
926 tx_fifo = sh_msiof_spi_write_fifo_s32;
928 if ((unsigned long)rx_buf & 0x03)
929 rx_fifo = sh_msiof_spi_read_fifo_s32u;
931 rx_fifo = sh_msiof_spi_read_fifo_s32;
934 if ((unsigned long)tx_buf & 0x03)
935 tx_fifo = sh_msiof_spi_write_fifo_32u;
937 tx_fifo = sh_msiof_spi_write_fifo_32;
939 if ((unsigned long)rx_buf & 0x03)
940 rx_fifo = sh_msiof_spi_read_fifo_32u;
942 rx_fifo = sh_msiof_spi_read_fifo_32;
945 /* transfer in fifo sized chunks */
946 words = len / bytes_per_word;
949 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf,
955 tx_buf += n * bytes_per_word;
957 rx_buf += n * bytes_per_word;
964 static const struct sh_msiof_chipdata sh_data = {
970 static const struct sh_msiof_chipdata r8a779x_data = {
973 .master_flags = SPI_MASTER_MUST_TX,
976 static const struct of_device_id sh_msiof_match[] = {
977 { .compatible = "renesas,sh-msiof", .data = &sh_data },
978 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
979 { .compatible = "renesas,msiof-r8a7790", .data = &r8a779x_data },
980 { .compatible = "renesas,msiof-r8a7791", .data = &r8a779x_data },
981 { .compatible = "renesas,msiof-r8a7792", .data = &r8a779x_data },
982 { .compatible = "renesas,msiof-r8a7793", .data = &r8a779x_data },
983 { .compatible = "renesas,msiof-r8a7794", .data = &r8a779x_data },
986 MODULE_DEVICE_TABLE(of, sh_msiof_match);
989 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
991 struct sh_msiof_spi_info *info;
992 struct device_node *np = dev->of_node;
995 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
999 /* Parse the MSIOF properties */
1000 of_property_read_u32(np, "num-cs", &num_cs);
1001 of_property_read_u32(np, "renesas,tx-fifo-size",
1002 &info->tx_fifo_override);
1003 of_property_read_u32(np, "renesas,rx-fifo-size",
1004 &info->rx_fifo_override);
1005 of_property_read_u32(np, "renesas,dtdl", &info->dtdl);
1006 of_property_read_u32(np, "renesas,syncdl", &info->syncdl);
1008 info->num_chipselect = num_cs;
1013 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1019 static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev,
1020 enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr)
1022 dma_cap_mask_t mask;
1023 struct dma_chan *chan;
1024 struct dma_slave_config cfg;
1028 dma_cap_set(DMA_SLAVE, mask);
1030 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1031 (void *)(unsigned long)id, dev,
1032 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1034 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1038 memset(&cfg, 0, sizeof(cfg));
1039 cfg.direction = dir;
1040 if (dir == DMA_MEM_TO_DEV) {
1041 cfg.dst_addr = port_addr;
1042 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1044 cfg.src_addr = port_addr;
1045 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1048 ret = dmaengine_slave_config(chan, &cfg);
1050 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1051 dma_release_channel(chan);
1058 static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
1060 struct platform_device *pdev = p->pdev;
1061 struct device *dev = &pdev->dev;
1062 const struct sh_msiof_spi_info *info = dev_get_platdata(dev);
1063 unsigned int dma_tx_id, dma_rx_id;
1064 const struct resource *res;
1065 struct spi_master *master;
1066 struct device *tx_dev, *rx_dev;
1069 /* In the OF case we will get the slave IDs from the DT */
1072 } else if (info && info->dma_tx_id && info->dma_rx_id) {
1073 dma_tx_id = info->dma_tx_id;
1074 dma_rx_id = info->dma_rx_id;
1076 /* The driver assumes no error */
1080 /* The DMA engine uses the second register set, if present */
1081 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1083 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1086 master->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,
1089 if (!master->dma_tx)
1092 master->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,
1095 if (!master->dma_rx)
1098 p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1099 if (!p->tx_dma_page)
1102 p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1103 if (!p->rx_dma_page)
1106 tx_dev = master->dma_tx->device->dev;
1107 p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE,
1109 if (dma_mapping_error(tx_dev, p->tx_dma_addr))
1112 rx_dev = master->dma_rx->device->dev;
1113 p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE,
1115 if (dma_mapping_error(rx_dev, p->rx_dma_addr))
1118 dev_info(dev, "DMA available");
1122 dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE);
1124 free_page((unsigned long)p->rx_dma_page);
1126 free_page((unsigned long)p->tx_dma_page);
1128 dma_release_channel(master->dma_rx);
1130 dma_release_channel(master->dma_tx);
1131 master->dma_tx = NULL;
1135 static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p)
1137 struct spi_master *master = p->master;
1140 if (!master->dma_tx)
1143 dev = &p->pdev->dev;
1144 dma_unmap_single(master->dma_rx->device->dev, p->rx_dma_addr,
1145 PAGE_SIZE, DMA_FROM_DEVICE);
1146 dma_unmap_single(master->dma_tx->device->dev, p->tx_dma_addr,
1147 PAGE_SIZE, DMA_TO_DEVICE);
1148 free_page((unsigned long)p->rx_dma_page);
1149 free_page((unsigned long)p->tx_dma_page);
1150 dma_release_channel(master->dma_rx);
1151 dma_release_channel(master->dma_tx);
1154 static int sh_msiof_spi_probe(struct platform_device *pdev)
1157 struct spi_master *master;
1158 const struct sh_msiof_chipdata *chipdata;
1159 const struct of_device_id *of_id;
1160 struct sh_msiof_spi_priv *p;
1164 master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv));
1165 if (master == NULL) {
1166 dev_err(&pdev->dev, "failed to allocate spi master\n");
1170 p = spi_master_get_devdata(master);
1172 platform_set_drvdata(pdev, p);
1175 of_id = of_match_device(sh_msiof_match, &pdev->dev);
1177 chipdata = of_id->data;
1178 p->info = sh_msiof_spi_parse_dt(&pdev->dev);
1180 chipdata = (const void *)pdev->id_entry->driver_data;
1181 p->info = dev_get_platdata(&pdev->dev);
1185 dev_err(&pdev->dev, "failed to obtain device info\n");
1190 init_completion(&p->done);
1192 p->clk = devm_clk_get(&pdev->dev, NULL);
1193 if (IS_ERR(p->clk)) {
1194 dev_err(&pdev->dev, "cannot get clock\n");
1195 ret = PTR_ERR(p->clk);
1199 i = platform_get_irq(pdev, 0);
1201 dev_err(&pdev->dev, "cannot get IRQ\n");
1206 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1207 p->mapbase = devm_ioremap_resource(&pdev->dev, r);
1208 if (IS_ERR(p->mapbase)) {
1209 ret = PTR_ERR(p->mapbase);
1213 ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
1214 dev_name(&pdev->dev), p);
1216 dev_err(&pdev->dev, "unable to request irq\n");
1221 pm_runtime_enable(&pdev->dev);
1223 /* Platform data may override FIFO sizes */
1224 p->tx_fifo_size = chipdata->tx_fifo_size;
1225 p->rx_fifo_size = chipdata->rx_fifo_size;
1226 if (p->info->tx_fifo_override)
1227 p->tx_fifo_size = p->info->tx_fifo_override;
1228 if (p->info->rx_fifo_override)
1229 p->rx_fifo_size = p->info->rx_fifo_override;
1231 /* init master code */
1232 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1233 master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
1234 master->flags = chipdata->master_flags;
1235 master->bus_num = pdev->id;
1236 master->dev.of_node = pdev->dev.of_node;
1237 master->num_chipselect = p->info->num_chipselect;
1238 master->setup = sh_msiof_spi_setup;
1239 master->prepare_message = sh_msiof_prepare_message;
1240 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
1241 master->auto_runtime_pm = true;
1242 master->transfer_one = sh_msiof_transfer_one;
1244 ret = sh_msiof_request_dma(p);
1246 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1248 ret = devm_spi_register_master(&pdev->dev, master);
1250 dev_err(&pdev->dev, "spi_register_master error.\n");
1257 sh_msiof_release_dma(p);
1258 pm_runtime_disable(&pdev->dev);
1260 spi_master_put(master);
1264 static int sh_msiof_spi_remove(struct platform_device *pdev)
1266 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1268 sh_msiof_release_dma(p);
1269 pm_runtime_disable(&pdev->dev);
1273 static const struct platform_device_id spi_driver_ids[] = {
1274 { "spi_sh_msiof", (kernel_ulong_t)&sh_data },
1277 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1279 #ifdef CONFIG_PM_SLEEP
1280 static int sh_msiof_spi_suspend(struct device *dev)
1282 struct platform_device *pdev = to_platform_device(dev);
1283 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1285 return spi_master_suspend(p->master);
1288 static int sh_msiof_spi_resume(struct device *dev)
1290 struct platform_device *pdev = to_platform_device(dev);
1291 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1293 return spi_master_resume(p->master);
1296 static SIMPLE_DEV_PM_OPS(sh_msiof_spi_pm_ops, sh_msiof_spi_suspend,
1297 sh_msiof_spi_resume);
1298 #define DEV_PM_OPS &sh_msiof_spi_pm_ops
1300 #define DEV_PM_OPS NULL
1301 #endif /* CONFIG_PM_SLEEP */
1303 static struct platform_driver sh_msiof_spi_drv = {
1304 .probe = sh_msiof_spi_probe,
1305 .remove = sh_msiof_spi_remove,
1306 .id_table = spi_driver_ids,
1308 .name = "spi_sh_msiof",
1310 .of_match_table = of_match_ptr(sh_msiof_match),
1313 module_platform_driver(sh_msiof_spi_drv);
1315 MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver");
1316 MODULE_AUTHOR("Magnus Damm");
1317 MODULE_LICENSE("GPL v2");
1318 MODULE_ALIAS("platform:spi_sh_msiof");