GNU Linux-libre 4.14.302-gnu1
[releases.git] / drivers / spi / spi-s3c64xx.c
1 /*
2  * Copyright (C) 2009 Samsung Electronics Ltd.
3  *      Jaswinder Singh <jassi.brar@samsung.com>
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation; either version 2 of the License, or
8  * (at your option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/interrupt.h>
19 #include <linux/delay.h>
20 #include <linux/clk.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/dmaengine.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/spi/spi.h>
26 #include <linux/gpio.h>
27 #include <linux/of.h>
28 #include <linux/of_gpio.h>
29
30 #include <linux/platform_data/spi-s3c64xx.h>
31
32 #define MAX_SPI_PORTS           6
33 #define S3C64XX_SPI_QUIRK_POLL          (1 << 0)
34 #define S3C64XX_SPI_QUIRK_CS_AUTO       (1 << 1)
35 #define AUTOSUSPEND_TIMEOUT     2000
36
37 /* Registers and bit-fields */
38
39 #define S3C64XX_SPI_CH_CFG              0x00
40 #define S3C64XX_SPI_CLK_CFG             0x04
41 #define S3C64XX_SPI_MODE_CFG    0x08
42 #define S3C64XX_SPI_SLAVE_SEL   0x0C
43 #define S3C64XX_SPI_INT_EN              0x10
44 #define S3C64XX_SPI_STATUS              0x14
45 #define S3C64XX_SPI_TX_DATA             0x18
46 #define S3C64XX_SPI_RX_DATA             0x1C
47 #define S3C64XX_SPI_PACKET_CNT  0x20
48 #define S3C64XX_SPI_PENDING_CLR 0x24
49 #define S3C64XX_SPI_SWAP_CFG    0x28
50 #define S3C64XX_SPI_FB_CLK              0x2C
51
52 #define S3C64XX_SPI_CH_HS_EN            (1<<6)  /* High Speed Enable */
53 #define S3C64XX_SPI_CH_SW_RST           (1<<5)
54 #define S3C64XX_SPI_CH_SLAVE            (1<<4)
55 #define S3C64XX_SPI_CPOL_L              (1<<3)
56 #define S3C64XX_SPI_CPHA_B              (1<<2)
57 #define S3C64XX_SPI_CH_RXCH_ON          (1<<1)
58 #define S3C64XX_SPI_CH_TXCH_ON          (1<<0)
59
60 #define S3C64XX_SPI_CLKSEL_SRCMSK       (3<<9)
61 #define S3C64XX_SPI_CLKSEL_SRCSHFT      9
62 #define S3C64XX_SPI_ENCLK_ENABLE        (1<<8)
63 #define S3C64XX_SPI_PSR_MASK            0xff
64
65 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE            (0<<29)
66 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD        (1<<29)
67 #define S3C64XX_SPI_MODE_CH_TSZ_WORD            (2<<29)
68 #define S3C64XX_SPI_MODE_CH_TSZ_MASK            (3<<29)
69 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE           (0<<17)
70 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD       (1<<17)
71 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD           (2<<17)
72 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK           (3<<17)
73 #define S3C64XX_SPI_MODE_RXDMA_ON               (1<<2)
74 #define S3C64XX_SPI_MODE_TXDMA_ON               (1<<1)
75 #define S3C64XX_SPI_MODE_4BURST                 (1<<0)
76
77 #define S3C64XX_SPI_SLAVE_AUTO                  (1<<1)
78 #define S3C64XX_SPI_SLAVE_SIG_INACT             (1<<0)
79 #define S3C64XX_SPI_SLAVE_NSC_CNT_2             (2<<4)
80
81 #define S3C64XX_SPI_INT_TRAILING_EN             (1<<6)
82 #define S3C64XX_SPI_INT_RX_OVERRUN_EN           (1<<5)
83 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN          (1<<4)
84 #define S3C64XX_SPI_INT_TX_OVERRUN_EN           (1<<3)
85 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN          (1<<2)
86 #define S3C64XX_SPI_INT_RX_FIFORDY_EN           (1<<1)
87 #define S3C64XX_SPI_INT_TX_FIFORDY_EN           (1<<0)
88
89 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR           (1<<5)
90 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR  (1<<4)
91 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR           (1<<3)
92 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR  (1<<2)
93 #define S3C64XX_SPI_ST_RX_FIFORDY               (1<<1)
94 #define S3C64XX_SPI_ST_TX_FIFORDY               (1<<0)
95
96 #define S3C64XX_SPI_PACKET_CNT_EN               (1<<16)
97 #define S3C64XX_SPI_PACKET_CNT_MASK             GENMASK(15, 0)
98
99 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR         (1<<4)
100 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR          (1<<3)
101 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR         (1<<2)
102 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR          (1<<1)
103 #define S3C64XX_SPI_PND_TRAILING_CLR            (1<<0)
104
105 #define S3C64XX_SPI_SWAP_RX_HALF_WORD           (1<<7)
106 #define S3C64XX_SPI_SWAP_RX_BYTE                (1<<6)
107 #define S3C64XX_SPI_SWAP_RX_BIT                 (1<<5)
108 #define S3C64XX_SPI_SWAP_RX_EN                  (1<<4)
109 #define S3C64XX_SPI_SWAP_TX_HALF_WORD           (1<<3)
110 #define S3C64XX_SPI_SWAP_TX_BYTE                (1<<2)
111 #define S3C64XX_SPI_SWAP_TX_BIT                 (1<<1)
112 #define S3C64XX_SPI_SWAP_TX_EN                  (1<<0)
113
114 #define S3C64XX_SPI_FBCLK_MSK           (3<<0)
115
116 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
117 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
118                                 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
119 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
120 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
121                                         FIFO_LVL_MASK(i))
122
123 #define S3C64XX_SPI_MAX_TRAILCNT        0x3ff
124 #define S3C64XX_SPI_TRAILCNT_OFF        19
125
126 #define S3C64XX_SPI_TRAILCNT            S3C64XX_SPI_MAX_TRAILCNT
127
128 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
129 #define is_polling(x)   (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
130
131 #define RXBUSY    (1<<2)
132 #define TXBUSY    (1<<3)
133
134 struct s3c64xx_spi_dma_data {
135         struct dma_chan *ch;
136         enum dma_transfer_direction direction;
137 };
138
139 /**
140  * struct s3c64xx_spi_info - SPI Controller hardware info
141  * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
142  * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
143  * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
144  * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
145  * @clk_from_cmu: True, if the controller does not include a clock mux and
146  *      prescaler unit.
147  *
148  * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
149  * differ in some aspects such as the size of the fifo and spi bus clock
150  * setup. Such differences are specified to the driver using this structure
151  * which is provided as driver data to the driver.
152  */
153 struct s3c64xx_spi_port_config {
154         int     fifo_lvl_mask[MAX_SPI_PORTS];
155         int     rx_lvl_offset;
156         int     tx_st_done;
157         int     quirks;
158         bool    high_speed;
159         bool    clk_from_cmu;
160         bool    clk_ioclk;
161 };
162
163 /**
164  * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
165  * @clk: Pointer to the spi clock.
166  * @src_clk: Pointer to the clock used to generate SPI signals.
167  * @ioclk: Pointer to the i/o clock between master and slave
168  * @master: Pointer to the SPI Protocol master.
169  * @cntrlr_info: Platform specific data for the controller this driver manages.
170  * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
171  * @lock: Controller specific lock.
172  * @state: Set of FLAGS to indicate status.
173  * @rx_dmach: Controller's DMA channel for Rx.
174  * @tx_dmach: Controller's DMA channel for Tx.
175  * @sfr_start: BUS address of SPI controller regs.
176  * @regs: Pointer to ioremap'ed controller registers.
177  * @irq: interrupt
178  * @xfer_completion: To indicate completion of xfer task.
179  * @cur_mode: Stores the active configuration of the controller.
180  * @cur_bpw: Stores the active bits per word settings.
181  * @cur_speed: Stores the active xfer clock speed.
182  */
183 struct s3c64xx_spi_driver_data {
184         void __iomem                    *regs;
185         struct clk                      *clk;
186         struct clk                      *src_clk;
187         struct clk                      *ioclk;
188         struct platform_device          *pdev;
189         struct spi_master               *master;
190         struct s3c64xx_spi_info  *cntrlr_info;
191         struct spi_device               *tgl_spi;
192         spinlock_t                      lock;
193         unsigned long                   sfr_start;
194         struct completion               xfer_completion;
195         unsigned                        state;
196         unsigned                        cur_mode, cur_bpw;
197         unsigned                        cur_speed;
198         struct s3c64xx_spi_dma_data     rx_dma;
199         struct s3c64xx_spi_dma_data     tx_dma;
200         struct s3c64xx_spi_port_config  *port_conf;
201         unsigned int                    port_id;
202 };
203
204 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
205 {
206         void __iomem *regs = sdd->regs;
207         unsigned long loops;
208         u32 val;
209
210         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
211
212         val = readl(regs + S3C64XX_SPI_CH_CFG);
213         val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
214         writel(val, regs + S3C64XX_SPI_CH_CFG);
215
216         val = readl(regs + S3C64XX_SPI_CH_CFG);
217         val |= S3C64XX_SPI_CH_SW_RST;
218         val &= ~S3C64XX_SPI_CH_HS_EN;
219         writel(val, regs + S3C64XX_SPI_CH_CFG);
220
221         /* Flush TxFIFO*/
222         loops = msecs_to_loops(1);
223         do {
224                 val = readl(regs + S3C64XX_SPI_STATUS);
225         } while (TX_FIFO_LVL(val, sdd) && loops--);
226
227         if (loops == 0)
228                 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
229
230         /* Flush RxFIFO*/
231         loops = msecs_to_loops(1);
232         do {
233                 val = readl(regs + S3C64XX_SPI_STATUS);
234                 if (RX_FIFO_LVL(val, sdd))
235                         readl(regs + S3C64XX_SPI_RX_DATA);
236                 else
237                         break;
238         } while (loops--);
239
240         if (loops == 0)
241                 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
242
243         val = readl(regs + S3C64XX_SPI_CH_CFG);
244         val &= ~S3C64XX_SPI_CH_SW_RST;
245         writel(val, regs + S3C64XX_SPI_CH_CFG);
246
247         val = readl(regs + S3C64XX_SPI_MODE_CFG);
248         val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
249         writel(val, regs + S3C64XX_SPI_MODE_CFG);
250 }
251
252 static void s3c64xx_spi_dmacb(void *data)
253 {
254         struct s3c64xx_spi_driver_data *sdd;
255         struct s3c64xx_spi_dma_data *dma = data;
256         unsigned long flags;
257
258         if (dma->direction == DMA_DEV_TO_MEM)
259                 sdd = container_of(data,
260                         struct s3c64xx_spi_driver_data, rx_dma);
261         else
262                 sdd = container_of(data,
263                         struct s3c64xx_spi_driver_data, tx_dma);
264
265         spin_lock_irqsave(&sdd->lock, flags);
266
267         if (dma->direction == DMA_DEV_TO_MEM) {
268                 sdd->state &= ~RXBUSY;
269                 if (!(sdd->state & TXBUSY))
270                         complete(&sdd->xfer_completion);
271         } else {
272                 sdd->state &= ~TXBUSY;
273                 if (!(sdd->state & RXBUSY))
274                         complete(&sdd->xfer_completion);
275         }
276
277         spin_unlock_irqrestore(&sdd->lock, flags);
278 }
279
280 static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
281                         struct sg_table *sgt)
282 {
283         struct s3c64xx_spi_driver_data *sdd;
284         struct dma_slave_config config;
285         struct dma_async_tx_descriptor *desc;
286
287         memset(&config, 0, sizeof(config));
288
289         if (dma->direction == DMA_DEV_TO_MEM) {
290                 sdd = container_of((void *)dma,
291                         struct s3c64xx_spi_driver_data, rx_dma);
292                 config.direction = dma->direction;
293                 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
294                 config.src_addr_width = sdd->cur_bpw / 8;
295                 config.src_maxburst = 1;
296                 dmaengine_slave_config(dma->ch, &config);
297         } else {
298                 sdd = container_of((void *)dma,
299                         struct s3c64xx_spi_driver_data, tx_dma);
300                 config.direction = dma->direction;
301                 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
302                 config.dst_addr_width = sdd->cur_bpw / 8;
303                 config.dst_maxburst = 1;
304                 dmaengine_slave_config(dma->ch, &config);
305         }
306
307         desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
308                                        dma->direction, DMA_PREP_INTERRUPT);
309
310         desc->callback = s3c64xx_spi_dmacb;
311         desc->callback_param = dma;
312
313         dmaengine_submit(desc);
314         dma_async_issue_pending(dma->ch);
315 }
316
317 static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
318 {
319         struct s3c64xx_spi_driver_data *sdd =
320                                         spi_master_get_devdata(spi->master);
321
322         if (sdd->cntrlr_info->no_cs)
323                 return;
324
325         if (enable) {
326                 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) {
327                         writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
328                 } else {
329                         u32 ssel = readl(sdd->regs + S3C64XX_SPI_SLAVE_SEL);
330
331                         ssel |= (S3C64XX_SPI_SLAVE_AUTO |
332                                                 S3C64XX_SPI_SLAVE_NSC_CNT_2);
333                         writel(ssel, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
334                 }
335         } else {
336                 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
337                         writel(S3C64XX_SPI_SLAVE_SIG_INACT,
338                                sdd->regs + S3C64XX_SPI_SLAVE_SEL);
339         }
340 }
341
342 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
343 {
344         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
345
346         if (is_polling(sdd))
347                 return 0;
348
349         spi->dma_rx = sdd->rx_dma.ch;
350         spi->dma_tx = sdd->tx_dma.ch;
351
352         return 0;
353 }
354
355 static bool s3c64xx_spi_can_dma(struct spi_master *master,
356                                 struct spi_device *spi,
357                                 struct spi_transfer *xfer)
358 {
359         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
360
361         return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
362 }
363
364 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
365                                 struct spi_device *spi,
366                                 struct spi_transfer *xfer, int dma_mode)
367 {
368         void __iomem *regs = sdd->regs;
369         u32 modecfg, chcfg;
370
371         modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
372         modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
373
374         chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
375         chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
376
377         if (dma_mode) {
378                 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
379         } else {
380                 /* Always shift in data in FIFO, even if xfer is Tx only,
381                  * this helps setting PCKT_CNT value for generating clocks
382                  * as exactly needed.
383                  */
384                 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
385                 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
386                                         | S3C64XX_SPI_PACKET_CNT_EN,
387                                         regs + S3C64XX_SPI_PACKET_CNT);
388         }
389
390         if (xfer->tx_buf != NULL) {
391                 sdd->state |= TXBUSY;
392                 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
393                 if (dma_mode) {
394                         modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
395                         prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
396                 } else {
397                         switch (sdd->cur_bpw) {
398                         case 32:
399                                 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
400                                         xfer->tx_buf, xfer->len / 4);
401                                 break;
402                         case 16:
403                                 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
404                                         xfer->tx_buf, xfer->len / 2);
405                                 break;
406                         default:
407                                 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
408                                         xfer->tx_buf, xfer->len);
409                                 break;
410                         }
411                 }
412         }
413
414         if (xfer->rx_buf != NULL) {
415                 sdd->state |= RXBUSY;
416
417                 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
418                                         && !(sdd->cur_mode & SPI_CPHA))
419                         chcfg |= S3C64XX_SPI_CH_HS_EN;
420
421                 if (dma_mode) {
422                         modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
423                         chcfg |= S3C64XX_SPI_CH_RXCH_ON;
424                         writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
425                                         | S3C64XX_SPI_PACKET_CNT_EN,
426                                         regs + S3C64XX_SPI_PACKET_CNT);
427                         prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
428                 }
429         }
430
431         writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
432         writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
433 }
434
435 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
436                                         int timeout_ms)
437 {
438         void __iomem *regs = sdd->regs;
439         unsigned long val = 1;
440         u32 status;
441
442         /* max fifo depth available */
443         u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
444
445         if (timeout_ms)
446                 val = msecs_to_loops(timeout_ms);
447
448         do {
449                 status = readl(regs + S3C64XX_SPI_STATUS);
450         } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
451
452         /* return the actual received data length */
453         return RX_FIFO_LVL(status, sdd);
454 }
455
456 static int wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
457                         struct spi_transfer *xfer)
458 {
459         void __iomem *regs = sdd->regs;
460         unsigned long val;
461         u32 status;
462         int ms;
463
464         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
465         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
466         ms += 10; /* some tolerance */
467
468         val = msecs_to_jiffies(ms) + 10;
469         val = wait_for_completion_timeout(&sdd->xfer_completion, val);
470
471         /*
472          * If the previous xfer was completed within timeout, then
473          * proceed further else return -EIO.
474          * DmaTx returns after simply writing data in the FIFO,
475          * w/o waiting for real transmission on the bus to finish.
476          * DmaRx returns only after Dma read data from FIFO which
477          * needs bus transmission to finish, so we don't worry if
478          * Xfer involved Rx(with or without Tx).
479          */
480         if (val && !xfer->rx_buf) {
481                 val = msecs_to_loops(10);
482                 status = readl(regs + S3C64XX_SPI_STATUS);
483                 while ((TX_FIFO_LVL(status, sdd)
484                         || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
485                        && --val) {
486                         cpu_relax();
487                         status = readl(regs + S3C64XX_SPI_STATUS);
488                 }
489
490         }
491
492         /* If timed out while checking rx/tx status return error */
493         if (!val)
494                 return -EIO;
495
496         return 0;
497 }
498
499 static int wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
500                         struct spi_transfer *xfer)
501 {
502         void __iomem *regs = sdd->regs;
503         unsigned long val;
504         u32 status;
505         int loops;
506         u32 cpy_len;
507         u8 *buf;
508         int ms;
509
510         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
511         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
512         ms += 10; /* some tolerance */
513
514         val = msecs_to_loops(ms);
515         do {
516                 status = readl(regs + S3C64XX_SPI_STATUS);
517         } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
518
519
520         /* If it was only Tx */
521         if (!xfer->rx_buf) {
522                 sdd->state &= ~TXBUSY;
523                 return 0;
524         }
525
526         /*
527          * If the receive length is bigger than the controller fifo
528          * size, calculate the loops and read the fifo as many times.
529          * loops = length / max fifo size (calculated by using the
530          * fifo mask).
531          * For any size less than the fifo size the below code is
532          * executed atleast once.
533          */
534         loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
535         buf = xfer->rx_buf;
536         do {
537                 /* wait for data to be received in the fifo */
538                 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
539                                                        (loops ? ms : 0));
540
541                 switch (sdd->cur_bpw) {
542                 case 32:
543                         ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
544                                      buf, cpy_len / 4);
545                         break;
546                 case 16:
547                         ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
548                                      buf, cpy_len / 2);
549                         break;
550                 default:
551                         ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
552                                     buf, cpy_len);
553                         break;
554                 }
555
556                 buf = buf + cpy_len;
557         } while (loops--);
558         sdd->state &= ~RXBUSY;
559
560         return 0;
561 }
562
563 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
564 {
565         void __iomem *regs = sdd->regs;
566         u32 val;
567
568         /* Disable Clock */
569         if (!sdd->port_conf->clk_from_cmu) {
570                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
571                 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
572                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
573         }
574
575         /* Set Polarity and Phase */
576         val = readl(regs + S3C64XX_SPI_CH_CFG);
577         val &= ~(S3C64XX_SPI_CH_SLAVE |
578                         S3C64XX_SPI_CPOL_L |
579                         S3C64XX_SPI_CPHA_B);
580
581         if (sdd->cur_mode & SPI_CPOL)
582                 val |= S3C64XX_SPI_CPOL_L;
583
584         if (sdd->cur_mode & SPI_CPHA)
585                 val |= S3C64XX_SPI_CPHA_B;
586
587         writel(val, regs + S3C64XX_SPI_CH_CFG);
588
589         /* Set Channel & DMA Mode */
590         val = readl(regs + S3C64XX_SPI_MODE_CFG);
591         val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
592                         | S3C64XX_SPI_MODE_CH_TSZ_MASK);
593
594         switch (sdd->cur_bpw) {
595         case 32:
596                 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
597                 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
598                 break;
599         case 16:
600                 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
601                 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
602                 break;
603         default:
604                 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
605                 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
606                 break;
607         }
608
609         writel(val, regs + S3C64XX_SPI_MODE_CFG);
610
611         if (sdd->port_conf->clk_from_cmu) {
612                 /* The src_clk clock is divided internally by 2 */
613                 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
614         } else {
615                 /* Configure Clock */
616                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
617                 val &= ~S3C64XX_SPI_PSR_MASK;
618                 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
619                                 & S3C64XX_SPI_PSR_MASK);
620                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
621
622                 /* Enable Clock */
623                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
624                 val |= S3C64XX_SPI_ENCLK_ENABLE;
625                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
626         }
627 }
628
629 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
630
631 static int s3c64xx_spi_prepare_message(struct spi_master *master,
632                                        struct spi_message *msg)
633 {
634         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
635         struct spi_device *spi = msg->spi;
636         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
637
638         /* Configure feedback delay */
639         writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
640
641         return 0;
642 }
643
644 static size_t s3c64xx_spi_max_transfer_size(struct spi_device *spi)
645 {
646         struct spi_controller *ctlr = spi->controller;
647
648         return ctlr->can_dma ? S3C64XX_SPI_PACKET_CNT_MASK : SIZE_MAX;
649 }
650
651 static int s3c64xx_spi_transfer_one(struct spi_master *master,
652                                     struct spi_device *spi,
653                                     struct spi_transfer *xfer)
654 {
655         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
656         int status;
657         u32 speed;
658         u8 bpw;
659         unsigned long flags;
660         int use_dma;
661
662         reinit_completion(&sdd->xfer_completion);
663
664         /* Only BPW and Speed may change across transfers */
665         bpw = xfer->bits_per_word;
666         speed = xfer->speed_hz;
667
668         if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
669                 sdd->cur_bpw = bpw;
670                 sdd->cur_speed = speed;
671                 sdd->cur_mode = spi->mode;
672                 s3c64xx_spi_config(sdd);
673         }
674
675         /* Polling method for xfers not bigger than FIFO capacity */
676         use_dma = 0;
677         if (!is_polling(sdd) &&
678             (sdd->rx_dma.ch && sdd->tx_dma.ch &&
679              (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1))))
680                 use_dma = 1;
681
682         spin_lock_irqsave(&sdd->lock, flags);
683
684         /* Pending only which is to be done */
685         sdd->state &= ~RXBUSY;
686         sdd->state &= ~TXBUSY;
687
688         enable_datapath(sdd, spi, xfer, use_dma);
689
690         /* Start the signals */
691         s3c64xx_spi_set_cs(spi, true);
692
693         spin_unlock_irqrestore(&sdd->lock, flags);
694
695         if (use_dma)
696                 status = wait_for_dma(sdd, xfer);
697         else
698                 status = wait_for_pio(sdd, xfer);
699
700         if (status) {
701                 dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
702                         xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
703                         (sdd->state & RXBUSY) ? 'f' : 'p',
704                         (sdd->state & TXBUSY) ? 'f' : 'p',
705                         xfer->len);
706
707                 if (use_dma) {
708                         if (xfer->tx_buf != NULL
709                             && (sdd->state & TXBUSY))
710                                 dmaengine_terminate_all(sdd->tx_dma.ch);
711                         if (xfer->rx_buf != NULL
712                             && (sdd->state & RXBUSY))
713                                 dmaengine_terminate_all(sdd->rx_dma.ch);
714                 }
715         } else {
716                 flush_fifo(sdd);
717         }
718
719         return status;
720 }
721
722 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
723                                 struct spi_device *spi)
724 {
725         struct s3c64xx_spi_csinfo *cs;
726         struct device_node *slave_np, *data_np = NULL;
727         u32 fb_delay = 0;
728
729         slave_np = spi->dev.of_node;
730         if (!slave_np) {
731                 dev_err(&spi->dev, "device node not found\n");
732                 return ERR_PTR(-EINVAL);
733         }
734
735         data_np = of_get_child_by_name(slave_np, "controller-data");
736         if (!data_np) {
737                 dev_err(&spi->dev, "child node 'controller-data' not found\n");
738                 return ERR_PTR(-EINVAL);
739         }
740
741         cs = kzalloc(sizeof(*cs), GFP_KERNEL);
742         if (!cs) {
743                 of_node_put(data_np);
744                 return ERR_PTR(-ENOMEM);
745         }
746
747         of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
748         cs->fb_delay = fb_delay;
749         of_node_put(data_np);
750         return cs;
751 }
752
753 /*
754  * Here we only check the validity of requested configuration
755  * and save the configuration in a local data-structure.
756  * The controller is actually configured only just before we
757  * get a message to transfer.
758  */
759 static int s3c64xx_spi_setup(struct spi_device *spi)
760 {
761         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
762         struct s3c64xx_spi_driver_data *sdd;
763         struct s3c64xx_spi_info *sci;
764         int err;
765
766         sdd = spi_master_get_devdata(spi->master);
767         if (spi->dev.of_node) {
768                 cs = s3c64xx_get_slave_ctrldata(spi);
769                 spi->controller_data = cs;
770         } else if (cs) {
771                 /* On non-DT platforms the SPI core will set spi->cs_gpio
772                  * to -ENOENT. The GPIO pin used to drive the chip select
773                  * is defined by using platform data so spi->cs_gpio value
774                  * has to be override to have the proper GPIO pin number.
775                  */
776                 spi->cs_gpio = cs->line;
777         }
778
779         if (IS_ERR_OR_NULL(cs)) {
780                 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
781                 return -ENODEV;
782         }
783
784         if (!spi_get_ctldata(spi)) {
785                 if (gpio_is_valid(spi->cs_gpio)) {
786                         err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH,
787                                                dev_name(&spi->dev));
788                         if (err) {
789                                 dev_err(&spi->dev,
790                                         "Failed to get /CS gpio [%d]: %d\n",
791                                         spi->cs_gpio, err);
792                                 goto err_gpio_req;
793                         }
794                 }
795
796                 spi_set_ctldata(spi, cs);
797         }
798
799         sci = sdd->cntrlr_info;
800
801         pm_runtime_get_sync(&sdd->pdev->dev);
802
803         /* Check if we can provide the requested rate */
804         if (!sdd->port_conf->clk_from_cmu) {
805                 u32 psr, speed;
806
807                 /* Max possible */
808                 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
809
810                 if (spi->max_speed_hz > speed)
811                         spi->max_speed_hz = speed;
812
813                 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
814                 psr &= S3C64XX_SPI_PSR_MASK;
815                 if (psr == S3C64XX_SPI_PSR_MASK)
816                         psr--;
817
818                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
819                 if (spi->max_speed_hz < speed) {
820                         if (psr+1 < S3C64XX_SPI_PSR_MASK) {
821                                 psr++;
822                         } else {
823                                 err = -EINVAL;
824                                 goto setup_exit;
825                         }
826                 }
827
828                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
829                 if (spi->max_speed_hz >= speed) {
830                         spi->max_speed_hz = speed;
831                 } else {
832                         dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
833                                 spi->max_speed_hz);
834                         err = -EINVAL;
835                         goto setup_exit;
836                 }
837         }
838
839         pm_runtime_mark_last_busy(&sdd->pdev->dev);
840         pm_runtime_put_autosuspend(&sdd->pdev->dev);
841         s3c64xx_spi_set_cs(spi, false);
842
843         return 0;
844
845 setup_exit:
846         pm_runtime_mark_last_busy(&sdd->pdev->dev);
847         pm_runtime_put_autosuspend(&sdd->pdev->dev);
848         /* setup() returns with device de-selected */
849         s3c64xx_spi_set_cs(spi, false);
850
851         if (gpio_is_valid(spi->cs_gpio))
852                 gpio_free(spi->cs_gpio);
853         spi_set_ctldata(spi, NULL);
854
855 err_gpio_req:
856         if (spi->dev.of_node)
857                 kfree(cs);
858
859         return err;
860 }
861
862 static void s3c64xx_spi_cleanup(struct spi_device *spi)
863 {
864         struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
865
866         if (gpio_is_valid(spi->cs_gpio)) {
867                 gpio_free(spi->cs_gpio);
868                 if (spi->dev.of_node)
869                         kfree(cs);
870                 else {
871                         /* On non-DT platforms, the SPI core sets
872                          * spi->cs_gpio to -ENOENT and .setup()
873                          * overrides it with the GPIO pin value
874                          * passed using platform data.
875                          */
876                         spi->cs_gpio = -ENOENT;
877                 }
878         }
879
880         spi_set_ctldata(spi, NULL);
881 }
882
883 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
884 {
885         struct s3c64xx_spi_driver_data *sdd = data;
886         struct spi_master *spi = sdd->master;
887         unsigned int val, clr = 0;
888
889         val = readl(sdd->regs + S3C64XX_SPI_STATUS);
890
891         if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
892                 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
893                 dev_err(&spi->dev, "RX overrun\n");
894         }
895         if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
896                 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
897                 dev_err(&spi->dev, "RX underrun\n");
898         }
899         if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
900                 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
901                 dev_err(&spi->dev, "TX overrun\n");
902         }
903         if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
904                 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
905                 dev_err(&spi->dev, "TX underrun\n");
906         }
907
908         /* Clear the pending irq by setting and then clearing it */
909         writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
910         writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
911
912         return IRQ_HANDLED;
913 }
914
915 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
916 {
917         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
918         void __iomem *regs = sdd->regs;
919         unsigned int val;
920
921         sdd->cur_speed = 0;
922
923         if (sci->no_cs)
924                 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
925         else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
926                 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
927
928         /* Disable Interrupts - we use Polling if not DMA mode */
929         writel(0, regs + S3C64XX_SPI_INT_EN);
930
931         if (!sdd->port_conf->clk_from_cmu)
932                 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
933                                 regs + S3C64XX_SPI_CLK_CFG);
934         writel(0, regs + S3C64XX_SPI_MODE_CFG);
935         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
936
937         /* Clear any irq pending bits, should set and clear the bits */
938         val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
939                 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
940                 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
941                 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
942         writel(val, regs + S3C64XX_SPI_PENDING_CLR);
943         writel(0, regs + S3C64XX_SPI_PENDING_CLR);
944
945         writel(0, regs + S3C64XX_SPI_SWAP_CFG);
946
947         val = readl(regs + S3C64XX_SPI_MODE_CFG);
948         val &= ~S3C64XX_SPI_MODE_4BURST;
949         val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
950         val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
951         writel(val, regs + S3C64XX_SPI_MODE_CFG);
952
953         flush_fifo(sdd);
954 }
955
956 #ifdef CONFIG_OF
957 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
958 {
959         struct s3c64xx_spi_info *sci;
960         u32 temp;
961
962         sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
963         if (!sci)
964                 return ERR_PTR(-ENOMEM);
965
966         if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
967                 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
968                 sci->src_clk_nr = 0;
969         } else {
970                 sci->src_clk_nr = temp;
971         }
972
973         if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
974                 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
975                 sci->num_cs = 1;
976         } else {
977                 sci->num_cs = temp;
978         }
979
980         sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback");
981
982         return sci;
983 }
984 #else
985 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
986 {
987         return dev_get_platdata(dev);
988 }
989 #endif
990
991 static const struct of_device_id s3c64xx_spi_dt_match[];
992
993 static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
994                                                 struct platform_device *pdev)
995 {
996 #ifdef CONFIG_OF
997         if (pdev->dev.of_node) {
998                 const struct of_device_id *match;
999                 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1000                 return (struct s3c64xx_spi_port_config *)match->data;
1001         }
1002 #endif
1003         return (struct s3c64xx_spi_port_config *)
1004                          platform_get_device_id(pdev)->driver_data;
1005 }
1006
1007 static int s3c64xx_spi_probe(struct platform_device *pdev)
1008 {
1009         struct resource *mem_res;
1010         struct s3c64xx_spi_driver_data *sdd;
1011         struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1012         struct spi_master *master;
1013         int ret, irq;
1014         char clk_name[16];
1015
1016         if (!sci && pdev->dev.of_node) {
1017                 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1018                 if (IS_ERR(sci))
1019                         return PTR_ERR(sci);
1020         }
1021
1022         if (!sci) {
1023                 dev_err(&pdev->dev, "platform_data missing!\n");
1024                 return -ENODEV;
1025         }
1026
1027         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1028         if (mem_res == NULL) {
1029                 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1030                 return -ENXIO;
1031         }
1032
1033         irq = platform_get_irq(pdev, 0);
1034         if (irq < 0) {
1035                 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1036                 return irq;
1037         }
1038
1039         master = spi_alloc_master(&pdev->dev,
1040                                 sizeof(struct s3c64xx_spi_driver_data));
1041         if (master == NULL) {
1042                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1043                 return -ENOMEM;
1044         }
1045
1046         platform_set_drvdata(pdev, master);
1047
1048         sdd = spi_master_get_devdata(master);
1049         sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1050         sdd->master = master;
1051         sdd->cntrlr_info = sci;
1052         sdd->pdev = pdev;
1053         sdd->sfr_start = mem_res->start;
1054         if (pdev->dev.of_node) {
1055                 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1056                 if (ret < 0) {
1057                         dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1058                                 ret);
1059                         goto err_deref_master;
1060                 }
1061                 sdd->port_id = ret;
1062         } else {
1063                 sdd->port_id = pdev->id;
1064         }
1065
1066         sdd->cur_bpw = 8;
1067
1068         sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1069         sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1070
1071         master->dev.of_node = pdev->dev.of_node;
1072         master->bus_num = sdd->port_id;
1073         master->setup = s3c64xx_spi_setup;
1074         master->cleanup = s3c64xx_spi_cleanup;
1075         master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1076         master->prepare_message = s3c64xx_spi_prepare_message;
1077         master->transfer_one = s3c64xx_spi_transfer_one;
1078         master->max_transfer_size = s3c64xx_spi_max_transfer_size;
1079         master->num_chipselect = sci->num_cs;
1080         master->dma_alignment = 8;
1081         master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1082                                         SPI_BPW_MASK(8);
1083         /* the spi->mode bits understood by this driver: */
1084         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1085         master->auto_runtime_pm = true;
1086         if (!is_polling(sdd))
1087                 master->can_dma = s3c64xx_spi_can_dma;
1088
1089         sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1090         if (IS_ERR(sdd->regs)) {
1091                 ret = PTR_ERR(sdd->regs);
1092                 goto err_deref_master;
1093         }
1094
1095         if (sci->cfg_gpio && sci->cfg_gpio()) {
1096                 dev_err(&pdev->dev, "Unable to config gpio\n");
1097                 ret = -EBUSY;
1098                 goto err_deref_master;
1099         }
1100
1101         /* Setup clocks */
1102         sdd->clk = devm_clk_get(&pdev->dev, "spi");
1103         if (IS_ERR(sdd->clk)) {
1104                 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1105                 ret = PTR_ERR(sdd->clk);
1106                 goto err_deref_master;
1107         }
1108
1109         ret = clk_prepare_enable(sdd->clk);
1110         if (ret) {
1111                 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1112                 goto err_deref_master;
1113         }
1114
1115         sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1116         sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1117         if (IS_ERR(sdd->src_clk)) {
1118                 dev_err(&pdev->dev,
1119                         "Unable to acquire clock '%s'\n", clk_name);
1120                 ret = PTR_ERR(sdd->src_clk);
1121                 goto err_disable_clk;
1122         }
1123
1124         ret = clk_prepare_enable(sdd->src_clk);
1125         if (ret) {
1126                 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1127                 goto err_disable_clk;
1128         }
1129
1130         if (sdd->port_conf->clk_ioclk) {
1131                 sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk");
1132                 if (IS_ERR(sdd->ioclk)) {
1133                         dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n");
1134                         ret = PTR_ERR(sdd->ioclk);
1135                         goto err_disable_src_clk;
1136                 }
1137
1138                 ret = clk_prepare_enable(sdd->ioclk);
1139                 if (ret) {
1140                         dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n");
1141                         goto err_disable_src_clk;
1142                 }
1143         }
1144
1145         if (!is_polling(sdd)) {
1146                 /* Acquire DMA channels */
1147                 sdd->rx_dma.ch = dma_request_slave_channel_reason(&pdev->dev,
1148                                                                   "rx");
1149                 if (IS_ERR(sdd->rx_dma.ch)) {
1150                         dev_err(&pdev->dev, "Failed to get RX DMA channel\n");
1151                         ret = PTR_ERR(sdd->rx_dma.ch);
1152                         goto err_disable_io_clk;
1153                 }
1154                 sdd->tx_dma.ch = dma_request_slave_channel_reason(&pdev->dev,
1155                                                                   "tx");
1156                 if (IS_ERR(sdd->tx_dma.ch)) {
1157                         dev_err(&pdev->dev, "Failed to get TX DMA channel\n");
1158                         ret = PTR_ERR(sdd->tx_dma.ch);
1159                         goto err_release_rx_dma;
1160                 }
1161         }
1162
1163         pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1164         pm_runtime_use_autosuspend(&pdev->dev);
1165         pm_runtime_set_active(&pdev->dev);
1166         pm_runtime_enable(&pdev->dev);
1167         pm_runtime_get_sync(&pdev->dev);
1168
1169         /* Setup Deufult Mode */
1170         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1171
1172         spin_lock_init(&sdd->lock);
1173         init_completion(&sdd->xfer_completion);
1174
1175         ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1176                                 "spi-s3c64xx", sdd);
1177         if (ret != 0) {
1178                 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1179                         irq, ret);
1180                 goto err_pm_put;
1181         }
1182
1183         writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1184                S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1185                sdd->regs + S3C64XX_SPI_INT_EN);
1186
1187         ret = devm_spi_register_master(&pdev->dev, master);
1188         if (ret != 0) {
1189                 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
1190                 goto err_pm_put;
1191         }
1192
1193         dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1194                                         sdd->port_id, master->num_chipselect);
1195         dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n",
1196                                         mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1);
1197
1198         pm_runtime_mark_last_busy(&pdev->dev);
1199         pm_runtime_put_autosuspend(&pdev->dev);
1200
1201         return 0;
1202
1203 err_pm_put:
1204         pm_runtime_put_noidle(&pdev->dev);
1205         pm_runtime_disable(&pdev->dev);
1206         pm_runtime_set_suspended(&pdev->dev);
1207
1208         if (!is_polling(sdd))
1209                 dma_release_channel(sdd->tx_dma.ch);
1210 err_release_rx_dma:
1211         if (!is_polling(sdd))
1212                 dma_release_channel(sdd->rx_dma.ch);
1213 err_disable_io_clk:
1214         clk_disable_unprepare(sdd->ioclk);
1215 err_disable_src_clk:
1216         clk_disable_unprepare(sdd->src_clk);
1217 err_disable_clk:
1218         clk_disable_unprepare(sdd->clk);
1219 err_deref_master:
1220         spi_master_put(master);
1221
1222         return ret;
1223 }
1224
1225 static int s3c64xx_spi_remove(struct platform_device *pdev)
1226 {
1227         struct spi_master *master = platform_get_drvdata(pdev);
1228         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1229
1230         pm_runtime_get_sync(&pdev->dev);
1231
1232         writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1233
1234         if (!is_polling(sdd)) {
1235                 dma_release_channel(sdd->rx_dma.ch);
1236                 dma_release_channel(sdd->tx_dma.ch);
1237         }
1238
1239         clk_disable_unprepare(sdd->ioclk);
1240
1241         clk_disable_unprepare(sdd->src_clk);
1242
1243         clk_disable_unprepare(sdd->clk);
1244
1245         pm_runtime_put_noidle(&pdev->dev);
1246         pm_runtime_disable(&pdev->dev);
1247         pm_runtime_set_suspended(&pdev->dev);
1248
1249         return 0;
1250 }
1251
1252 #ifdef CONFIG_PM_SLEEP
1253 static int s3c64xx_spi_suspend(struct device *dev)
1254 {
1255         struct spi_master *master = dev_get_drvdata(dev);
1256         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1257
1258         int ret = spi_master_suspend(master);
1259         if (ret)
1260                 return ret;
1261
1262         ret = pm_runtime_force_suspend(dev);
1263         if (ret < 0)
1264                 return ret;
1265
1266         sdd->cur_speed = 0; /* Output Clock is stopped */
1267
1268         return 0;
1269 }
1270
1271 static int s3c64xx_spi_resume(struct device *dev)
1272 {
1273         struct spi_master *master = dev_get_drvdata(dev);
1274         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1275         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1276         int ret;
1277
1278         if (sci->cfg_gpio)
1279                 sci->cfg_gpio();
1280
1281         ret = pm_runtime_force_resume(dev);
1282         if (ret < 0)
1283                 return ret;
1284
1285         return spi_master_resume(master);
1286 }
1287 #endif /* CONFIG_PM_SLEEP */
1288
1289 #ifdef CONFIG_PM
1290 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1291 {
1292         struct spi_master *master = dev_get_drvdata(dev);
1293         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1294
1295         clk_disable_unprepare(sdd->clk);
1296         clk_disable_unprepare(sdd->src_clk);
1297         clk_disable_unprepare(sdd->ioclk);
1298
1299         return 0;
1300 }
1301
1302 static int s3c64xx_spi_runtime_resume(struct device *dev)
1303 {
1304         struct spi_master *master = dev_get_drvdata(dev);
1305         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1306         int ret;
1307
1308         if (sdd->port_conf->clk_ioclk) {
1309                 ret = clk_prepare_enable(sdd->ioclk);
1310                 if (ret != 0)
1311                         return ret;
1312         }
1313
1314         ret = clk_prepare_enable(sdd->src_clk);
1315         if (ret != 0)
1316                 goto err_disable_ioclk;
1317
1318         ret = clk_prepare_enable(sdd->clk);
1319         if (ret != 0)
1320                 goto err_disable_src_clk;
1321
1322         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1323
1324         return 0;
1325
1326 err_disable_src_clk:
1327         clk_disable_unprepare(sdd->src_clk);
1328 err_disable_ioclk:
1329         clk_disable_unprepare(sdd->ioclk);
1330
1331         return ret;
1332 }
1333 #endif /* CONFIG_PM */
1334
1335 static const struct dev_pm_ops s3c64xx_spi_pm = {
1336         SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1337         SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1338                            s3c64xx_spi_runtime_resume, NULL)
1339 };
1340
1341 static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1342         .fifo_lvl_mask  = { 0x7f },
1343         .rx_lvl_offset  = 13,
1344         .tx_st_done     = 21,
1345         .high_speed     = true,
1346 };
1347
1348 static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1349         .fifo_lvl_mask  = { 0x7f, 0x7F },
1350         .rx_lvl_offset  = 13,
1351         .tx_st_done     = 21,
1352 };
1353
1354 static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1355         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1356         .rx_lvl_offset  = 15,
1357         .tx_st_done     = 25,
1358         .high_speed     = true,
1359 };
1360
1361 static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1362         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F },
1363         .rx_lvl_offset  = 15,
1364         .tx_st_done     = 25,
1365         .high_speed     = true,
1366         .clk_from_cmu   = true,
1367 };
1368
1369 static struct s3c64xx_spi_port_config exynos5440_spi_port_config = {
1370         .fifo_lvl_mask  = { 0x1ff },
1371         .rx_lvl_offset  = 15,
1372         .tx_st_done     = 25,
1373         .high_speed     = true,
1374         .clk_from_cmu   = true,
1375         .quirks         = S3C64XX_SPI_QUIRK_POLL,
1376 };
1377
1378 static struct s3c64xx_spi_port_config exynos7_spi_port_config = {
1379         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
1380         .rx_lvl_offset  = 15,
1381         .tx_st_done     = 25,
1382         .high_speed     = true,
1383         .clk_from_cmu   = true,
1384         .quirks         = S3C64XX_SPI_QUIRK_CS_AUTO,
1385 };
1386
1387 static struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
1388         .fifo_lvl_mask  = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff},
1389         .rx_lvl_offset  = 15,
1390         .tx_st_done     = 25,
1391         .high_speed     = true,
1392         .clk_from_cmu   = true,
1393         .clk_ioclk      = true,
1394         .quirks         = S3C64XX_SPI_QUIRK_CS_AUTO,
1395 };
1396
1397 static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
1398         {
1399                 .name           = "s3c2443-spi",
1400                 .driver_data    = (kernel_ulong_t)&s3c2443_spi_port_config,
1401         }, {
1402                 .name           = "s3c6410-spi",
1403                 .driver_data    = (kernel_ulong_t)&s3c6410_spi_port_config,
1404         },
1405         { },
1406 };
1407
1408 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1409         { .compatible = "samsung,s3c2443-spi",
1410                         .data = (void *)&s3c2443_spi_port_config,
1411         },
1412         { .compatible = "samsung,s3c6410-spi",
1413                         .data = (void *)&s3c6410_spi_port_config,
1414         },
1415         { .compatible = "samsung,s5pv210-spi",
1416                         .data = (void *)&s5pv210_spi_port_config,
1417         },
1418         { .compatible = "samsung,exynos4210-spi",
1419                         .data = (void *)&exynos4_spi_port_config,
1420         },
1421         { .compatible = "samsung,exynos5440-spi",
1422                         .data = (void *)&exynos5440_spi_port_config,
1423         },
1424         { .compatible = "samsung,exynos7-spi",
1425                         .data = (void *)&exynos7_spi_port_config,
1426         },
1427         { .compatible = "samsung,exynos5433-spi",
1428                         .data = (void *)&exynos5433_spi_port_config,
1429         },
1430         { },
1431 };
1432 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1433
1434 static struct platform_driver s3c64xx_spi_driver = {
1435         .driver = {
1436                 .name   = "s3c64xx-spi",
1437                 .pm = &s3c64xx_spi_pm,
1438                 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1439         },
1440         .probe = s3c64xx_spi_probe,
1441         .remove = s3c64xx_spi_remove,
1442         .id_table = s3c64xx_spi_driver_ids,
1443 };
1444 MODULE_ALIAS("platform:s3c64xx-spi");
1445
1446 module_platform_driver(s3c64xx_spi_driver);
1447
1448 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1449 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1450 MODULE_LICENSE("GPL");