2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
3 * Author: Addy Ke <addy.ke@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 #include <linux/clk.h>
17 #include <linux/dmaengine.h>
18 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/spi/spi.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/scatterlist.h>
25 #define DRIVER_NAME "rockchip-spi"
27 /* SPI register offsets */
28 #define ROCKCHIP_SPI_CTRLR0 0x0000
29 #define ROCKCHIP_SPI_CTRLR1 0x0004
30 #define ROCKCHIP_SPI_SSIENR 0x0008
31 #define ROCKCHIP_SPI_SER 0x000c
32 #define ROCKCHIP_SPI_BAUDR 0x0010
33 #define ROCKCHIP_SPI_TXFTLR 0x0014
34 #define ROCKCHIP_SPI_RXFTLR 0x0018
35 #define ROCKCHIP_SPI_TXFLR 0x001c
36 #define ROCKCHIP_SPI_RXFLR 0x0020
37 #define ROCKCHIP_SPI_SR 0x0024
38 #define ROCKCHIP_SPI_IPR 0x0028
39 #define ROCKCHIP_SPI_IMR 0x002c
40 #define ROCKCHIP_SPI_ISR 0x0030
41 #define ROCKCHIP_SPI_RISR 0x0034
42 #define ROCKCHIP_SPI_ICR 0x0038
43 #define ROCKCHIP_SPI_DMACR 0x003c
44 #define ROCKCHIP_SPI_DMATDLR 0x0040
45 #define ROCKCHIP_SPI_DMARDLR 0x0044
46 #define ROCKCHIP_SPI_TXDR 0x0400
47 #define ROCKCHIP_SPI_RXDR 0x0800
49 /* Bit fields in CTRLR0 */
50 #define CR0_DFS_OFFSET 0
52 #define CR0_CFS_OFFSET 2
54 #define CR0_SCPH_OFFSET 6
56 #define CR0_SCPOL_OFFSET 7
58 #define CR0_CSM_OFFSET 8
59 #define CR0_CSM_KEEP 0x0
60 /* ss_n be high for half sclk_out cycles */
61 #define CR0_CSM_HALF 0X1
62 /* ss_n be high for one sclk_out cycle */
63 #define CR0_CSM_ONE 0x2
65 /* ss_n to sclk_out delay */
66 #define CR0_SSD_OFFSET 10
68 * The period between ss_n active and
69 * sclk_out active is half sclk_out cycles
71 #define CR0_SSD_HALF 0x0
73 * The period between ss_n active and
74 * sclk_out active is one sclk_out cycle
76 #define CR0_SSD_ONE 0x1
78 #define CR0_EM_OFFSET 11
79 #define CR0_EM_LITTLE 0x0
80 #define CR0_EM_BIG 0x1
82 #define CR0_FBM_OFFSET 12
83 #define CR0_FBM_MSB 0x0
84 #define CR0_FBM_LSB 0x1
86 #define CR0_BHT_OFFSET 13
87 #define CR0_BHT_16BIT 0x0
88 #define CR0_BHT_8BIT 0x1
90 #define CR0_RSD_OFFSET 14
92 #define CR0_FRF_OFFSET 16
93 #define CR0_FRF_SPI 0x0
94 #define CR0_FRF_SSP 0x1
95 #define CR0_FRF_MICROWIRE 0x2
97 #define CR0_XFM_OFFSET 18
98 #define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET)
99 #define CR0_XFM_TR 0x0
100 #define CR0_XFM_TO 0x1
101 #define CR0_XFM_RO 0x2
103 #define CR0_OPM_OFFSET 20
104 #define CR0_OPM_MASTER 0x0
105 #define CR0_OPM_SLAVE 0x1
107 #define CR0_MTM_OFFSET 0x21
109 /* Bit fields in SER, 2bit */
112 /* Bit fields in SR, 5bit */
114 #define SR_BUSY (1 << 0)
115 #define SR_TF_FULL (1 << 1)
116 #define SR_TF_EMPTY (1 << 2)
117 #define SR_RF_EMPTY (1 << 3)
118 #define SR_RF_FULL (1 << 4)
120 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */
121 #define INT_MASK 0x1f
122 #define INT_TF_EMPTY (1 << 0)
123 #define INT_TF_OVERFLOW (1 << 1)
124 #define INT_RF_UNDERFLOW (1 << 2)
125 #define INT_RF_OVERFLOW (1 << 3)
126 #define INT_RF_FULL (1 << 4)
128 /* Bit fields in ICR, 4bit */
129 #define ICR_MASK 0x0f
130 #define ICR_ALL (1 << 0)
131 #define ICR_RF_UNDERFLOW (1 << 1)
132 #define ICR_RF_OVERFLOW (1 << 2)
133 #define ICR_TF_OVERFLOW (1 << 3)
135 /* Bit fields in DMACR */
136 #define RF_DMA_EN (1 << 0)
137 #define TF_DMA_EN (1 << 1)
139 #define RXBUSY (1 << 0)
140 #define TXBUSY (1 << 1)
142 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
143 #define MAX_SCLK_OUT 50000000
146 * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
147 * the controller seems to hang when given 0x10000, so stick with this for now.
149 #define ROCKCHIP_SPI_MAX_TRANLEN 0xffff
151 enum rockchip_ssi_type {
157 struct rockchip_spi_dma_data {
159 enum dma_transfer_direction direction;
163 struct rockchip_spi {
165 struct spi_master *master;
168 struct clk *apb_pclk;
171 /*depth of the FIFO buffer */
173 /* max bus freq supported */
175 /* supported slave numbers */
176 enum rockchip_ssi_type type;
196 struct sg_table tx_sg;
197 struct sg_table rx_sg;
198 struct rockchip_spi_dma_data dma_rx;
199 struct rockchip_spi_dma_data dma_tx;
200 struct dma_slave_caps dma_caps;
203 static inline void spi_enable_chip(struct rockchip_spi *rs, int enable)
205 writel_relaxed((enable ? 1 : 0), rs->regs + ROCKCHIP_SPI_SSIENR);
208 static inline void spi_set_clk(struct rockchip_spi *rs, u16 div)
210 writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR);
213 static inline void flush_fifo(struct rockchip_spi *rs)
215 while (readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR))
216 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
219 static inline void wait_for_idle(struct rockchip_spi *rs)
221 unsigned long timeout = jiffies + msecs_to_jiffies(5);
224 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
226 } while (!time_after(jiffies, timeout));
228 dev_warn(rs->dev, "spi controller is in busy state!\n");
231 static u32 get_fifo_len(struct rockchip_spi *rs)
235 for (fifo = 2; fifo < 32; fifo++) {
236 writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR);
237 if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR))
241 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR);
243 return (fifo == 31) ? 0 : fifo;
246 static inline u32 tx_max(struct rockchip_spi *rs)
248 u32 tx_left, tx_room;
250 tx_left = (rs->tx_end - rs->tx) / rs->n_bytes;
251 tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
253 return min(tx_left, tx_room);
256 static inline u32 rx_max(struct rockchip_spi *rs)
258 u32 rx_left = (rs->rx_end - rs->rx) / rs->n_bytes;
259 u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
261 return min(rx_left, rx_room);
264 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
267 struct spi_master *master = spi->master;
268 struct rockchip_spi *rs = spi_master_get_devdata(master);
270 pm_runtime_get_sync(rs->dev);
272 ser = readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & SER_MASK;
276 * static void spi_set_cs(struct spi_device *spi, bool enable)
278 * if (spi->mode & SPI_CS_HIGH)
281 * if (spi->cs_gpio >= 0)
282 * gpio_set_value(spi->cs_gpio, !enable);
283 * else if (spi->master->set_cs)
284 * spi->master->set_cs(spi, !enable);
287 * Note: enable(rockchip_spi_set_cs) = !enable(spi_set_cs)
290 ser |= 1 << spi->chip_select;
292 ser &= ~(1 << spi->chip_select);
294 writel_relaxed(ser, rs->regs + ROCKCHIP_SPI_SER);
296 pm_runtime_put_sync(rs->dev);
299 static int rockchip_spi_prepare_message(struct spi_master *master,
300 struct spi_message *msg)
302 struct rockchip_spi *rs = spi_master_get_devdata(master);
303 struct spi_device *spi = msg->spi;
305 rs->mode = spi->mode;
310 static void rockchip_spi_handle_err(struct spi_master *master,
311 struct spi_message *msg)
314 struct rockchip_spi *rs = spi_master_get_devdata(master);
316 spin_lock_irqsave(&rs->lock, flags);
319 * For DMA mode, we need terminate DMA channel and flush
320 * fifo for the next transfer if DMA thansfer timeout.
321 * handle_err() was called by core if transfer failed.
322 * Maybe it is reasonable for error handling here.
325 if (rs->state & RXBUSY) {
326 dmaengine_terminate_async(rs->dma_rx.ch);
330 if (rs->state & TXBUSY)
331 dmaengine_terminate_async(rs->dma_tx.ch);
334 spin_unlock_irqrestore(&rs->lock, flags);
337 static int rockchip_spi_unprepare_message(struct spi_master *master,
338 struct spi_message *msg)
340 struct rockchip_spi *rs = spi_master_get_devdata(master);
342 spi_enable_chip(rs, 0);
347 static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
349 u32 max = tx_max(rs);
353 if (rs->n_bytes == 1)
354 txw = *(u8 *)(rs->tx);
356 txw = *(u16 *)(rs->tx);
358 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
359 rs->tx += rs->n_bytes;
363 static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
365 u32 max = rx_max(rs);
369 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
370 if (rs->n_bytes == 1)
371 *(u8 *)(rs->rx) = (u8)rxw;
373 *(u16 *)(rs->rx) = (u16)rxw;
374 rs->rx += rs->n_bytes;
378 static int rockchip_spi_pio_transfer(struct rockchip_spi *rs)
384 remain = rs->tx_end - rs->tx;
385 rockchip_spi_pio_writer(rs);
389 remain = rs->rx_end - rs->rx;
390 rockchip_spi_pio_reader(rs);
396 /* If tx, wait until the FIFO data completely. */
400 spi_enable_chip(rs, 0);
405 static void rockchip_spi_dma_rxcb(void *data)
408 struct rockchip_spi *rs = data;
410 spin_lock_irqsave(&rs->lock, flags);
412 rs->state &= ~RXBUSY;
413 if (!(rs->state & TXBUSY)) {
414 spi_enable_chip(rs, 0);
415 spi_finalize_current_transfer(rs->master);
418 spin_unlock_irqrestore(&rs->lock, flags);
421 static void rockchip_spi_dma_txcb(void *data)
424 struct rockchip_spi *rs = data;
426 /* Wait until the FIFO data completely. */
429 spin_lock_irqsave(&rs->lock, flags);
431 rs->state &= ~TXBUSY;
432 if (!(rs->state & RXBUSY)) {
433 spi_enable_chip(rs, 0);
434 spi_finalize_current_transfer(rs->master);
437 spin_unlock_irqrestore(&rs->lock, flags);
440 static int rockchip_spi_prepare_dma(struct rockchip_spi *rs)
443 struct dma_slave_config rxconf, txconf;
444 struct dma_async_tx_descriptor *rxdesc, *txdesc;
446 memset(&rxconf, 0, sizeof(rxconf));
447 memset(&txconf, 0, sizeof(txconf));
449 spin_lock_irqsave(&rs->lock, flags);
450 rs->state &= ~RXBUSY;
451 rs->state &= ~TXBUSY;
452 spin_unlock_irqrestore(&rs->lock, flags);
456 rxconf.direction = rs->dma_rx.direction;
457 rxconf.src_addr = rs->dma_rx.addr;
458 rxconf.src_addr_width = rs->n_bytes;
459 if (rs->dma_caps.max_burst > 4)
460 rxconf.src_maxburst = 4;
462 rxconf.src_maxburst = 1;
463 dmaengine_slave_config(rs->dma_rx.ch, &rxconf);
465 rxdesc = dmaengine_prep_slave_sg(
467 rs->rx_sg.sgl, rs->rx_sg.nents,
468 rs->dma_rx.direction, DMA_PREP_INTERRUPT);
472 rxdesc->callback = rockchip_spi_dma_rxcb;
473 rxdesc->callback_param = rs;
478 txconf.direction = rs->dma_tx.direction;
479 txconf.dst_addr = rs->dma_tx.addr;
480 txconf.dst_addr_width = rs->n_bytes;
481 if (rs->dma_caps.max_burst > 4)
482 txconf.dst_maxburst = 4;
484 txconf.dst_maxburst = 1;
485 dmaengine_slave_config(rs->dma_tx.ch, &txconf);
487 txdesc = dmaengine_prep_slave_sg(
489 rs->tx_sg.sgl, rs->tx_sg.nents,
490 rs->dma_tx.direction, DMA_PREP_INTERRUPT);
493 dmaengine_terminate_sync(rs->dma_rx.ch);
497 txdesc->callback = rockchip_spi_dma_txcb;
498 txdesc->callback_param = rs;
501 /* rx must be started before tx due to spi instinct */
503 spin_lock_irqsave(&rs->lock, flags);
505 spin_unlock_irqrestore(&rs->lock, flags);
506 dmaengine_submit(rxdesc);
507 dma_async_issue_pending(rs->dma_rx.ch);
511 spin_lock_irqsave(&rs->lock, flags);
513 spin_unlock_irqrestore(&rs->lock, flags);
514 dmaengine_submit(txdesc);
515 dma_async_issue_pending(rs->dma_tx.ch);
521 static void rockchip_spi_config(struct rockchip_spi *rs)
527 u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET)
528 | (CR0_SSD_ONE << CR0_SSD_OFFSET)
529 | (CR0_EM_BIG << CR0_EM_OFFSET);
531 cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
532 cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);
533 cr0 |= (rs->tmode << CR0_XFM_OFFSET);
534 cr0 |= (rs->type << CR0_FRF_OFFSET);
543 if (WARN_ON(rs->speed > MAX_SCLK_OUT))
544 rs->speed = MAX_SCLK_OUT;
546 /* the minimum divisor is 2 */
547 if (rs->max_freq < 2 * rs->speed) {
548 clk_set_rate(rs->spiclk, 2 * rs->speed);
549 rs->max_freq = clk_get_rate(rs->spiclk);
552 /* div doesn't support odd number */
553 div = DIV_ROUND_UP(rs->max_freq, rs->speed);
554 div = (div + 1) & 0xfffe;
556 /* Rx sample delay is expressed in parent clock cycles (max 3) */
557 rsd = DIV_ROUND_CLOSEST(rs->rsd_nsecs * (rs->max_freq >> 8),
559 if (!rsd && rs->rsd_nsecs) {
560 pr_warn_once("rockchip-spi: %u Hz are too slow to express %u ns delay\n",
561 rs->max_freq, rs->rsd_nsecs);
562 } else if (rsd > 3) {
564 pr_warn_once("rockchip-spi: %u Hz are too fast to express %u ns delay, clamping at %u ns\n",
565 rs->max_freq, rs->rsd_nsecs,
566 rsd * 1000000000U / rs->max_freq);
568 cr0 |= rsd << CR0_RSD_OFFSET;
570 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
572 writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
573 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR);
574 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
576 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMATDLR);
577 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR);
578 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
580 spi_set_clk(rs, div);
582 dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div);
585 static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
587 return ROCKCHIP_SPI_MAX_TRANLEN;
590 static int rockchip_spi_transfer_one(
591 struct spi_master *master,
592 struct spi_device *spi,
593 struct spi_transfer *xfer)
596 struct rockchip_spi *rs = spi_master_get_devdata(master);
598 WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
599 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
601 if (!xfer->tx_buf && !xfer->rx_buf) {
602 dev_err(rs->dev, "No buffer for transfer\n");
606 if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) {
607 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len);
611 rs->speed = xfer->speed_hz;
612 rs->bpw = xfer->bits_per_word;
613 rs->n_bytes = rs->bpw >> 3;
615 rs->tx = xfer->tx_buf;
616 rs->tx_end = rs->tx + xfer->len;
617 rs->rx = xfer->rx_buf;
618 rs->rx_end = rs->rx + xfer->len;
621 rs->tx_sg = xfer->tx_sg;
622 rs->rx_sg = xfer->rx_sg;
624 if (rs->tx && rs->rx)
625 rs->tmode = CR0_XFM_TR;
627 rs->tmode = CR0_XFM_TO;
629 rs->tmode = CR0_XFM_RO;
631 /* we need prepare dma before spi was enabled */
632 if (master->can_dma && master->can_dma(master, spi, xfer))
637 rockchip_spi_config(rs);
640 if (rs->tmode == CR0_XFM_RO) {
641 /* rx: dma must be prepared first */
642 ret = rockchip_spi_prepare_dma(rs);
643 spi_enable_chip(rs, 1);
645 /* tx or tr: spi must be enabled first */
646 spi_enable_chip(rs, 1);
647 ret = rockchip_spi_prepare_dma(rs);
649 /* successful DMA prepare means the transfer is in progress */
652 spi_enable_chip(rs, 1);
653 ret = rockchip_spi_pio_transfer(rs);
659 static bool rockchip_spi_can_dma(struct spi_master *master,
660 struct spi_device *spi,
661 struct spi_transfer *xfer)
663 struct rockchip_spi *rs = spi_master_get_devdata(master);
665 return (xfer->len > rs->fifo_len);
668 static int rockchip_spi_probe(struct platform_device *pdev)
671 struct rockchip_spi *rs;
672 struct spi_master *master;
673 struct resource *mem;
676 master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi));
680 platform_set_drvdata(pdev, master);
682 rs = spi_master_get_devdata(master);
684 /* Get basic io resource and map it */
685 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
686 rs->regs = devm_ioremap_resource(&pdev->dev, mem);
687 if (IS_ERR(rs->regs)) {
688 ret = PTR_ERR(rs->regs);
689 goto err_ioremap_resource;
692 rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
693 if (IS_ERR(rs->apb_pclk)) {
694 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
695 ret = PTR_ERR(rs->apb_pclk);
696 goto err_ioremap_resource;
699 rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
700 if (IS_ERR(rs->spiclk)) {
701 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
702 ret = PTR_ERR(rs->spiclk);
703 goto err_ioremap_resource;
706 ret = clk_prepare_enable(rs->apb_pclk);
708 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
709 goto err_ioremap_resource;
712 ret = clk_prepare_enable(rs->spiclk);
714 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
715 goto err_spiclk_enable;
718 spi_enable_chip(rs, 0);
720 rs->type = SSI_MOTO_SPI;
722 rs->dev = &pdev->dev;
723 rs->max_freq = clk_get_rate(rs->spiclk);
725 if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
727 rs->rsd_nsecs = rsd_nsecs;
729 rs->fifo_len = get_fifo_len(rs);
731 dev_err(&pdev->dev, "Failed to get fifo length\n");
733 goto err_get_fifo_len;
736 spin_lock_init(&rs->lock);
738 pm_runtime_set_active(&pdev->dev);
739 pm_runtime_enable(&pdev->dev);
741 master->auto_runtime_pm = true;
742 master->bus_num = pdev->id;
743 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
744 master->num_chipselect = 2;
745 master->dev.of_node = pdev->dev.of_node;
746 master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
748 master->set_cs = rockchip_spi_set_cs;
749 master->prepare_message = rockchip_spi_prepare_message;
750 master->unprepare_message = rockchip_spi_unprepare_message;
751 master->transfer_one = rockchip_spi_transfer_one;
752 master->max_transfer_size = rockchip_spi_max_transfer_size;
753 master->handle_err = rockchip_spi_handle_err;
755 rs->dma_tx.ch = dma_request_chan(rs->dev, "tx");
756 if (IS_ERR(rs->dma_tx.ch)) {
757 /* Check tx to see if we need defer probing driver */
758 if (PTR_ERR(rs->dma_tx.ch) == -EPROBE_DEFER) {
760 goto err_get_fifo_len;
762 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
763 rs->dma_tx.ch = NULL;
766 rs->dma_rx.ch = dma_request_chan(rs->dev, "rx");
767 if (IS_ERR(rs->dma_rx.ch)) {
768 if (PTR_ERR(rs->dma_rx.ch) == -EPROBE_DEFER) {
770 goto err_free_dma_tx;
772 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
773 rs->dma_rx.ch = NULL;
776 if (rs->dma_tx.ch && rs->dma_rx.ch) {
777 dma_get_slave_caps(rs->dma_rx.ch, &(rs->dma_caps));
778 rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR);
779 rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR);
780 rs->dma_tx.direction = DMA_MEM_TO_DEV;
781 rs->dma_rx.direction = DMA_DEV_TO_MEM;
783 master->can_dma = rockchip_spi_can_dma;
784 master->dma_tx = rs->dma_tx.ch;
785 master->dma_rx = rs->dma_rx.ch;
788 ret = devm_spi_register_master(&pdev->dev, master);
790 dev_err(&pdev->dev, "Failed to register master\n");
791 goto err_register_master;
797 pm_runtime_disable(&pdev->dev);
799 dma_release_channel(rs->dma_rx.ch);
802 dma_release_channel(rs->dma_tx.ch);
804 clk_disable_unprepare(rs->spiclk);
806 clk_disable_unprepare(rs->apb_pclk);
807 err_ioremap_resource:
808 spi_master_put(master);
813 static int rockchip_spi_remove(struct platform_device *pdev)
815 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
816 struct rockchip_spi *rs = spi_master_get_devdata(master);
818 pm_runtime_disable(&pdev->dev);
820 clk_disable_unprepare(rs->spiclk);
821 clk_disable_unprepare(rs->apb_pclk);
824 dma_release_channel(rs->dma_tx.ch);
826 dma_release_channel(rs->dma_rx.ch);
828 spi_master_put(master);
833 #ifdef CONFIG_PM_SLEEP
834 static int rockchip_spi_suspend(struct device *dev)
837 struct spi_master *master = dev_get_drvdata(dev);
838 struct rockchip_spi *rs = spi_master_get_devdata(master);
840 ret = spi_master_suspend(rs->master);
844 if (!pm_runtime_suspended(dev)) {
845 clk_disable_unprepare(rs->spiclk);
846 clk_disable_unprepare(rs->apb_pclk);
852 static int rockchip_spi_resume(struct device *dev)
855 struct spi_master *master = dev_get_drvdata(dev);
856 struct rockchip_spi *rs = spi_master_get_devdata(master);
858 if (!pm_runtime_suspended(dev)) {
859 ret = clk_prepare_enable(rs->apb_pclk);
863 ret = clk_prepare_enable(rs->spiclk);
865 clk_disable_unprepare(rs->apb_pclk);
870 ret = spi_master_resume(rs->master);
872 clk_disable_unprepare(rs->spiclk);
873 clk_disable_unprepare(rs->apb_pclk);
878 #endif /* CONFIG_PM_SLEEP */
881 static int rockchip_spi_runtime_suspend(struct device *dev)
883 struct spi_master *master = dev_get_drvdata(dev);
884 struct rockchip_spi *rs = spi_master_get_devdata(master);
886 clk_disable_unprepare(rs->spiclk);
887 clk_disable_unprepare(rs->apb_pclk);
892 static int rockchip_spi_runtime_resume(struct device *dev)
895 struct spi_master *master = dev_get_drvdata(dev);
896 struct rockchip_spi *rs = spi_master_get_devdata(master);
898 ret = clk_prepare_enable(rs->apb_pclk);
902 ret = clk_prepare_enable(rs->spiclk);
904 clk_disable_unprepare(rs->apb_pclk);
908 #endif /* CONFIG_PM */
910 static const struct dev_pm_ops rockchip_spi_pm = {
911 SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
912 SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
913 rockchip_spi_runtime_resume, NULL)
916 static const struct of_device_id rockchip_spi_dt_match[] = {
917 { .compatible = "rockchip,rk3036-spi", },
918 { .compatible = "rockchip,rk3066-spi", },
919 { .compatible = "rockchip,rk3188-spi", },
920 { .compatible = "rockchip,rk3228-spi", },
921 { .compatible = "rockchip,rk3288-spi", },
922 { .compatible = "rockchip,rk3368-spi", },
923 { .compatible = "rockchip,rk3399-spi", },
926 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
928 static struct platform_driver rockchip_spi_driver = {
931 .pm = &rockchip_spi_pm,
932 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
934 .probe = rockchip_spi_probe,
935 .remove = rockchip_spi_remove,
938 module_platform_driver(rockchip_spi_driver);
940 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
941 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
942 MODULE_LICENSE("GPL v2");