drivers/spi/spi-pxa2xx.c

   1 /*
   2  * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
   3  * Copyright (C) 2013, Intel Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/bitops.h>
  17 #include <linux/init.h>
  18 #include <linux/module.h>
  19 #include <linux/device.h>
  20 #include <linux/ioport.h>
  21 #include <linux/errno.h>
  22 #include <linux/err.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/kernel.h>
  25 #include <linux/pci.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/spi/pxa2xx_spi.h>
  28 #include <linux/spi/spi.h>
  29 #include <linux/delay.h>
  30 #include <linux/gpio.h>
  31 #include <linux/gpio/consumer.h>
  32 #include <linux/slab.h>
  33 #include <linux/clk.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/acpi.h>
  36
  37 #include "spi-pxa2xx.h"
  38
  39 MODULE_AUTHOR("Stephen Street");
  40 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
  41 MODULE_LICENSE("GPL");
  42 MODULE_ALIAS("platform:pxa2xx-spi");
  43
  44 #define TIMOUT_DFLT             1000
  45
  46 /*
  47  * for testing SSCR1 changes that require SSP restart, basically
  48  * everything except the service and interrupt enables, the pxa270 developer
  49  * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
  50  * list, but the PXA255 dev man says all bits without really meaning the
  51  * service and interrupt enables
  52  */
  53 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
  54                                 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
  55                                 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
  56                                 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
  57                                 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
  58                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  59
  60 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF   \
  61                                 | QUARK_X1000_SSCR1_EFWR        \
  62                                 | QUARK_X1000_SSCR1_RFT         \
  63                                 | QUARK_X1000_SSCR1_TFT         \
  64                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  65
  66 #define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
  67                                 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
  68                                 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
  69                                 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
  70                                 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
  71                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  72
  73 #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE   BIT(24)
  74 #define LPSS_CS_CONTROL_SW_MODE                 BIT(0)
  75 #define LPSS_CS_CONTROL_CS_HIGH                 BIT(1)
  76 #define LPSS_CAPS_CS_EN_SHIFT                   9
  77 #define LPSS_CAPS_CS_EN_MASK                    (0xf << LPSS_CAPS_CS_EN_SHIFT)
  78
  79 #define LPSS_PRIV_CLOCK_GATE 0x38
  80 #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3
  81 #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3
  82
  83 struct lpss_config {
  84         /* LPSS offset from drv_data->ioaddr */
  85         unsigned offset;
  86         /* Register offsets from drv_data->lpss_base or -1 */
  87         int reg_general;
  88         int reg_ssp;
  89         int reg_cs_ctrl;
  90         int reg_capabilities;
  91         /* FIFO thresholds */
  92         u32 rx_threshold;
  93         u32 tx_threshold_lo;
  94         u32 tx_threshold_hi;
  95         /* Chip select control */
  96         unsigned cs_sel_shift;
  97         unsigned cs_sel_mask;
  98         unsigned cs_num;
  99         /* Quirks */
 100         unsigned cs_clk_stays_gated : 1;
 101 };
 102
 103 /* Keep these sorted with enum pxa_ssp_type */
 104 static const struct lpss_config lpss_platforms[] = {
 105         {       /* LPSS_LPT_SSP */
 106                 .offset = 0x800,
 107                 .reg_general = 0x08,
 108                 .reg_ssp = 0x0c,
 109                 .reg_cs_ctrl = 0x18,
 110                 .reg_capabilities = -1,
 111                 .rx_threshold = 64,
 112                 .tx_threshold_lo = 160,
 113                 .tx_threshold_hi = 224,
 114         },
 115         {       /* LPSS_BYT_SSP */
 116                 .offset = 0x400,
 117                 .reg_general = 0x08,
 118                 .reg_ssp = 0x0c,
 119                 .reg_cs_ctrl = 0x18,
 120                 .reg_capabilities = -1,
 121                 .rx_threshold = 64,
 122                 .tx_threshold_lo = 160,
 123                 .tx_threshold_hi = 224,
 124         },
 125         {       /* LPSS_BSW_SSP */
 126                 .offset = 0x400,
 127                 .reg_general = 0x08,
 128                 .reg_ssp = 0x0c,
 129                 .reg_cs_ctrl = 0x18,
 130                 .reg_capabilities = -1,
 131                 .rx_threshold = 64,
 132                 .tx_threshold_lo = 160,
 133                 .tx_threshold_hi = 224,
 134                 .cs_sel_shift = 2,
 135                 .cs_sel_mask = 1 << 2,
 136                 .cs_num = 2,
 137         },
 138         {       /* LPSS_SPT_SSP */
 139                 .offset = 0x200,
 140                 .reg_general = -1,
 141                 .reg_ssp = 0x20,
 142                 .reg_cs_ctrl = 0x24,
 143                 .reg_capabilities = -1,
 144                 .rx_threshold = 1,
 145                 .tx_threshold_lo = 32,
 146                 .tx_threshold_hi = 56,
 147         },
 148         {       /* LPSS_BXT_SSP */
 149                 .offset = 0x200,
 150                 .reg_general = -1,
 151                 .reg_ssp = 0x20,
 152                 .reg_cs_ctrl = 0x24,
 153                 .reg_capabilities = 0xfc,
 154                 .rx_threshold = 1,
 155                 .tx_threshold_lo = 16,
 156                 .tx_threshold_hi = 48,
 157                 .cs_sel_shift = 8,
 158                 .cs_sel_mask = 3 << 8,
 159                 .cs_clk_stays_gated = true,
 160         },
 161         {       /* LPSS_CNL_SSP */
 162                 .offset = 0x200,
 163                 .reg_general = -1,
 164                 .reg_ssp = 0x20,
 165                 .reg_cs_ctrl = 0x24,
 166                 .reg_capabilities = 0xfc,
 167                 .rx_threshold = 1,
 168                 .tx_threshold_lo = 32,
 169                 .tx_threshold_hi = 56,
 170                 .cs_sel_shift = 8,
 171                 .cs_sel_mask = 3 << 8,
 172                 .cs_clk_stays_gated = true,
 173         },
 174 };
 175
 176 static inline const struct lpss_config
 177 *lpss_get_config(const struct driver_data *drv_data)
 178 {
 179         return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
 180 }
 181
 182 static bool is_lpss_ssp(const struct driver_data *drv_data)
 183 {
 184         switch (drv_data->ssp_type) {
 185         case LPSS_LPT_SSP:
 186         case LPSS_BYT_SSP:
 187         case LPSS_BSW_SSP:
 188         case LPSS_SPT_SSP:
 189         case LPSS_BXT_SSP:
 190         case LPSS_CNL_SSP:
 191                 return true;
 192         default:
 193                 return false;
 194         }
 195 }
 196
 197 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
 198 {
 199         return drv_data->ssp_type == QUARK_X1000_SSP;
 200 }
 201
 202 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
 203 {
 204         switch (drv_data->ssp_type) {
 205         case QUARK_X1000_SSP:
 206                 return QUARK_X1000_SSCR1_CHANGE_MASK;
 207         case CE4100_SSP:
 208                 return CE4100_SSCR1_CHANGE_MASK;
 209         default:
 210                 return SSCR1_CHANGE_MASK;
 211         }
 212 }
 213
 214 static u32
 215 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
 216 {
 217         switch (drv_data->ssp_type) {
 218         case QUARK_X1000_SSP:
 219                 return RX_THRESH_QUARK_X1000_DFLT;
 220         case CE4100_SSP:
 221                 return RX_THRESH_CE4100_DFLT;
 222         default:
 223                 return RX_THRESH_DFLT;
 224         }
 225 }
 226
 227 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
 228 {
 229         u32 mask;
 230
 231         switch (drv_data->ssp_type) {
 232         case QUARK_X1000_SSP:
 233                 mask = QUARK_X1000_SSSR_TFL_MASK;
 234                 break;
 235         case CE4100_SSP:
 236                 mask = CE4100_SSSR_TFL_MASK;
 237                 break;
 238         default:
 239                 mask = SSSR_TFL_MASK;
 240                 break;
 241         }
 242
 243         return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
 244 }
 245
 246 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
 247                                      u32 *sccr1_reg)
 248 {
 249         u32 mask;
 250
 251         switch (drv_data->ssp_type) {
 252         case QUARK_X1000_SSP:
 253                 mask = QUARK_X1000_SSCR1_RFT;
 254                 break;
 255         case CE4100_SSP:
 256                 mask = CE4100_SSCR1_RFT;
 257                 break;
 258         default:
 259                 mask = SSCR1_RFT;
 260                 break;
 261         }
 262         *sccr1_reg &= ~mask;
 263 }
 264
 265 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
 266                                    u32 *sccr1_reg, u32 threshold)
 267 {
 268         switch (drv_data->ssp_type) {
 269         case QUARK_X1000_SSP:
 270                 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
 271                 break;
 272         case CE4100_SSP:
 273                 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
 274                 break;
 275         default:
 276                 *sccr1_reg |= SSCR1_RxTresh(threshold);
 277                 break;
 278         }
 279 }
 280
 281 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
 282                                   u32 clk_div, u8 bits)
 283 {
 284         switch (drv_data->ssp_type) {
 285         case QUARK_X1000_SSP:
 286                 return clk_div
 287                         | QUARK_X1000_SSCR0_Motorola
 288                         | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
 289                         | SSCR0_SSE;
 290         default:
 291                 return clk_div
 292                         | SSCR0_Motorola
 293                         | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
 294                         | SSCR0_SSE
 295                         | (bits > 16 ? SSCR0_EDSS : 0);
 296         }
 297 }
 298
 299 /*
 300  * Read and write LPSS SSP private registers. Caller must first check that
 301  * is_lpss_ssp() returns true before these can be called.
 302  */
 303 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
 304 {
 305         WARN_ON(!drv_data->lpss_base);
 306         return readl(drv_data->lpss_base + offset);
 307 }
 308
 309 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
 310                                   unsigned offset, u32 value)
 311 {
 312         WARN_ON(!drv_data->lpss_base);
 313         writel(value, drv_data->lpss_base + offset);
 314 }
 315
 316 /*
 317  * lpss_ssp_setup - perform LPSS SSP specific setup
 318  * @drv_data: pointer to the driver private data
 319  *
 320  * Perform LPSS SSP specific setup. This function must be called first if
 321  * one is going to use LPSS SSP private registers.
 322  */
 323 static void lpss_ssp_setup(struct driver_data *drv_data)
 324 {
 325         const struct lpss_config *config;
 326         u32 value;
 327
 328         config = lpss_get_config(drv_data);
 329         drv_data->lpss_base = drv_data->ioaddr + config->offset;
 330
 331         /* Enable software chip select control */
 332         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 333         value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
 334         value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
 335         __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
 336
 337         /* Enable multiblock DMA transfers */
 338         if (drv_data->master_info->enable_dma) {
 339                 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
 340
 341                 if (config->reg_general >= 0) {
 342                         value = __lpss_ssp_read_priv(drv_data,
 343                                                      config->reg_general);
 344                         value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
 345                         __lpss_ssp_write_priv(drv_data,
 346                                               config->reg_general, value);
 347                 }
 348         }
 349 }
 350
 351 static void lpss_ssp_select_cs(struct driver_data *drv_data,
 352                                const struct lpss_config *config)
 353 {
 354         u32 value, cs;
 355
 356         if (!config->cs_sel_mask)
 357                 return;
 358
 359         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 360
 361         cs = drv_data->master->cur_msg->spi->chip_select;
 362         cs <<= config->cs_sel_shift;
 363         if (cs != (value & config->cs_sel_mask)) {
 364                 /*
 365                  * When switching another chip select output active the
 366                  * output must be selected first and wait 2 ssp_clk cycles
 367                  * before changing state to active. Otherwise a short
 368                  * glitch will occur on the previous chip select since
 369                  * output select is latched but state control is not.
 370                  */
 371                 value &= ~config->cs_sel_mask;
 372                 value |= cs;
 373                 __lpss_ssp_write_priv(drv_data,
 374                                       config->reg_cs_ctrl, value);
 375                 ndelay(1000000000 /
 376                        (drv_data->master->max_speed_hz / 2));
 377         }
 378 }
 379
 380 static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
 381 {
 382         const struct lpss_config *config;
 383         u32 value;
 384
 385         config = lpss_get_config(drv_data);
 386
 387         if (enable)
 388                 lpss_ssp_select_cs(drv_data, config);
 389
 390         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 391         if (enable)
 392                 value &= ~LPSS_CS_CONTROL_CS_HIGH;
 393         else
 394                 value |= LPSS_CS_CONTROL_CS_HIGH;
 395         __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
 396         if (config->cs_clk_stays_gated) {
 397                 u32 clkgate;
 398
 399                 /*
 400                  * Changing CS alone when dynamic clock gating is on won't
 401                  * actually flip CS at that time. This ruins SPI transfers
 402                  * that specify delays, or have no data. Toggle the clock mode
 403                  * to force on briefly to poke the CS pin to move.
 404                  */
 405                 clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
 406                 value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) |
 407                         LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON;
 408
 409                 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
 410                 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
 411         }
 412 }
 413
 414 static void cs_assert(struct driver_data *drv_data)
 415 {
 416         struct chip_data *chip =
 417                 spi_get_ctldata(drv_data->master->cur_msg->spi);
 418
 419         if (drv_data->ssp_type == CE4100_SSP) {
 420                 pxa2xx_spi_write(drv_data, SSSR, chip->frm);
 421                 return;
 422         }
 423
 424         if (chip->cs_control) {
 425                 chip->cs_control(PXA2XX_CS_ASSERT);
 426                 return;
 427         }
 428
 429         if (chip->gpiod_cs) {
 430                 gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted);
 431                 return;
 432         }
 433
 434         if (is_lpss_ssp(drv_data))
 435                 lpss_ssp_cs_control(drv_data, true);
 436 }
 437
 438 static void cs_deassert(struct driver_data *drv_data)
 439 {
 440         struct chip_data *chip =
 441                 spi_get_ctldata(drv_data->master->cur_msg->spi);
 442
 443         if (drv_data->ssp_type == CE4100_SSP)
 444                 return;
 445
 446         if (chip->cs_control) {
 447                 chip->cs_control(PXA2XX_CS_DEASSERT);
 448                 return;
 449         }
 450
 451         if (chip->gpiod_cs) {
 452                 gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted);
 453                 return;
 454         }
 455
 456         if (is_lpss_ssp(drv_data))
 457                 lpss_ssp_cs_control(drv_data, false);
 458 }
 459
 460 int pxa2xx_spi_flush(struct driver_data *drv_data)
 461 {
 462         unsigned long limit = loops_per_jiffy << 1;
 463
 464         do {
 465                 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 466                         pxa2xx_spi_read(drv_data, SSDR);
 467         } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
 468         write_SSSR_CS(drv_data, SSSR_ROR);
 469
 470         return limit;
 471 }
 472
 473 static int null_writer(struct driver_data *drv_data)
 474 {
 475         u8 n_bytes = drv_data->n_bytes;
 476
 477         if (pxa2xx_spi_txfifo_full(drv_data)
 478                 || (drv_data->tx == drv_data->tx_end))
 479                 return 0;
 480
 481         pxa2xx_spi_write(drv_data, SSDR, 0);
 482         drv_data->tx += n_bytes;
 483
 484         return 1;
 485 }
 486
 487 static int null_reader(struct driver_data *drv_data)
 488 {
 489         u8 n_bytes = drv_data->n_bytes;
 490
 491         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 492                && (drv_data->rx < drv_data->rx_end)) {
 493                 pxa2xx_spi_read(drv_data, SSDR);
 494                 drv_data->rx += n_bytes;
 495         }
 496
 497         return drv_data->rx == drv_data->rx_end;
 498 }
 499
 500 static int u8_writer(struct driver_data *drv_data)
 501 {
 502         if (pxa2xx_spi_txfifo_full(drv_data)
 503                 || (drv_data->tx == drv_data->tx_end))
 504                 return 0;
 505
 506         pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
 507         ++drv_data->tx;
 508
 509         return 1;
 510 }
 511
 512 static int u8_reader(struct driver_data *drv_data)
 513 {
 514         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 515                && (drv_data->rx < drv_data->rx_end)) {
 516                 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 517                 ++drv_data->rx;
 518         }
 519
 520         return drv_data->rx == drv_data->rx_end;
 521 }
 522
 523 static int u16_writer(struct driver_data *drv_data)
 524 {
 525         if (pxa2xx_spi_txfifo_full(drv_data)
 526                 || (drv_data->tx == drv_data->tx_end))
 527                 return 0;
 528
 529         pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
 530         drv_data->tx += 2;
 531
 532         return 1;
 533 }
 534
 535 static int u16_reader(struct driver_data *drv_data)
 536 {
 537         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 538                && (drv_data->rx < drv_data->rx_end)) {
 539                 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 540                 drv_data->rx += 2;
 541         }
 542
 543         return drv_data->rx == drv_data->rx_end;
 544 }
 545
 546 static int u32_writer(struct driver_data *drv_data)
 547 {
 548         if (pxa2xx_spi_txfifo_full(drv_data)
 549                 || (drv_data->tx == drv_data->tx_end))
 550                 return 0;
 551
 552         pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
 553         drv_data->tx += 4;
 554
 555         return 1;
 556 }
 557
 558 static int u32_reader(struct driver_data *drv_data)
 559 {
 560         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 561                && (drv_data->rx < drv_data->rx_end)) {
 562                 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 563                 drv_data->rx += 4;
 564         }
 565
 566         return drv_data->rx == drv_data->rx_end;
 567 }
 568
 569 void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
 570 {
 571         struct spi_message *msg = drv_data->master->cur_msg;
 572         struct spi_transfer *trans = drv_data->cur_transfer;
 573
 574         /* Move to next transfer */
 575         if (trans->transfer_list.next != &msg->transfers) {
 576                 drv_data->cur_transfer =
 577                         list_entry(trans->transfer_list.next,
 578                                         struct spi_transfer,
 579                                         transfer_list);
 580                 return RUNNING_STATE;
 581         } else
 582                 return DONE_STATE;
 583 }
 584
 585 /* caller already set message->status; dma and pio irqs are blocked */
 586 static void giveback(struct driver_data *drv_data)
 587 {
 588         struct spi_transfer* last_transfer;
 589         struct spi_message *msg;
 590         unsigned long timeout;
 591
 592         msg = drv_data->master->cur_msg;
 593         drv_data->cur_transfer = NULL;
 594
 595         last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
 596                                         transfer_list);
 597
 598         /* Delay if requested before any change in chip select */
 599         if (last_transfer->delay_usecs)
 600                 udelay(last_transfer->delay_usecs);
 601
 602         /* Wait until SSP becomes idle before deasserting the CS */
 603         timeout = jiffies + msecs_to_jiffies(10);
 604         while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
 605                !time_after(jiffies, timeout))
 606                 cpu_relax();
 607
 608         /* Drop chip select UNLESS cs_change is true or we are returning
 609          * a message with an error, or next message is for another chip
 610          */
 611         if (!last_transfer->cs_change)
 612                 cs_deassert(drv_data);
 613         else {
 614                 struct spi_message *next_msg;
 615
 616                 /* Holding of cs was hinted, but we need to make sure
 617                  * the next message is for the same chip.  Don't waste
 618                  * time with the following tests unless this was hinted.
 619                  *
 620                  * We cannot postpone this until pump_messages, because
 621                  * after calling msg->complete (below) the driver that
 622                  * sent the current message could be unloaded, which
 623                  * could invalidate the cs_control() callback...
 624                  */
 625
 626                 /* get a pointer to the next message, if any */
 627                 next_msg = spi_get_next_queued_message(drv_data->master);
 628
 629                 /* see if the next and current messages point
 630                  * to the same chip
 631                  */
 632                 if ((next_msg && next_msg->spi != msg->spi) ||
 633                     msg->state == ERROR_STATE)
 634                         cs_deassert(drv_data);
 635         }
 636
 637         spi_finalize_current_message(drv_data->master);
 638 }
 639
 640 static void reset_sccr1(struct driver_data *drv_data)
 641 {
 642         struct chip_data *chip =
 643                 spi_get_ctldata(drv_data->master->cur_msg->spi);
 644         u32 sccr1_reg;
 645
 646         sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
 647         switch (drv_data->ssp_type) {
 648         case QUARK_X1000_SSP:
 649                 sccr1_reg &= ~QUARK_X1000_SSCR1_RFT;
 650                 break;
 651         case CE4100_SSP:
 652                 sccr1_reg &= ~CE4100_SSCR1_RFT;
 653                 break;
 654         default:
 655                 sccr1_reg &= ~SSCR1_RFT;
 656                 break;
 657         }
 658         sccr1_reg |= chip->threshold;
 659         pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
 660 }
 661
 662 static void int_error_stop(struct driver_data *drv_data, const char* msg)
 663 {
 664         /* Stop and reset SSP */
 665         write_SSSR_CS(drv_data, drv_data->clear_sr);
 666         reset_sccr1(drv_data);
 667         if (!pxa25x_ssp_comp(drv_data))
 668                 pxa2xx_spi_write(drv_data, SSTO, 0);
 669         pxa2xx_spi_flush(drv_data);
 670         pxa2xx_spi_write(drv_data, SSCR0,
 671                          pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
 672
 673         dev_err(&drv_data->pdev->dev, "%s\n", msg);
 674
 675         drv_data->master->cur_msg->state = ERROR_STATE;
 676         tasklet_schedule(&drv_data->pump_transfers);
 677 }
 678
 679 static void int_transfer_complete(struct driver_data *drv_data)
 680 {
 681         /* Clear and disable interrupts */
 682         write_SSSR_CS(drv_data, drv_data->clear_sr);
 683         reset_sccr1(drv_data);
 684         if (!pxa25x_ssp_comp(drv_data))
 685                 pxa2xx_spi_write(drv_data, SSTO, 0);
 686
 687         /* Update total byte transferred return count actual bytes read */
 688         drv_data->master->cur_msg->actual_length += drv_data->len -
 689                                 (drv_data->rx_end - drv_data->rx);
 690
 691         /* Transfer delays and chip select release are
 692          * handled in pump_transfers or giveback
 693          */
 694
 695         /* Move to next transfer */
 696         drv_data->master->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
 697
 698         /* Schedule transfer tasklet */
 699         tasklet_schedule(&drv_data->pump_transfers);
 700 }
 701
 702 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
 703 {
 704         u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
 705                        drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
 706
 707         u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
 708
 709         if (irq_status & SSSR_ROR) {
 710                 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
 711                 return IRQ_HANDLED;
 712         }
 713
 714         if (irq_status & SSSR_TINT) {
 715                 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
 716                 if (drv_data->read(drv_data)) {
 717                         int_transfer_complete(drv_data);
 718                         return IRQ_HANDLED;
 719                 }
 720         }
 721
 722         /* Drain rx fifo, Fill tx fifo and prevent overruns */
 723         do {
 724                 if (drv_data->read(drv_data)) {
 725                         int_transfer_complete(drv_data);
 726                         return IRQ_HANDLED;
 727                 }
 728         } while (drv_data->write(drv_data));
 729
 730         if (drv_data->read(drv_data)) {
 731                 int_transfer_complete(drv_data);
 732                 return IRQ_HANDLED;
 733         }
 734
 735         if (drv_data->tx == drv_data->tx_end) {
 736                 u32 bytes_left;
 737                 u32 sccr1_reg;
 738
 739                 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
 740                 sccr1_reg &= ~SSCR1_TIE;
 741
 742                 /*
 743                  * PXA25x_SSP has no timeout, set up rx threshould for the
 744                  * remaining RX bytes.
 745                  */
 746                 if (pxa25x_ssp_comp(drv_data)) {
 747                         u32 rx_thre;
 748
 749                         pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
 750
 751                         bytes_left = drv_data->rx_end - drv_data->rx;
 752                         switch (drv_data->n_bytes) {
 753                         case 4:
 754                                 bytes_left >>= 1;
 755                         case 2:
 756                                 bytes_left >>= 1;
 757                         }
 758
 759                         rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
 760                         if (rx_thre > bytes_left)
 761                                 rx_thre = bytes_left;
 762
 763                         pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
 764                 }
 765                 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
 766         }
 767
 768         /* We did something */
 769         return IRQ_HANDLED;
 770 }
 771
 772 static void handle_bad_msg(struct driver_data *drv_data)
 773 {
 774         pxa2xx_spi_write(drv_data, SSCR0,
 775                          pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
 776         pxa2xx_spi_write(drv_data, SSCR1,
 777                          pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1);
 778         if (!pxa25x_ssp_comp(drv_data))
 779                 pxa2xx_spi_write(drv_data, SSTO, 0);
 780         write_SSSR_CS(drv_data, drv_data->clear_sr);
 781
 782         dev_err(&drv_data->pdev->dev,
 783                 "bad message state in interrupt handler\n");
 784 }
 785
 786 static irqreturn_t ssp_int(int irq, void *dev_id)
 787 {
 788         struct driver_data *drv_data = dev_id;
 789         u32 sccr1_reg;
 790         u32 mask = drv_data->mask_sr;
 791         u32 status;
 792
 793         /*
 794          * The IRQ might be shared with other peripherals so we must first
 795          * check that are we RPM suspended or not. If we are we assume that
 796          * the IRQ was not for us (we shouldn't be RPM suspended when the
 797          * interrupt is enabled).
 798          */
 799         if (pm_runtime_suspended(&drv_data->pdev->dev))
 800                 return IRQ_NONE;
 801
 802         /*
 803          * If the device is not yet in RPM suspended state and we get an
 804          * interrupt that is meant for another device, check if status bits
 805          * are all set to one. That means that the device is already
 806          * powered off.
 807          */
 808         status = pxa2xx_spi_read(drv_data, SSSR);
 809         if (status == ~0)
 810                 return IRQ_NONE;
 811
 812         sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
 813
 814         /* Ignore possible writes if we don't need to write */
 815         if (!(sccr1_reg & SSCR1_TIE))
 816                 mask &= ~SSSR_TFS;
 817
 818         /* Ignore RX timeout interrupt if it is disabled */
 819         if (!(sccr1_reg & SSCR1_TINTE))
 820                 mask &= ~SSSR_TINT;
 821
 822         if (!(status & mask))
 823                 return IRQ_NONE;
 824
 825         pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
 826         pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
 827
 828         if (!drv_data->master->cur_msg) {
 829                 handle_bad_msg(drv_data);
 830                 /* Never fail */
 831                 return IRQ_HANDLED;
 832         }
 833
 834         return drv_data->transfer_handler(drv_data);
 835 }
 836
 837 /*
 838  * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
 839  * input frequency by fractions of 2^24. It also has a divider by 5.
 840  *
 841  * There are formulas to get baud rate value for given input frequency and
 842  * divider parameters, such as DDS_CLK_RATE and SCR:
 843  *
 844  * Fsys = 200MHz
 845  *
 846  * Fssp = Fsys * DDS_CLK_RATE / 2^24                    (1)
 847  * Baud rate = Fsclk = Fssp / (2 * (SCR + 1))           (2)
 848  *
 849  * DDS_CLK_RATE either 2^n or 2^n / 5.
 850  * SCR is in range 0 .. 255
 851  *
 852  * Divisor = 5^i * 2^j * 2 * k
 853  *       i = [0, 1]      i = 1 iff j = 0 or j > 3
 854  *       j = [0, 23]     j = 0 iff i = 1
 855  *       k = [1, 256]
 856  * Special case: j = 0, i = 1: Divisor = 2 / 5
 857  *
 858  * Accordingly to the specification the recommended values for DDS_CLK_RATE
 859  * are:
 860  *      Case 1:         2^n, n = [0, 23]
 861  *      Case 2:         2^24 * 2 / 5 (0x666666)
 862  *      Case 3:         less than or equal to 2^24 / 5 / 16 (0x33333)
 863  *
 864  * In all cases the lowest possible value is better.
 865  *
 866  * The function calculates parameters for all cases and chooses the one closest
 867  * to the asked baud rate.
 868  */
 869 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
 870 {
 871         unsigned long xtal = 200000000;
 872         unsigned long fref = xtal / 2;          /* mandatory division by 2,
 873                                                    see (2) */
 874                                                 /* case 3 */
 875         unsigned long fref1 = fref / 2;         /* case 1 */
 876         unsigned long fref2 = fref * 2 / 5;     /* case 2 */
 877         unsigned long scale;
 878         unsigned long q, q1, q2;
 879         long r, r1, r2;
 880         u32 mul;
 881
 882         /* Case 1 */
 883
 884         /* Set initial value for DDS_CLK_RATE */
 885         mul = (1 << 24) >> 1;
 886
 887         /* Calculate initial quot */
 888         q1 = DIV_ROUND_UP(fref1, rate);
 889
 890         /* Scale q1 if it's too big */
 891         if (q1 > 256) {
 892                 /* Scale q1 to range [1, 512] */
 893                 scale = fls_long(q1 - 1);
 894                 if (scale > 9) {
 895                         q1 >>= scale - 9;
 896                         mul >>= scale - 9;
 897                 }
 898
 899                 /* Round the result if we have a remainder */
 900                 q1 += q1 & 1;
 901         }
 902
 903         /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
 904         scale = __ffs(q1);
 905         q1 >>= scale;
 906         mul >>= scale;
 907
 908         /* Get the remainder */
 909         r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
 910
 911         /* Case 2 */
 912
 913         q2 = DIV_ROUND_UP(fref2, rate);
 914         r2 = abs(fref2 / q2 - rate);
 915
 916         /*
 917          * Choose the best between two: less remainder we have the better. We
 918          * can't go case 2 if q2 is greater than 256 since SCR register can
 919          * hold only values 0 .. 255.
 920          */
 921         if (r2 >= r1 || q2 > 256) {
 922                 /* case 1 is better */
 923                 r = r1;
 924                 q = q1;
 925         } else {
 926                 /* case 2 is better */
 927                 r = r2;
 928                 q = q2;
 929                 mul = (1 << 24) * 2 / 5;
 930         }
 931
 932         /* Check case 3 only if the divisor is big enough */
 933         if (fref / rate >= 80) {
 934                 u64 fssp;
 935                 u32 m;
 936
 937                 /* Calculate initial quot */
 938                 q1 = DIV_ROUND_UP(fref, rate);
 939                 m = (1 << 24) / q1;
 940
 941                 /* Get the remainder */
 942                 fssp = (u64)fref * m;
 943                 do_div(fssp, 1 << 24);
 944                 r1 = abs(fssp - rate);
 945
 946                 /* Choose this one if it suits better */
 947                 if (r1 < r) {
 948                         /* case 3 is better */
 949                         q = 1;
 950                         mul = m;
 951                 }
 952         }
 953
 954         *dds = mul;
 955         return q - 1;
 956 }
 957
 958 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
 959 {
 960         unsigned long ssp_clk = drv_data->master->max_speed_hz;
 961         const struct ssp_device *ssp = drv_data->ssp;
 962
 963         rate = min_t(int, ssp_clk, rate);
 964
 965         /*
 966          * Calculate the divisor for the SCR (Serial Clock Rate), avoiding
 967          * that the SSP transmission rate can be greater than the device rate
 968          */
 969         if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
 970                 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff;
 971         else
 972                 return (DIV_ROUND_UP(ssp_clk, rate) - 1)  & 0xfff;
 973 }
 974
 975 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
 976                                            int rate)
 977 {
 978         struct chip_data *chip =
 979                 spi_get_ctldata(drv_data->master->cur_msg->spi);
 980         unsigned int clk_div;
 981
 982         switch (drv_data->ssp_type) {
 983         case QUARK_X1000_SSP:
 984                 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
 985                 break;
 986         default:
 987                 clk_div = ssp_get_clk_div(drv_data, rate);
 988                 break;
 989         }
 990         return clk_div << 8;
 991 }
 992
 993 static bool pxa2xx_spi_can_dma(struct spi_master *master,
 994                                struct spi_device *spi,
 995                                struct spi_transfer *xfer)
 996 {
 997         struct chip_data *chip = spi_get_ctldata(spi);
 998
 999         return chip->enable_dma &&
1000                xfer->len <= MAX_DMA_LEN &&
1001                xfer->len >= chip->dma_burst_size;
1002 }
1003
1004 static void pump_transfers(unsigned long data)
1005 {
1006         struct driver_data *drv_data = (struct driver_data *)data;
1007         struct spi_master *master = drv_data->master;
1008         struct spi_message *message = master->cur_msg;
1009         struct chip_data *chip = spi_get_ctldata(message->spi);
1010         u32 dma_thresh = chip->dma_threshold;
1011         u32 dma_burst = chip->dma_burst_size;
1012         u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
1013         struct spi_transfer *transfer;
1014         struct spi_transfer *previous;
1015         u32 clk_div;
1016         u8 bits;
1017         u32 speed;
1018         u32 cr0;
1019         u32 cr1;
1020         int err;
1021         int dma_mapped;
1022
1023         /* Get current state information */
1024         transfer = drv_data->cur_transfer;
1025
1026         /* Handle for abort */
1027         if (message->state == ERROR_STATE) {
1028                 message->status = -EIO;
1029                 giveback(drv_data);
1030                 return;
1031         }
1032
1033         /* Handle end of message */
1034         if (message->state == DONE_STATE) {
1035                 message->status = 0;
1036                 giveback(drv_data);
1037                 return;
1038         }
1039
1040         /* Delay if requested at end of transfer before CS change */
1041         if (message->state == RUNNING_STATE) {
1042                 previous = list_entry(transfer->transfer_list.prev,
1043                                         struct spi_transfer,
1044                                         transfer_list);
1045                 if (previous->delay_usecs)
1046                         udelay(previous->delay_usecs);
1047
1048                 /* Drop chip select only if cs_change is requested */
1049                 if (previous->cs_change)
1050                         cs_deassert(drv_data);
1051         }
1052
1053         /* Check if we can DMA this transfer */
1054         if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
1055
1056                 /* reject already-mapped transfers; PIO won't always work */
1057                 if (message->is_dma_mapped
1058                                 || transfer->rx_dma || transfer->tx_dma) {
1059                         dev_err(&drv_data->pdev->dev,
1060                                 "pump_transfers: mapped transfer length of "
1061                                 "%u is greater than %d\n",
1062                                 transfer->len, MAX_DMA_LEN);
1063                         message->status = -EINVAL;
1064                         giveback(drv_data);
1065                         return;
1066                 }
1067
1068                 /* warn ... we force this to PIO mode */
1069                 dev_warn_ratelimited(&message->spi->dev,
1070                                      "pump_transfers: DMA disabled for transfer length %ld "
1071                                      "greater than %d\n",
1072                                      (long)drv_data->len, MAX_DMA_LEN);
1073         }
1074
1075         /* Setup the transfer state based on the type of transfer */
1076         if (pxa2xx_spi_flush(drv_data) == 0) {
1077                 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
1078                 message->status = -EIO;
1079                 giveback(drv_data);
1080                 return;
1081         }
1082         drv_data->n_bytes = chip->n_bytes;
1083         drv_data->tx = (void *)transfer->tx_buf;
1084         drv_data->tx_end = drv_data->tx + transfer->len;
1085         drv_data->rx = transfer->rx_buf;
1086         drv_data->rx_end = drv_data->rx + transfer->len;
1087         drv_data->len = transfer->len;
1088         drv_data->write = drv_data->tx ? chip->write : null_writer;
1089         drv_data->read = drv_data->rx ? chip->read : null_reader;
1090
1091         /* Change speed and bit per word on a per transfer */
1092         bits = transfer->bits_per_word;
1093         speed = transfer->speed_hz;
1094
1095         clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
1096
1097         if (bits <= 8) {
1098                 drv_data->n_bytes = 1;
1099                 drv_data->read = drv_data->read != null_reader ?
1100                                         u8_reader : null_reader;
1101                 drv_data->write = drv_data->write != null_writer ?
1102                                         u8_writer : null_writer;
1103         } else if (bits <= 16) {
1104                 drv_data->n_bytes = 2;
1105                 drv_data->read = drv_data->read != null_reader ?
1106                                         u16_reader : null_reader;
1107                 drv_data->write = drv_data->write != null_writer ?
1108                                         u16_writer : null_writer;
1109         } else if (bits <= 32) {
1110                 drv_data->n_bytes = 4;
1111                 drv_data->read = drv_data->read != null_reader ?
1112                                         u32_reader : null_reader;
1113                 drv_data->write = drv_data->write != null_writer ?
1114                                         u32_writer : null_writer;
1115         }
1116         /*
1117          * if bits/word is changed in dma mode, then must check the
1118          * thresholds and burst also
1119          */
1120         if (chip->enable_dma) {
1121                 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
1122                                                 message->spi,
1123                                                 bits, &dma_burst,
1124                                                 &dma_thresh))
1125                         dev_warn_ratelimited(&message->spi->dev,
1126                                              "pump_transfers: DMA burst size reduced to match bits_per_word\n");
1127         }
1128
1129         message->state = RUNNING_STATE;
1130
1131         dma_mapped = master->can_dma &&
1132                      master->can_dma(master, message->spi, transfer) &&
1133                      master->cur_msg_mapped;
1134         if (dma_mapped) {
1135
1136                 /* Ensure we have the correct interrupt handler */
1137                 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1138
1139                 err = pxa2xx_spi_dma_prepare(drv_data, dma_burst);
1140                 if (err) {
1141                         message->status = err;
1142                         giveback(drv_data);
1143                         return;
1144                 }
1145
1146                 /* Clear status and start DMA engine */
1147                 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1148                 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1149
1150                 pxa2xx_spi_dma_start(drv_data);
1151         } else {
1152                 /* Ensure we have the correct interrupt handler */
1153                 drv_data->transfer_handler = interrupt_transfer;
1154
1155                 /* Clear status  */
1156                 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1157                 write_SSSR_CS(drv_data, drv_data->clear_sr);
1158         }
1159
1160         /* NOTE:  PXA25x_SSP _could_ use external clocking ... */
1161         cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1162         if (!pxa25x_ssp_comp(drv_data))
1163                 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1164                         master->max_speed_hz
1165                                 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1166                         dma_mapped ? "DMA" : "PIO");
1167         else
1168                 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1169                         master->max_speed_hz / 2
1170                                 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1171                         dma_mapped ? "DMA" : "PIO");
1172
1173         if (is_lpss_ssp(drv_data)) {
1174                 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1175                     != chip->lpss_rx_threshold)
1176                         pxa2xx_spi_write(drv_data, SSIRF,
1177                                          chip->lpss_rx_threshold);
1178                 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1179                     != chip->lpss_tx_threshold)
1180                         pxa2xx_spi_write(drv_data, SSITF,
1181                                          chip->lpss_tx_threshold);
1182         }
1183
1184         if (is_quark_x1000_ssp(drv_data) &&
1185             (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1186                 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1187
1188         /* see if we need to reload the config registers */
1189         if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1190             || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1191             != (cr1 & change_mask)) {
1192                 /* stop the SSP, and update the other bits */
1193                 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1194                 if (!pxa25x_ssp_comp(drv_data))
1195                         pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1196                 /* first set CR1 without interrupt and service enables */
1197                 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1198                 /* restart the SSP */
1199                 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1200
1201         } else {
1202                 if (!pxa25x_ssp_comp(drv_data))
1203                         pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1204         }
1205
1206         cs_assert(drv_data);
1207
1208         /* after chip select, release the data by enabling service
1209          * requests and interrupts, without changing any mode bits */
1210         pxa2xx_spi_write(drv_data, SSCR1, cr1);
1211 }
1212
1213 static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
1214                                            struct spi_message *msg)
1215 {
1216         struct driver_data *drv_data = spi_master_get_devdata(master);
1217
1218         /* Initial message state*/
1219         msg->state = START_STATE;
1220         drv_data->cur_transfer = list_entry(msg->transfers.next,
1221                                                 struct spi_transfer,
1222                                                 transfer_list);
1223
1224         /* Mark as busy and launch transfers */
1225         tasklet_schedule(&drv_data->pump_transfers);
1226         return 0;
1227 }
1228
1229 static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
1230 {
1231         struct driver_data *drv_data = spi_master_get_devdata(master);
1232
1233         /* Disable the SSP now */
1234         pxa2xx_spi_write(drv_data, SSCR0,
1235                          pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1236
1237         return 0;
1238 }
1239
1240 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1241                     struct pxa2xx_spi_chip *chip_info)
1242 {
1243         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1244         struct gpio_desc *gpiod;
1245         int err = 0;
1246
1247         if (chip == NULL)
1248                 return 0;
1249
1250         if (drv_data->cs_gpiods) {
1251                 gpiod = drv_data->cs_gpiods[spi->chip_select];
1252                 if (gpiod) {
1253                         chip->gpiod_cs = gpiod;
1254                         chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1255                         gpiod_set_value(gpiod, chip->gpio_cs_inverted);
1256                 }
1257
1258                 return 0;
1259         }
1260
1261         if (chip_info == NULL)
1262                 return 0;
1263
1264         /* NOTE: setup() can be called multiple times, possibly with
1265          * different chip_info, release previously requested GPIO
1266          */
1267         if (chip->gpiod_cs) {
1268                 gpio_free(desc_to_gpio(chip->gpiod_cs));
1269                 chip->gpiod_cs = NULL;
1270         }
1271
1272         /* If (*cs_control) is provided, ignore GPIO chip select */
1273         if (chip_info->cs_control) {
1274                 chip->cs_control = chip_info->cs_control;
1275                 return 0;
1276         }
1277
1278         if (gpio_is_valid(chip_info->gpio_cs)) {
1279                 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1280                 if (err) {
1281                         dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1282                                 chip_info->gpio_cs);
1283                         return err;
1284                 }
1285
1286                 gpiod = gpio_to_desc(chip_info->gpio_cs);
1287                 chip->gpiod_cs = gpiod;
1288                 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1289
1290                 err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted);
1291         }
1292
1293         return err;
1294 }
1295
1296 static int setup(struct spi_device *spi)
1297 {
1298         struct pxa2xx_spi_chip *chip_info;
1299         struct chip_data *chip;
1300         const struct lpss_config *config;
1301         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1302         uint tx_thres, tx_hi_thres, rx_thres;
1303
1304         switch (drv_data->ssp_type) {
1305         case QUARK_X1000_SSP:
1306                 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1307                 tx_hi_thres = 0;
1308                 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1309                 break;
1310         case CE4100_SSP:
1311                 tx_thres = TX_THRESH_CE4100_DFLT;
1312                 tx_hi_thres = 0;
1313                 rx_thres = RX_THRESH_CE4100_DFLT;
1314                 break;
1315         case LPSS_LPT_SSP:
1316         case LPSS_BYT_SSP:
1317         case LPSS_BSW_SSP:
1318         case LPSS_SPT_SSP:
1319         case LPSS_BXT_SSP:
1320         case LPSS_CNL_SSP:
1321                 config = lpss_get_config(drv_data);
1322                 tx_thres = config->tx_threshold_lo;
1323                 tx_hi_thres = config->tx_threshold_hi;
1324                 rx_thres = config->rx_threshold;
1325                 break;
1326         default:
1327                 tx_thres = TX_THRESH_DFLT;
1328                 tx_hi_thres = 0;
1329                 rx_thres = RX_THRESH_DFLT;
1330                 break;
1331         }
1332
1333         /* Only alloc on first setup */
1334         chip = spi_get_ctldata(spi);
1335         if (!chip) {
1336                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1337                 if (!chip)
1338                         return -ENOMEM;
1339
1340                 if (drv_data->ssp_type == CE4100_SSP) {
1341                         if (spi->chip_select > 4) {
1342                                 dev_err(&spi->dev,
1343                                         "failed setup: cs number must not be > 4.\n");
1344                                 kfree(chip);
1345                                 return -EINVAL;
1346                         }
1347
1348                         chip->frm = spi->chip_select;
1349                 }
1350                 chip->enable_dma = drv_data->master_info->enable_dma;
1351                 chip->timeout = TIMOUT_DFLT;
1352         }
1353
1354         /* protocol drivers may change the chip settings, so...
1355          * if chip_info exists, use it */
1356         chip_info = spi->controller_data;
1357
1358         /* chip_info isn't always needed */
1359         chip->cr1 = 0;
1360         if (chip_info) {
1361                 if (chip_info->timeout)
1362                         chip->timeout = chip_info->timeout;
1363                 if (chip_info->tx_threshold)
1364                         tx_thres = chip_info->tx_threshold;
1365                 if (chip_info->tx_hi_threshold)
1366                         tx_hi_thres = chip_info->tx_hi_threshold;
1367                 if (chip_info->rx_threshold)
1368                         rx_thres = chip_info->rx_threshold;
1369                 chip->dma_threshold = 0;
1370                 if (chip_info->enable_loopback)
1371                         chip->cr1 = SSCR1_LBM;
1372         }
1373
1374         chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1375         chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1376                                 | SSITF_TxHiThresh(tx_hi_thres);
1377
1378         /* set dma burst and threshold outside of chip_info path so that if
1379          * chip_info goes away after setting chip->enable_dma, the
1380          * burst and threshold can still respond to changes in bits_per_word */
1381         if (chip->enable_dma) {
1382                 /* set up legal burst and threshold for dma */
1383                 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1384                                                 spi->bits_per_word,
1385                                                 &chip->dma_burst_size,
1386                                                 &chip->dma_threshold)) {
1387                         dev_warn(&spi->dev,
1388                                  "in setup: DMA burst size reduced to match bits_per_word\n");
1389                 }
1390         }
1391
1392         switch (drv_data->ssp_type) {
1393         case QUARK_X1000_SSP:
1394                 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1395                                    & QUARK_X1000_SSCR1_RFT)
1396                                    | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1397                                    & QUARK_X1000_SSCR1_TFT);
1398                 break;
1399         case CE4100_SSP:
1400                 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
1401                         (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
1402                 break;
1403         default:
1404                 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1405                         (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1406                 break;
1407         }
1408
1409         chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1410         chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1411                         | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1412
1413         if (spi->mode & SPI_LOOP)
1414                 chip->cr1 |= SSCR1_LBM;
1415
1416         if (spi->bits_per_word <= 8) {
1417                 chip->n_bytes = 1;
1418                 chip->read = u8_reader;
1419                 chip->write = u8_writer;
1420         } else if (spi->bits_per_word <= 16) {
1421                 chip->n_bytes = 2;
1422                 chip->read = u16_reader;
1423                 chip->write = u16_writer;
1424         } else if (spi->bits_per_word <= 32) {
1425                 chip->n_bytes = 4;
1426                 chip->read = u32_reader;
1427                 chip->write = u32_writer;
1428         }
1429
1430         spi_set_ctldata(spi, chip);
1431
1432         if (drv_data->ssp_type == CE4100_SSP)
1433                 return 0;
1434
1435         return setup_cs(spi, chip, chip_info);
1436 }
1437
1438 static void cleanup(struct spi_device *spi)
1439 {
1440         struct chip_data *chip = spi_get_ctldata(spi);
1441         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1442
1443         if (!chip)
1444                 return;
1445
1446         if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods &&
1447             chip->gpiod_cs)
1448                 gpio_free(desc_to_gpio(chip->gpiod_cs));
1449
1450         kfree(chip);
1451 }
1452
1453 #ifdef CONFIG_PCI
1454 #ifdef CONFIG_ACPI
1455
1456 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1457         { "INT33C0", LPSS_LPT_SSP },
1458         { "INT33C1", LPSS_LPT_SSP },
1459         { "INT3430", LPSS_LPT_SSP },
1460         { "INT3431", LPSS_LPT_SSP },
1461         { "80860F0E", LPSS_BYT_SSP },
1462         { "8086228E", LPSS_BSW_SSP },
1463         { },
1464 };
1465 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1466
1467 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1468 {
1469         unsigned int devid;
1470         int port_id = -1;
1471
1472         if (adev && adev->pnp.unique_id &&
1473             !kstrtouint(adev->pnp.unique_id, 0, &devid))
1474                 port_id = devid;
1475         return port_id;
1476 }
1477 #else /* !CONFIG_ACPI */
1478 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1479 {
1480         return -1;
1481 }
1482 #endif
1483
1484 /*
1485  * PCI IDs of compound devices that integrate both host controller and private
1486  * integrated DMA engine. Please note these are not used in module
1487  * autoloading and probing in this module but matching the LPSS SSP type.
1488  */
1489 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1490         /* SPT-LP */
1491         { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1492         { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1493         /* SPT-H */
1494         { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1495         { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1496         /* KBL-H */
1497         { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP },
1498         { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP },
1499         /* BXT A-Step */
1500         { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1501         { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1502         { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1503         /* BXT B-Step */
1504         { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
1505         { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
1506         { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },
1507         /* GLK */
1508         { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP },
1509         { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP },
1510         { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP },
1511         /* ICL-LP */
1512         { PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP },
1513         { PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP },
1514         { PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP },
1515         /* APL */
1516         { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1517         { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1518         { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1519         /* CNL-LP */
1520         { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP },
1521         { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP },
1522         { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP },
1523         /* CNL-H */
1524         { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP },
1525         { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP },
1526         { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP },
1527         { },
1528 };
1529
1530 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1531 {
1532         return param == chan->device->dev;
1533 }
1534
1535 static struct pxa2xx_spi_master *
1536 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1537 {
1538         struct pxa2xx_spi_master *pdata;
1539         struct acpi_device *adev;
1540         struct ssp_device *ssp;
1541         struct resource *res;
1542         const struct acpi_device_id *adev_id = NULL;
1543         const struct pci_device_id *pcidev_id = NULL;
1544         int type;
1545
1546         adev = ACPI_COMPANION(&pdev->dev);
1547
1548         if (dev_is_pci(pdev->dev.parent))
1549                 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
1550                                          to_pci_dev(pdev->dev.parent));
1551         else if (adev)
1552                 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
1553                                             &pdev->dev);
1554         else
1555                 return NULL;
1556
1557         if (adev_id)
1558                 type = (int)adev_id->driver_data;
1559         else if (pcidev_id)
1560                 type = (int)pcidev_id->driver_data;
1561         else
1562                 return NULL;
1563
1564         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1565         if (!pdata)
1566                 return NULL;
1567
1568         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1569         if (!res)
1570                 return NULL;
1571
1572         ssp = &pdata->ssp;
1573
1574         ssp->phys_base = res->start;
1575         ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1576         if (IS_ERR(ssp->mmio_base))
1577                 return NULL;
1578
1579         if (pcidev_id) {
1580                 pdata->tx_param = pdev->dev.parent;
1581                 pdata->rx_param = pdev->dev.parent;
1582                 pdata->dma_filter = pxa2xx_spi_idma_filter;
1583         }
1584
1585         ssp->clk = devm_clk_get(&pdev->dev, NULL);
1586         if (IS_ERR(ssp->clk))
1587                 return NULL;
1588
1589         ssp->irq = platform_get_irq(pdev, 0);
1590         if (ssp->irq < 0)
1591                 return NULL;
1592
1593         ssp->type = type;
1594         ssp->pdev = pdev;
1595         ssp->port_id = pxa2xx_spi_get_port_id(adev);
1596
1597         pdata->num_chipselect = 1;
1598         pdata->enable_dma = true;
1599
1600         return pdata;
1601 }
1602
1603 #else /* !CONFIG_PCI */
1604 static inline struct pxa2xx_spi_master *
1605 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1606 {
1607         return NULL;
1608 }
1609 #endif
1610
1611 static int pxa2xx_spi_fw_translate_cs(struct spi_master *master, unsigned cs)
1612 {
1613         struct driver_data *drv_data = spi_master_get_devdata(master);
1614
1615         if (has_acpi_companion(&drv_data->pdev->dev)) {
1616                 switch (drv_data->ssp_type) {
1617                 /*
1618                  * For Atoms the ACPI DeviceSelection used by the Windows
1619                  * driver starts from 1 instead of 0 so translate it here
1620                  * to match what Linux expects.
1621                  */
1622                 case LPSS_BYT_SSP:
1623                 case LPSS_BSW_SSP:
1624                         return cs - 1;
1625
1626                 default:
1627                         break;
1628                 }
1629         }
1630
1631         return cs;
1632 }
1633
1634 static int pxa2xx_spi_probe(struct platform_device *pdev)
1635 {
1636         struct device *dev = &pdev->dev;
1637         struct pxa2xx_spi_master *platform_info;
1638         struct spi_master *master;
1639         struct driver_data *drv_data;
1640         struct ssp_device *ssp;
1641         const struct lpss_config *config;
1642         int status, count;
1643         u32 tmp;
1644
1645         platform_info = dev_get_platdata(dev);
1646         if (!platform_info) {
1647                 platform_info = pxa2xx_spi_init_pdata(pdev);
1648                 if (!platform_info) {
1649                         dev_err(&pdev->dev, "missing platform data\n");
1650                         return -ENODEV;
1651                 }
1652         }
1653
1654         ssp = pxa_ssp_request(pdev->id, pdev->name);
1655         if (!ssp)
1656                 ssp = &platform_info->ssp;
1657
1658         if (!ssp->mmio_base) {
1659                 dev_err(&pdev->dev, "failed to get ssp\n");
1660                 return -ENODEV;
1661         }
1662
1663         master = devm_spi_alloc_master(dev, sizeof(*drv_data));
1664         if (!master) {
1665                 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1666                 pxa_ssp_free(ssp);
1667                 return -ENOMEM;
1668         }
1669         drv_data = spi_master_get_devdata(master);
1670         drv_data->master = master;
1671         drv_data->master_info = platform_info;
1672         drv_data->pdev = pdev;
1673         drv_data->ssp = ssp;
1674
1675         master->dev.of_node = pdev->dev.of_node;
1676         /* the spi->mode bits understood by this driver: */
1677         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1678
1679         master->bus_num = ssp->port_id;
1680         master->dma_alignment = DMA_ALIGNMENT;
1681         master->cleanup = cleanup;
1682         master->setup = setup;
1683         master->transfer_one_message = pxa2xx_spi_transfer_one_message;
1684         master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1685         master->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1686         master->auto_runtime_pm = true;
1687         master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
1688
1689         drv_data->ssp_type = ssp->type;
1690
1691         drv_data->ioaddr = ssp->mmio_base;
1692         drv_data->ssdr_physical = ssp->phys_base + SSDR;
1693         if (pxa25x_ssp_comp(drv_data)) {
1694                 switch (drv_data->ssp_type) {
1695                 case QUARK_X1000_SSP:
1696                         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1697                         break;
1698                 default:
1699                         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1700                         break;
1701                 }
1702
1703                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1704                 drv_data->dma_cr1 = 0;
1705                 drv_data->clear_sr = SSSR_ROR;
1706                 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1707         } else {
1708                 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1709                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1710                 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1711                 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1712                 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1713         }
1714
1715         status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1716                         drv_data);
1717         if (status < 0) {
1718                 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1719                 goto out_error_master_alloc;
1720         }
1721
1722         /* Setup DMA if requested */
1723         if (platform_info->enable_dma) {
1724                 status = pxa2xx_spi_dma_setup(drv_data);
1725                 if (status) {
1726                         dev_dbg(dev, "no DMA channels available, using PIO\n");
1727                         platform_info->enable_dma = false;
1728                 } else {
1729                         master->can_dma = pxa2xx_spi_can_dma;
1730                         master->max_dma_len = MAX_DMA_LEN;
1731                 }
1732         }
1733
1734         /* Enable SOC clock */
1735         clk_prepare_enable(ssp->clk);
1736
1737         master->max_speed_hz = clk_get_rate(ssp->clk);
1738
1739         /* Load default SSP configuration */
1740         pxa2xx_spi_write(drv_data, SSCR0, 0);
1741         switch (drv_data->ssp_type) {
1742         case QUARK_X1000_SSP:
1743                 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1744                       QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1745                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1746
1747                 /* using the Motorola SPI protocol and use 8 bit frame */
1748                 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
1749                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1750                 break;
1751         case CE4100_SSP:
1752                 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
1753                       CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
1754                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1755                 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1756                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1757                 break;
1758         default:
1759                 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1760                       SSCR1_TxTresh(TX_THRESH_DFLT);
1761                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1762                 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1763                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1764                 break;
1765         }
1766
1767         if (!pxa25x_ssp_comp(drv_data))
1768                 pxa2xx_spi_write(drv_data, SSTO, 0);
1769
1770         if (!is_quark_x1000_ssp(drv_data))
1771                 pxa2xx_spi_write(drv_data, SSPSP, 0);
1772
1773         if (is_lpss_ssp(drv_data)) {
1774                 lpss_ssp_setup(drv_data);
1775                 config = lpss_get_config(drv_data);
1776                 if (config->reg_capabilities >= 0) {
1777                         tmp = __lpss_ssp_read_priv(drv_data,
1778                                                    config->reg_capabilities);
1779                         tmp &= LPSS_CAPS_CS_EN_MASK;
1780                         tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1781                         platform_info->num_chipselect = ffz(tmp);
1782                 } else if (config->cs_num) {
1783                         platform_info->num_chipselect = config->cs_num;
1784                 }
1785         }
1786         master->num_chipselect = platform_info->num_chipselect;
1787
1788         count = gpiod_count(&pdev->dev, "cs");
1789         if (count > 0) {
1790                 int i;
1791
1792                 master->num_chipselect = max_t(int, count,
1793                         master->num_chipselect);
1794
1795                 drv_data->cs_gpiods = devm_kcalloc(&pdev->dev,
1796                         master->num_chipselect, sizeof(struct gpio_desc *),
1797                         GFP_KERNEL);
1798                 if (!drv_data->cs_gpiods) {
1799                         status = -ENOMEM;
1800                         goto out_error_clock_enabled;
1801                 }
1802
1803                 for (i = 0; i < master->num_chipselect; i++) {
1804                         struct gpio_desc *gpiod;
1805
1806                         gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
1807                         if (IS_ERR(gpiod)) {
1808                                 /* Means use native chip select */
1809                                 if (PTR_ERR(gpiod) == -ENOENT)
1810                                         continue;
1811
1812                                 status = (int)PTR_ERR(gpiod);
1813                                 goto out_error_clock_enabled;
1814                         } else {
1815                                 drv_data->cs_gpiods[i] = gpiod;
1816                         }
1817                 }
1818         }
1819
1820         tasklet_init(&drv_data->pump_transfers, pump_transfers,
1821                      (unsigned long)drv_data);
1822
1823         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1824         pm_runtime_use_autosuspend(&pdev->dev);
1825         pm_runtime_set_active(&pdev->dev);
1826         pm_runtime_enable(&pdev->dev);
1827
1828         /* Register with the SPI framework */
1829         platform_set_drvdata(pdev, drv_data);
1830         status = spi_register_master(master);
1831         if (status != 0) {
1832                 dev_err(&pdev->dev, "problem registering spi master\n");
1833                 goto out_error_clock_enabled;
1834         }
1835
1836         return status;
1837
1838 out_error_clock_enabled:
1839         clk_disable_unprepare(ssp->clk);
1840         pxa2xx_spi_dma_release(drv_data);
1841         free_irq(ssp->irq, drv_data);
1842
1843 out_error_master_alloc:
1844         pxa_ssp_free(ssp);
1845         return status;
1846 }
1847
1848 static int pxa2xx_spi_remove(struct platform_device *pdev)
1849 {
1850         struct driver_data *drv_data = platform_get_drvdata(pdev);
1851         struct ssp_device *ssp;
1852
1853         if (!drv_data)
1854                 return 0;
1855         ssp = drv_data->ssp;
1856
1857         pm_runtime_get_sync(&pdev->dev);
1858
1859         spi_unregister_master(drv_data->master);
1860
1861         /* Disable the SSP at the peripheral and SOC level */
1862         pxa2xx_spi_write(drv_data, SSCR0, 0);
1863         clk_disable_unprepare(ssp->clk);
1864
1865         /* Release DMA */
1866         if (drv_data->master_info->enable_dma)
1867                 pxa2xx_spi_dma_release(drv_data);
1868
1869         pm_runtime_put_noidle(&pdev->dev);
1870         pm_runtime_disable(&pdev->dev);
1871
1872         /* Release IRQ */
1873         free_irq(ssp->irq, drv_data);
1874
1875         /* Release SSP */
1876         pxa_ssp_free(ssp);
1877
1878         return 0;
1879 }
1880
1881 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1882 {
1883         int status = 0;
1884
1885         if ((status = pxa2xx_spi_remove(pdev)) != 0)
1886                 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1887 }
1888
1889 #ifdef CONFIG_PM_SLEEP
1890 static int pxa2xx_spi_suspend(struct device *dev)
1891 {
1892         struct driver_data *drv_data = dev_get_drvdata(dev);
1893         struct ssp_device *ssp = drv_data->ssp;
1894         int status;
1895
1896         status = spi_master_suspend(drv_data->master);
1897         if (status != 0)
1898                 return status;
1899         pxa2xx_spi_write(drv_data, SSCR0, 0);
1900
1901         if (!pm_runtime_suspended(dev))
1902                 clk_disable_unprepare(ssp->clk);
1903
1904         return 0;
1905 }
1906
1907 static int pxa2xx_spi_resume(struct device *dev)
1908 {
1909         struct driver_data *drv_data = dev_get_drvdata(dev);
1910         struct ssp_device *ssp = drv_data->ssp;
1911         int status;
1912
1913         /* Enable the SSP clock */
1914         if (!pm_runtime_suspended(dev))
1915                 clk_prepare_enable(ssp->clk);
1916
1917         /* Restore LPSS private register bits */
1918         if (is_lpss_ssp(drv_data))
1919                 lpss_ssp_setup(drv_data);
1920
1921         /* Start the queue running */
1922         status = spi_master_resume(drv_data->master);
1923         if (status != 0) {
1924                 dev_err(dev, "problem starting queue (%d)\n", status);
1925                 return status;
1926         }
1927
1928         return 0;
1929 }
1930 #endif
1931
1932 #ifdef CONFIG_PM
1933 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1934 {
1935         struct driver_data *drv_data = dev_get_drvdata(dev);
1936
1937         clk_disable_unprepare(drv_data->ssp->clk);
1938         return 0;
1939 }
1940
1941 static int pxa2xx_spi_runtime_resume(struct device *dev)
1942 {
1943         struct driver_data *drv_data = dev_get_drvdata(dev);
1944
1945         clk_prepare_enable(drv_data->ssp->clk);
1946         return 0;
1947 }
1948 #endif
1949
1950 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1951         SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1952         SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1953                            pxa2xx_spi_runtime_resume, NULL)
1954 };
1955
1956 static struct platform_driver driver = {
1957         .driver = {
1958                 .name   = "pxa2xx-spi",
1959                 .pm     = &pxa2xx_spi_pm_ops,
1960                 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1961         },
1962         .probe = pxa2xx_spi_probe,
1963         .remove = pxa2xx_spi_remove,
1964         .shutdown = pxa2xx_spi_shutdown,
1965 };
1966
1967 static int __init pxa2xx_spi_init(void)
1968 {
1969         return platform_driver_register(&driver);
1970 }
1971 subsys_initcall(pxa2xx_spi_init);
1972
1973 static void __exit pxa2xx_spi_exit(void)
1974 {
1975         platform_driver_unregister(&driver);
1976 }
1977 module_exit(pxa2xx_spi_exit);