2 * OMAP2 McSPI controller driver
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrj�l� <juha.yrjola@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/interrupt.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmaengine.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/platform_device.h>
28 #include <linux/err.h>
29 #include <linux/clk.h>
31 #include <linux/slab.h>
32 #include <linux/pm_runtime.h>
34 #include <linux/of_device.h>
35 #include <linux/gcd.h>
37 #include <linux/spi/spi.h>
38 #include <linux/gpio.h>
40 #include <linux/platform_data/spi-omap2-mcspi.h>
42 #define OMAP2_MCSPI_MAX_FREQ 48000000
43 #define OMAP2_MCSPI_MAX_DIVIDER 4096
44 #define OMAP2_MCSPI_MAX_FIFODEPTH 64
45 #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF
46 #define SPI_AUTOSUSPEND_TIMEOUT 2000
48 #define OMAP2_MCSPI_REVISION 0x00
49 #define OMAP2_MCSPI_SYSSTATUS 0x14
50 #define OMAP2_MCSPI_IRQSTATUS 0x18
51 #define OMAP2_MCSPI_IRQENABLE 0x1c
52 #define OMAP2_MCSPI_WAKEUPENABLE 0x20
53 #define OMAP2_MCSPI_SYST 0x24
54 #define OMAP2_MCSPI_MODULCTRL 0x28
55 #define OMAP2_MCSPI_XFERLEVEL 0x7c
57 /* per-channel banks, 0x14 bytes each, first is: */
58 #define OMAP2_MCSPI_CHCONF0 0x2c
59 #define OMAP2_MCSPI_CHSTAT0 0x30
60 #define OMAP2_MCSPI_CHCTRL0 0x34
61 #define OMAP2_MCSPI_TX0 0x38
62 #define OMAP2_MCSPI_RX0 0x3c
64 /* per-register bitmasks: */
65 #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17)
67 #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
68 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
69 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
71 #define OMAP2_MCSPI_CHCONF_PHA BIT(0)
72 #define OMAP2_MCSPI_CHCONF_POL BIT(1)
73 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
74 #define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
75 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
76 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
77 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
78 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
79 #define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
80 #define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
81 #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
82 #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
83 #define OMAP2_MCSPI_CHCONF_IS BIT(18)
84 #define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
85 #define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
86 #define OMAP2_MCSPI_CHCONF_FFET BIT(27)
87 #define OMAP2_MCSPI_CHCONF_FFER BIT(28)
88 #define OMAP2_MCSPI_CHCONF_CLKG BIT(29)
90 #define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
91 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
92 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
93 #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3)
95 #define OMAP2_MCSPI_CHCTRL_EN BIT(0)
96 #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8)
98 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
100 /* We have 2 DMA channels per CS, one for RX and one for TX */
101 struct omap2_mcspi_dma {
102 struct dma_chan *dma_tx;
103 struct dma_chan *dma_rx;
105 struct completion dma_tx_completion;
106 struct completion dma_rx_completion;
108 char dma_rx_ch_name[14];
109 char dma_tx_ch_name[14];
112 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
113 * cache operations; better heuristics consider wordsize and bitrate.
115 #define DMA_MIN_BYTES 160
119 * Used for context save and restore, structure members to be updated whenever
120 * corresponding registers are modified.
122 struct omap2_mcspi_regs {
129 struct spi_master *master;
130 /* Virtual base address of the controller */
133 /* SPI1 has 4 channels, while SPI2 has 2 */
134 struct omap2_mcspi_dma *dma_channels;
136 struct omap2_mcspi_regs ctx;
138 unsigned int pin_dir:1;
141 struct omap2_mcspi_cs {
146 struct list_head node;
147 /* Context save and restore shadow register */
148 u32 chconf0, chctrl0;
151 static inline void mcspi_write_reg(struct spi_master *master,
154 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
156 writel_relaxed(val, mcspi->base + idx);
159 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
161 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
163 return readl_relaxed(mcspi->base + idx);
166 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
169 struct omap2_mcspi_cs *cs = spi->controller_state;
171 writel_relaxed(val, cs->base + idx);
174 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
176 struct omap2_mcspi_cs *cs = spi->controller_state;
178 return readl_relaxed(cs->base + idx);
181 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
183 struct omap2_mcspi_cs *cs = spi->controller_state;
188 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
190 struct omap2_mcspi_cs *cs = spi->controller_state;
193 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
194 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
197 static inline int mcspi_bytes_per_word(int word_len)
201 else if (word_len <= 16)
203 else /* word_len <= 32 */
207 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
208 int is_read, int enable)
212 l = mcspi_cached_chconf0(spi);
214 if (is_read) /* 1 is read, 0 write */
215 rw = OMAP2_MCSPI_CHCONF_DMAR;
217 rw = OMAP2_MCSPI_CHCONF_DMAW;
224 mcspi_write_chconf0(spi, l);
227 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
229 struct omap2_mcspi_cs *cs = spi->controller_state;
234 l |= OMAP2_MCSPI_CHCTRL_EN;
236 l &= ~OMAP2_MCSPI_CHCTRL_EN;
238 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
239 /* Flash post-writes */
240 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
243 static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable)
245 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
248 /* The controller handles the inverted chip selects
249 * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert
250 * the inversion from the core spi_set_cs function.
252 if (spi->mode & SPI_CS_HIGH)
255 if (spi->controller_state) {
256 int err = pm_runtime_get_sync(mcspi->dev);
258 dev_err(mcspi->dev, "failed to get sync: %d\n", err);
262 l = mcspi_cached_chconf0(spi);
265 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
267 l |= OMAP2_MCSPI_CHCONF_FORCE;
269 mcspi_write_chconf0(spi, l);
271 pm_runtime_mark_last_busy(mcspi->dev);
272 pm_runtime_put_autosuspend(mcspi->dev);
276 static void omap2_mcspi_set_master_mode(struct spi_master *master)
278 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
279 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
283 * Setup when switching from (reset default) slave mode
284 * to single-channel master mode
286 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
287 l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
288 l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
289 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
294 static void omap2_mcspi_set_fifo(const struct spi_device *spi,
295 struct spi_transfer *t, int enable)
297 struct spi_master *master = spi->master;
298 struct omap2_mcspi_cs *cs = spi->controller_state;
299 struct omap2_mcspi *mcspi;
301 int max_fifo_depth, bytes_per_word;
302 u32 chconf, xferlevel;
304 mcspi = spi_master_get_devdata(master);
306 chconf = mcspi_cached_chconf0(spi);
308 bytes_per_word = mcspi_bytes_per_word(cs->word_len);
309 if (t->len % bytes_per_word != 0)
312 if (t->rx_buf != NULL && t->tx_buf != NULL)
313 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2;
315 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH;
317 wcnt = t->len / bytes_per_word;
318 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
321 xferlevel = wcnt << 16;
322 if (t->rx_buf != NULL) {
323 chconf |= OMAP2_MCSPI_CHCONF_FFER;
324 xferlevel |= (bytes_per_word - 1) << 8;
327 if (t->tx_buf != NULL) {
328 chconf |= OMAP2_MCSPI_CHCONF_FFET;
329 xferlevel |= bytes_per_word - 1;
332 mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
333 mcspi_write_chconf0(spi, chconf);
334 mcspi->fifo_depth = max_fifo_depth;
340 if (t->rx_buf != NULL)
341 chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
343 if (t->tx_buf != NULL)
344 chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
346 mcspi_write_chconf0(spi, chconf);
347 mcspi->fifo_depth = 0;
350 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
352 struct spi_master *spi_cntrl = mcspi->master;
353 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
354 struct omap2_mcspi_cs *cs;
356 /* McSPI: context restore */
357 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
358 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
360 list_for_each_entry(cs, &ctx->cs, node)
361 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
364 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
366 unsigned long timeout;
368 timeout = jiffies + msecs_to_jiffies(1000);
369 while (!(readl_relaxed(reg) & bit)) {
370 if (time_after(jiffies, timeout)) {
371 if (!(readl_relaxed(reg) & bit))
381 static void omap2_mcspi_rx_callback(void *data)
383 struct spi_device *spi = data;
384 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
385 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
387 /* We must disable the DMA RX request */
388 omap2_mcspi_set_dma_req(spi, 1, 0);
390 complete(&mcspi_dma->dma_rx_completion);
393 static void omap2_mcspi_tx_callback(void *data)
395 struct spi_device *spi = data;
396 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
397 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
399 /* We must disable the DMA TX request */
400 omap2_mcspi_set_dma_req(spi, 0, 0);
402 complete(&mcspi_dma->dma_tx_completion);
405 static void omap2_mcspi_tx_dma(struct spi_device *spi,
406 struct spi_transfer *xfer,
407 struct dma_slave_config cfg)
409 struct omap2_mcspi *mcspi;
410 struct omap2_mcspi_dma *mcspi_dma;
413 mcspi = spi_master_get_devdata(spi->master);
414 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
417 if (mcspi_dma->dma_tx) {
418 struct dma_async_tx_descriptor *tx;
420 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
422 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl,
425 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
427 tx->callback = omap2_mcspi_tx_callback;
428 tx->callback_param = spi;
429 dmaengine_submit(tx);
431 /* FIXME: fall back to PIO? */
434 dma_async_issue_pending(mcspi_dma->dma_tx);
435 omap2_mcspi_set_dma_req(spi, 0, 1);
440 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
441 struct dma_slave_config cfg,
444 struct omap2_mcspi *mcspi;
445 struct omap2_mcspi_dma *mcspi_dma;
446 unsigned int count, transfer_reduction = 0;
447 struct scatterlist *sg_out[2];
448 int nb_sizes = 0, out_mapped_nents[2], ret, x;
452 int word_len, element_count;
453 struct omap2_mcspi_cs *cs = spi->controller_state;
454 void __iomem *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
456 mcspi = spi_master_get_devdata(spi->master);
457 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
461 * In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM
462 * it mentions reducing DMA transfer length by one element in master
465 if (mcspi->fifo_depth == 0)
466 transfer_reduction = es;
468 word_len = cs->word_len;
469 l = mcspi_cached_chconf0(spi);
472 element_count = count;
473 else if (word_len <= 16)
474 element_count = count >> 1;
475 else /* word_len <= 32 */
476 element_count = count >> 2;
478 if (mcspi_dma->dma_rx) {
479 struct dma_async_tx_descriptor *tx;
481 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
484 * Reduce DMA transfer length by one more if McSPI is
485 * configured in turbo mode.
487 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
488 transfer_reduction += es;
490 if (transfer_reduction) {
491 /* Split sgl into two. The second sgl won't be used. */
492 sizes[0] = count - transfer_reduction;
493 sizes[1] = transfer_reduction;
497 * Don't bother splitting the sgl. This essentially
498 * clones the original sgl.
504 ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents,
507 sg_out, out_mapped_nents,
511 dev_err(&spi->dev, "sg_split failed\n");
515 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx,
519 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
521 tx->callback = omap2_mcspi_rx_callback;
522 tx->callback_param = spi;
523 dmaengine_submit(tx);
525 /* FIXME: fall back to PIO? */
529 dma_async_issue_pending(mcspi_dma->dma_rx);
530 omap2_mcspi_set_dma_req(spi, 1, 1);
532 wait_for_completion(&mcspi_dma->dma_rx_completion);
534 for (x = 0; x < nb_sizes; x++)
537 if (mcspi->fifo_depth > 0)
541 * Due to the DMA transfer length reduction the missing bytes must
542 * be read manually to receive all of the expected data.
544 omap2_mcspi_set_enable(spi, 0);
546 elements = element_count - 1;
548 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
551 if (!mcspi_wait_for_reg_bit(chstat_reg,
552 OMAP2_MCSPI_CHSTAT_RXS)) {
555 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
557 ((u8 *)xfer->rx_buf)[elements++] = w;
558 else if (word_len <= 16)
559 ((u16 *)xfer->rx_buf)[elements++] = w;
560 else /* word_len <= 32 */
561 ((u32 *)xfer->rx_buf)[elements++] = w;
563 int bytes_per_word = mcspi_bytes_per_word(word_len);
564 dev_err(&spi->dev, "DMA RX penultimate word empty\n");
565 count -= (bytes_per_word << 1);
566 omap2_mcspi_set_enable(spi, 1);
570 if (!mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_RXS)) {
573 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
575 ((u8 *)xfer->rx_buf)[elements] = w;
576 else if (word_len <= 16)
577 ((u16 *)xfer->rx_buf)[elements] = w;
578 else /* word_len <= 32 */
579 ((u32 *)xfer->rx_buf)[elements] = w;
581 dev_err(&spi->dev, "DMA RX last word empty\n");
582 count -= mcspi_bytes_per_word(word_len);
584 omap2_mcspi_set_enable(spi, 1);
589 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
591 struct omap2_mcspi *mcspi;
592 struct omap2_mcspi_cs *cs = spi->controller_state;
593 struct omap2_mcspi_dma *mcspi_dma;
598 struct dma_slave_config cfg;
599 enum dma_slave_buswidth width;
601 void __iomem *chstat_reg;
602 void __iomem *irqstat_reg;
605 mcspi = spi_master_get_devdata(spi->master);
606 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
607 l = mcspi_cached_chconf0(spi);
610 if (cs->word_len <= 8) {
611 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
613 } else if (cs->word_len <= 16) {
614 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
617 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
623 memset(&cfg, 0, sizeof(cfg));
624 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
625 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
626 cfg.src_addr_width = width;
627 cfg.dst_addr_width = width;
628 cfg.src_maxburst = 1;
629 cfg.dst_maxburst = 1;
635 omap2_mcspi_tx_dma(spi, xfer, cfg);
638 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
641 wait_for_completion(&mcspi_dma->dma_tx_completion);
643 if (mcspi->fifo_depth > 0) {
644 irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
646 if (mcspi_wait_for_reg_bit(irqstat_reg,
647 OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
648 dev_err(&spi->dev, "EOW timed out\n");
650 mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
651 OMAP2_MCSPI_IRQSTATUS_EOW);
654 /* for TX_ONLY mode, be sure all words have shifted out */
656 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
657 if (mcspi->fifo_depth > 0) {
658 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
659 OMAP2_MCSPI_CHSTAT_TXFFE);
661 dev_err(&spi->dev, "TXFFE timed out\n");
663 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
664 OMAP2_MCSPI_CHSTAT_TXS);
666 dev_err(&spi->dev, "TXS timed out\n");
669 (mcspi_wait_for_reg_bit(chstat_reg,
670 OMAP2_MCSPI_CHSTAT_EOT) < 0))
671 dev_err(&spi->dev, "EOT timed out\n");
678 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
680 struct omap2_mcspi *mcspi;
681 struct omap2_mcspi_cs *cs = spi->controller_state;
682 unsigned int count, c;
684 void __iomem *base = cs->base;
685 void __iomem *tx_reg;
686 void __iomem *rx_reg;
687 void __iomem *chstat_reg;
690 mcspi = spi_master_get_devdata(spi->master);
693 word_len = cs->word_len;
695 l = mcspi_cached_chconf0(spi);
697 /* We store the pre-calculated register addresses on stack to speed
698 * up the transfer loop. */
699 tx_reg = base + OMAP2_MCSPI_TX0;
700 rx_reg = base + OMAP2_MCSPI_RX0;
701 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
703 if (c < (word_len>>3))
716 if (mcspi_wait_for_reg_bit(chstat_reg,
717 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
718 dev_err(&spi->dev, "TXS timed out\n");
721 dev_vdbg(&spi->dev, "write-%d %02x\n",
723 writel_relaxed(*tx++, tx_reg);
726 if (mcspi_wait_for_reg_bit(chstat_reg,
727 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
728 dev_err(&spi->dev, "RXS timed out\n");
732 if (c == 1 && tx == NULL &&
733 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
734 omap2_mcspi_set_enable(spi, 0);
735 *rx++ = readl_relaxed(rx_reg);
736 dev_vdbg(&spi->dev, "read-%d %02x\n",
737 word_len, *(rx - 1));
738 if (mcspi_wait_for_reg_bit(chstat_reg,
739 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
745 } else if (c == 0 && tx == NULL) {
746 omap2_mcspi_set_enable(spi, 0);
749 *rx++ = readl_relaxed(rx_reg);
750 dev_vdbg(&spi->dev, "read-%d %02x\n",
751 word_len, *(rx - 1));
754 } else if (word_len <= 16) {
763 if (mcspi_wait_for_reg_bit(chstat_reg,
764 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
765 dev_err(&spi->dev, "TXS timed out\n");
768 dev_vdbg(&spi->dev, "write-%d %04x\n",
770 writel_relaxed(*tx++, tx_reg);
773 if (mcspi_wait_for_reg_bit(chstat_reg,
774 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
775 dev_err(&spi->dev, "RXS timed out\n");
779 if (c == 2 && tx == NULL &&
780 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
781 omap2_mcspi_set_enable(spi, 0);
782 *rx++ = readl_relaxed(rx_reg);
783 dev_vdbg(&spi->dev, "read-%d %04x\n",
784 word_len, *(rx - 1));
785 if (mcspi_wait_for_reg_bit(chstat_reg,
786 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
792 } else if (c == 0 && tx == NULL) {
793 omap2_mcspi_set_enable(spi, 0);
796 *rx++ = readl_relaxed(rx_reg);
797 dev_vdbg(&spi->dev, "read-%d %04x\n",
798 word_len, *(rx - 1));
801 } else if (word_len <= 32) {
810 if (mcspi_wait_for_reg_bit(chstat_reg,
811 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
812 dev_err(&spi->dev, "TXS timed out\n");
815 dev_vdbg(&spi->dev, "write-%d %08x\n",
817 writel_relaxed(*tx++, tx_reg);
820 if (mcspi_wait_for_reg_bit(chstat_reg,
821 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
822 dev_err(&spi->dev, "RXS timed out\n");
826 if (c == 4 && tx == NULL &&
827 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
828 omap2_mcspi_set_enable(spi, 0);
829 *rx++ = readl_relaxed(rx_reg);
830 dev_vdbg(&spi->dev, "read-%d %08x\n",
831 word_len, *(rx - 1));
832 if (mcspi_wait_for_reg_bit(chstat_reg,
833 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
839 } else if (c == 0 && tx == NULL) {
840 omap2_mcspi_set_enable(spi, 0);
843 *rx++ = readl_relaxed(rx_reg);
844 dev_vdbg(&spi->dev, "read-%d %08x\n",
845 word_len, *(rx - 1));
850 /* for TX_ONLY mode, be sure all words have shifted out */
851 if (xfer->rx_buf == NULL) {
852 if (mcspi_wait_for_reg_bit(chstat_reg,
853 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
854 dev_err(&spi->dev, "TXS timed out\n");
855 } else if (mcspi_wait_for_reg_bit(chstat_reg,
856 OMAP2_MCSPI_CHSTAT_EOT) < 0)
857 dev_err(&spi->dev, "EOT timed out\n");
859 /* disable chan to purge rx datas received in TX_ONLY transfer,
860 * otherwise these rx datas will affect the direct following
863 omap2_mcspi_set_enable(spi, 0);
866 omap2_mcspi_set_enable(spi, 1);
870 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
874 for (div = 0; div < 15; div++)
875 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
881 /* called only when no transfer is active to this device */
882 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
883 struct spi_transfer *t)
885 struct omap2_mcspi_cs *cs = spi->controller_state;
886 struct omap2_mcspi *mcspi;
887 struct spi_master *spi_cntrl;
888 u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0;
889 u8 word_len = spi->bits_per_word;
890 u32 speed_hz = spi->max_speed_hz;
892 mcspi = spi_master_get_devdata(spi->master);
893 spi_cntrl = mcspi->master;
895 if (t != NULL && t->bits_per_word)
896 word_len = t->bits_per_word;
898 cs->word_len = word_len;
900 if (t && t->speed_hz)
901 speed_hz = t->speed_hz;
903 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
904 if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) {
905 clkd = omap2_mcspi_calc_divisor(speed_hz);
906 speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd;
909 div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz;
910 speed_hz = OMAP2_MCSPI_MAX_FREQ / div;
911 clkd = (div - 1) & 0xf;
912 extclk = (div - 1) >> 4;
913 clkg = OMAP2_MCSPI_CHCONF_CLKG;
916 l = mcspi_cached_chconf0(spi);
918 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
919 * REVISIT: this controller could support SPI_3WIRE mode.
921 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
922 l &= ~OMAP2_MCSPI_CHCONF_IS;
923 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
924 l |= OMAP2_MCSPI_CHCONF_DPE0;
926 l |= OMAP2_MCSPI_CHCONF_IS;
927 l |= OMAP2_MCSPI_CHCONF_DPE1;
928 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
932 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
933 l |= (word_len - 1) << 7;
935 /* set chipselect polarity; manage with FORCE */
936 if (!(spi->mode & SPI_CS_HIGH))
937 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
939 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
941 /* set clock divisor */
942 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
945 /* set clock granularity */
946 l &= ~OMAP2_MCSPI_CHCONF_CLKG;
949 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
950 cs->chctrl0 |= extclk << 8;
951 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
954 /* set SPI mode 0..3 */
955 if (spi->mode & SPI_CPOL)
956 l |= OMAP2_MCSPI_CHCONF_POL;
958 l &= ~OMAP2_MCSPI_CHCONF_POL;
959 if (spi->mode & SPI_CPHA)
960 l |= OMAP2_MCSPI_CHCONF_PHA;
962 l &= ~OMAP2_MCSPI_CHCONF_PHA;
964 mcspi_write_chconf0(spi, l);
966 cs->mode = spi->mode;
968 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
970 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
971 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
977 * Note that we currently allow DMA only if we get a channel
978 * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
980 static int omap2_mcspi_request_dma(struct spi_device *spi)
982 struct spi_master *master = spi->master;
983 struct omap2_mcspi *mcspi;
984 struct omap2_mcspi_dma *mcspi_dma;
987 mcspi = spi_master_get_devdata(master);
988 mcspi_dma = mcspi->dma_channels + spi->chip_select;
990 init_completion(&mcspi_dma->dma_rx_completion);
991 init_completion(&mcspi_dma->dma_tx_completion);
993 mcspi_dma->dma_rx = dma_request_chan(&master->dev,
994 mcspi_dma->dma_rx_ch_name);
995 if (IS_ERR(mcspi_dma->dma_rx)) {
996 ret = PTR_ERR(mcspi_dma->dma_rx);
997 mcspi_dma->dma_rx = NULL;
1001 mcspi_dma->dma_tx = dma_request_chan(&master->dev,
1002 mcspi_dma->dma_tx_ch_name);
1003 if (IS_ERR(mcspi_dma->dma_tx)) {
1004 ret = PTR_ERR(mcspi_dma->dma_tx);
1005 mcspi_dma->dma_tx = NULL;
1006 dma_release_channel(mcspi_dma->dma_rx);
1007 mcspi_dma->dma_rx = NULL;
1014 static int omap2_mcspi_setup(struct spi_device *spi)
1017 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
1018 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1019 struct omap2_mcspi_dma *mcspi_dma;
1020 struct omap2_mcspi_cs *cs = spi->controller_state;
1022 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1025 cs = kzalloc(sizeof *cs, GFP_KERNEL);
1028 cs->base = mcspi->base + spi->chip_select * 0x14;
1029 cs->phys = mcspi->phys + spi->chip_select * 0x14;
1033 spi->controller_state = cs;
1034 /* Link this to context save list */
1035 list_add_tail(&cs->node, &ctx->cs);
1037 if (gpio_is_valid(spi->cs_gpio)) {
1038 ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
1040 dev_err(&spi->dev, "failed to request gpio\n");
1043 gpio_direction_output(spi->cs_gpio,
1044 !(spi->mode & SPI_CS_HIGH));
1048 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
1049 ret = omap2_mcspi_request_dma(spi);
1051 dev_warn(&spi->dev, "not using DMA for McSPI (%d)\n",
1055 ret = pm_runtime_get_sync(mcspi->dev);
1059 ret = omap2_mcspi_setup_transfer(spi, NULL);
1060 pm_runtime_mark_last_busy(mcspi->dev);
1061 pm_runtime_put_autosuspend(mcspi->dev);
1066 static void omap2_mcspi_cleanup(struct spi_device *spi)
1068 struct omap2_mcspi *mcspi;
1069 struct omap2_mcspi_dma *mcspi_dma;
1070 struct omap2_mcspi_cs *cs;
1072 mcspi = spi_master_get_devdata(spi->master);
1074 if (spi->controller_state) {
1075 /* Unlink controller state from context save list */
1076 cs = spi->controller_state;
1077 list_del(&cs->node);
1082 if (spi->chip_select < spi->master->num_chipselect) {
1083 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1085 if (mcspi_dma->dma_rx) {
1086 dma_release_channel(mcspi_dma->dma_rx);
1087 mcspi_dma->dma_rx = NULL;
1089 if (mcspi_dma->dma_tx) {
1090 dma_release_channel(mcspi_dma->dma_tx);
1091 mcspi_dma->dma_tx = NULL;
1095 if (gpio_is_valid(spi->cs_gpio))
1096 gpio_free(spi->cs_gpio);
1099 static int omap2_mcspi_transfer_one(struct spi_master *master,
1100 struct spi_device *spi,
1101 struct spi_transfer *t)
1104 /* We only enable one channel at a time -- the one whose message is
1105 * -- although this controller would gladly
1106 * arbitrate among multiple channels. This corresponds to "single
1107 * channel" master mode. As a side effect, we need to manage the
1108 * chipselect with the FORCE bit ... CS != channel enable.
1111 struct omap2_mcspi *mcspi;
1112 struct omap2_mcspi_dma *mcspi_dma;
1113 struct omap2_mcspi_cs *cs;
1114 struct omap2_mcspi_device_config *cd;
1115 int par_override = 0;
1119 mcspi = spi_master_get_devdata(master);
1120 mcspi_dma = mcspi->dma_channels + spi->chip_select;
1121 cs = spi->controller_state;
1122 cd = spi->controller_data;
1125 * The slave driver could have changed spi->mode in which case
1126 * it will be different from cs->mode (the current hardware setup).
1127 * If so, set par_override (even though its not a parity issue) so
1128 * omap2_mcspi_setup_transfer will be called to configure the hardware
1129 * with the correct mode on the first iteration of the loop below.
1131 if (spi->mode != cs->mode)
1134 omap2_mcspi_set_enable(spi, 0);
1136 if (gpio_is_valid(spi->cs_gpio))
1137 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);
1140 (t->speed_hz != spi->max_speed_hz) ||
1141 (t->bits_per_word != spi->bits_per_word)) {
1143 status = omap2_mcspi_setup_transfer(spi, t);
1146 if (t->speed_hz == spi->max_speed_hz &&
1147 t->bits_per_word == spi->bits_per_word)
1150 if (cd && cd->cs_per_word) {
1151 chconf = mcspi->ctx.modulctrl;
1152 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
1153 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1154 mcspi->ctx.modulctrl =
1155 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1158 chconf = mcspi_cached_chconf0(spi);
1159 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
1160 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
1162 if (t->tx_buf == NULL)
1163 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
1164 else if (t->rx_buf == NULL)
1165 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
1167 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
1168 /* Turbo mode is for more than one word */
1169 if (t->len > ((cs->word_len + 7) >> 3))
1170 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
1173 mcspi_write_chconf0(spi, chconf);
1178 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1179 master->cur_msg_mapped &&
1180 master->can_dma(master, spi, t))
1181 omap2_mcspi_set_fifo(spi, t, 1);
1183 omap2_mcspi_set_enable(spi, 1);
1185 /* RX_ONLY mode needs dummy data in TX reg */
1186 if (t->tx_buf == NULL)
1187 writel_relaxed(0, cs->base
1190 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1191 master->cur_msg_mapped &&
1192 master->can_dma(master, spi, t))
1193 count = omap2_mcspi_txrx_dma(spi, t);
1195 count = omap2_mcspi_txrx_pio(spi, t);
1197 if (count != t->len) {
1203 omap2_mcspi_set_enable(spi, 0);
1205 if (mcspi->fifo_depth > 0)
1206 omap2_mcspi_set_fifo(spi, t, 0);
1209 /* Restore defaults if they were overriden */
1212 status = omap2_mcspi_setup_transfer(spi, NULL);
1215 if (cd && cd->cs_per_word) {
1216 chconf = mcspi->ctx.modulctrl;
1217 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1218 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1219 mcspi->ctx.modulctrl =
1220 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1223 omap2_mcspi_set_enable(spi, 0);
1225 if (gpio_is_valid(spi->cs_gpio))
1226 omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));
1228 if (mcspi->fifo_depth > 0 && t)
1229 omap2_mcspi_set_fifo(spi, t, 0);
1234 static int omap2_mcspi_prepare_message(struct spi_master *master,
1235 struct spi_message *msg)
1237 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1238 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1239 struct omap2_mcspi_cs *cs;
1241 /* Only a single channel can have the FORCE bit enabled
1242 * in its chconf0 register.
1243 * Scan all channels and disable them except the current one.
1244 * A FORCE can remain from a last transfer having cs_change enabled
1246 list_for_each_entry(cs, &ctx->cs, node) {
1247 if (msg->spi->controller_state == cs)
1250 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) {
1251 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1252 writel_relaxed(cs->chconf0,
1253 cs->base + OMAP2_MCSPI_CHCONF0);
1254 readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0);
1261 static bool omap2_mcspi_can_dma(struct spi_master *master,
1262 struct spi_device *spi,
1263 struct spi_transfer *xfer)
1265 return (xfer->len >= DMA_MIN_BYTES);
1268 static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1270 struct spi_master *master = mcspi->master;
1271 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1274 ret = pm_runtime_get_sync(mcspi->dev);
1278 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1279 OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1280 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1282 omap2_mcspi_set_master_mode(master);
1283 pm_runtime_mark_last_busy(mcspi->dev);
1284 pm_runtime_put_autosuspend(mcspi->dev);
1288 static int omap_mcspi_runtime_resume(struct device *dev)
1290 struct omap2_mcspi *mcspi;
1291 struct spi_master *master;
1293 master = dev_get_drvdata(dev);
1294 mcspi = spi_master_get_devdata(master);
1295 omap2_mcspi_restore_ctx(mcspi);
1300 static struct omap2_mcspi_platform_config omap2_pdata = {
1304 static struct omap2_mcspi_platform_config omap4_pdata = {
1305 .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1308 static const struct of_device_id omap_mcspi_of_match[] = {
1310 .compatible = "ti,omap2-mcspi",
1311 .data = &omap2_pdata,
1314 .compatible = "ti,omap4-mcspi",
1315 .data = &omap4_pdata,
1319 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1321 static int omap2_mcspi_probe(struct platform_device *pdev)
1323 struct spi_master *master;
1324 const struct omap2_mcspi_platform_config *pdata;
1325 struct omap2_mcspi *mcspi;
1328 u32 regs_offset = 0;
1329 static int bus_num = 1;
1330 struct device_node *node = pdev->dev.of_node;
1331 const struct of_device_id *match;
1333 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1334 if (master == NULL) {
1335 dev_dbg(&pdev->dev, "master allocation failed\n");
1339 /* the spi->mode bits understood by this driver: */
1340 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1341 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1342 master->setup = omap2_mcspi_setup;
1343 master->auto_runtime_pm = true;
1344 master->prepare_message = omap2_mcspi_prepare_message;
1345 master->can_dma = omap2_mcspi_can_dma;
1346 master->transfer_one = omap2_mcspi_transfer_one;
1347 master->set_cs = omap2_mcspi_set_cs;
1348 master->cleanup = omap2_mcspi_cleanup;
1349 master->dev.of_node = node;
1350 master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
1351 master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
1353 platform_set_drvdata(pdev, master);
1355 mcspi = spi_master_get_devdata(master);
1356 mcspi->master = master;
1358 match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1360 u32 num_cs = 1; /* default number of chipselect */
1361 pdata = match->data;
1363 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1364 master->num_chipselect = num_cs;
1365 master->bus_num = bus_num++;
1366 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1367 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1369 pdata = dev_get_platdata(&pdev->dev);
1370 master->num_chipselect = pdata->num_cs;
1372 master->bus_num = pdev->id;
1373 mcspi->pin_dir = pdata->pin_dir;
1375 regs_offset = pdata->regs_offset;
1377 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1383 r->start += regs_offset;
1384 r->end += regs_offset;
1385 mcspi->phys = r->start;
1387 mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1388 if (IS_ERR(mcspi->base)) {
1389 status = PTR_ERR(mcspi->base);
1393 mcspi->dev = &pdev->dev;
1395 INIT_LIST_HEAD(&mcspi->ctx.cs);
1397 mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect,
1398 sizeof(struct omap2_mcspi_dma),
1400 if (mcspi->dma_channels == NULL) {
1405 for (i = 0; i < master->num_chipselect; i++) {
1406 sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i);
1407 sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i);
1413 pm_runtime_use_autosuspend(&pdev->dev);
1414 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1415 pm_runtime_enable(&pdev->dev);
1417 status = omap2_mcspi_master_setup(mcspi);
1421 status = devm_spi_register_master(&pdev->dev, master);
1428 pm_runtime_dont_use_autosuspend(&pdev->dev);
1429 pm_runtime_put_sync(&pdev->dev);
1430 pm_runtime_disable(&pdev->dev);
1432 spi_master_put(master);
1436 static int omap2_mcspi_remove(struct platform_device *pdev)
1438 struct spi_master *master = platform_get_drvdata(pdev);
1439 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1441 pm_runtime_dont_use_autosuspend(mcspi->dev);
1442 pm_runtime_put_sync(mcspi->dev);
1443 pm_runtime_disable(&pdev->dev);
1448 /* work with hotplug and coldplug */
1449 MODULE_ALIAS("platform:omap2_mcspi");
1451 #ifdef CONFIG_SUSPEND
1453 * When SPI wake up from off-mode, CS is in activate state. If it was in
1454 * unactive state when driver was suspend, then force it to unactive state at
1457 static int omap2_mcspi_resume(struct device *dev)
1459 struct spi_master *master = dev_get_drvdata(dev);
1460 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1461 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1462 struct omap2_mcspi_cs *cs;
1464 pm_runtime_get_sync(mcspi->dev);
1465 list_for_each_entry(cs, &ctx->cs, node) {
1466 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1468 * We need to toggle CS state for OMAP take this
1469 * change in account.
1471 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1472 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1473 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1474 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1477 pm_runtime_mark_last_busy(mcspi->dev);
1478 pm_runtime_put_autosuspend(mcspi->dev);
1480 return pinctrl_pm_select_default_state(dev);
1483 static int omap2_mcspi_suspend(struct device *dev)
1485 return pinctrl_pm_select_sleep_state(dev);
1489 #define omap2_mcspi_suspend NULL
1490 #define omap2_mcspi_resume NULL
1493 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1494 .resume = omap2_mcspi_resume,
1495 .suspend = omap2_mcspi_suspend,
1496 .runtime_resume = omap_mcspi_runtime_resume,
1499 static struct platform_driver omap2_mcspi_driver = {
1501 .name = "omap2_mcspi",
1502 .pm = &omap2_mcspi_pm_ops,
1503 .of_match_table = omap_mcspi_of_match,
1505 .probe = omap2_mcspi_probe,
1506 .remove = omap2_mcspi_remove,
1509 module_platform_driver(omap2_mcspi_driver);
1510 MODULE_LICENSE("GPL");