drivers/spi/spi-omap2-mcspi.c

   1 /*
   2  * OMAP2 McSPI controller driver
   3  *
   4  * Copyright (C) 2005, 2006 Nokia Corporation
   5  * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
   6  *              Juha Yrj�l� <juha.yrjola@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/module.h>
  22 #include <linux/device.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/dmaengine.h>
  26 #include <linux/pinctrl/consumer.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/err.h>
  29 #include <linux/clk.h>
  30 #include <linux/io.h>
  31 #include <linux/slab.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/of.h>
  34 #include <linux/of_device.h>
  35 #include <linux/gcd.h>
  36
  37 #include <linux/spi/spi.h>
  38 #include <linux/gpio.h>
  39
  40 #include <linux/platform_data/spi-omap2-mcspi.h>
  41
  42 #define OMAP2_MCSPI_MAX_FREQ            48000000
  43 #define OMAP2_MCSPI_MAX_DIVIDER         4096
  44 #define OMAP2_MCSPI_MAX_FIFODEPTH       64
  45 #define OMAP2_MCSPI_MAX_FIFOWCNT        0xFFFF
  46 #define SPI_AUTOSUSPEND_TIMEOUT         2000
  47
  48 #define OMAP2_MCSPI_REVISION            0x00
  49 #define OMAP2_MCSPI_SYSSTATUS           0x14
  50 #define OMAP2_MCSPI_IRQSTATUS           0x18
  51 #define OMAP2_MCSPI_IRQENABLE           0x1c
  52 #define OMAP2_MCSPI_WAKEUPENABLE        0x20
  53 #define OMAP2_MCSPI_SYST                0x24
  54 #define OMAP2_MCSPI_MODULCTRL           0x28
  55 #define OMAP2_MCSPI_XFERLEVEL           0x7c
  56
  57 /* per-channel banks, 0x14 bytes each, first is: */
  58 #define OMAP2_MCSPI_CHCONF0             0x2c
  59 #define OMAP2_MCSPI_CHSTAT0             0x30
  60 #define OMAP2_MCSPI_CHCTRL0             0x34
  61 #define OMAP2_MCSPI_TX0                 0x38
  62 #define OMAP2_MCSPI_RX0                 0x3c
  63
  64 /* per-register bitmasks: */
  65 #define OMAP2_MCSPI_IRQSTATUS_EOW       BIT(17)
  66
  67 #define OMAP2_MCSPI_MODULCTRL_SINGLE    BIT(0)
  68 #define OMAP2_MCSPI_MODULCTRL_MS        BIT(2)
  69 #define OMAP2_MCSPI_MODULCTRL_STEST     BIT(3)
  70
  71 #define OMAP2_MCSPI_CHCONF_PHA          BIT(0)
  72 #define OMAP2_MCSPI_CHCONF_POL          BIT(1)
  73 #define OMAP2_MCSPI_CHCONF_CLKD_MASK    (0x0f << 2)
  74 #define OMAP2_MCSPI_CHCONF_EPOL         BIT(6)
  75 #define OMAP2_MCSPI_CHCONF_WL_MASK      (0x1f << 7)
  76 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY  BIT(12)
  77 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY  BIT(13)
  78 #define OMAP2_MCSPI_CHCONF_TRM_MASK     (0x03 << 12)
  79 #define OMAP2_MCSPI_CHCONF_DMAW         BIT(14)
  80 #define OMAP2_MCSPI_CHCONF_DMAR         BIT(15)
  81 #define OMAP2_MCSPI_CHCONF_DPE0         BIT(16)
  82 #define OMAP2_MCSPI_CHCONF_DPE1         BIT(17)
  83 #define OMAP2_MCSPI_CHCONF_IS           BIT(18)
  84 #define OMAP2_MCSPI_CHCONF_TURBO        BIT(19)
  85 #define OMAP2_MCSPI_CHCONF_FORCE        BIT(20)
  86 #define OMAP2_MCSPI_CHCONF_FFET         BIT(27)
  87 #define OMAP2_MCSPI_CHCONF_FFER         BIT(28)
  88 #define OMAP2_MCSPI_CHCONF_CLKG         BIT(29)
  89
  90 #define OMAP2_MCSPI_CHSTAT_RXS          BIT(0)
  91 #define OMAP2_MCSPI_CHSTAT_TXS          BIT(1)
  92 #define OMAP2_MCSPI_CHSTAT_EOT          BIT(2)
  93 #define OMAP2_MCSPI_CHSTAT_TXFFE        BIT(3)
  94
  95 #define OMAP2_MCSPI_CHCTRL_EN           BIT(0)
  96 #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK  (0xff << 8)
  97
  98 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN   BIT(0)
  99
 100 /* We have 2 DMA channels per CS, one for RX and one for TX */
 101 struct omap2_mcspi_dma {
 102         struct dma_chan *dma_tx;
 103         struct dma_chan *dma_rx;
 104
 105         struct completion dma_tx_completion;
 106         struct completion dma_rx_completion;
 107
 108         char dma_rx_ch_name[14];
 109         char dma_tx_ch_name[14];
 110 };
 111
 112 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 113  * cache operations; better heuristics consider wordsize and bitrate.
 114  */
 115 #define DMA_MIN_BYTES                   160
 116
 117
 118 /*
 119  * Used for context save and restore, structure members to be updated whenever
 120  * corresponding registers are modified.
 121  */
 122 struct omap2_mcspi_regs {
 123         u32 modulctrl;
 124         u32 wakeupenable;
 125         struct list_head cs;
 126 };
 127
 128 struct omap2_mcspi {
 129         struct spi_master       *master;
 130         /* Virtual base address of the controller */
 131         void __iomem            *base;
 132         unsigned long           phys;
 133         /* SPI1 has 4 channels, while SPI2 has 2 */
 134         struct omap2_mcspi_dma  *dma_channels;
 135         struct device           *dev;
 136         struct omap2_mcspi_regs ctx;
 137         int                     fifo_depth;
 138         unsigned int            pin_dir:1;
 139 };
 140
 141 struct omap2_mcspi_cs {
 142         void __iomem            *base;
 143         unsigned long           phys;
 144         int                     word_len;
 145         u16                     mode;
 146         struct list_head        node;
 147         /* Context save and restore shadow register */
 148         u32                     chconf0, chctrl0;
 149 };
 150
 151 static inline void mcspi_write_reg(struct spi_master *master,
 152                 int idx, u32 val)
 153 {
 154         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 155
 156         writel_relaxed(val, mcspi->base + idx);
 157 }
 158
 159 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
 160 {
 161         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 162
 163         return readl_relaxed(mcspi->base + idx);
 164 }
 165
 166 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
 167                 int idx, u32 val)
 168 {
 169         struct omap2_mcspi_cs   *cs = spi->controller_state;
 170
 171         writel_relaxed(val, cs->base +  idx);
 172 }
 173
 174 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
 175 {
 176         struct omap2_mcspi_cs   *cs = spi->controller_state;
 177
 178         return readl_relaxed(cs->base + idx);
 179 }
 180
 181 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
 182 {
 183         struct omap2_mcspi_cs *cs = spi->controller_state;
 184
 185         return cs->chconf0;
 186 }
 187
 188 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
 189 {
 190         struct omap2_mcspi_cs *cs = spi->controller_state;
 191
 192         cs->chconf0 = val;
 193         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
 194         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 195 }
 196
 197 static inline int mcspi_bytes_per_word(int word_len)
 198 {
 199         if (word_len <= 8)
 200                 return 1;
 201         else if (word_len <= 16)
 202                 return 2;
 203         else /* word_len <= 32 */
 204                 return 4;
 205 }
 206
 207 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
 208                 int is_read, int enable)
 209 {
 210         u32 l, rw;
 211
 212         l = mcspi_cached_chconf0(spi);
 213
 214         if (is_read) /* 1 is read, 0 write */
 215                 rw = OMAP2_MCSPI_CHCONF_DMAR;
 216         else
 217                 rw = OMAP2_MCSPI_CHCONF_DMAW;
 218
 219         if (enable)
 220                 l |= rw;
 221         else
 222                 l &= ~rw;
 223
 224         mcspi_write_chconf0(spi, l);
 225 }
 226
 227 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
 228 {
 229         struct omap2_mcspi_cs *cs = spi->controller_state;
 230         u32 l;
 231
 232         l = cs->chctrl0;
 233         if (enable)
 234                 l |= OMAP2_MCSPI_CHCTRL_EN;
 235         else
 236                 l &= ~OMAP2_MCSPI_CHCTRL_EN;
 237         cs->chctrl0 = l;
 238         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
 239         /* Flash post-writes */
 240         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
 241 }
 242
 243 static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable)
 244 {
 245         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 246         u32 l;
 247
 248         /* The controller handles the inverted chip selects
 249          * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert
 250          * the inversion from the core spi_set_cs function.
 251          */
 252         if (spi->mode & SPI_CS_HIGH)
 253                 enable = !enable;
 254
 255         if (spi->controller_state) {
 256                 int err = pm_runtime_get_sync(mcspi->dev);
 257                 if (err < 0) {
 258                         dev_err(mcspi->dev, "failed to get sync: %d\n", err);
 259                         return;
 260                 }
 261
 262                 l = mcspi_cached_chconf0(spi);
 263
 264                 if (enable)
 265                         l &= ~OMAP2_MCSPI_CHCONF_FORCE;
 266                 else
 267                         l |= OMAP2_MCSPI_CHCONF_FORCE;
 268
 269                 mcspi_write_chconf0(spi, l);
 270
 271                 pm_runtime_mark_last_busy(mcspi->dev);
 272                 pm_runtime_put_autosuspend(mcspi->dev);
 273         }
 274 }
 275
 276 static void omap2_mcspi_set_master_mode(struct spi_master *master)
 277 {
 278         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
 279         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 280         u32 l;
 281
 282         /*
 283          * Setup when switching from (reset default) slave mode
 284          * to single-channel master mode
 285          */
 286         l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
 287         l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
 288         l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
 289         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
 290
 291         ctx->modulctrl = l;
 292 }
 293
 294 static void omap2_mcspi_set_fifo(const struct spi_device *spi,
 295                                 struct spi_transfer *t, int enable)
 296 {
 297         struct spi_master *master = spi->master;
 298         struct omap2_mcspi_cs *cs = spi->controller_state;
 299         struct omap2_mcspi *mcspi;
 300         unsigned int wcnt;
 301         int max_fifo_depth, bytes_per_word;
 302         u32 chconf, xferlevel;
 303
 304         mcspi = spi_master_get_devdata(master);
 305
 306         chconf = mcspi_cached_chconf0(spi);
 307         if (enable) {
 308                 bytes_per_word = mcspi_bytes_per_word(cs->word_len);
 309                 if (t->len % bytes_per_word != 0)
 310                         goto disable_fifo;
 311
 312                 if (t->rx_buf != NULL && t->tx_buf != NULL)
 313                         max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2;
 314                 else
 315                         max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH;
 316
 317                 wcnt = t->len / bytes_per_word;
 318                 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
 319                         goto disable_fifo;
 320
 321                 xferlevel = wcnt << 16;
 322                 if (t->rx_buf != NULL) {
 323                         chconf |= OMAP2_MCSPI_CHCONF_FFER;
 324                         xferlevel |= (bytes_per_word - 1) << 8;
 325                 }
 326
 327                 if (t->tx_buf != NULL) {
 328                         chconf |= OMAP2_MCSPI_CHCONF_FFET;
 329                         xferlevel |= bytes_per_word - 1;
 330                 }
 331
 332                 mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
 333                 mcspi_write_chconf0(spi, chconf);
 334                 mcspi->fifo_depth = max_fifo_depth;
 335
 336                 return;
 337         }
 338
 339 disable_fifo:
 340         if (t->rx_buf != NULL)
 341                 chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
 342
 343         if (t->tx_buf != NULL)
 344                 chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
 345
 346         mcspi_write_chconf0(spi, chconf);
 347         mcspi->fifo_depth = 0;
 348 }
 349
 350 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
 351 {
 352         struct spi_master       *spi_cntrl = mcspi->master;
 353         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 354         struct omap2_mcspi_cs   *cs;
 355
 356         /* McSPI: context restore */
 357         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
 358         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
 359
 360         list_for_each_entry(cs, &ctx->cs, node)
 361                 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
 362 }
 363
 364 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
 365 {
 366         unsigned long timeout;
 367
 368         timeout = jiffies + msecs_to_jiffies(1000);
 369         while (!(readl_relaxed(reg) & bit)) {
 370                 if (time_after(jiffies, timeout)) {
 371                         if (!(readl_relaxed(reg) & bit))
 372                                 return -ETIMEDOUT;
 373                         else
 374                                 return 0;
 375                 }
 376                 cpu_relax();
 377         }
 378         return 0;
 379 }
 380
 381 static void omap2_mcspi_rx_callback(void *data)
 382 {
 383         struct spi_device *spi = data;
 384         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 385         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 386
 387         /* We must disable the DMA RX request */
 388         omap2_mcspi_set_dma_req(spi, 1, 0);
 389
 390         complete(&mcspi_dma->dma_rx_completion);
 391 }
 392
 393 static void omap2_mcspi_tx_callback(void *data)
 394 {
 395         struct spi_device *spi = data;
 396         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 397         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 398
 399         /* We must disable the DMA TX request */
 400         omap2_mcspi_set_dma_req(spi, 0, 0);
 401
 402         complete(&mcspi_dma->dma_tx_completion);
 403 }
 404
 405 static void omap2_mcspi_tx_dma(struct spi_device *spi,
 406                                 struct spi_transfer *xfer,
 407                                 struct dma_slave_config cfg)
 408 {
 409         struct omap2_mcspi      *mcspi;
 410         struct omap2_mcspi_dma  *mcspi_dma;
 411         unsigned int            count;
 412
 413         mcspi = spi_master_get_devdata(spi->master);
 414         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 415         count = xfer->len;
 416
 417         if (mcspi_dma->dma_tx) {
 418                 struct dma_async_tx_descriptor *tx;
 419
 420                 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
 421
 422                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl,
 423                                              xfer->tx_sg.nents,
 424                                              DMA_MEM_TO_DEV,
 425                                              DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 426                 if (tx) {
 427                         tx->callback = omap2_mcspi_tx_callback;
 428                         tx->callback_param = spi;
 429                         dmaengine_submit(tx);
 430                 } else {
 431                         /* FIXME: fall back to PIO? */
 432                 }
 433         }
 434         dma_async_issue_pending(mcspi_dma->dma_tx);
 435         omap2_mcspi_set_dma_req(spi, 0, 1);
 436
 437 }
 438
 439 static unsigned
 440 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
 441                                 struct dma_slave_config cfg,
 442                                 unsigned es)
 443 {
 444         struct omap2_mcspi      *mcspi;
 445         struct omap2_mcspi_dma  *mcspi_dma;
 446         unsigned int            count, transfer_reduction = 0;
 447         struct scatterlist      *sg_out[2];
 448         int                     nb_sizes = 0, out_mapped_nents[2], ret, x;
 449         size_t                  sizes[2];
 450         u32                     l;
 451         int                     elements = 0;
 452         int                     word_len, element_count;
 453         struct omap2_mcspi_cs   *cs = spi->controller_state;
 454         void __iomem            *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
 455
 456         mcspi = spi_master_get_devdata(spi->master);
 457         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 458         count = xfer->len;
 459
 460         /*
 461          *  In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM
 462          *  it mentions reducing DMA transfer length by one element in master
 463          *  normal mode.
 464          */
 465         if (mcspi->fifo_depth == 0)
 466                 transfer_reduction = es;
 467
 468         word_len = cs->word_len;
 469         l = mcspi_cached_chconf0(spi);
 470
 471         if (word_len <= 8)
 472                 element_count = count;
 473         else if (word_len <= 16)
 474                 element_count = count >> 1;
 475         else /* word_len <= 32 */
 476                 element_count = count >> 2;
 477
 478         if (mcspi_dma->dma_rx) {
 479                 struct dma_async_tx_descriptor *tx;
 480
 481                 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
 482
 483                 /*
 484                  *  Reduce DMA transfer length by one more if McSPI is
 485                  *  configured in turbo mode.
 486                  */
 487                 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
 488                         transfer_reduction += es;
 489
 490                 if (transfer_reduction) {
 491                         /* Split sgl into two. The second sgl won't be used. */
 492                         sizes[0] = count - transfer_reduction;
 493                         sizes[1] = transfer_reduction;
 494                         nb_sizes = 2;
 495                 } else {
 496                         /*
 497                          * Don't bother splitting the sgl. This essentially
 498                          * clones the original sgl.
 499                          */
 500                         sizes[0] = count;
 501                         nb_sizes = 1;
 502                 }
 503
 504                 ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents,
 505                                0, nb_sizes,
 506                                sizes,
 507                                sg_out, out_mapped_nents,
 508                                GFP_KERNEL);
 509
 510                 if (ret < 0) {
 511                         dev_err(&spi->dev, "sg_split failed\n");
 512                         return 0;
 513                 }
 514
 515                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx,
 516                                              sg_out[0],
 517                                              out_mapped_nents[0],
 518                                              DMA_DEV_TO_MEM,
 519                                              DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 520                 if (tx) {
 521                         tx->callback = omap2_mcspi_rx_callback;
 522                         tx->callback_param = spi;
 523                         dmaengine_submit(tx);
 524                 } else {
 525                                 /* FIXME: fall back to PIO? */
 526                 }
 527         }
 528
 529         dma_async_issue_pending(mcspi_dma->dma_rx);
 530         omap2_mcspi_set_dma_req(spi, 1, 1);
 531
 532         wait_for_completion(&mcspi_dma->dma_rx_completion);
 533
 534         for (x = 0; x < nb_sizes; x++)
 535                 kfree(sg_out[x]);
 536
 537         if (mcspi->fifo_depth > 0)
 538                 return count;
 539
 540         /*
 541          *  Due to the DMA transfer length reduction the missing bytes must
 542          *  be read manually to receive all of the expected data.
 543          */
 544         omap2_mcspi_set_enable(spi, 0);
 545
 546         elements = element_count - 1;
 547
 548         if (l & OMAP2_MCSPI_CHCONF_TURBO) {
 549                 elements--;
 550
 551                 if (!mcspi_wait_for_reg_bit(chstat_reg,
 552                                             OMAP2_MCSPI_CHSTAT_RXS)) {
 553                         u32 w;
 554
 555                         w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 556                         if (word_len <= 8)
 557                                 ((u8 *)xfer->rx_buf)[elements++] = w;
 558                         else if (word_len <= 16)
 559                                 ((u16 *)xfer->rx_buf)[elements++] = w;
 560                         else /* word_len <= 32 */
 561                                 ((u32 *)xfer->rx_buf)[elements++] = w;
 562                 } else {
 563                         int bytes_per_word = mcspi_bytes_per_word(word_len);
 564                         dev_err(&spi->dev, "DMA RX penultimate word empty\n");
 565                         count -= (bytes_per_word << 1);
 566                         omap2_mcspi_set_enable(spi, 1);
 567                         return count;
 568                 }
 569         }
 570         if (!mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_RXS)) {
 571                 u32 w;
 572
 573                 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 574                 if (word_len <= 8)
 575                         ((u8 *)xfer->rx_buf)[elements] = w;
 576                 else if (word_len <= 16)
 577                         ((u16 *)xfer->rx_buf)[elements] = w;
 578                 else /* word_len <= 32 */
 579                         ((u32 *)xfer->rx_buf)[elements] = w;
 580         } else {
 581                 dev_err(&spi->dev, "DMA RX last word empty\n");
 582                 count -= mcspi_bytes_per_word(word_len);
 583         }
 584         omap2_mcspi_set_enable(spi, 1);
 585         return count;
 586 }
 587
 588 static unsigned
 589 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
 590 {
 591         struct omap2_mcspi      *mcspi;
 592         struct omap2_mcspi_cs   *cs = spi->controller_state;
 593         struct omap2_mcspi_dma  *mcspi_dma;
 594         unsigned int            count;
 595         u32                     l;
 596         u8                      *rx;
 597         const u8                *tx;
 598         struct dma_slave_config cfg;
 599         enum dma_slave_buswidth width;
 600         unsigned es;
 601         void __iomem            *chstat_reg;
 602         void __iomem            *irqstat_reg;
 603         int                     wait_res;
 604
 605         mcspi = spi_master_get_devdata(spi->master);
 606         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 607         l = mcspi_cached_chconf0(spi);
 608
 609
 610         if (cs->word_len <= 8) {
 611                 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 612                 es = 1;
 613         } else if (cs->word_len <= 16) {
 614                 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 615                 es = 2;
 616         } else {
 617                 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 618                 es = 4;
 619         }
 620
 621         count = xfer->len;
 622
 623         memset(&cfg, 0, sizeof(cfg));
 624         cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
 625         cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
 626         cfg.src_addr_width = width;
 627         cfg.dst_addr_width = width;
 628         cfg.src_maxburst = 1;
 629         cfg.dst_maxburst = 1;
 630
 631         rx = xfer->rx_buf;
 632         tx = xfer->tx_buf;
 633
 634         if (tx != NULL)
 635                 omap2_mcspi_tx_dma(spi, xfer, cfg);
 636
 637         if (rx != NULL)
 638                 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
 639
 640         if (tx != NULL) {
 641                 wait_for_completion(&mcspi_dma->dma_tx_completion);
 642
 643                 if (mcspi->fifo_depth > 0) {
 644                         irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
 645
 646                         if (mcspi_wait_for_reg_bit(irqstat_reg,
 647                                                 OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
 648                                 dev_err(&spi->dev, "EOW timed out\n");
 649
 650                         mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
 651                                         OMAP2_MCSPI_IRQSTATUS_EOW);
 652                 }
 653
 654                 /* for TX_ONLY mode, be sure all words have shifted out */
 655                 if (rx == NULL) {
 656                         chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
 657                         if (mcspi->fifo_depth > 0) {
 658                                 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
 659                                                 OMAP2_MCSPI_CHSTAT_TXFFE);
 660                                 if (wait_res < 0)
 661                                         dev_err(&spi->dev, "TXFFE timed out\n");
 662                         } else {
 663                                 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
 664                                                 OMAP2_MCSPI_CHSTAT_TXS);
 665                                 if (wait_res < 0)
 666                                         dev_err(&spi->dev, "TXS timed out\n");
 667                         }
 668                         if (wait_res >= 0 &&
 669                                 (mcspi_wait_for_reg_bit(chstat_reg,
 670                                         OMAP2_MCSPI_CHSTAT_EOT) < 0))
 671                                 dev_err(&spi->dev, "EOT timed out\n");
 672                 }
 673         }
 674         return count;
 675 }
 676
 677 static unsigned
 678 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 679 {
 680         struct omap2_mcspi      *mcspi;
 681         struct omap2_mcspi_cs   *cs = spi->controller_state;
 682         unsigned int            count, c;
 683         u32                     l;
 684         void __iomem            *base = cs->base;
 685         void __iomem            *tx_reg;
 686         void __iomem            *rx_reg;
 687         void __iomem            *chstat_reg;
 688         int                     word_len;
 689
 690         mcspi = spi_master_get_devdata(spi->master);
 691         count = xfer->len;
 692         c = count;
 693         word_len = cs->word_len;
 694
 695         l = mcspi_cached_chconf0(spi);
 696
 697         /* We store the pre-calculated register addresses on stack to speed
 698          * up the transfer loop. */
 699         tx_reg          = base + OMAP2_MCSPI_TX0;
 700         rx_reg          = base + OMAP2_MCSPI_RX0;
 701         chstat_reg      = base + OMAP2_MCSPI_CHSTAT0;
 702
 703         if (c < (word_len>>3))
 704                 return 0;
 705
 706         if (word_len <= 8) {
 707                 u8              *rx;
 708                 const u8        *tx;
 709
 710                 rx = xfer->rx_buf;
 711                 tx = xfer->tx_buf;
 712
 713                 do {
 714                         c -= 1;
 715                         if (tx != NULL) {
 716                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 717                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 718                                         dev_err(&spi->dev, "TXS timed out\n");
 719                                         goto out;
 720                                 }
 721                                 dev_vdbg(&spi->dev, "write-%d %02x\n",
 722                                                 word_len, *tx);
 723                                 writel_relaxed(*tx++, tx_reg);
 724                         }
 725                         if (rx != NULL) {
 726                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 727                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 728                                         dev_err(&spi->dev, "RXS timed out\n");
 729                                         goto out;
 730                                 }
 731
 732                                 if (c == 1 && tx == NULL &&
 733                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 734                                         omap2_mcspi_set_enable(spi, 0);
 735                                         *rx++ = readl_relaxed(rx_reg);
 736                                         dev_vdbg(&spi->dev, "read-%d %02x\n",
 737                                                     word_len, *(rx - 1));
 738                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 739                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 740                                                 dev_err(&spi->dev,
 741                                                         "RXS timed out\n");
 742                                                 goto out;
 743                                         }
 744                                         c = 0;
 745                                 } else if (c == 0 && tx == NULL) {
 746                                         omap2_mcspi_set_enable(spi, 0);
 747                                 }
 748
 749                                 *rx++ = readl_relaxed(rx_reg);
 750                                 dev_vdbg(&spi->dev, "read-%d %02x\n",
 751                                                 word_len, *(rx - 1));
 752                         }
 753                 } while (c);
 754         } else if (word_len <= 16) {
 755                 u16             *rx;
 756                 const u16       *tx;
 757
 758                 rx = xfer->rx_buf;
 759                 tx = xfer->tx_buf;
 760                 do {
 761                         c -= 2;
 762                         if (tx != NULL) {
 763                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 764                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 765                                         dev_err(&spi->dev, "TXS timed out\n");
 766                                         goto out;
 767                                 }
 768                                 dev_vdbg(&spi->dev, "write-%d %04x\n",
 769                                                 word_len, *tx);
 770                                 writel_relaxed(*tx++, tx_reg);
 771                         }
 772                         if (rx != NULL) {
 773                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 774                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 775                                         dev_err(&spi->dev, "RXS timed out\n");
 776                                         goto out;
 777                                 }
 778
 779                                 if (c == 2 && tx == NULL &&
 780                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 781                                         omap2_mcspi_set_enable(spi, 0);
 782                                         *rx++ = readl_relaxed(rx_reg);
 783                                         dev_vdbg(&spi->dev, "read-%d %04x\n",
 784                                                     word_len, *(rx - 1));
 785                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 786                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 787                                                 dev_err(&spi->dev,
 788                                                         "RXS timed out\n");
 789                                                 goto out;
 790                                         }
 791                                         c = 0;
 792                                 } else if (c == 0 && tx == NULL) {
 793                                         omap2_mcspi_set_enable(spi, 0);
 794                                 }
 795
 796                                 *rx++ = readl_relaxed(rx_reg);
 797                                 dev_vdbg(&spi->dev, "read-%d %04x\n",
 798                                                 word_len, *(rx - 1));
 799                         }
 800                 } while (c >= 2);
 801         } else if (word_len <= 32) {
 802                 u32             *rx;
 803                 const u32       *tx;
 804
 805                 rx = xfer->rx_buf;
 806                 tx = xfer->tx_buf;
 807                 do {
 808                         c -= 4;
 809                         if (tx != NULL) {
 810                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 811                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 812                                         dev_err(&spi->dev, "TXS timed out\n");
 813                                         goto out;
 814                                 }
 815                                 dev_vdbg(&spi->dev, "write-%d %08x\n",
 816                                                 word_len, *tx);
 817                                 writel_relaxed(*tx++, tx_reg);
 818                         }
 819                         if (rx != NULL) {
 820                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 821                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 822                                         dev_err(&spi->dev, "RXS timed out\n");
 823                                         goto out;
 824                                 }
 825
 826                                 if (c == 4 && tx == NULL &&
 827                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 828                                         omap2_mcspi_set_enable(spi, 0);
 829                                         *rx++ = readl_relaxed(rx_reg);
 830                                         dev_vdbg(&spi->dev, "read-%d %08x\n",
 831                                                     word_len, *(rx - 1));
 832                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 833                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 834                                                 dev_err(&spi->dev,
 835                                                         "RXS timed out\n");
 836                                                 goto out;
 837                                         }
 838                                         c = 0;
 839                                 } else if (c == 0 && tx == NULL) {
 840                                         omap2_mcspi_set_enable(spi, 0);
 841                                 }
 842
 843                                 *rx++ = readl_relaxed(rx_reg);
 844                                 dev_vdbg(&spi->dev, "read-%d %08x\n",
 845                                                 word_len, *(rx - 1));
 846                         }
 847                 } while (c >= 4);
 848         }
 849
 850         /* for TX_ONLY mode, be sure all words have shifted out */
 851         if (xfer->rx_buf == NULL) {
 852                 if (mcspi_wait_for_reg_bit(chstat_reg,
 853                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 854                         dev_err(&spi->dev, "TXS timed out\n");
 855                 } else if (mcspi_wait_for_reg_bit(chstat_reg,
 856                                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
 857                         dev_err(&spi->dev, "EOT timed out\n");
 858
 859                 /* disable chan to purge rx datas received in TX_ONLY transfer,
 860                  * otherwise these rx datas will affect the direct following
 861                  * RX_ONLY transfer.
 862                  */
 863                 omap2_mcspi_set_enable(spi, 0);
 864         }
 865 out:
 866         omap2_mcspi_set_enable(spi, 1);
 867         return count - c;
 868 }
 869
 870 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
 871 {
 872         u32 div;
 873
 874         for (div = 0; div < 15; div++)
 875                 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
 876                         return div;
 877
 878         return 15;
 879 }
 880
 881 /* called only when no transfer is active to this device */
 882 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
 883                 struct spi_transfer *t)
 884 {
 885         struct omap2_mcspi_cs *cs = spi->controller_state;
 886         struct omap2_mcspi *mcspi;
 887         struct spi_master *spi_cntrl;
 888         u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0;
 889         u8 word_len = spi->bits_per_word;
 890         u32 speed_hz = spi->max_speed_hz;
 891
 892         mcspi = spi_master_get_devdata(spi->master);
 893         spi_cntrl = mcspi->master;
 894
 895         if (t != NULL && t->bits_per_word)
 896                 word_len = t->bits_per_word;
 897
 898         cs->word_len = word_len;
 899
 900         if (t && t->speed_hz)
 901                 speed_hz = t->speed_hz;
 902
 903         speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
 904         if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) {
 905                 clkd = omap2_mcspi_calc_divisor(speed_hz);
 906                 speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd;
 907                 clkg = 0;
 908         } else {
 909                 div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz;
 910                 speed_hz = OMAP2_MCSPI_MAX_FREQ / div;
 911                 clkd = (div - 1) & 0xf;
 912                 extclk = (div - 1) >> 4;
 913                 clkg = OMAP2_MCSPI_CHCONF_CLKG;
 914         }
 915
 916         l = mcspi_cached_chconf0(spi);
 917
 918         /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
 919          * REVISIT: this controller could support SPI_3WIRE mode.
 920          */
 921         if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
 922                 l &= ~OMAP2_MCSPI_CHCONF_IS;
 923                 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
 924                 l |= OMAP2_MCSPI_CHCONF_DPE0;
 925         } else {
 926                 l |= OMAP2_MCSPI_CHCONF_IS;
 927                 l |= OMAP2_MCSPI_CHCONF_DPE1;
 928                 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
 929         }
 930
 931         /* wordlength */
 932         l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
 933         l |= (word_len - 1) << 7;
 934
 935         /* set chipselect polarity; manage with FORCE */
 936         if (!(spi->mode & SPI_CS_HIGH))
 937                 l |= OMAP2_MCSPI_CHCONF_EPOL;   /* active-low; normal */
 938         else
 939                 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
 940
 941         /* set clock divisor */
 942         l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
 943         l |= clkd << 2;
 944
 945         /* set clock granularity */
 946         l &= ~OMAP2_MCSPI_CHCONF_CLKG;
 947         l |= clkg;
 948         if (clkg) {
 949                 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
 950                 cs->chctrl0 |= extclk << 8;
 951                 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
 952         }
 953
 954         /* set SPI mode 0..3 */
 955         if (spi->mode & SPI_CPOL)
 956                 l |= OMAP2_MCSPI_CHCONF_POL;
 957         else
 958                 l &= ~OMAP2_MCSPI_CHCONF_POL;
 959         if (spi->mode & SPI_CPHA)
 960                 l |= OMAP2_MCSPI_CHCONF_PHA;
 961         else
 962                 l &= ~OMAP2_MCSPI_CHCONF_PHA;
 963
 964         mcspi_write_chconf0(spi, l);
 965
 966         cs->mode = spi->mode;
 967
 968         dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
 969                         speed_hz,
 970                         (spi->mode & SPI_CPHA) ? "trailing" : "leading",
 971                         (spi->mode & SPI_CPOL) ? "inverted" : "normal");
 972
 973         return 0;
 974 }
 975
 976 /*
 977  * Note that we currently allow DMA only if we get a channel
 978  * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
 979  */
 980 static int omap2_mcspi_request_dma(struct spi_device *spi)
 981 {
 982         struct spi_master       *master = spi->master;
 983         struct omap2_mcspi      *mcspi;
 984         struct omap2_mcspi_dma  *mcspi_dma;
 985         int ret = 0;
 986
 987         mcspi = spi_master_get_devdata(master);
 988         mcspi_dma = mcspi->dma_channels + spi->chip_select;
 989
 990         init_completion(&mcspi_dma->dma_rx_completion);
 991         init_completion(&mcspi_dma->dma_tx_completion);
 992
 993         mcspi_dma->dma_rx = dma_request_chan(&master->dev,
 994                                              mcspi_dma->dma_rx_ch_name);
 995         if (IS_ERR(mcspi_dma->dma_rx)) {
 996                 ret = PTR_ERR(mcspi_dma->dma_rx);
 997                 mcspi_dma->dma_rx = NULL;
 998                 goto no_dma;
 999         }
1000
1001         mcspi_dma->dma_tx = dma_request_chan(&master->dev,
1002                                              mcspi_dma->dma_tx_ch_name);
1003         if (IS_ERR(mcspi_dma->dma_tx)) {
1004                 ret = PTR_ERR(mcspi_dma->dma_tx);
1005                 mcspi_dma->dma_tx = NULL;
1006                 dma_release_channel(mcspi_dma->dma_rx);
1007                 mcspi_dma->dma_rx = NULL;
1008         }
1009
1010 no_dma:
1011         return ret;
1012 }
1013
1014 static int omap2_mcspi_setup(struct spi_device *spi)
1015 {
1016         int                     ret;
1017         struct omap2_mcspi      *mcspi = spi_master_get_devdata(spi->master);
1018         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1019         struct omap2_mcspi_dma  *mcspi_dma;
1020         struct omap2_mcspi_cs   *cs = spi->controller_state;
1021
1022         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1023
1024         if (!cs) {
1025                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
1026                 if (!cs)
1027                         return -ENOMEM;
1028                 cs->base = mcspi->base + spi->chip_select * 0x14;
1029                 cs->phys = mcspi->phys + spi->chip_select * 0x14;
1030                 cs->mode = 0;
1031                 cs->chconf0 = 0;
1032                 cs->chctrl0 = 0;
1033                 spi->controller_state = cs;
1034                 /* Link this to context save list */
1035                 list_add_tail(&cs->node, &ctx->cs);
1036
1037                 if (gpio_is_valid(spi->cs_gpio)) {
1038                         ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
1039                         if (ret) {
1040                                 dev_err(&spi->dev, "failed to request gpio\n");
1041                                 return ret;
1042                         }
1043                         gpio_direction_output(spi->cs_gpio,
1044                                          !(spi->mode & SPI_CS_HIGH));
1045                 }
1046         }
1047
1048         if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
1049                 ret = omap2_mcspi_request_dma(spi);
1050                 if (ret)
1051                         dev_warn(&spi->dev, "not using DMA for McSPI (%d)\n",
1052                                  ret);
1053         }
1054
1055         ret = pm_runtime_get_sync(mcspi->dev);
1056         if (ret < 0)
1057                 return ret;
1058
1059         ret = omap2_mcspi_setup_transfer(spi, NULL);
1060         pm_runtime_mark_last_busy(mcspi->dev);
1061         pm_runtime_put_autosuspend(mcspi->dev);
1062
1063         return ret;
1064 }
1065
1066 static void omap2_mcspi_cleanup(struct spi_device *spi)
1067 {
1068         struct omap2_mcspi      *mcspi;
1069         struct omap2_mcspi_dma  *mcspi_dma;
1070         struct omap2_mcspi_cs   *cs;
1071
1072         mcspi = spi_master_get_devdata(spi->master);
1073
1074         if (spi->controller_state) {
1075                 /* Unlink controller state from context save list */
1076                 cs = spi->controller_state;
1077                 list_del(&cs->node);
1078
1079                 kfree(cs);
1080         }
1081
1082         if (spi->chip_select < spi->master->num_chipselect) {
1083                 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1084
1085                 if (mcspi_dma->dma_rx) {
1086                         dma_release_channel(mcspi_dma->dma_rx);
1087                         mcspi_dma->dma_rx = NULL;
1088                 }
1089                 if (mcspi_dma->dma_tx) {
1090                         dma_release_channel(mcspi_dma->dma_tx);
1091                         mcspi_dma->dma_tx = NULL;
1092                 }
1093         }
1094
1095         if (gpio_is_valid(spi->cs_gpio))
1096                 gpio_free(spi->cs_gpio);
1097 }
1098
1099 static int omap2_mcspi_transfer_one(struct spi_master *master,
1100                                     struct spi_device *spi,
1101                                     struct spi_transfer *t)
1102 {
1103
1104         /* We only enable one channel at a time -- the one whose message is
1105          * -- although this controller would gladly
1106          * arbitrate among multiple channels.  This corresponds to "single
1107          * channel" master mode.  As a side effect, we need to manage the
1108          * chipselect with the FORCE bit ... CS != channel enable.
1109          */
1110
1111         struct omap2_mcspi              *mcspi;
1112         struct omap2_mcspi_dma          *mcspi_dma;
1113         struct omap2_mcspi_cs           *cs;
1114         struct omap2_mcspi_device_config *cd;
1115         int                             par_override = 0;
1116         int                             status = 0;
1117         u32                             chconf;
1118
1119         mcspi = spi_master_get_devdata(master);
1120         mcspi_dma = mcspi->dma_channels + spi->chip_select;
1121         cs = spi->controller_state;
1122         cd = spi->controller_data;
1123
1124         /*
1125          * The slave driver could have changed spi->mode in which case
1126          * it will be different from cs->mode (the current hardware setup).
1127          * If so, set par_override (even though its not a parity issue) so
1128          * omap2_mcspi_setup_transfer will be called to configure the hardware
1129          * with the correct mode on the first iteration of the loop below.
1130          */
1131         if (spi->mode != cs->mode)
1132                 par_override = 1;
1133
1134         omap2_mcspi_set_enable(spi, 0);
1135
1136         if (gpio_is_valid(spi->cs_gpio))
1137                 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);
1138
1139         if (par_override ||
1140             (t->speed_hz != spi->max_speed_hz) ||
1141             (t->bits_per_word != spi->bits_per_word)) {
1142                 par_override = 1;
1143                 status = omap2_mcspi_setup_transfer(spi, t);
1144                 if (status < 0)
1145                         goto out;
1146                 if (t->speed_hz == spi->max_speed_hz &&
1147                     t->bits_per_word == spi->bits_per_word)
1148                         par_override = 0;
1149         }
1150         if (cd && cd->cs_per_word) {
1151                 chconf = mcspi->ctx.modulctrl;
1152                 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
1153                 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1154                 mcspi->ctx.modulctrl =
1155                         mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1156         }
1157
1158         chconf = mcspi_cached_chconf0(spi);
1159         chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
1160         chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
1161
1162         if (t->tx_buf == NULL)
1163                 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
1164         else if (t->rx_buf == NULL)
1165                 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
1166
1167         if (cd && cd->turbo_mode && t->tx_buf == NULL) {
1168                 /* Turbo mode is for more than one word */
1169                 if (t->len > ((cs->word_len + 7) >> 3))
1170                         chconf |= OMAP2_MCSPI_CHCONF_TURBO;
1171         }
1172
1173         mcspi_write_chconf0(spi, chconf);
1174
1175         if (t->len) {
1176                 unsigned        count;
1177
1178                 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1179                     master->cur_msg_mapped &&
1180                     master->can_dma(master, spi, t))
1181                         omap2_mcspi_set_fifo(spi, t, 1);
1182
1183                 omap2_mcspi_set_enable(spi, 1);
1184
1185                 /* RX_ONLY mode needs dummy data in TX reg */
1186                 if (t->tx_buf == NULL)
1187                         writel_relaxed(0, cs->base
1188                                         + OMAP2_MCSPI_TX0);
1189
1190                 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1191                     master->cur_msg_mapped &&
1192                     master->can_dma(master, spi, t))
1193                         count = omap2_mcspi_txrx_dma(spi, t);
1194                 else
1195                         count = omap2_mcspi_txrx_pio(spi, t);
1196
1197                 if (count != t->len) {
1198                         status = -EIO;
1199                         goto out;
1200                 }
1201         }
1202
1203         omap2_mcspi_set_enable(spi, 0);
1204
1205         if (mcspi->fifo_depth > 0)
1206                 omap2_mcspi_set_fifo(spi, t, 0);
1207
1208 out:
1209         /* Restore defaults if they were overriden */
1210         if (par_override) {
1211                 par_override = 0;
1212                 status = omap2_mcspi_setup_transfer(spi, NULL);
1213         }
1214
1215         if (cd && cd->cs_per_word) {
1216                 chconf = mcspi->ctx.modulctrl;
1217                 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1218                 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1219                 mcspi->ctx.modulctrl =
1220                         mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1221         }
1222
1223         omap2_mcspi_set_enable(spi, 0);
1224
1225         if (gpio_is_valid(spi->cs_gpio))
1226                 omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));
1227
1228         if (mcspi->fifo_depth > 0 && t)
1229                 omap2_mcspi_set_fifo(spi, t, 0);
1230
1231         return status;
1232 }
1233
1234 static int omap2_mcspi_prepare_message(struct spi_master *master,
1235                                        struct spi_message *msg)
1236 {
1237         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
1238         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1239         struct omap2_mcspi_cs   *cs;
1240
1241         /* Only a single channel can have the FORCE bit enabled
1242          * in its chconf0 register.
1243          * Scan all channels and disable them except the current one.
1244          * A FORCE can remain from a last transfer having cs_change enabled
1245          */
1246         list_for_each_entry(cs, &ctx->cs, node) {
1247                 if (msg->spi->controller_state == cs)
1248                         continue;
1249
1250                 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) {
1251                         cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1252                         writel_relaxed(cs->chconf0,
1253                                         cs->base + OMAP2_MCSPI_CHCONF0);
1254                         readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0);
1255                 }
1256         }
1257
1258         return 0;
1259 }
1260
1261 static bool omap2_mcspi_can_dma(struct spi_master *master,
1262                                 struct spi_device *spi,
1263                                 struct spi_transfer *xfer)
1264 {
1265         return (xfer->len >= DMA_MIN_BYTES);
1266 }
1267
1268 static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1269 {
1270         struct spi_master       *master = mcspi->master;
1271         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1272         int                     ret = 0;
1273
1274         ret = pm_runtime_get_sync(mcspi->dev);
1275         if (ret < 0)
1276                 return ret;
1277
1278         mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1279                         OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1280         ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1281
1282         omap2_mcspi_set_master_mode(master);
1283         pm_runtime_mark_last_busy(mcspi->dev);
1284         pm_runtime_put_autosuspend(mcspi->dev);
1285         return 0;
1286 }
1287
1288 static int omap_mcspi_runtime_resume(struct device *dev)
1289 {
1290         struct omap2_mcspi      *mcspi;
1291         struct spi_master       *master;
1292
1293         master = dev_get_drvdata(dev);
1294         mcspi = spi_master_get_devdata(master);
1295         omap2_mcspi_restore_ctx(mcspi);
1296
1297         return 0;
1298 }
1299
1300 static struct omap2_mcspi_platform_config omap2_pdata = {
1301         .regs_offset = 0,
1302 };
1303
1304 static struct omap2_mcspi_platform_config omap4_pdata = {
1305         .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1306 };
1307
1308 static const struct of_device_id omap_mcspi_of_match[] = {
1309         {
1310                 .compatible = "ti,omap2-mcspi",
1311                 .data = &omap2_pdata,
1312         },
1313         {
1314                 .compatible = "ti,omap4-mcspi",
1315                 .data = &omap4_pdata,
1316         },
1317         { },
1318 };
1319 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1320
1321 static int omap2_mcspi_probe(struct platform_device *pdev)
1322 {
1323         struct spi_master       *master;
1324         const struct omap2_mcspi_platform_config *pdata;
1325         struct omap2_mcspi      *mcspi;
1326         struct resource         *r;
1327         int                     status = 0, i;
1328         u32                     regs_offset = 0;
1329         static int              bus_num = 1;
1330         struct device_node      *node = pdev->dev.of_node;
1331         const struct of_device_id *match;
1332
1333         master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1334         if (master == NULL) {
1335                 dev_dbg(&pdev->dev, "master allocation failed\n");
1336                 return -ENOMEM;
1337         }
1338
1339         /* the spi->mode bits understood by this driver: */
1340         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1341         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1342         master->setup = omap2_mcspi_setup;
1343         master->auto_runtime_pm = true;
1344         master->prepare_message = omap2_mcspi_prepare_message;
1345         master->can_dma = omap2_mcspi_can_dma;
1346         master->transfer_one = omap2_mcspi_transfer_one;
1347         master->set_cs = omap2_mcspi_set_cs;
1348         master->cleanup = omap2_mcspi_cleanup;
1349         master->dev.of_node = node;
1350         master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
1351         master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
1352
1353         platform_set_drvdata(pdev, master);
1354
1355         mcspi = spi_master_get_devdata(master);
1356         mcspi->master = master;
1357
1358         match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1359         if (match) {
1360                 u32 num_cs = 1; /* default number of chipselect */
1361                 pdata = match->data;
1362
1363                 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1364                 master->num_chipselect = num_cs;
1365                 master->bus_num = bus_num++;
1366                 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1367                         mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1368         } else {
1369                 pdata = dev_get_platdata(&pdev->dev);
1370                 master->num_chipselect = pdata->num_cs;
1371                 if (pdev->id != -1)
1372                         master->bus_num = pdev->id;
1373                 mcspi->pin_dir = pdata->pin_dir;
1374         }
1375         regs_offset = pdata->regs_offset;
1376
1377         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1378         if (r == NULL) {
1379                 status = -ENODEV;
1380                 goto free_master;
1381         }
1382
1383         r->start += regs_offset;
1384         r->end += regs_offset;
1385         mcspi->phys = r->start;
1386
1387         mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1388         if (IS_ERR(mcspi->base)) {
1389                 status = PTR_ERR(mcspi->base);
1390                 goto free_master;
1391         }
1392
1393         mcspi->dev = &pdev->dev;
1394
1395         INIT_LIST_HEAD(&mcspi->ctx.cs);
1396
1397         mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect,
1398                                            sizeof(struct omap2_mcspi_dma),
1399                                            GFP_KERNEL);
1400         if (mcspi->dma_channels == NULL) {
1401                 status = -ENOMEM;
1402                 goto free_master;
1403         }
1404
1405         for (i = 0; i < master->num_chipselect; i++) {
1406                 sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i);
1407                 sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i);
1408         }
1409
1410         if (status < 0)
1411                 goto free_master;
1412
1413         pm_runtime_use_autosuspend(&pdev->dev);
1414         pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1415         pm_runtime_enable(&pdev->dev);
1416
1417         status = omap2_mcspi_master_setup(mcspi);
1418         if (status < 0)
1419                 goto disable_pm;
1420
1421         status = devm_spi_register_master(&pdev->dev, master);
1422         if (status < 0)
1423                 goto disable_pm;
1424
1425         return status;
1426
1427 disable_pm:
1428         pm_runtime_dont_use_autosuspend(&pdev->dev);
1429         pm_runtime_put_sync(&pdev->dev);
1430         pm_runtime_disable(&pdev->dev);
1431 free_master:
1432         spi_master_put(master);
1433         return status;
1434 }
1435
1436 static int omap2_mcspi_remove(struct platform_device *pdev)
1437 {
1438         struct spi_master *master = platform_get_drvdata(pdev);
1439         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1440
1441         pm_runtime_dont_use_autosuspend(mcspi->dev);
1442         pm_runtime_put_sync(mcspi->dev);
1443         pm_runtime_disable(&pdev->dev);
1444
1445         return 0;
1446 }
1447
1448 /* work with hotplug and coldplug */
1449 MODULE_ALIAS("platform:omap2_mcspi");
1450
1451 #ifdef  CONFIG_SUSPEND
1452 /*
1453  * When SPI wake up from off-mode, CS is in activate state. If it was in
1454  * unactive state when driver was suspend, then force it to unactive state at
1455  * wake up.
1456  */
1457 static int omap2_mcspi_resume(struct device *dev)
1458 {
1459         struct spi_master       *master = dev_get_drvdata(dev);
1460         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
1461         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1462         struct omap2_mcspi_cs   *cs;
1463
1464         pm_runtime_get_sync(mcspi->dev);
1465         list_for_each_entry(cs, &ctx->cs, node) {
1466                 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1467                         /*
1468                          * We need to toggle CS state for OMAP take this
1469                          * change in account.
1470                          */
1471                         cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1472                         writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1473                         cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1474                         writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1475                 }
1476         }
1477         pm_runtime_mark_last_busy(mcspi->dev);
1478         pm_runtime_put_autosuspend(mcspi->dev);
1479
1480         return pinctrl_pm_select_default_state(dev);
1481 }
1482
1483 static int omap2_mcspi_suspend(struct device *dev)
1484 {
1485         return pinctrl_pm_select_sleep_state(dev);
1486 }
1487
1488 #else
1489 #define omap2_mcspi_suspend     NULL
1490 #define omap2_mcspi_resume      NULL
1491 #endif
1492
1493 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1494         .resume = omap2_mcspi_resume,
1495         .suspend = omap2_mcspi_suspend,
1496         .runtime_resume = omap_mcspi_runtime_resume,
1497 };
1498
1499 static struct platform_driver omap2_mcspi_driver = {
1500         .driver = {
1501                 .name =         "omap2_mcspi",
1502                 .pm =           &omap2_mcspi_pm_ops,
1503                 .of_match_table = omap_mcspi_of_match,
1504         },
1505         .probe =        omap2_mcspi_probe,
1506         .remove =       omap2_mcspi_remove,
1507 };
1508
1509 module_platform_driver(omap2_mcspi_driver);
1510 MODULE_LICENSE("GPL");