GNU Linux-libre 5.10.219-gnu1
[releases.git] / drivers / spi / spi-omap-100k.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * OMAP7xx SPI 100k controller driver
4  * Author: Fabrice Crohas <fcrohas@gmail.com>
5  * from original omap1_mcspi driver
6  *
7  * Copyright (C) 2005, 2006 Nokia Corporation
8  * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
9  *              Juha Yrj�l� <juha.yrjola@nokia.com>
10  */
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/module.h>
15 #include <linux/device.h>
16 #include <linux/delay.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22 #include <linux/slab.h>
23
24 #include <linux/spi/spi.h>
25
26 #define OMAP1_SPI100K_MAX_FREQ          48000000
27
28 #define ICR_SPITAS      (OMAP7XX_ICR_BASE + 0x12)
29
30 #define SPI_SETUP1      0x00
31 #define SPI_SETUP2      0x02
32 #define SPI_CTRL        0x04
33 #define SPI_STATUS      0x06
34 #define SPI_TX_LSB      0x08
35 #define SPI_TX_MSB      0x0a
36 #define SPI_RX_LSB      0x0c
37 #define SPI_RX_MSB      0x0e
38
39 #define SPI_SETUP1_INT_READ_ENABLE      (1UL << 5)
40 #define SPI_SETUP1_INT_WRITE_ENABLE     (1UL << 4)
41 #define SPI_SETUP1_CLOCK_DIVISOR(x)     ((x) << 1)
42 #define SPI_SETUP1_CLOCK_ENABLE         (1UL << 0)
43
44 #define SPI_SETUP2_ACTIVE_EDGE_FALLING  (0UL << 0)
45 #define SPI_SETUP2_ACTIVE_EDGE_RISING   (1UL << 0)
46 #define SPI_SETUP2_NEGATIVE_LEVEL       (0UL << 5)
47 #define SPI_SETUP2_POSITIVE_LEVEL       (1UL << 5)
48 #define SPI_SETUP2_LEVEL_TRIGGER        (0UL << 10)
49 #define SPI_SETUP2_EDGE_TRIGGER         (1UL << 10)
50
51 #define SPI_CTRL_SEN(x)                 ((x) << 7)
52 #define SPI_CTRL_WORD_SIZE(x)           (((x) - 1) << 2)
53 #define SPI_CTRL_WR                     (1UL << 1)
54 #define SPI_CTRL_RD                     (1UL << 0)
55
56 #define SPI_STATUS_WE                   (1UL << 1)
57 #define SPI_STATUS_RD                   (1UL << 0)
58
59 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
60  * cache operations; better heuristics consider wordsize and bitrate.
61  */
62 #define DMA_MIN_BYTES                   8
63
64 #define SPI_RUNNING     0
65 #define SPI_SHUTDOWN    1
66
67 struct omap1_spi100k {
68         struct clk              *ick;
69         struct clk              *fck;
70
71         /* Virtual base address of the controller */
72         void __iomem            *base;
73 };
74
75 struct omap1_spi100k_cs {
76         void __iomem            *base;
77         int                     word_len;
78 };
79
80 static void spi100k_enable_clock(struct spi_master *master)
81 {
82         unsigned int val;
83         struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
84
85         /* enable SPI */
86         val = readw(spi100k->base + SPI_SETUP1);
87         val |= SPI_SETUP1_CLOCK_ENABLE;
88         writew(val, spi100k->base + SPI_SETUP1);
89 }
90
91 static void spi100k_disable_clock(struct spi_master *master)
92 {
93         unsigned int val;
94         struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
95
96         /* disable SPI */
97         val = readw(spi100k->base + SPI_SETUP1);
98         val &= ~SPI_SETUP1_CLOCK_ENABLE;
99         writew(val, spi100k->base + SPI_SETUP1);
100 }
101
102 static void spi100k_write_data(struct spi_master *master, int len, int data)
103 {
104         struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
105
106         /* write 16-bit word, shifting 8-bit data if necessary */
107         if (len <= 8) {
108                 data <<= 8;
109                 len = 16;
110         }
111
112         spi100k_enable_clock(master);
113         writew(data , spi100k->base + SPI_TX_MSB);
114
115         writew(SPI_CTRL_SEN(0) |
116                SPI_CTRL_WORD_SIZE(len) |
117                SPI_CTRL_WR,
118                spi100k->base + SPI_CTRL);
119
120         /* Wait for bit ack send change */
121         while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_WE) != SPI_STATUS_WE)
122                 ;
123         udelay(1000);
124
125         spi100k_disable_clock(master);
126 }
127
128 static int spi100k_read_data(struct spi_master *master, int len)
129 {
130         int dataL;
131         struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
132
133         /* Always do at least 16 bits */
134         if (len <= 8)
135                 len = 16;
136
137         spi100k_enable_clock(master);
138         writew(SPI_CTRL_SEN(0) |
139                SPI_CTRL_WORD_SIZE(len) |
140                SPI_CTRL_RD,
141                spi100k->base + SPI_CTRL);
142
143         while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_RD) != SPI_STATUS_RD)
144                 ;
145         udelay(1000);
146
147         dataL = readw(spi100k->base + SPI_RX_LSB);
148         readw(spi100k->base + SPI_RX_MSB);
149         spi100k_disable_clock(master);
150
151         return dataL;
152 }
153
154 static void spi100k_open(struct spi_master *master)
155 {
156         /* get control of SPI */
157         struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
158
159         writew(SPI_SETUP1_INT_READ_ENABLE |
160                SPI_SETUP1_INT_WRITE_ENABLE |
161                SPI_SETUP1_CLOCK_DIVISOR(0), spi100k->base + SPI_SETUP1);
162
163         /* configure clock and interrupts */
164         writew(SPI_SETUP2_ACTIVE_EDGE_FALLING |
165                SPI_SETUP2_NEGATIVE_LEVEL |
166                SPI_SETUP2_LEVEL_TRIGGER, spi100k->base + SPI_SETUP2);
167 }
168
169 static void omap1_spi100k_force_cs(struct omap1_spi100k *spi100k, int enable)
170 {
171         if (enable)
172                 writew(0x05fc, spi100k->base + SPI_CTRL);
173         else
174                 writew(0x05fd, spi100k->base + SPI_CTRL);
175 }
176
177 static unsigned
178 omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
179 {
180         struct omap1_spi100k_cs *cs = spi->controller_state;
181         unsigned int            count, c;
182         int                     word_len;
183
184         count = xfer->len;
185         c = count;
186         word_len = cs->word_len;
187
188         if (word_len <= 8) {
189                 u8              *rx;
190                 const u8        *tx;
191
192                 rx = xfer->rx_buf;
193                 tx = xfer->tx_buf;
194                 do {
195                         c -= 1;
196                         if (xfer->tx_buf != NULL)
197                                 spi100k_write_data(spi->master, word_len, *tx++);
198                         if (xfer->rx_buf != NULL)
199                                 *rx++ = spi100k_read_data(spi->master, word_len);
200                 } while (c);
201         } else if (word_len <= 16) {
202                 u16             *rx;
203                 const u16       *tx;
204
205                 rx = xfer->rx_buf;
206                 tx = xfer->tx_buf;
207                 do {
208                         c -= 2;
209                         if (xfer->tx_buf != NULL)
210                                 spi100k_write_data(spi->master, word_len, *tx++);
211                         if (xfer->rx_buf != NULL)
212                                 *rx++ = spi100k_read_data(spi->master, word_len);
213                 } while (c);
214         } else if (word_len <= 32) {
215                 u32             *rx;
216                 const u32       *tx;
217
218                 rx = xfer->rx_buf;
219                 tx = xfer->tx_buf;
220                 do {
221                         c -= 4;
222                         if (xfer->tx_buf != NULL)
223                                 spi100k_write_data(spi->master, word_len, *tx);
224                         if (xfer->rx_buf != NULL)
225                                 *rx = spi100k_read_data(spi->master, word_len);
226                 } while (c);
227         }
228         return count - c;
229 }
230
231 /* called only when no transfer is active to this device */
232 static int omap1_spi100k_setup_transfer(struct spi_device *spi,
233                 struct spi_transfer *t)
234 {
235         struct omap1_spi100k *spi100k = spi_master_get_devdata(spi->master);
236         struct omap1_spi100k_cs *cs = spi->controller_state;
237         u8 word_len;
238
239         if (t != NULL)
240                 word_len = t->bits_per_word;
241         else
242                 word_len = spi->bits_per_word;
243
244         if (word_len > 32)
245                 return -EINVAL;
246         cs->word_len = word_len;
247
248         /* SPI init before transfer */
249         writew(0x3e , spi100k->base + SPI_SETUP1);
250         writew(0x00 , spi100k->base + SPI_STATUS);
251         writew(0x3e , spi100k->base + SPI_CTRL);
252
253         return 0;
254 }
255
256 /* the spi->mode bits understood by this driver: */
257 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
258
259 static int omap1_spi100k_setup(struct spi_device *spi)
260 {
261         int                     ret;
262         struct omap1_spi100k    *spi100k;
263         struct omap1_spi100k_cs *cs = spi->controller_state;
264
265         spi100k = spi_master_get_devdata(spi->master);
266
267         if (!cs) {
268                 cs = devm_kzalloc(&spi->dev, sizeof(*cs), GFP_KERNEL);
269                 if (!cs)
270                         return -ENOMEM;
271                 cs->base = spi100k->base + spi->chip_select * 0x14;
272                 spi->controller_state = cs;
273         }
274
275         spi100k_open(spi->master);
276
277         clk_prepare_enable(spi100k->ick);
278         clk_prepare_enable(spi100k->fck);
279
280         ret = omap1_spi100k_setup_transfer(spi, NULL);
281
282         clk_disable_unprepare(spi100k->ick);
283         clk_disable_unprepare(spi100k->fck);
284
285         return ret;
286 }
287
288 static int omap1_spi100k_transfer_one_message(struct spi_master *master,
289                                               struct spi_message *m)
290 {
291         struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
292         struct spi_device *spi = m->spi;
293         struct spi_transfer *t = NULL;
294         int cs_active = 0;
295         int status = 0;
296
297         list_for_each_entry(t, &m->transfers, transfer_list) {
298                 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
299                         status = -EINVAL;
300                         break;
301                 }
302                 status = omap1_spi100k_setup_transfer(spi, t);
303                 if (status < 0)
304                         break;
305
306                 if (!cs_active) {
307                         omap1_spi100k_force_cs(spi100k, 1);
308                         cs_active = 1;
309                 }
310
311                 if (t->len) {
312                         unsigned count;
313
314                         count = omap1_spi100k_txrx_pio(spi, t);
315                         m->actual_length += count;
316
317                         if (count != t->len) {
318                                 status = -EIO;
319                                 break;
320                         }
321                 }
322
323                 spi_transfer_delay_exec(t);
324
325                 /* ignore the "leave it on after last xfer" hint */
326
327                 if (t->cs_change) {
328                         omap1_spi100k_force_cs(spi100k, 0);
329                         cs_active = 0;
330                 }
331         }
332
333         status = omap1_spi100k_setup_transfer(spi, NULL);
334
335         if (cs_active)
336                 omap1_spi100k_force_cs(spi100k, 0);
337
338         m->status = status;
339
340         spi_finalize_current_message(master);
341
342         return status;
343 }
344
345 static int omap1_spi100k_probe(struct platform_device *pdev)
346 {
347         struct spi_master       *master;
348         struct omap1_spi100k    *spi100k;
349         int                     status = 0;
350
351         if (!pdev->id)
352                 return -EINVAL;
353
354         master = spi_alloc_master(&pdev->dev, sizeof(*spi100k));
355         if (master == NULL) {
356                 dev_dbg(&pdev->dev, "master allocation failed\n");
357                 return -ENOMEM;
358         }
359
360         if (pdev->id != -1)
361                 master->bus_num = pdev->id;
362
363         master->setup = omap1_spi100k_setup;
364         master->transfer_one_message = omap1_spi100k_transfer_one_message;
365         master->num_chipselect = 2;
366         master->mode_bits = MODEBITS;
367         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
368         master->min_speed_hz = OMAP1_SPI100K_MAX_FREQ/(1<<16);
369         master->max_speed_hz = OMAP1_SPI100K_MAX_FREQ;
370         master->auto_runtime_pm = true;
371
372         spi100k = spi_master_get_devdata(master);
373
374         /*
375          * The memory region base address is taken as the platform_data.
376          * You should allocate this with ioremap() before initializing
377          * the SPI.
378          */
379         spi100k->base = (void __iomem *)dev_get_platdata(&pdev->dev);
380
381         spi100k->ick = devm_clk_get(&pdev->dev, "ick");
382         if (IS_ERR(spi100k->ick)) {
383                 dev_dbg(&pdev->dev, "can't get spi100k_ick\n");
384                 status = PTR_ERR(spi100k->ick);
385                 goto err;
386         }
387
388         spi100k->fck = devm_clk_get(&pdev->dev, "fck");
389         if (IS_ERR(spi100k->fck)) {
390                 dev_dbg(&pdev->dev, "can't get spi100k_fck\n");
391                 status = PTR_ERR(spi100k->fck);
392                 goto err;
393         }
394
395         status = clk_prepare_enable(spi100k->ick);
396         if (status != 0) {
397                 dev_err(&pdev->dev, "failed to enable ick: %d\n", status);
398                 goto err;
399         }
400
401         status = clk_prepare_enable(spi100k->fck);
402         if (status != 0) {
403                 dev_err(&pdev->dev, "failed to enable fck: %d\n", status);
404                 goto err_ick;
405         }
406
407         pm_runtime_enable(&pdev->dev);
408         pm_runtime_set_active(&pdev->dev);
409
410         status = devm_spi_register_master(&pdev->dev, master);
411         if (status < 0)
412                 goto err_fck;
413
414         return status;
415
416 err_fck:
417         pm_runtime_disable(&pdev->dev);
418         clk_disable_unprepare(spi100k->fck);
419 err_ick:
420         clk_disable_unprepare(spi100k->ick);
421 err:
422         spi_master_put(master);
423         return status;
424 }
425
426 static int omap1_spi100k_remove(struct platform_device *pdev)
427 {
428         struct spi_master *master = platform_get_drvdata(pdev);
429         struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
430
431         pm_runtime_disable(&pdev->dev);
432
433         clk_disable_unprepare(spi100k->fck);
434         clk_disable_unprepare(spi100k->ick);
435
436         return 0;
437 }
438
439 #ifdef CONFIG_PM
440 static int omap1_spi100k_runtime_suspend(struct device *dev)
441 {
442         struct spi_master *master = dev_get_drvdata(dev);
443         struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
444
445         clk_disable_unprepare(spi100k->ick);
446         clk_disable_unprepare(spi100k->fck);
447
448         return 0;
449 }
450
451 static int omap1_spi100k_runtime_resume(struct device *dev)
452 {
453         struct spi_master *master = dev_get_drvdata(dev);
454         struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
455         int ret;
456
457         ret = clk_prepare_enable(spi100k->ick);
458         if (ret != 0) {
459                 dev_err(dev, "Failed to enable ick: %d\n", ret);
460                 return ret;
461         }
462
463         ret = clk_prepare_enable(spi100k->fck);
464         if (ret != 0) {
465                 dev_err(dev, "Failed to enable fck: %d\n", ret);
466                 clk_disable_unprepare(spi100k->ick);
467                 return ret;
468         }
469
470         return 0;
471 }
472 #endif
473
474 static const struct dev_pm_ops omap1_spi100k_pm = {
475         SET_RUNTIME_PM_OPS(omap1_spi100k_runtime_suspend,
476                            omap1_spi100k_runtime_resume, NULL)
477 };
478
479 static struct platform_driver omap1_spi100k_driver = {
480         .driver = {
481                 .name           = "omap1_spi100k",
482                 .pm             = &omap1_spi100k_pm,
483         },
484         .probe          = omap1_spi100k_probe,
485         .remove         = omap1_spi100k_remove,
486 };
487
488 module_platform_driver(omap1_spi100k_driver);
489
490 MODULE_DESCRIPTION("OMAP7xx SPI 100k controller driver");
491 MODULE_AUTHOR("Fabrice Crohas <fcrohas@gmail.com>");
492 MODULE_LICENSE("GPL");