2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Leilk Liu <leilk.liu@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/clk.h>
16 #include <linux/device.h>
17 #include <linux/err.h>
18 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/module.h>
23 #include <linux/of_gpio.h>
24 #include <linux/platform_device.h>
25 #include <linux/platform_data/spi-mt65xx.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/spi/spi.h>
29 #define SPI_CFG0_REG 0x0000
30 #define SPI_CFG1_REG 0x0004
31 #define SPI_TX_SRC_REG 0x0008
32 #define SPI_RX_DST_REG 0x000c
33 #define SPI_TX_DATA_REG 0x0010
34 #define SPI_RX_DATA_REG 0x0014
35 #define SPI_CMD_REG 0x0018
36 #define SPI_STATUS0_REG 0x001c
37 #define SPI_PAD_SEL_REG 0x0024
38 #define SPI_CFG2_REG 0x0028
40 #define SPI_CFG0_SCK_HIGH_OFFSET 0
41 #define SPI_CFG0_SCK_LOW_OFFSET 8
42 #define SPI_CFG0_CS_HOLD_OFFSET 16
43 #define SPI_CFG0_CS_SETUP_OFFSET 24
44 #define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0
45 #define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16
47 #define SPI_CFG1_CS_IDLE_OFFSET 0
48 #define SPI_CFG1_PACKET_LOOP_OFFSET 8
49 #define SPI_CFG1_PACKET_LENGTH_OFFSET 16
50 #define SPI_CFG1_GET_TICK_DLY_OFFSET 30
52 #define SPI_CFG1_CS_IDLE_MASK 0xff
53 #define SPI_CFG1_PACKET_LOOP_MASK 0xff00
54 #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
55 #define SPI_CFG2_SCK_HIGH_OFFSET 0
56 #define SPI_CFG2_SCK_LOW_OFFSET 16
58 #define SPI_CMD_ACT BIT(0)
59 #define SPI_CMD_RESUME BIT(1)
60 #define SPI_CMD_RST BIT(2)
61 #define SPI_CMD_PAUSE_EN BIT(4)
62 #define SPI_CMD_DEASSERT BIT(5)
63 #define SPI_CMD_SAMPLE_SEL BIT(6)
64 #define SPI_CMD_CS_POL BIT(7)
65 #define SPI_CMD_CPHA BIT(8)
66 #define SPI_CMD_CPOL BIT(9)
67 #define SPI_CMD_RX_DMA BIT(10)
68 #define SPI_CMD_TX_DMA BIT(11)
69 #define SPI_CMD_TXMSBF BIT(12)
70 #define SPI_CMD_RXMSBF BIT(13)
71 #define SPI_CMD_RX_ENDIAN BIT(14)
72 #define SPI_CMD_TX_ENDIAN BIT(15)
73 #define SPI_CMD_FINISH_IE BIT(16)
74 #define SPI_CMD_PAUSE_IE BIT(17)
76 #define MT8173_SPI_MAX_PAD_SEL 3
78 #define MTK_SPI_PAUSE_INT_STATUS 0x2
80 #define MTK_SPI_IDLE 0
81 #define MTK_SPI_PAUSED 1
83 #define MTK_SPI_MAX_FIFO_SIZE 32U
84 #define MTK_SPI_PACKET_SIZE 1024
86 struct mtk_spi_compatible {
88 /* Must explicitly send dummy Tx bytes to do Rx only transfer */
90 /* some IC design adjust cfg register to enhance time accuracy */
99 struct clk *parent_clk, *sel_clk, *spi_clk;
100 struct spi_transfer *cur_transfer;
103 struct scatterlist *tx_sgl, *rx_sgl;
104 u32 tx_sgl_len, rx_sgl_len;
105 const struct mtk_spi_compatible *dev_comp;
108 static const struct mtk_spi_compatible mtk_common_compat;
110 static const struct mtk_spi_compatible mt2712_compat = {
114 static const struct mtk_spi_compatible mt7622_compat = {
116 .enhance_timing = true,
119 static const struct mtk_spi_compatible mt8173_compat = {
120 .need_pad_sel = true,
125 * A piece of default chip info unless the platform
128 static const struct mtk_chip_config mtk_default_chip_info = {
135 static const struct of_device_id mtk_spi_of_match[] = {
136 { .compatible = "mediatek,mt2701-spi",
137 .data = (void *)&mtk_common_compat,
139 { .compatible = "mediatek,mt2712-spi",
140 .data = (void *)&mt2712_compat,
142 { .compatible = "mediatek,mt6589-spi",
143 .data = (void *)&mtk_common_compat,
145 { .compatible = "mediatek,mt7622-spi",
146 .data = (void *)&mt7622_compat,
148 { .compatible = "mediatek,mt8135-spi",
149 .data = (void *)&mtk_common_compat,
151 { .compatible = "mediatek,mt8173-spi",
152 .data = (void *)&mt8173_compat,
156 MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
158 static void mtk_spi_reset(struct mtk_spi *mdata)
162 /* set the software reset bit in SPI_CMD_REG. */
163 reg_val = readl(mdata->base + SPI_CMD_REG);
164 reg_val |= SPI_CMD_RST;
165 writel(reg_val, mdata->base + SPI_CMD_REG);
167 reg_val = readl(mdata->base + SPI_CMD_REG);
168 reg_val &= ~SPI_CMD_RST;
169 writel(reg_val, mdata->base + SPI_CMD_REG);
172 static int mtk_spi_prepare_message(struct spi_master *master,
173 struct spi_message *msg)
177 struct spi_device *spi = msg->spi;
178 struct mtk_chip_config *chip_config = spi->controller_data;
179 struct mtk_spi *mdata = spi_master_get_devdata(master);
181 cpha = spi->mode & SPI_CPHA ? 1 : 0;
182 cpol = spi->mode & SPI_CPOL ? 1 : 0;
184 reg_val = readl(mdata->base + SPI_CMD_REG);
186 reg_val |= SPI_CMD_CPHA;
188 reg_val &= ~SPI_CMD_CPHA;
190 reg_val |= SPI_CMD_CPOL;
192 reg_val &= ~SPI_CMD_CPOL;
194 /* set the mlsbx and mlsbtx */
195 if (chip_config->tx_mlsb)
196 reg_val |= SPI_CMD_TXMSBF;
198 reg_val &= ~SPI_CMD_TXMSBF;
199 if (chip_config->rx_mlsb)
200 reg_val |= SPI_CMD_RXMSBF;
202 reg_val &= ~SPI_CMD_RXMSBF;
204 /* set the tx/rx endian */
205 #ifdef __LITTLE_ENDIAN
206 reg_val &= ~SPI_CMD_TX_ENDIAN;
207 reg_val &= ~SPI_CMD_RX_ENDIAN;
209 reg_val |= SPI_CMD_TX_ENDIAN;
210 reg_val |= SPI_CMD_RX_ENDIAN;
213 if (mdata->dev_comp->enhance_timing) {
214 if (chip_config->cs_pol)
215 reg_val |= SPI_CMD_CS_POL;
217 reg_val &= ~SPI_CMD_CS_POL;
218 if (chip_config->sample_sel)
219 reg_val |= SPI_CMD_SAMPLE_SEL;
221 reg_val &= ~SPI_CMD_SAMPLE_SEL;
224 /* set finish and pause interrupt always enable */
225 reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;
227 /* disable dma mode */
228 reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
230 /* disable deassert mode */
231 reg_val &= ~SPI_CMD_DEASSERT;
233 writel(reg_val, mdata->base + SPI_CMD_REG);
236 if (mdata->dev_comp->need_pad_sel)
237 writel(mdata->pad_sel[spi->chip_select],
238 mdata->base + SPI_PAD_SEL_REG);
243 static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
246 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
248 reg_val = readl(mdata->base + SPI_CMD_REG);
250 reg_val |= SPI_CMD_PAUSE_EN;
251 writel(reg_val, mdata->base + SPI_CMD_REG);
253 reg_val &= ~SPI_CMD_PAUSE_EN;
254 writel(reg_val, mdata->base + SPI_CMD_REG);
255 mdata->state = MTK_SPI_IDLE;
256 mtk_spi_reset(mdata);
260 static void mtk_spi_prepare_transfer(struct spi_master *master,
261 struct spi_transfer *xfer)
263 u32 spi_clk_hz, div, sck_time, cs_time, reg_val;
264 struct mtk_spi *mdata = spi_master_get_devdata(master);
266 spi_clk_hz = clk_get_rate(mdata->spi_clk);
267 if (xfer->speed_hz < spi_clk_hz / 2)
268 div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz);
272 sck_time = (div + 1) / 2;
273 cs_time = sck_time * 2;
275 if (mdata->dev_comp->enhance_timing) {
276 reg_val = (((sck_time - 1) & 0xffff)
277 << SPI_CFG2_SCK_HIGH_OFFSET);
278 reg_val |= (((sck_time - 1) & 0xffff)
279 << SPI_CFG2_SCK_LOW_OFFSET);
280 writel(reg_val, mdata->base + SPI_CFG2_REG);
281 reg_val = (((cs_time - 1) & 0xffff)
282 << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
283 reg_val |= (((cs_time - 1) & 0xffff)
284 << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
285 writel(reg_val, mdata->base + SPI_CFG0_REG);
287 reg_val = (((sck_time - 1) & 0xff)
288 << SPI_CFG0_SCK_HIGH_OFFSET);
289 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
290 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
291 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET);
292 writel(reg_val, mdata->base + SPI_CFG0_REG);
295 reg_val = readl(mdata->base + SPI_CFG1_REG);
296 reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
297 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
298 writel(reg_val, mdata->base + SPI_CFG1_REG);
301 static void mtk_spi_setup_packet(struct spi_master *master)
303 u32 packet_size, packet_loop, reg_val;
304 struct mtk_spi *mdata = spi_master_get_devdata(master);
306 packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
307 packet_loop = mdata->xfer_len / packet_size;
309 reg_val = readl(mdata->base + SPI_CFG1_REG);
310 reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);
311 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
312 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
313 writel(reg_val, mdata->base + SPI_CFG1_REG);
316 static void mtk_spi_enable_transfer(struct spi_master *master)
319 struct mtk_spi *mdata = spi_master_get_devdata(master);
321 cmd = readl(mdata->base + SPI_CMD_REG);
322 if (mdata->state == MTK_SPI_IDLE)
325 cmd |= SPI_CMD_RESUME;
326 writel(cmd, mdata->base + SPI_CMD_REG);
329 static int mtk_spi_get_mult_delta(u32 xfer_len)
333 if (xfer_len > MTK_SPI_PACKET_SIZE)
334 mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
341 static void mtk_spi_update_mdata_len(struct spi_master *master)
344 struct mtk_spi *mdata = spi_master_get_devdata(master);
346 if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
347 if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
348 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
349 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
350 mdata->rx_sgl_len = mult_delta;
351 mdata->tx_sgl_len -= mdata->xfer_len;
353 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
354 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
355 mdata->tx_sgl_len = mult_delta;
356 mdata->rx_sgl_len -= mdata->xfer_len;
358 } else if (mdata->tx_sgl_len) {
359 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
360 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
361 mdata->tx_sgl_len = mult_delta;
362 } else if (mdata->rx_sgl_len) {
363 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
364 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
365 mdata->rx_sgl_len = mult_delta;
369 static void mtk_spi_setup_dma_addr(struct spi_master *master,
370 struct spi_transfer *xfer)
372 struct mtk_spi *mdata = spi_master_get_devdata(master);
375 writel(xfer->tx_dma, mdata->base + SPI_TX_SRC_REG);
377 writel(xfer->rx_dma, mdata->base + SPI_RX_DST_REG);
380 static int mtk_spi_fifo_transfer(struct spi_master *master,
381 struct spi_device *spi,
382 struct spi_transfer *xfer)
386 struct mtk_spi *mdata = spi_master_get_devdata(master);
388 mdata->cur_transfer = xfer;
389 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len);
390 mdata->num_xfered = 0;
391 mtk_spi_prepare_transfer(master, xfer);
392 mtk_spi_setup_packet(master);
396 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
397 remainder = xfer->len % 4;
400 memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder);
401 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
405 mtk_spi_enable_transfer(master);
410 static int mtk_spi_dma_transfer(struct spi_master *master,
411 struct spi_device *spi,
412 struct spi_transfer *xfer)
415 struct mtk_spi *mdata = spi_master_get_devdata(master);
417 mdata->tx_sgl = NULL;
418 mdata->rx_sgl = NULL;
419 mdata->tx_sgl_len = 0;
420 mdata->rx_sgl_len = 0;
421 mdata->cur_transfer = xfer;
422 mdata->num_xfered = 0;
424 mtk_spi_prepare_transfer(master, xfer);
426 cmd = readl(mdata->base + SPI_CMD_REG);
428 cmd |= SPI_CMD_TX_DMA;
430 cmd |= SPI_CMD_RX_DMA;
431 writel(cmd, mdata->base + SPI_CMD_REG);
434 mdata->tx_sgl = xfer->tx_sg.sgl;
436 mdata->rx_sgl = xfer->rx_sg.sgl;
439 xfer->tx_dma = sg_dma_address(mdata->tx_sgl);
440 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
443 xfer->rx_dma = sg_dma_address(mdata->rx_sgl);
444 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
447 mtk_spi_update_mdata_len(master);
448 mtk_spi_setup_packet(master);
449 mtk_spi_setup_dma_addr(master, xfer);
450 mtk_spi_enable_transfer(master);
455 static int mtk_spi_transfer_one(struct spi_master *master,
456 struct spi_device *spi,
457 struct spi_transfer *xfer)
459 if (master->can_dma(master, spi, xfer))
460 return mtk_spi_dma_transfer(master, spi, xfer);
462 return mtk_spi_fifo_transfer(master, spi, xfer);
465 static bool mtk_spi_can_dma(struct spi_master *master,
466 struct spi_device *spi,
467 struct spi_transfer *xfer)
469 /* Buffers for DMA transactions must be 4-byte aligned */
470 return (xfer->len > MTK_SPI_MAX_FIFO_SIZE &&
471 (unsigned long)xfer->tx_buf % 4 == 0 &&
472 (unsigned long)xfer->rx_buf % 4 == 0);
475 static int mtk_spi_setup(struct spi_device *spi)
477 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
479 if (!spi->controller_data)
480 spi->controller_data = (void *)&mtk_default_chip_info;
482 if (mdata->dev_comp->need_pad_sel && gpio_is_valid(spi->cs_gpio))
483 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
488 static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
490 u32 cmd, reg_val, cnt, remainder, len;
491 struct spi_master *master = dev_id;
492 struct mtk_spi *mdata = spi_master_get_devdata(master);
493 struct spi_transfer *trans = mdata->cur_transfer;
495 reg_val = readl(mdata->base + SPI_STATUS0_REG);
496 if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
497 mdata->state = MTK_SPI_PAUSED;
499 mdata->state = MTK_SPI_IDLE;
501 if (!master->can_dma(master, master->cur_msg->spi, trans)) {
503 cnt = mdata->xfer_len / 4;
504 ioread32_rep(mdata->base + SPI_RX_DATA_REG,
505 trans->rx_buf + mdata->num_xfered, cnt);
506 remainder = mdata->xfer_len % 4;
508 reg_val = readl(mdata->base + SPI_RX_DATA_REG);
509 memcpy(trans->rx_buf +
517 mdata->num_xfered += mdata->xfer_len;
518 if (mdata->num_xfered == trans->len) {
519 spi_finalize_current_transfer(master);
523 len = trans->len - mdata->num_xfered;
524 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len);
525 mtk_spi_setup_packet(master);
527 cnt = mdata->xfer_len / 4;
528 iowrite32_rep(mdata->base + SPI_TX_DATA_REG,
529 trans->tx_buf + mdata->num_xfered, cnt);
531 remainder = mdata->xfer_len % 4;
535 trans->tx_buf + (cnt * 4) + mdata->num_xfered,
537 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
540 mtk_spi_enable_transfer(master);
546 trans->tx_dma += mdata->xfer_len;
548 trans->rx_dma += mdata->xfer_len;
550 if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) {
551 mdata->tx_sgl = sg_next(mdata->tx_sgl);
553 trans->tx_dma = sg_dma_address(mdata->tx_sgl);
554 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
557 if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) {
558 mdata->rx_sgl = sg_next(mdata->rx_sgl);
560 trans->rx_dma = sg_dma_address(mdata->rx_sgl);
561 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
565 if (!mdata->tx_sgl && !mdata->rx_sgl) {
566 /* spi disable dma */
567 cmd = readl(mdata->base + SPI_CMD_REG);
568 cmd &= ~SPI_CMD_TX_DMA;
569 cmd &= ~SPI_CMD_RX_DMA;
570 writel(cmd, mdata->base + SPI_CMD_REG);
572 spi_finalize_current_transfer(master);
576 mtk_spi_update_mdata_len(master);
577 mtk_spi_setup_packet(master);
578 mtk_spi_setup_dma_addr(master, trans);
579 mtk_spi_enable_transfer(master);
584 static int mtk_spi_probe(struct platform_device *pdev)
586 struct spi_master *master;
587 struct mtk_spi *mdata;
588 const struct of_device_id *of_id;
589 struct resource *res;
592 master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
594 dev_err(&pdev->dev, "failed to alloc spi master\n");
598 master->auto_runtime_pm = true;
599 master->dev.of_node = pdev->dev.of_node;
600 master->mode_bits = SPI_CPOL | SPI_CPHA;
602 master->set_cs = mtk_spi_set_cs;
603 master->prepare_message = mtk_spi_prepare_message;
604 master->transfer_one = mtk_spi_transfer_one;
605 master->can_dma = mtk_spi_can_dma;
606 master->setup = mtk_spi_setup;
608 of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
610 dev_err(&pdev->dev, "failed to probe of_node\n");
615 mdata = spi_master_get_devdata(master);
616 mdata->dev_comp = of_id->data;
617 if (mdata->dev_comp->must_tx)
618 master->flags = SPI_MASTER_MUST_TX;
620 if (mdata->dev_comp->need_pad_sel) {
621 mdata->pad_num = of_property_count_u32_elems(
623 "mediatek,pad-select");
624 if (mdata->pad_num < 0) {
626 "No 'mediatek,pad-select' property\n");
631 mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num,
632 sizeof(u32), GFP_KERNEL);
633 if (!mdata->pad_sel) {
638 for (i = 0; i < mdata->pad_num; i++) {
639 of_property_read_u32_index(pdev->dev.of_node,
640 "mediatek,pad-select",
641 i, &mdata->pad_sel[i]);
642 if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) {
643 dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n",
644 i, mdata->pad_sel[i]);
651 platform_set_drvdata(pdev, master);
653 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
656 dev_err(&pdev->dev, "failed to determine base address\n");
660 mdata->base = devm_ioremap_resource(&pdev->dev, res);
661 if (IS_ERR(mdata->base)) {
662 ret = PTR_ERR(mdata->base);
666 irq = platform_get_irq(pdev, 0);
668 dev_err(&pdev->dev, "failed to get irq (%d)\n", irq);
673 if (!pdev->dev.dma_mask)
674 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
676 ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt,
677 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master);
679 dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
683 mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
684 if (IS_ERR(mdata->parent_clk)) {
685 ret = PTR_ERR(mdata->parent_clk);
686 dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret);
690 mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk");
691 if (IS_ERR(mdata->sel_clk)) {
692 ret = PTR_ERR(mdata->sel_clk);
693 dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret);
697 mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
698 if (IS_ERR(mdata->spi_clk)) {
699 ret = PTR_ERR(mdata->spi_clk);
700 dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
704 ret = clk_prepare_enable(mdata->spi_clk);
706 dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
710 ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
712 dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
713 clk_disable_unprepare(mdata->spi_clk);
717 clk_disable_unprepare(mdata->spi_clk);
719 pm_runtime_enable(&pdev->dev);
721 ret = devm_spi_register_master(&pdev->dev, master);
723 dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
724 goto err_disable_runtime_pm;
727 if (mdata->dev_comp->need_pad_sel) {
728 if (mdata->pad_num != master->num_chipselect) {
730 "pad_num does not match num_chipselect(%d != %d)\n",
731 mdata->pad_num, master->num_chipselect);
733 goto err_disable_runtime_pm;
736 if (!master->cs_gpios && master->num_chipselect > 1) {
738 "cs_gpios not specified and num_chipselect > 1\n");
740 goto err_disable_runtime_pm;
743 if (master->cs_gpios) {
744 for (i = 0; i < master->num_chipselect; i++) {
745 ret = devm_gpio_request(&pdev->dev,
747 dev_name(&pdev->dev));
750 "can't get CS GPIO %i\n", i);
751 goto err_disable_runtime_pm;
759 err_disable_runtime_pm:
760 pm_runtime_disable(&pdev->dev);
762 spi_master_put(master);
767 static int mtk_spi_remove(struct platform_device *pdev)
769 struct spi_master *master = platform_get_drvdata(pdev);
770 struct mtk_spi *mdata = spi_master_get_devdata(master);
772 pm_runtime_disable(&pdev->dev);
774 mtk_spi_reset(mdata);
779 #ifdef CONFIG_PM_SLEEP
780 static int mtk_spi_suspend(struct device *dev)
783 struct spi_master *master = dev_get_drvdata(dev);
784 struct mtk_spi *mdata = spi_master_get_devdata(master);
786 ret = spi_master_suspend(master);
790 if (!pm_runtime_suspended(dev))
791 clk_disable_unprepare(mdata->spi_clk);
796 static int mtk_spi_resume(struct device *dev)
799 struct spi_master *master = dev_get_drvdata(dev);
800 struct mtk_spi *mdata = spi_master_get_devdata(master);
802 if (!pm_runtime_suspended(dev)) {
803 ret = clk_prepare_enable(mdata->spi_clk);
805 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
810 ret = spi_master_resume(master);
812 clk_disable_unprepare(mdata->spi_clk);
816 #endif /* CONFIG_PM_SLEEP */
819 static int mtk_spi_runtime_suspend(struct device *dev)
821 struct spi_master *master = dev_get_drvdata(dev);
822 struct mtk_spi *mdata = spi_master_get_devdata(master);
824 clk_disable_unprepare(mdata->spi_clk);
829 static int mtk_spi_runtime_resume(struct device *dev)
831 struct spi_master *master = dev_get_drvdata(dev);
832 struct mtk_spi *mdata = spi_master_get_devdata(master);
835 ret = clk_prepare_enable(mdata->spi_clk);
837 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
843 #endif /* CONFIG_PM */
845 static const struct dev_pm_ops mtk_spi_pm = {
846 SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume)
847 SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend,
848 mtk_spi_runtime_resume, NULL)
851 static struct platform_driver mtk_spi_driver = {
855 .of_match_table = mtk_spi_of_match,
857 .probe = mtk_spi_probe,
858 .remove = mtk_spi_remove,
861 module_platform_driver(mtk_spi_driver);
863 MODULE_DESCRIPTION("MTK SPI Controller driver");
864 MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
865 MODULE_LICENSE("GPL v2");
866 MODULE_ALIAS("platform:mtk-spi");