1 // SPDX-License-Identifier: GPL-2.0-only
3 * MPC52xx SPI bus driver.
5 * Copyright (C) 2008 Secret Lab Technologies Ltd.
7 * This is the driver for the MPC5200's dedicated SPI controller.
9 * Note: this driver does not support the MPC5200 PSC in SPI mode. For
10 * that driver see drivers/spi/mpc52xx_psc_spi.c
13 #include <linux/module.h>
14 #include <linux/errno.h>
15 #include <linux/of_platform.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/spi/spi.h>
20 #include <linux/of_gpio.h>
21 #include <linux/slab.h>
22 #include <linux/of_address.h>
23 #include <linux/of_irq.h>
26 #include <asm/mpc52xx.h>
28 MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
29 MODULE_DESCRIPTION("MPC52xx SPI (non-PSC) Driver");
30 MODULE_LICENSE("GPL");
32 /* Register offsets */
33 #define SPI_CTRL1 0x00
34 #define SPI_CTRL1_SPIE (1 << 7)
35 #define SPI_CTRL1_SPE (1 << 6)
36 #define SPI_CTRL1_MSTR (1 << 4)
37 #define SPI_CTRL1_CPOL (1 << 3)
38 #define SPI_CTRL1_CPHA (1 << 2)
39 #define SPI_CTRL1_SSOE (1 << 1)
40 #define SPI_CTRL1_LSBFE (1 << 0)
42 #define SPI_CTRL2 0x01
45 #define SPI_STATUS 0x05
46 #define SPI_STATUS_SPIF (1 << 7)
47 #define SPI_STATUS_WCOL (1 << 6)
48 #define SPI_STATUS_MODF (1 << 4)
51 #define SPI_PORTDATA 0x0d
52 #define SPI_DATADIR 0x10
54 /* FSM state return values */
55 #define FSM_STOP 0 /* Nothing more for the state machine to */
56 /* do. If something interesting happens */
57 /* then an IRQ will be received */
58 #define FSM_POLL 1 /* need to poll for completion, an IRQ is */
60 #define FSM_CONTINUE 2 /* Keep iterating the state machine */
62 /* Driver internal data */
64 struct spi_master *master;
66 int irq0; /* MODF irq */
67 int irq1; /* SPIF irq */
68 unsigned int ipb_freq;
70 /* Statistics; not used now, but will be reintroduced for debugfs */
74 u32 wcol_tx_timestamp;
78 struct list_head queue; /* queue of pending messages */
80 struct work_struct work;
82 /* Details of current transfer (length, and buffer pointers) */
83 struct spi_message *message; /* current message */
84 struct spi_transfer *transfer; /* current transfer */
85 int (*state)(int irq, struct mpc52xx_spi *ms, u8 status, u8 data);
92 unsigned int *gpio_cs;
98 static void mpc52xx_spi_chipsel(struct mpc52xx_spi *ms, int value)
102 if (ms->gpio_cs_count > 0) {
103 cs = ms->message->spi->chip_select;
104 gpio_set_value(ms->gpio_cs[cs], value ? 0 : 1);
106 out_8(ms->regs + SPI_PORTDATA, value ? 0 : 0x08);
110 * Start a new transfer. This is called both by the idle state
111 * for the first transfer in a message, and by the wait state when the
112 * previous transfer in a message is complete.
114 static void mpc52xx_spi_start_transfer(struct mpc52xx_spi *ms)
116 ms->rx_buf = ms->transfer->rx_buf;
117 ms->tx_buf = ms->transfer->tx_buf;
118 ms->len = ms->transfer->len;
120 /* Activate the chip select */
122 mpc52xx_spi_chipsel(ms, 1);
123 ms->cs_change = ms->transfer->cs_change;
125 /* Write out the first byte */
126 ms->wcol_tx_timestamp = mftb();
128 out_8(ms->regs + SPI_DATA, *ms->tx_buf++);
130 out_8(ms->regs + SPI_DATA, 0);
133 /* Forward declaration of state handlers */
134 static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms,
136 static int mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms,
142 * No transfers are in progress; if another transfer is pending then retrieve
143 * it and kick it off. Otherwise, stop processing the state machine
146 mpc52xx_spi_fsmstate_idle(int irq, struct mpc52xx_spi *ms, u8 status, u8 data)
148 struct spi_device *spi;
152 if (status && (irq != NO_IRQ))
153 dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n",
156 /* Check if there is another transfer waiting. */
157 if (list_empty(&ms->queue))
160 /* get the head of the queue */
161 ms->message = list_first_entry(&ms->queue, struct spi_message, queue);
162 list_del_init(&ms->message->queue);
164 /* Setup the controller parameters */
165 ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR;
166 spi = ms->message->spi;
167 if (spi->mode & SPI_CPHA)
168 ctrl1 |= SPI_CTRL1_CPHA;
169 if (spi->mode & SPI_CPOL)
170 ctrl1 |= SPI_CTRL1_CPOL;
171 if (spi->mode & SPI_LSB_FIRST)
172 ctrl1 |= SPI_CTRL1_LSBFE;
173 out_8(ms->regs + SPI_CTRL1, ctrl1);
175 /* Setup the controller speed */
176 /* minimum divider is '2'. Also, add '1' to force rounding the
178 sppr = ((ms->ipb_freq / ms->message->spi->max_speed_hz) + 1) >> 1;
182 while (((sppr - 1) & ~0x7) != 0) {
183 sppr = (sppr + 1) >> 1; /* add '1' to force rounding up */
186 sppr--; /* sppr quantity in register is offset by 1 */
188 /* Don't overrun limits of SPI baudrate register */
192 out_8(ms->regs + SPI_BRR, sppr << 4 | spr); /* Set speed */
195 ms->transfer = container_of(ms->message->transfers.next,
196 struct spi_transfer, transfer_list);
198 mpc52xx_spi_start_transfer(ms);
199 ms->state = mpc52xx_spi_fsmstate_transfer;
207 * In the middle of a transfer. If the SPI core has completed processing
208 * a byte, then read out the received data and write out the next byte
209 * (unless this transfer is finished; in which case go on to the wait
212 static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms,
216 return ms->irq0 ? FSM_STOP : FSM_POLL;
218 if (status & SPI_STATUS_WCOL) {
219 /* The SPI controller is stoopid. At slower speeds, it may
220 * raise the SPIF flag before the state machine is actually
221 * finished, which causes a collision (internal to the state
222 * machine only). The manual recommends inserting a delay
223 * between receiving the interrupt and sending the next byte,
224 * but it can also be worked around simply by retrying the
225 * transfer which is what we do here. */
227 ms->wcol_ticks += mftb() - ms->wcol_tx_timestamp;
228 ms->wcol_tx_timestamp = mftb();
231 data = *(ms->tx_buf - 1);
232 out_8(ms->regs + SPI_DATA, data); /* try again */
234 } else if (status & SPI_STATUS_MODF) {
236 dev_err(&ms->master->dev, "mode fault\n");
237 mpc52xx_spi_chipsel(ms, 0);
238 ms->message->status = -EIO;
239 if (ms->message->complete)
240 ms->message->complete(ms->message->context);
241 ms->state = mpc52xx_spi_fsmstate_idle;
245 /* Read data out of the spi device */
248 *ms->rx_buf++ = data;
250 /* Is the transfer complete? */
253 ms->timestamp = mftb();
254 if (ms->transfer->delay.unit == SPI_DELAY_UNIT_USECS)
255 ms->timestamp += ms->transfer->delay.value *
257 ms->state = mpc52xx_spi_fsmstate_wait;
261 /* Write out the next byte */
262 ms->wcol_tx_timestamp = mftb();
264 out_8(ms->regs + SPI_DATA, *ms->tx_buf++);
266 out_8(ms->regs + SPI_DATA, 0);
274 * A transfer has completed; need to wait for the delay period to complete
275 * before starting the next transfer
278 mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms, u8 status, u8 data)
281 dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n",
284 if (((int)mftb()) - ms->timestamp < 0)
287 ms->message->actual_length += ms->transfer->len;
289 /* Check if there is another transfer in this message. If there
290 * aren't then deactivate CS, notify sender, and drop back to idle
291 * to start the next message. */
292 if (ms->transfer->transfer_list.next == &ms->message->transfers) {
294 mpc52xx_spi_chipsel(ms, 0);
295 ms->message->status = 0;
296 if (ms->message->complete)
297 ms->message->complete(ms->message->context);
298 ms->state = mpc52xx_spi_fsmstate_idle;
302 /* There is another transfer; kick it off */
305 mpc52xx_spi_chipsel(ms, 0);
307 ms->transfer = container_of(ms->transfer->transfer_list.next,
308 struct spi_transfer, transfer_list);
309 mpc52xx_spi_start_transfer(ms);
310 ms->state = mpc52xx_spi_fsmstate_transfer;
315 * mpc52xx_spi_fsm_process - Finite State Machine iteration function
316 * @irq: irq number that triggered the FSM or 0 for polling
317 * @ms: pointer to mpc52xx_spi driver data
319 static void mpc52xx_spi_fsm_process(int irq, struct mpc52xx_spi *ms)
321 int rc = FSM_CONTINUE;
324 while (rc == FSM_CONTINUE) {
325 /* Interrupt cleared by read of STATUS followed by
326 * read of DATA registers */
327 status = in_8(ms->regs + SPI_STATUS);
328 data = in_8(ms->regs + SPI_DATA);
329 rc = ms->state(irq, ms, status, data);
333 schedule_work(&ms->work);
337 * mpc52xx_spi_irq - IRQ handler
339 static irqreturn_t mpc52xx_spi_irq(int irq, void *_ms)
341 struct mpc52xx_spi *ms = _ms;
342 spin_lock(&ms->lock);
343 mpc52xx_spi_fsm_process(irq, ms);
344 spin_unlock(&ms->lock);
349 * mpc52xx_spi_wq - Workqueue function for polling the state machine
351 static void mpc52xx_spi_wq(struct work_struct *work)
353 struct mpc52xx_spi *ms = container_of(work, struct mpc52xx_spi, work);
356 spin_lock_irqsave(&ms->lock, flags);
357 mpc52xx_spi_fsm_process(0, ms);
358 spin_unlock_irqrestore(&ms->lock, flags);
365 static int mpc52xx_spi_transfer(struct spi_device *spi, struct spi_message *m)
367 struct mpc52xx_spi *ms = spi_master_get_devdata(spi->master);
370 m->actual_length = 0;
371 m->status = -EINPROGRESS;
373 spin_lock_irqsave(&ms->lock, flags);
374 list_add_tail(&m->queue, &ms->queue);
375 spin_unlock_irqrestore(&ms->lock, flags);
376 schedule_work(&ms->work);
382 * OF Platform Bus Binding
384 static int mpc52xx_spi_probe(struct platform_device *op)
386 struct spi_master *master;
387 struct mpc52xx_spi *ms;
394 dev_dbg(&op->dev, "probing mpc5200 SPI device\n");
395 regs = of_iomap(op->dev.of_node, 0);
399 /* initialize the device */
400 ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR;
401 out_8(regs + SPI_CTRL1, ctrl1);
402 out_8(regs + SPI_CTRL2, 0x0);
403 out_8(regs + SPI_DATADIR, 0xe); /* Set output pins */
404 out_8(regs + SPI_PORTDATA, 0x8); /* Deassert /SS signal */
406 /* Clear the status register and re-read it to check for a MODF
407 * failure. This driver cannot currently handle multiple masters
408 * on the SPI bus. This fault will also occur if the SPI signals
409 * are not connected to any pins (port_config setting) */
410 in_8(regs + SPI_STATUS);
411 out_8(regs + SPI_CTRL1, ctrl1);
413 in_8(regs + SPI_DATA);
414 if (in_8(regs + SPI_STATUS) & SPI_STATUS_MODF) {
415 dev_err(&op->dev, "mode fault; is port_config correct?\n");
420 dev_dbg(&op->dev, "allocating spi_master struct\n");
421 master = spi_alloc_master(&op->dev, sizeof(*ms));
427 master->transfer = mpc52xx_spi_transfer;
428 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
429 master->bits_per_word_mask = SPI_BPW_MASK(8);
430 master->dev.of_node = op->dev.of_node;
432 platform_set_drvdata(op, master);
434 ms = spi_master_get_devdata(master);
437 ms->irq0 = irq_of_parse_and_map(op->dev.of_node, 0);
438 ms->irq1 = irq_of_parse_and_map(op->dev.of_node, 1);
439 ms->state = mpc52xx_spi_fsmstate_idle;
440 ms->ipb_freq = mpc5xxx_get_bus_frequency(op->dev.of_node);
441 ms->gpio_cs_count = of_gpio_count(op->dev.of_node);
442 if (ms->gpio_cs_count > 0) {
443 master->num_chipselect = ms->gpio_cs_count;
444 ms->gpio_cs = kmalloc_array(ms->gpio_cs_count,
445 sizeof(*ms->gpio_cs),
452 for (i = 0; i < ms->gpio_cs_count; i++) {
453 gpio_cs = of_get_gpio(op->dev.of_node, i);
454 if (!gpio_is_valid(gpio_cs)) {
456 "could not parse the gpio field in oftree\n");
461 rc = gpio_request(gpio_cs, dev_name(&op->dev));
464 "can't request spi cs gpio #%d on gpio line %d\n",
469 gpio_direction_output(gpio_cs, 1);
470 ms->gpio_cs[i] = gpio_cs;
474 spin_lock_init(&ms->lock);
475 INIT_LIST_HEAD(&ms->queue);
476 INIT_WORK(&ms->work, mpc52xx_spi_wq);
478 /* Decide if interrupts can be used */
479 if (ms->irq0 && ms->irq1) {
480 rc = request_irq(ms->irq0, mpc52xx_spi_irq, 0,
481 "mpc5200-spi-modf", ms);
482 rc |= request_irq(ms->irq1, mpc52xx_spi_irq, 0,
483 "mpc5200-spi-spif", ms);
485 free_irq(ms->irq0, ms);
486 free_irq(ms->irq1, ms);
487 ms->irq0 = ms->irq1 = 0;
490 /* operate in polled mode */
491 ms->irq0 = ms->irq1 = 0;
495 dev_info(&op->dev, "using polled mode\n");
497 dev_dbg(&op->dev, "registering spi_master struct\n");
498 rc = spi_register_master(master);
502 dev_info(&ms->master->dev, "registered MPC5200 SPI bus\n");
507 dev_err(&ms->master->dev, "initialization failed\n");
510 gpio_free(ms->gpio_cs[i]);
514 spi_master_put(master);
521 static int mpc52xx_spi_remove(struct platform_device *op)
523 struct spi_master *master = spi_master_get(platform_get_drvdata(op));
524 struct mpc52xx_spi *ms = spi_master_get_devdata(master);
527 free_irq(ms->irq0, ms);
528 free_irq(ms->irq1, ms);
530 for (i = 0; i < ms->gpio_cs_count; i++)
531 gpio_free(ms->gpio_cs[i]);
534 spi_unregister_master(master);
536 spi_master_put(master);
541 static const struct of_device_id mpc52xx_spi_match[] = {
542 { .compatible = "fsl,mpc5200-spi", },
545 MODULE_DEVICE_TABLE(of, mpc52xx_spi_match);
547 static struct platform_driver mpc52xx_spi_of_driver = {
549 .name = "mpc52xx-spi",
550 .of_match_table = mpc52xx_spi_match,
552 .probe = mpc52xx_spi_probe,
553 .remove = mpc52xx_spi_remove,
555 module_platform_driver(mpc52xx_spi_of_driver);