drivers/spi/spi-mpc52xx-psc.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * MPC52xx PSC in SPI mode driver.
   4  *
   5  * Maintainer: Dragos Carp
   6  *
   7  * Copyright (C) 2006 TOPTICA Photonics AG.
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/types.h>
  12 #include <linux/errno.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/of_address.h>
  15 #include <linux/of_platform.h>
  16 #include <linux/workqueue.h>
  17 #include <linux/completion.h>
  18 #include <linux/io.h>
  19 #include <linux/delay.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/fsl_devices.h>
  22 #include <linux/slab.h>
  23 #include <linux/of_irq.h>
  24
  25 #include <asm/mpc52xx.h>
  26 #include <asm/mpc52xx_psc.h>
  27
  28 #define MCLK 20000000 /* PSC port MClk in hz */
  29
  30 struct mpc52xx_psc_spi {
  31         /* fsl_spi_platform data */
  32         void (*cs_control)(struct spi_device *spi, bool on);
  33         u32 sysclk;
  34
  35         /* driver internal data */
  36         struct mpc52xx_psc __iomem *psc;
  37         struct mpc52xx_psc_fifo __iomem *fifo;
  38         unsigned int irq;
  39         u8 bits_per_word;
  40         u8 busy;
  41
  42         struct work_struct work;
  43
  44         struct list_head queue;
  45         spinlock_t lock;
  46
  47         struct completion done;
  48 };
  49
  50 /* controller state */
  51 struct mpc52xx_psc_spi_cs {
  52         int bits_per_word;
  53         int speed_hz;
  54 };
  55
  56 /* set clock freq, clock ramp, bits per work
  57  * if t is NULL then reset the values to the default values
  58  */
  59 static int mpc52xx_psc_spi_transfer_setup(struct spi_device *spi,
  60                 struct spi_transfer *t)
  61 {
  62         struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
  63
  64         cs->speed_hz = (t && t->speed_hz)
  65                         ? t->speed_hz : spi->max_speed_hz;
  66         cs->bits_per_word = (t && t->bits_per_word)
  67                         ? t->bits_per_word : spi->bits_per_word;
  68         cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
  69         return 0;
  70 }
  71
  72 static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
  73 {
  74         struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
  75         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
  76         struct mpc52xx_psc __iomem *psc = mps->psc;
  77         u32 sicr;
  78         u16 ccr;
  79
  80         sicr = in_be32(&psc->sicr);
  81
  82         /* Set clock phase and polarity */
  83         if (spi->mode & SPI_CPHA)
  84                 sicr |= 0x00001000;
  85         else
  86                 sicr &= ~0x00001000;
  87         if (spi->mode & SPI_CPOL)
  88                 sicr |= 0x00002000;
  89         else
  90                 sicr &= ~0x00002000;
  91
  92         if (spi->mode & SPI_LSB_FIRST)
  93                 sicr |= 0x10000000;
  94         else
  95                 sicr &= ~0x10000000;
  96         out_be32(&psc->sicr, sicr);
  97
  98         /* Set clock frequency and bits per word
  99          * Because psc->ccr is defined as 16bit register instead of 32bit
 100          * just set the lower byte of BitClkDiv
 101          */
 102         ccr = in_be16((u16 __iomem *)&psc->ccr);
 103         ccr &= 0xFF00;
 104         if (cs->speed_hz)
 105                 ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
 106         else /* by default SPI Clk 1MHz */
 107                 ccr |= (MCLK / 1000000 - 1) & 0xFF;
 108         out_be16((u16 __iomem *)&psc->ccr, ccr);
 109         mps->bits_per_word = cs->bits_per_word;
 110
 111         if (mps->cs_control)
 112                 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
 113 }
 114
 115 static void mpc52xx_psc_spi_deactivate_cs(struct spi_device *spi)
 116 {
 117         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
 118
 119         if (mps->cs_control)
 120                 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
 121 }
 122
 123 #define MPC52xx_PSC_BUFSIZE (MPC52xx_PSC_RFNUM_MASK + 1)
 124 /* wake up when 80% fifo full */
 125 #define MPC52xx_PSC_RFALARM (MPC52xx_PSC_BUFSIZE * 20 / 100)
 126
 127 static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi,
 128                                                 struct spi_transfer *t)
 129 {
 130         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
 131         struct mpc52xx_psc __iomem *psc = mps->psc;
 132         struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
 133         unsigned rb = 0;        /* number of bytes receieved */
 134         unsigned sb = 0;        /* number of bytes sent */
 135         unsigned char *rx_buf = (unsigned char *)t->rx_buf;
 136         unsigned char *tx_buf = (unsigned char *)t->tx_buf;
 137         unsigned rfalarm;
 138         unsigned send_at_once = MPC52xx_PSC_BUFSIZE;
 139         unsigned recv_at_once;
 140         int last_block = 0;
 141
 142         if (!t->tx_buf && !t->rx_buf && t->len)
 143                 return -EINVAL;
 144
 145         /* enable transmiter/receiver */
 146         out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
 147         while (rb < t->len) {
 148                 if (t->len - rb > MPC52xx_PSC_BUFSIZE) {
 149                         rfalarm = MPC52xx_PSC_RFALARM;
 150                         last_block = 0;
 151                 } else {
 152                         send_at_once = t->len - sb;
 153                         rfalarm = MPC52xx_PSC_BUFSIZE - (t->len - rb);
 154                         last_block = 1;
 155                 }
 156
 157                 dev_dbg(&spi->dev, "send %d bytes...\n", send_at_once);
 158                 for (; send_at_once; sb++, send_at_once--) {
 159                         /* set EOF flag before the last word is sent */
 160                         if (send_at_once == 1 && last_block)
 161                                 out_8(&psc->ircr2, 0x01);
 162
 163                         if (tx_buf)
 164                                 out_8(&psc->mpc52xx_psc_buffer_8, tx_buf[sb]);
 165                         else
 166                                 out_8(&psc->mpc52xx_psc_buffer_8, 0);
 167                 }
 168
 169
 170                 /* enable interrupts and wait for wake up
 171                  * if just one byte is expected the Rx FIFO genererates no
 172                  * FFULL interrupt, so activate the RxRDY interrupt
 173                  */
 174                 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
 175                 if (t->len - rb == 1) {
 176                         out_8(&psc->mode, 0);
 177                 } else {
 178                         out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
 179                         out_be16(&fifo->rfalarm, rfalarm);
 180                 }
 181                 out_be16(&psc->mpc52xx_psc_imr, MPC52xx_PSC_IMR_RXRDY);
 182                 wait_for_completion(&mps->done);
 183                 recv_at_once = in_be16(&fifo->rfnum);
 184                 dev_dbg(&spi->dev, "%d bytes received\n", recv_at_once);
 185
 186                 send_at_once = recv_at_once;
 187                 if (rx_buf) {
 188                         for (; recv_at_once; rb++, recv_at_once--)
 189                                 rx_buf[rb] = in_8(&psc->mpc52xx_psc_buffer_8);
 190                 } else {
 191                         for (; recv_at_once; rb++, recv_at_once--)
 192                                 in_8(&psc->mpc52xx_psc_buffer_8);
 193                 }
 194         }
 195         /* disable transmiter/receiver */
 196         out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
 197
 198         return 0;
 199 }
 200
 201 static void mpc52xx_psc_spi_work(struct work_struct *work)
 202 {
 203         struct mpc52xx_psc_spi *mps =
 204                 container_of(work, struct mpc52xx_psc_spi, work);
 205
 206         spin_lock_irq(&mps->lock);
 207         mps->busy = 1;
 208         while (!list_empty(&mps->queue)) {
 209                 struct spi_message *m;
 210                 struct spi_device *spi;
 211                 struct spi_transfer *t = NULL;
 212                 unsigned cs_change;
 213                 int status;
 214
 215                 m = container_of(mps->queue.next, struct spi_message, queue);
 216                 list_del_init(&m->queue);
 217                 spin_unlock_irq(&mps->lock);
 218
 219                 spi = m->spi;
 220                 cs_change = 1;
 221                 status = 0;
 222                 list_for_each_entry (t, &m->transfers, transfer_list) {
 223                         if (t->bits_per_word || t->speed_hz) {
 224                                 status = mpc52xx_psc_spi_transfer_setup(spi, t);
 225                                 if (status < 0)
 226                                         break;
 227                         }
 228
 229                         if (cs_change)
 230                                 mpc52xx_psc_spi_activate_cs(spi);
 231                         cs_change = t->cs_change;
 232
 233                         status = mpc52xx_psc_spi_transfer_rxtx(spi, t);
 234                         if (status)
 235                                 break;
 236                         m->actual_length += t->len;
 237
 238                         spi_transfer_delay_exec(t);
 239
 240                         if (cs_change)
 241                                 mpc52xx_psc_spi_deactivate_cs(spi);
 242                 }
 243
 244                 m->status = status;
 245                 if (m->complete)
 246                         m->complete(m->context);
 247
 248                 if (status || !cs_change)
 249                         mpc52xx_psc_spi_deactivate_cs(spi);
 250
 251                 mpc52xx_psc_spi_transfer_setup(spi, NULL);
 252
 253                 spin_lock_irq(&mps->lock);
 254         }
 255         mps->busy = 0;
 256         spin_unlock_irq(&mps->lock);
 257 }
 258
 259 static int mpc52xx_psc_spi_setup(struct spi_device *spi)
 260 {
 261         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
 262         struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
 263         unsigned long flags;
 264
 265         if (spi->bits_per_word%8)
 266                 return -EINVAL;
 267
 268         if (!cs) {
 269                 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 270                 if (!cs)
 271                         return -ENOMEM;
 272                 spi->controller_state = cs;
 273         }
 274
 275         cs->bits_per_word = spi->bits_per_word;
 276         cs->speed_hz = spi->max_speed_hz;
 277
 278         spin_lock_irqsave(&mps->lock, flags);
 279         if (!mps->busy)
 280                 mpc52xx_psc_spi_deactivate_cs(spi);
 281         spin_unlock_irqrestore(&mps->lock, flags);
 282
 283         return 0;
 284 }
 285
 286 static int mpc52xx_psc_spi_transfer(struct spi_device *spi,
 287                 struct spi_message *m)
 288 {
 289         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
 290         unsigned long flags;
 291
 292         m->actual_length = 0;
 293         m->status = -EINPROGRESS;
 294
 295         spin_lock_irqsave(&mps->lock, flags);
 296         list_add_tail(&m->queue, &mps->queue);
 297         schedule_work(&mps->work);
 298         spin_unlock_irqrestore(&mps->lock, flags);
 299
 300         return 0;
 301 }
 302
 303 static void mpc52xx_psc_spi_cleanup(struct spi_device *spi)
 304 {
 305         kfree(spi->controller_state);
 306 }
 307
 308 static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
 309 {
 310         struct mpc52xx_psc __iomem *psc = mps->psc;
 311         struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
 312         u32 mclken_div;
 313         int ret;
 314
 315         /* default sysclk is 512MHz */
 316         mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK;
 317         ret = mpc52xx_set_psc_clkdiv(psc_id, mclken_div);
 318         if (ret)
 319                 return ret;
 320
 321         /* Reset the PSC into a known state */
 322         out_8(&psc->command, MPC52xx_PSC_RST_RX);
 323         out_8(&psc->command, MPC52xx_PSC_RST_TX);
 324         out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
 325
 326         /* Disable interrupts, interrupts are based on alarm level */
 327         out_be16(&psc->mpc52xx_psc_imr, 0);
 328         out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
 329         out_8(&fifo->rfcntl, 0);
 330         out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
 331
 332         /* Configure 8bit codec mode as a SPI master and use EOF flags */
 333         /* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */
 334         out_be32(&psc->sicr, 0x0180C800);
 335         out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */
 336
 337         /* Set 2ms DTL delay */
 338         out_8(&psc->ctur, 0x00);
 339         out_8(&psc->ctlr, 0x84);
 340
 341         mps->bits_per_word = 8;
 342
 343         return 0;
 344 }
 345
 346 static irqreturn_t mpc52xx_psc_spi_isr(int irq, void *dev_id)
 347 {
 348         struct mpc52xx_psc_spi *mps = (struct mpc52xx_psc_spi *)dev_id;
 349         struct mpc52xx_psc __iomem *psc = mps->psc;
 350
 351         /* disable interrupt and wake up the work queue */
 352         if (in_be16(&psc->mpc52xx_psc_isr) & MPC52xx_PSC_IMR_RXRDY) {
 353                 out_be16(&psc->mpc52xx_psc_imr, 0);
 354                 complete(&mps->done);
 355                 return IRQ_HANDLED;
 356         }
 357         return IRQ_NONE;
 358 }
 359
 360 /* bus_num is used only for the case dev->platform_data == NULL */
 361 static int mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr,
 362                                 u32 size, unsigned int irq, s16 bus_num)
 363 {
 364         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 365         struct mpc52xx_psc_spi *mps;
 366         struct spi_master *master;
 367         int ret;
 368
 369         master = spi_alloc_master(dev, sizeof(*mps));
 370         if (master == NULL)
 371                 return -ENOMEM;
 372
 373         dev_set_drvdata(dev, master);
 374         mps = spi_master_get_devdata(master);
 375
 376         /* the spi->mode bits understood by this driver: */
 377         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
 378
 379         mps->irq = irq;
 380         if (pdata == NULL) {
 381                 dev_warn(dev,
 382                          "probe called without platform data, no cs_control function will be called\n");
 383                 mps->cs_control = NULL;
 384                 mps->sysclk = 0;
 385                 master->bus_num = bus_num;
 386                 master->num_chipselect = 255;
 387         } else {
 388                 mps->cs_control = pdata->cs_control;
 389                 mps->sysclk = pdata->sysclk;
 390                 master->bus_num = pdata->bus_num;
 391                 master->num_chipselect = pdata->max_chipselect;
 392         }
 393         master->setup = mpc52xx_psc_spi_setup;
 394         master->transfer = mpc52xx_psc_spi_transfer;
 395         master->cleanup = mpc52xx_psc_spi_cleanup;
 396         master->dev.of_node = dev->of_node;
 397
 398         mps->psc = ioremap(regaddr, size);
 399         if (!mps->psc) {
 400                 dev_err(dev, "could not ioremap I/O port range\n");
 401                 ret = -EFAULT;
 402                 goto free_master;
 403         }
 404         /* On the 5200, fifo regs are immediately ajacent to the psc regs */
 405         mps->fifo = ((void __iomem *)mps->psc) + sizeof(struct mpc52xx_psc);
 406
 407         ret = request_irq(mps->irq, mpc52xx_psc_spi_isr, 0, "mpc52xx-psc-spi",
 408                                 mps);
 409         if (ret)
 410                 goto free_master;
 411
 412         ret = mpc52xx_psc_spi_port_config(master->bus_num, mps);
 413         if (ret < 0) {
 414                 dev_err(dev, "can't configure PSC! Is it capable of SPI?\n");
 415                 goto free_irq;
 416         }
 417
 418         spin_lock_init(&mps->lock);
 419         init_completion(&mps->done);
 420         INIT_WORK(&mps->work, mpc52xx_psc_spi_work);
 421         INIT_LIST_HEAD(&mps->queue);
 422
 423         ret = spi_register_master(master);
 424         if (ret < 0)
 425                 goto free_irq;
 426
 427         return ret;
 428
 429 free_irq:
 430         free_irq(mps->irq, mps);
 431 free_master:
 432         if (mps->psc)
 433                 iounmap(mps->psc);
 434         spi_master_put(master);
 435
 436         return ret;
 437 }
 438
 439 static int mpc52xx_psc_spi_of_probe(struct platform_device *op)
 440 {
 441         const u32 *regaddr_p;
 442         u64 regaddr64, size64;
 443         s16 id = -1;
 444
 445         regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL);
 446         if (!regaddr_p) {
 447                 dev_err(&op->dev, "Invalid PSC address\n");
 448                 return -EINVAL;
 449         }
 450         regaddr64 = of_translate_address(op->dev.of_node, regaddr_p);
 451
 452         /* get PSC id (1..6, used by port_config) */
 453         if (op->dev.platform_data == NULL) {
 454                 const u32 *psc_nump;
 455
 456                 psc_nump = of_get_property(op->dev.of_node, "cell-index", NULL);
 457                 if (!psc_nump || *psc_nump > 5) {
 458                         dev_err(&op->dev, "Invalid cell-index property\n");
 459                         return -EINVAL;
 460                 }
 461                 id = *psc_nump + 1;
 462         }
 463
 464         return mpc52xx_psc_spi_do_probe(&op->dev, (u32)regaddr64, (u32)size64,
 465                                 irq_of_parse_and_map(op->dev.of_node, 0), id);
 466 }
 467
 468 static int mpc52xx_psc_spi_of_remove(struct platform_device *op)
 469 {
 470         struct spi_master *master = spi_master_get(platform_get_drvdata(op));
 471         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(master);
 472
 473         flush_work(&mps->work);
 474         spi_unregister_master(master);
 475         free_irq(mps->irq, mps);
 476         if (mps->psc)
 477                 iounmap(mps->psc);
 478         spi_master_put(master);
 479
 480         return 0;
 481 }
 482
 483 static const struct of_device_id mpc52xx_psc_spi_of_match[] = {
 484         { .compatible = "fsl,mpc5200-psc-spi", },
 485         { .compatible = "mpc5200-psc-spi", }, /* old */
 486         {}
 487 };
 488
 489 MODULE_DEVICE_TABLE(of, mpc52xx_psc_spi_of_match);
 490
 491 static struct platform_driver mpc52xx_psc_spi_of_driver = {
 492         .probe = mpc52xx_psc_spi_of_probe,
 493         .remove = mpc52xx_psc_spi_of_remove,
 494         .driver = {
 495                 .name = "mpc52xx-psc-spi",
 496                 .of_match_table = mpc52xx_psc_spi_of_match,
 497         },
 498 };
 499 module_platform_driver(mpc52xx_psc_spi_of_driver);
 500
 501 MODULE_AUTHOR("Dragos Carp");
 502 MODULE_DESCRIPTION("MPC52xx PSC SPI Driver");
 503 MODULE_LICENSE("GPL");