1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 // Copyright (C) 2008 Juergen Beisert
5 #include <linux/bits.h>
7 #include <linux/completion.h>
8 #include <linux/delay.h>
9 #include <linux/dmaengine.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/err.h>
12 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/pinctrl/consumer.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/slab.h>
21 #include <linux/spi/spi.h>
22 #include <linux/types.h>
24 #include <linux/property.h>
26 #include <linux/dma/imx-dma.h>
28 #define DRIVER_NAME "spi_imx"
30 static bool use_dma = true;
31 module_param(use_dma, bool, 0644);
32 MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)");
34 /* define polling limits */
35 static unsigned int polling_limit_us = 30;
36 module_param(polling_limit_us, uint, 0664);
37 MODULE_PARM_DESC(polling_limit_us,
38 "time in us to run a transfer in polling mode\n");
40 #define MXC_RPM_TIMEOUT 2000 /* 2000ms */
42 #define MXC_CSPIRXDATA 0x00
43 #define MXC_CSPITXDATA 0x04
44 #define MXC_CSPICTRL 0x08
45 #define MXC_CSPIINT 0x0c
46 #define MXC_RESET 0x1c
48 /* generic defines to abstract from the different register layouts */
49 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
50 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
51 #define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */
53 /* The maximum bytes that a sdma BD can transfer. */
54 #define MAX_SDMA_BD_BYTES (1 << 15)
55 #define MX51_ECSPI_CTRL_MAX_BURST 512
56 /* The maximum bytes that IMX53_ECSPI can transfer in target mode.*/
57 #define MX53_MAX_TRANSFER_BYTES 512
59 enum spi_imx_devtype {
64 IMX35_CSPI, /* CSPI on all i.mx except above */
65 IMX51_ECSPI, /* ECSPI on i.mx51 */
66 IMX53_ECSPI, /* ECSPI on i.mx53 and later */
71 struct spi_imx_devtype_data {
72 void (*intctrl)(struct spi_imx_data *spi_imx, int enable);
73 int (*prepare_message)(struct spi_imx_data *spi_imx, struct spi_message *msg);
74 int (*prepare_transfer)(struct spi_imx_data *spi_imx, struct spi_device *spi);
75 void (*trigger)(struct spi_imx_data *spi_imx);
76 int (*rx_available)(struct spi_imx_data *spi_imx);
77 void (*reset)(struct spi_imx_data *spi_imx);
78 void (*setup_wml)(struct spi_imx_data *spi_imx);
79 void (*disable)(struct spi_imx_data *spi_imx);
82 unsigned int fifo_size;
85 * ERR009165 fixed or not:
86 * https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
89 enum spi_imx_devtype devtype;
93 struct spi_controller *controller;
96 struct completion xfer_done;
98 unsigned long base_phys;
102 unsigned long spi_clk;
103 unsigned int spi_bus_clk;
105 unsigned int bits_per_word;
106 unsigned int spi_drctl;
108 unsigned int count, remainder;
109 void (*tx)(struct spi_imx_data *spi_imx);
110 void (*rx)(struct spi_imx_data *spi_imx);
113 unsigned int txfifo; /* number of words pushed in tx FIFO */
114 unsigned int dynamic_burst;
120 unsigned int target_burst;
125 struct completion dma_rx_completion;
126 struct completion dma_tx_completion;
128 const struct spi_imx_devtype_data *devtype_data;
131 static inline int is_imx27_cspi(struct spi_imx_data *d)
133 return d->devtype_data->devtype == IMX27_CSPI;
136 static inline int is_imx35_cspi(struct spi_imx_data *d)
138 return d->devtype_data->devtype == IMX35_CSPI;
141 static inline int is_imx51_ecspi(struct spi_imx_data *d)
143 return d->devtype_data->devtype == IMX51_ECSPI;
146 static inline int is_imx53_ecspi(struct spi_imx_data *d)
148 return d->devtype_data->devtype == IMX53_ECSPI;
151 #define MXC_SPI_BUF_RX(type) \
152 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
154 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
156 if (spi_imx->rx_buf) { \
157 *(type *)spi_imx->rx_buf = val; \
158 spi_imx->rx_buf += sizeof(type); \
161 spi_imx->remainder -= sizeof(type); \
164 #define MXC_SPI_BUF_TX(type) \
165 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
169 if (spi_imx->tx_buf) { \
170 val = *(type *)spi_imx->tx_buf; \
171 spi_imx->tx_buf += sizeof(type); \
174 spi_imx->count -= sizeof(type); \
176 writel(val, spi_imx->base + MXC_CSPITXDATA); \
186 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
187 * (which is currently not the case in this driver)
189 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
190 256, 384, 512, 768, 1024};
193 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
194 unsigned int fspi, unsigned int max, unsigned int *fres)
198 for (i = 2; i < max; i++)
199 if (fspi * mxc_clkdivs[i] >= fin)
202 *fres = fin / mxc_clkdivs[i];
206 /* MX1, MX31, MX35, MX51 CSPI */
207 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
208 unsigned int fspi, unsigned int *fres)
212 for (i = 0; i < 7; i++) {
213 if (fspi * div >= fin)
223 static int spi_imx_bytes_per_word(const int bits_per_word)
225 if (bits_per_word <= 8)
227 else if (bits_per_word <= 16)
233 static bool spi_imx_can_dma(struct spi_controller *controller, struct spi_device *spi,
234 struct spi_transfer *transfer)
236 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
238 if (!use_dma || controller->fallback)
241 if (!controller->dma_rx)
244 if (spi_imx->target_mode)
247 if (transfer->len < spi_imx->devtype_data->fifo_size)
250 spi_imx->dynamic_burst = 0;
256 * Note the number of natively supported chip selects for MX51 is 4. Some
257 * devices may have less actual SS pins but the register map supports 4. When
258 * using gpio chip selects the cs values passed into the macros below can go
259 * outside the range 0 - 3. We therefore need to limit the cs value to avoid
260 * corrupting bits outside the allocated locations.
262 * The simplest way to do this is to just mask the cs bits to 2 bits. This
263 * still allows all 4 native chip selects to work as well as gpio chip selects
264 * (which can use any of the 4 chip select configurations).
267 #define MX51_ECSPI_CTRL 0x08
268 #define MX51_ECSPI_CTRL_ENABLE (1 << 0)
269 #define MX51_ECSPI_CTRL_XCH (1 << 2)
270 #define MX51_ECSPI_CTRL_SMC (1 << 3)
271 #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
272 #define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16)
273 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
274 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
275 #define MX51_ECSPI_CTRL_CS(cs) ((cs & 3) << 18)
276 #define MX51_ECSPI_CTRL_BL_OFFSET 20
277 #define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20)
279 #define MX51_ECSPI_CONFIG 0x0c
280 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs & 3) + 0))
281 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs & 3) + 4))
282 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs & 3) + 8))
283 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs & 3) + 12))
284 #define MX51_ECSPI_CONFIG_DATACTL(cs) (1 << ((cs & 3) + 16))
285 #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs & 3) + 20))
287 #define MX51_ECSPI_INT 0x10
288 #define MX51_ECSPI_INT_TEEN (1 << 0)
289 #define MX51_ECSPI_INT_RREN (1 << 3)
290 #define MX51_ECSPI_INT_RDREN (1 << 4)
292 #define MX51_ECSPI_DMA 0x14
293 #define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f)
294 #define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16)
295 #define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24)
297 #define MX51_ECSPI_DMA_TEDEN (1 << 7)
298 #define MX51_ECSPI_DMA_RXDEN (1 << 23)
299 #define MX51_ECSPI_DMA_RXTDEN (1 << 31)
301 #define MX51_ECSPI_STAT 0x18
302 #define MX51_ECSPI_STAT_RR (1 << 3)
304 #define MX51_ECSPI_TESTREG 0x20
305 #define MX51_ECSPI_TESTREG_LBC BIT(31)
307 static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx)
309 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
311 if (spi_imx->rx_buf) {
312 #ifdef __LITTLE_ENDIAN
313 unsigned int bytes_per_word;
315 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
316 if (bytes_per_word == 1)
318 else if (bytes_per_word == 2)
321 *(u32 *)spi_imx->rx_buf = val;
322 spi_imx->rx_buf += sizeof(u32);
325 spi_imx->remainder -= sizeof(u32);
328 static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
333 unaligned = spi_imx->remainder % 4;
336 spi_imx_buf_rx_swap_u32(spi_imx);
340 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
341 spi_imx_buf_rx_u16(spi_imx);
345 val = readl(spi_imx->base + MXC_CSPIRXDATA);
347 while (unaligned--) {
348 if (spi_imx->rx_buf) {
349 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff;
352 spi_imx->remainder--;
356 static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx)
359 #ifdef __LITTLE_ENDIAN
360 unsigned int bytes_per_word;
363 if (spi_imx->tx_buf) {
364 val = *(u32 *)spi_imx->tx_buf;
365 spi_imx->tx_buf += sizeof(u32);
368 spi_imx->count -= sizeof(u32);
369 #ifdef __LITTLE_ENDIAN
370 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
372 if (bytes_per_word == 1)
374 else if (bytes_per_word == 2)
377 writel(val, spi_imx->base + MXC_CSPITXDATA);
380 static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
385 unaligned = spi_imx->count % 4;
388 spi_imx_buf_tx_swap_u32(spi_imx);
392 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
393 spi_imx_buf_tx_u16(spi_imx);
397 while (unaligned--) {
398 if (spi_imx->tx_buf) {
399 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned);
405 writel(val, spi_imx->base + MXC_CSPITXDATA);
408 static void mx53_ecspi_rx_target(struct spi_imx_data *spi_imx)
410 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA));
412 if (spi_imx->rx_buf) {
413 int n_bytes = spi_imx->target_burst % sizeof(val);
416 n_bytes = sizeof(val);
418 memcpy(spi_imx->rx_buf,
419 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes);
421 spi_imx->rx_buf += n_bytes;
422 spi_imx->target_burst -= n_bytes;
425 spi_imx->remainder -= sizeof(u32);
428 static void mx53_ecspi_tx_target(struct spi_imx_data *spi_imx)
431 int n_bytes = spi_imx->count % sizeof(val);
434 n_bytes = sizeof(val);
436 if (spi_imx->tx_buf) {
437 memcpy(((u8 *)&val) + sizeof(val) - n_bytes,
438 spi_imx->tx_buf, n_bytes);
439 val = cpu_to_be32(val);
440 spi_imx->tx_buf += n_bytes;
443 spi_imx->count -= n_bytes;
445 writel(val, spi_imx->base + MXC_CSPITXDATA);
449 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
450 unsigned int fspi, unsigned int *fres)
453 * there are two 4-bit dividers, the pre-divider divides by
454 * $pre, the post-divider by 2^$post
456 unsigned int pre, post;
457 unsigned int fin = spi_imx->spi_clk;
459 fspi = min(fspi, fin);
461 post = fls(fin) - fls(fspi);
462 if (fin > fspi << post)
465 /* now we have: (fin <= fspi << post) with post being minimal */
467 post = max(4U, post) - 4;
468 if (unlikely(post > 0xf)) {
469 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
474 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
476 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
477 __func__, fin, fspi, post, pre);
479 /* Resulting frequency for the SCLK line. */
480 *fres = (fin / (pre + 1)) >> post;
482 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
483 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
486 static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
488 unsigned int val = 0;
490 if (enable & MXC_INT_TE)
491 val |= MX51_ECSPI_INT_TEEN;
493 if (enable & MXC_INT_RR)
494 val |= MX51_ECSPI_INT_RREN;
496 if (enable & MXC_INT_RDR)
497 val |= MX51_ECSPI_INT_RDREN;
499 writel(val, spi_imx->base + MX51_ECSPI_INT);
502 static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
506 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
507 reg |= MX51_ECSPI_CTRL_XCH;
508 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
511 static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
515 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
516 ctrl &= ~MX51_ECSPI_CTRL_ENABLE;
517 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
520 static int mx51_ecspi_channel(const struct spi_device *spi)
522 if (!spi_get_csgpiod(spi, 0))
523 return spi_get_chipselect(spi, 0);
524 return spi->controller->unused_native_cs;
527 static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
528 struct spi_message *msg)
530 struct spi_device *spi = msg->spi;
531 struct spi_transfer *xfer;
532 u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
533 u32 min_speed_hz = ~0U;
535 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
536 u32 current_cfg = cfg;
537 int channel = mx51_ecspi_channel(spi);
539 /* set Host or Target mode */
540 if (spi_imx->target_mode)
541 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK;
543 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
546 * Enable SPI_RDY handling (falling edge/level triggered).
548 if (spi->mode & SPI_READY)
549 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
551 /* set chip select to use */
552 ctrl |= MX51_ECSPI_CTRL_CS(channel);
555 * The ctrl register must be written first, with the EN bit set other
556 * registers must not be written to.
558 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
560 testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
561 if (spi->mode & SPI_LOOP)
562 testreg |= MX51_ECSPI_TESTREG_LBC;
564 testreg &= ~MX51_ECSPI_TESTREG_LBC;
565 writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG);
568 * eCSPI burst completion by Chip Select signal in Target mode
569 * is not functional for imx53 Soc, config SPI burst completed when
570 * BURST_LENGTH + 1 bits are received
572 if (spi_imx->target_mode && is_imx53_ecspi(spi_imx))
573 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(channel);
575 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(channel);
577 if (spi->mode & SPI_CPOL) {
578 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(channel);
579 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(channel);
581 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(channel);
582 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(channel);
585 if (spi->mode & SPI_MOSI_IDLE_LOW)
586 cfg |= MX51_ECSPI_CONFIG_DATACTL(channel);
588 cfg &= ~MX51_ECSPI_CONFIG_DATACTL(channel);
590 if (spi->mode & SPI_CS_HIGH)
591 cfg |= MX51_ECSPI_CONFIG_SSBPOL(channel);
593 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(channel);
595 if (cfg == current_cfg)
598 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
601 * Wait until the changes in the configuration register CONFIGREG
602 * propagate into the hardware. It takes exactly one tick of the
603 * SCLK clock, but we will wait two SCLK clock just to be sure. The
604 * effect of the delay it takes for the hardware to apply changes
605 * is noticable if the SCLK clock run very slow. In such a case, if
606 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
607 * be asserted before the SCLK polarity changes, which would disrupt
608 * the SPI communication as the device on the other end would consider
609 * the change of SCLK polarity as a clock tick already.
611 * Because spi_imx->spi_bus_clk is only set in prepare_message
612 * callback, iterate over all the transfers in spi_message, find the
613 * one with lowest bus frequency, and use that bus frequency for the
614 * delay calculation. In case all transfers have speed_hz == 0, then
615 * min_speed_hz is ~0 and the resulting delay is zero.
617 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
620 min_speed_hz = min(xfer->speed_hz, min_speed_hz);
623 delay = (2 * 1000000) / min_speed_hz;
624 if (likely(delay < 10)) /* SCLK is faster than 200 kHz */
626 else /* SCLK is _very_ slow */
627 usleep_range(delay, delay + 10);
632 static void mx51_configure_cpha(struct spi_imx_data *spi_imx,
633 struct spi_device *spi)
635 bool cpha = (spi->mode & SPI_CPHA);
636 bool flip_cpha = (spi->mode & SPI_RX_CPHA_FLIP) && spi_imx->rx_only;
637 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
638 int channel = mx51_ecspi_channel(spi);
640 /* Flip cpha logical value iff flip_cpha */
644 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(channel);
646 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(channel);
648 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
651 static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
652 struct spi_device *spi)
654 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
657 /* Clear BL field and set the right value */
658 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
659 if (spi_imx->target_mode && is_imx53_ecspi(spi_imx))
660 ctrl |= (spi_imx->target_burst * 8 - 1)
661 << MX51_ECSPI_CTRL_BL_OFFSET;
663 if (spi_imx->usedma) {
664 ctrl |= (spi_imx->bits_per_word - 1)
665 << MX51_ECSPI_CTRL_BL_OFFSET;
667 if (spi_imx->count >= MX51_ECSPI_CTRL_MAX_BURST)
668 ctrl |= (MX51_ECSPI_CTRL_MAX_BURST * BITS_PER_BYTE - 1)
669 << MX51_ECSPI_CTRL_BL_OFFSET;
671 ctrl |= spi_imx->count / DIV_ROUND_UP(spi_imx->bits_per_word,
672 BITS_PER_BYTE) * spi_imx->bits_per_word
673 << MX51_ECSPI_CTRL_BL_OFFSET;
677 /* set clock speed */
678 ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET |
679 0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET);
680 ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk);
681 spi_imx->spi_bus_clk = clk;
683 mx51_configure_cpha(spi_imx, spi);
686 * ERR009165: work in XHC mode instead of SMC as PIO on the chips
689 if (spi_imx->usedma && spi_imx->devtype_data->tx_glitch_fixed)
690 ctrl |= MX51_ECSPI_CTRL_SMC;
692 ctrl &= ~MX51_ECSPI_CTRL_SMC;
694 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
699 static void mx51_setup_wml(struct spi_imx_data *spi_imx)
703 if (spi_imx->devtype_data->tx_glitch_fixed)
704 tx_wml = spi_imx->wml;
706 * Configure the DMA register: setup the watermark
707 * and enable DMA request.
709 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
710 MX51_ECSPI_DMA_TX_WML(tx_wml) |
711 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
712 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
713 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
716 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
718 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
721 static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
723 /* drain receive buffer */
724 while (mx51_ecspi_rx_available(spi_imx))
725 readl(spi_imx->base + MXC_CSPIRXDATA);
728 #define MX31_INTREG_TEEN (1 << 0)
729 #define MX31_INTREG_RREN (1 << 3)
731 #define MX31_CSPICTRL_ENABLE (1 << 0)
732 #define MX31_CSPICTRL_HOST (1 << 1)
733 #define MX31_CSPICTRL_XCH (1 << 2)
734 #define MX31_CSPICTRL_SMC (1 << 3)
735 #define MX31_CSPICTRL_POL (1 << 4)
736 #define MX31_CSPICTRL_PHA (1 << 5)
737 #define MX31_CSPICTRL_SSCTL (1 << 6)
738 #define MX31_CSPICTRL_SSPOL (1 << 7)
739 #define MX31_CSPICTRL_BC_SHIFT 8
740 #define MX35_CSPICTRL_BL_SHIFT 20
741 #define MX31_CSPICTRL_CS_SHIFT 24
742 #define MX35_CSPICTRL_CS_SHIFT 12
743 #define MX31_CSPICTRL_DR_SHIFT 16
745 #define MX31_CSPI_DMAREG 0x10
746 #define MX31_DMAREG_RH_DEN (1<<4)
747 #define MX31_DMAREG_TH_DEN (1<<1)
749 #define MX31_CSPISTATUS 0x14
750 #define MX31_STATUS_RR (1 << 3)
752 #define MX31_CSPI_TESTREG 0x1C
753 #define MX31_TEST_LBC (1 << 14)
755 /* These functions also work for the i.MX35, but be aware that
756 * the i.MX35 has a slightly different register layout for bits
757 * we do not use here.
759 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
761 unsigned int val = 0;
763 if (enable & MXC_INT_TE)
764 val |= MX31_INTREG_TEEN;
765 if (enable & MXC_INT_RR)
766 val |= MX31_INTREG_RREN;
768 writel(val, spi_imx->base + MXC_CSPIINT);
771 static void mx31_trigger(struct spi_imx_data *spi_imx)
775 reg = readl(spi_imx->base + MXC_CSPICTRL);
776 reg |= MX31_CSPICTRL_XCH;
777 writel(reg, spi_imx->base + MXC_CSPICTRL);
780 static int mx31_prepare_message(struct spi_imx_data *spi_imx,
781 struct spi_message *msg)
786 static int mx31_prepare_transfer(struct spi_imx_data *spi_imx,
787 struct spi_device *spi)
789 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_HOST;
792 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
793 MX31_CSPICTRL_DR_SHIFT;
794 spi_imx->spi_bus_clk = clk;
796 if (is_imx35_cspi(spi_imx)) {
797 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT;
798 reg |= MX31_CSPICTRL_SSCTL;
800 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT;
803 if (spi->mode & SPI_CPHA)
804 reg |= MX31_CSPICTRL_PHA;
805 if (spi->mode & SPI_CPOL)
806 reg |= MX31_CSPICTRL_POL;
807 if (spi->mode & SPI_CS_HIGH)
808 reg |= MX31_CSPICTRL_SSPOL;
809 if (!spi_get_csgpiod(spi, 0))
810 reg |= (spi_get_chipselect(spi, 0)) <<
811 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
812 MX31_CSPICTRL_CS_SHIFT);
815 reg |= MX31_CSPICTRL_SMC;
817 writel(reg, spi_imx->base + MXC_CSPICTRL);
819 reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
820 if (spi->mode & SPI_LOOP)
821 reg |= MX31_TEST_LBC;
823 reg &= ~MX31_TEST_LBC;
824 writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
826 if (spi_imx->usedma) {
828 * configure DMA requests when RXFIFO is half full and
829 * when TXFIFO is half empty
831 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
832 spi_imx->base + MX31_CSPI_DMAREG);
838 static int mx31_rx_available(struct spi_imx_data *spi_imx)
840 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
843 static void mx31_reset(struct spi_imx_data *spi_imx)
845 /* drain receive buffer */
846 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
847 readl(spi_imx->base + MXC_CSPIRXDATA);
850 #define MX21_INTREG_RR (1 << 4)
851 #define MX21_INTREG_TEEN (1 << 9)
852 #define MX21_INTREG_RREN (1 << 13)
854 #define MX21_CSPICTRL_POL (1 << 5)
855 #define MX21_CSPICTRL_PHA (1 << 6)
856 #define MX21_CSPICTRL_SSPOL (1 << 8)
857 #define MX21_CSPICTRL_XCH (1 << 9)
858 #define MX21_CSPICTRL_ENABLE (1 << 10)
859 #define MX21_CSPICTRL_HOST (1 << 11)
860 #define MX21_CSPICTRL_DR_SHIFT 14
861 #define MX21_CSPICTRL_CS_SHIFT 19
863 static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
865 unsigned int val = 0;
867 if (enable & MXC_INT_TE)
868 val |= MX21_INTREG_TEEN;
869 if (enable & MXC_INT_RR)
870 val |= MX21_INTREG_RREN;
872 writel(val, spi_imx->base + MXC_CSPIINT);
875 static void mx21_trigger(struct spi_imx_data *spi_imx)
879 reg = readl(spi_imx->base + MXC_CSPICTRL);
880 reg |= MX21_CSPICTRL_XCH;
881 writel(reg, spi_imx->base + MXC_CSPICTRL);
884 static int mx21_prepare_message(struct spi_imx_data *spi_imx,
885 struct spi_message *msg)
890 static int mx21_prepare_transfer(struct spi_imx_data *spi_imx,
891 struct spi_device *spi)
893 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_HOST;
894 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
897 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk)
898 << MX21_CSPICTRL_DR_SHIFT;
899 spi_imx->spi_bus_clk = clk;
901 reg |= spi_imx->bits_per_word - 1;
903 if (spi->mode & SPI_CPHA)
904 reg |= MX21_CSPICTRL_PHA;
905 if (spi->mode & SPI_CPOL)
906 reg |= MX21_CSPICTRL_POL;
907 if (spi->mode & SPI_CS_HIGH)
908 reg |= MX21_CSPICTRL_SSPOL;
909 if (!spi_get_csgpiod(spi, 0))
910 reg |= spi_get_chipselect(spi, 0) << MX21_CSPICTRL_CS_SHIFT;
912 writel(reg, spi_imx->base + MXC_CSPICTRL);
917 static int mx21_rx_available(struct spi_imx_data *spi_imx)
919 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
922 static void mx21_reset(struct spi_imx_data *spi_imx)
924 writel(1, spi_imx->base + MXC_RESET);
927 #define MX1_INTREG_RR (1 << 3)
928 #define MX1_INTREG_TEEN (1 << 8)
929 #define MX1_INTREG_RREN (1 << 11)
931 #define MX1_CSPICTRL_POL (1 << 4)
932 #define MX1_CSPICTRL_PHA (1 << 5)
933 #define MX1_CSPICTRL_XCH (1 << 8)
934 #define MX1_CSPICTRL_ENABLE (1 << 9)
935 #define MX1_CSPICTRL_HOST (1 << 10)
936 #define MX1_CSPICTRL_DR_SHIFT 13
938 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
940 unsigned int val = 0;
942 if (enable & MXC_INT_TE)
943 val |= MX1_INTREG_TEEN;
944 if (enable & MXC_INT_RR)
945 val |= MX1_INTREG_RREN;
947 writel(val, spi_imx->base + MXC_CSPIINT);
950 static void mx1_trigger(struct spi_imx_data *spi_imx)
954 reg = readl(spi_imx->base + MXC_CSPICTRL);
955 reg |= MX1_CSPICTRL_XCH;
956 writel(reg, spi_imx->base + MXC_CSPICTRL);
959 static int mx1_prepare_message(struct spi_imx_data *spi_imx,
960 struct spi_message *msg)
965 static int mx1_prepare_transfer(struct spi_imx_data *spi_imx,
966 struct spi_device *spi)
968 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_HOST;
971 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
972 MX1_CSPICTRL_DR_SHIFT;
973 spi_imx->spi_bus_clk = clk;
975 reg |= spi_imx->bits_per_word - 1;
977 if (spi->mode & SPI_CPHA)
978 reg |= MX1_CSPICTRL_PHA;
979 if (spi->mode & SPI_CPOL)
980 reg |= MX1_CSPICTRL_POL;
982 writel(reg, spi_imx->base + MXC_CSPICTRL);
987 static int mx1_rx_available(struct spi_imx_data *spi_imx)
989 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
992 static void mx1_reset(struct spi_imx_data *spi_imx)
994 writel(1, spi_imx->base + MXC_RESET);
997 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
998 .intctrl = mx1_intctrl,
999 .prepare_message = mx1_prepare_message,
1000 .prepare_transfer = mx1_prepare_transfer,
1001 .trigger = mx1_trigger,
1002 .rx_available = mx1_rx_available,
1005 .has_dmamode = false,
1006 .dynamic_burst = false,
1007 .has_targetmode = false,
1008 .devtype = IMX1_CSPI,
1011 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
1012 .intctrl = mx21_intctrl,
1013 .prepare_message = mx21_prepare_message,
1014 .prepare_transfer = mx21_prepare_transfer,
1015 .trigger = mx21_trigger,
1016 .rx_available = mx21_rx_available,
1017 .reset = mx21_reset,
1019 .has_dmamode = false,
1020 .dynamic_burst = false,
1021 .has_targetmode = false,
1022 .devtype = IMX21_CSPI,
1025 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
1026 /* i.mx27 cspi shares the functions with i.mx21 one */
1027 .intctrl = mx21_intctrl,
1028 .prepare_message = mx21_prepare_message,
1029 .prepare_transfer = mx21_prepare_transfer,
1030 .trigger = mx21_trigger,
1031 .rx_available = mx21_rx_available,
1032 .reset = mx21_reset,
1034 .has_dmamode = false,
1035 .dynamic_burst = false,
1036 .has_targetmode = false,
1037 .devtype = IMX27_CSPI,
1040 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
1041 .intctrl = mx31_intctrl,
1042 .prepare_message = mx31_prepare_message,
1043 .prepare_transfer = mx31_prepare_transfer,
1044 .trigger = mx31_trigger,
1045 .rx_available = mx31_rx_available,
1046 .reset = mx31_reset,
1048 .has_dmamode = false,
1049 .dynamic_burst = false,
1050 .has_targetmode = false,
1051 .devtype = IMX31_CSPI,
1054 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
1055 /* i.mx35 and later cspi shares the functions with i.mx31 one */
1056 .intctrl = mx31_intctrl,
1057 .prepare_message = mx31_prepare_message,
1058 .prepare_transfer = mx31_prepare_transfer,
1059 .trigger = mx31_trigger,
1060 .rx_available = mx31_rx_available,
1061 .reset = mx31_reset,
1063 .has_dmamode = true,
1064 .dynamic_burst = false,
1065 .has_targetmode = false,
1066 .devtype = IMX35_CSPI,
1069 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
1070 .intctrl = mx51_ecspi_intctrl,
1071 .prepare_message = mx51_ecspi_prepare_message,
1072 .prepare_transfer = mx51_ecspi_prepare_transfer,
1073 .trigger = mx51_ecspi_trigger,
1074 .rx_available = mx51_ecspi_rx_available,
1075 .reset = mx51_ecspi_reset,
1076 .setup_wml = mx51_setup_wml,
1078 .has_dmamode = true,
1079 .dynamic_burst = true,
1080 .has_targetmode = true,
1081 .disable = mx51_ecspi_disable,
1082 .devtype = IMX51_ECSPI,
1085 static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
1086 .intctrl = mx51_ecspi_intctrl,
1087 .prepare_message = mx51_ecspi_prepare_message,
1088 .prepare_transfer = mx51_ecspi_prepare_transfer,
1089 .trigger = mx51_ecspi_trigger,
1090 .rx_available = mx51_ecspi_rx_available,
1091 .reset = mx51_ecspi_reset,
1093 .has_dmamode = true,
1094 .has_targetmode = true,
1095 .disable = mx51_ecspi_disable,
1096 .devtype = IMX53_ECSPI,
1099 static struct spi_imx_devtype_data imx6ul_ecspi_devtype_data = {
1100 .intctrl = mx51_ecspi_intctrl,
1101 .prepare_message = mx51_ecspi_prepare_message,
1102 .prepare_transfer = mx51_ecspi_prepare_transfer,
1103 .trigger = mx51_ecspi_trigger,
1104 .rx_available = mx51_ecspi_rx_available,
1105 .reset = mx51_ecspi_reset,
1106 .setup_wml = mx51_setup_wml,
1108 .has_dmamode = true,
1109 .dynamic_burst = true,
1110 .has_targetmode = true,
1111 .tx_glitch_fixed = true,
1112 .disable = mx51_ecspi_disable,
1113 .devtype = IMX51_ECSPI,
1116 static const struct of_device_id spi_imx_dt_ids[] = {
1117 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
1118 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
1119 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
1120 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
1121 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
1122 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
1123 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
1124 { .compatible = "fsl,imx6ul-ecspi", .data = &imx6ul_ecspi_devtype_data, },
1127 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
1129 static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits)
1133 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
1134 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
1135 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET);
1136 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
1139 static void spi_imx_push(struct spi_imx_data *spi_imx)
1141 unsigned int burst_len;
1144 * Reload the FIFO when the remaining bytes to be transferred in the
1145 * current burst is 0. This only applies when bits_per_word is a
1148 if (!spi_imx->remainder) {
1149 if (spi_imx->dynamic_burst) {
1151 /* We need to deal unaligned data first */
1152 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST;
1155 burst_len = MX51_ECSPI_CTRL_MAX_BURST;
1157 spi_imx_set_burst_len(spi_imx, burst_len * 8);
1159 spi_imx->remainder = burst_len;
1161 spi_imx->remainder = spi_imx_bytes_per_word(spi_imx->bits_per_word);
1165 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) {
1166 if (!spi_imx->count)
1168 if (spi_imx->dynamic_burst &&
1169 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder, 4))
1171 spi_imx->tx(spi_imx);
1175 if (!spi_imx->target_mode)
1176 spi_imx->devtype_data->trigger(spi_imx);
1179 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
1181 struct spi_imx_data *spi_imx = dev_id;
1183 while (spi_imx->txfifo &&
1184 spi_imx->devtype_data->rx_available(spi_imx)) {
1185 spi_imx->rx(spi_imx);
1189 if (spi_imx->count) {
1190 spi_imx_push(spi_imx);
1194 if (spi_imx->txfifo) {
1195 /* No data left to push, but still waiting for rx data,
1196 * enable receive data available interrupt.
1198 spi_imx->devtype_data->intctrl(
1199 spi_imx, MXC_INT_RR);
1203 spi_imx->devtype_data->intctrl(spi_imx, 0);
1204 complete(&spi_imx->xfer_done);
1209 static int spi_imx_dma_configure(struct spi_controller *controller)
1212 enum dma_slave_buswidth buswidth;
1213 struct dma_slave_config rx = {}, tx = {};
1214 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1216 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) {
1218 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1221 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1224 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1230 tx.direction = DMA_MEM_TO_DEV;
1231 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
1232 tx.dst_addr_width = buswidth;
1233 tx.dst_maxburst = spi_imx->wml;
1234 ret = dmaengine_slave_config(controller->dma_tx, &tx);
1236 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
1240 rx.direction = DMA_DEV_TO_MEM;
1241 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
1242 rx.src_addr_width = buswidth;
1243 rx.src_maxburst = spi_imx->wml;
1244 ret = dmaengine_slave_config(controller->dma_rx, &rx);
1246 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
1253 static int spi_imx_setupxfer(struct spi_device *spi,
1254 struct spi_transfer *t)
1256 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1262 if (!spi->max_speed_hz) {
1263 dev_err(&spi->dev, "no speed_hz provided!\n");
1266 dev_dbg(&spi->dev, "using spi->max_speed_hz!\n");
1267 spi_imx->spi_bus_clk = spi->max_speed_hz;
1269 spi_imx->spi_bus_clk = t->speed_hz;
1271 spi_imx->bits_per_word = t->bits_per_word;
1272 spi_imx->count = t->len;
1275 * Initialize the functions for transfer. To transfer non byte-aligned
1276 * words, we have to use multiple word-size bursts, we can't use
1277 * dynamic_burst in that case.
1279 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->target_mode &&
1280 !(spi->mode & SPI_CS_WORD) &&
1281 (spi_imx->bits_per_word == 8 ||
1282 spi_imx->bits_per_word == 16 ||
1283 spi_imx->bits_per_word == 32)) {
1285 spi_imx->rx = spi_imx_buf_rx_swap;
1286 spi_imx->tx = spi_imx_buf_tx_swap;
1287 spi_imx->dynamic_burst = 1;
1290 if (spi_imx->bits_per_word <= 8) {
1291 spi_imx->rx = spi_imx_buf_rx_u8;
1292 spi_imx->tx = spi_imx_buf_tx_u8;
1293 } else if (spi_imx->bits_per_word <= 16) {
1294 spi_imx->rx = spi_imx_buf_rx_u16;
1295 spi_imx->tx = spi_imx_buf_tx_u16;
1297 spi_imx->rx = spi_imx_buf_rx_u32;
1298 spi_imx->tx = spi_imx_buf_tx_u32;
1300 spi_imx->dynamic_burst = 0;
1303 if (spi_imx_can_dma(spi_imx->controller, spi, t))
1304 spi_imx->usedma = true;
1306 spi_imx->usedma = false;
1308 spi_imx->rx_only = ((t->tx_buf == NULL)
1309 || (t->tx_buf == spi->controller->dummy_tx));
1311 if (is_imx53_ecspi(spi_imx) && spi_imx->target_mode) {
1312 spi_imx->rx = mx53_ecspi_rx_target;
1313 spi_imx->tx = mx53_ecspi_tx_target;
1314 spi_imx->target_burst = t->len;
1317 spi_imx->devtype_data->prepare_transfer(spi_imx, spi);
1322 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
1324 struct spi_controller *controller = spi_imx->controller;
1326 if (controller->dma_rx) {
1327 dma_release_channel(controller->dma_rx);
1328 controller->dma_rx = NULL;
1331 if (controller->dma_tx) {
1332 dma_release_channel(controller->dma_tx);
1333 controller->dma_tx = NULL;
1337 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
1338 struct spi_controller *controller)
1342 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
1344 /* Prepare for TX DMA: */
1345 controller->dma_tx = dma_request_chan(dev, "tx");
1346 if (IS_ERR(controller->dma_tx)) {
1347 ret = PTR_ERR(controller->dma_tx);
1348 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
1349 controller->dma_tx = NULL;
1353 /* Prepare for RX : */
1354 controller->dma_rx = dma_request_chan(dev, "rx");
1355 if (IS_ERR(controller->dma_rx)) {
1356 ret = PTR_ERR(controller->dma_rx);
1357 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
1358 controller->dma_rx = NULL;
1362 init_completion(&spi_imx->dma_rx_completion);
1363 init_completion(&spi_imx->dma_tx_completion);
1364 controller->can_dma = spi_imx_can_dma;
1365 controller->max_dma_len = MAX_SDMA_BD_BYTES;
1366 spi_imx->controller->flags = SPI_CONTROLLER_MUST_RX |
1367 SPI_CONTROLLER_MUST_TX;
1371 spi_imx_sdma_exit(spi_imx);
1375 static void spi_imx_dma_rx_callback(void *cookie)
1377 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1379 complete(&spi_imx->dma_rx_completion);
1382 static void spi_imx_dma_tx_callback(void *cookie)
1384 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1386 complete(&spi_imx->dma_tx_completion);
1389 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
1391 unsigned long timeout = 0;
1393 /* Time with actual data transfer and CS change delay related to HW */
1394 timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
1396 /* Add extra second for scheduler related activities */
1399 /* Double calculated timeout */
1400 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
1403 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
1404 struct spi_transfer *transfer)
1406 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
1407 unsigned long transfer_timeout;
1408 unsigned long timeout;
1409 struct spi_controller *controller = spi_imx->controller;
1410 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1411 struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents);
1412 unsigned int bytes_per_word, i;
1415 /* Get the right burst length from the last sg to ensure no tail data */
1416 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
1417 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
1418 if (!(sg_dma_len(last_sg) % (i * bytes_per_word)))
1421 /* Use 1 as wml in case no available burst length got */
1427 ret = spi_imx_dma_configure(controller);
1429 goto dma_failure_no_start;
1431 if (!spi_imx->devtype_data->setup_wml) {
1432 dev_err(spi_imx->dev, "No setup_wml()?\n");
1434 goto dma_failure_no_start;
1436 spi_imx->devtype_data->setup_wml(spi_imx);
1439 * The TX DMA setup starts the transfer, so make sure RX is configured
1442 desc_rx = dmaengine_prep_slave_sg(controller->dma_rx,
1443 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1444 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1447 goto dma_failure_no_start;
1450 desc_rx->callback = spi_imx_dma_rx_callback;
1451 desc_rx->callback_param = (void *)spi_imx;
1452 dmaengine_submit(desc_rx);
1453 reinit_completion(&spi_imx->dma_rx_completion);
1454 dma_async_issue_pending(controller->dma_rx);
1456 desc_tx = dmaengine_prep_slave_sg(controller->dma_tx,
1457 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1458 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1460 dmaengine_terminate_all(controller->dma_tx);
1461 dmaengine_terminate_all(controller->dma_rx);
1465 desc_tx->callback = spi_imx_dma_tx_callback;
1466 desc_tx->callback_param = (void *)spi_imx;
1467 dmaengine_submit(desc_tx);
1468 reinit_completion(&spi_imx->dma_tx_completion);
1469 dma_async_issue_pending(controller->dma_tx);
1471 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1473 /* Wait SDMA to finish the data transfer.*/
1474 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1477 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1478 dmaengine_terminate_all(controller->dma_tx);
1479 dmaengine_terminate_all(controller->dma_rx);
1483 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1486 dev_err(&controller->dev, "I/O Error in DMA RX\n");
1487 spi_imx->devtype_data->reset(spi_imx);
1488 dmaengine_terminate_all(controller->dma_rx);
1493 /* fallback to pio */
1494 dma_failure_no_start:
1495 transfer->error |= SPI_TRANS_FAIL_NO_START;
1499 static int spi_imx_pio_transfer(struct spi_device *spi,
1500 struct spi_transfer *transfer)
1502 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1503 unsigned long transfer_timeout;
1504 unsigned long timeout;
1506 spi_imx->tx_buf = transfer->tx_buf;
1507 spi_imx->rx_buf = transfer->rx_buf;
1508 spi_imx->count = transfer->len;
1509 spi_imx->txfifo = 0;
1510 spi_imx->remainder = 0;
1512 reinit_completion(&spi_imx->xfer_done);
1514 spi_imx_push(spi_imx);
1516 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1518 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1520 timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
1523 dev_err(&spi->dev, "I/O Error in PIO\n");
1524 spi_imx->devtype_data->reset(spi_imx);
1531 static int spi_imx_poll_transfer(struct spi_device *spi,
1532 struct spi_transfer *transfer)
1534 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1535 unsigned long timeout;
1537 spi_imx->tx_buf = transfer->tx_buf;
1538 spi_imx->rx_buf = transfer->rx_buf;
1539 spi_imx->count = transfer->len;
1540 spi_imx->txfifo = 0;
1541 spi_imx->remainder = 0;
1543 /* fill in the fifo before timeout calculations if we are
1544 * interrupted here, then the data is getting transferred by
1545 * the HW while we are interrupted
1547 spi_imx_push(spi_imx);
1549 timeout = spi_imx_calculate_timeout(spi_imx, transfer->len) + jiffies;
1550 while (spi_imx->txfifo) {
1552 while (spi_imx->txfifo &&
1553 spi_imx->devtype_data->rx_available(spi_imx)) {
1554 spi_imx->rx(spi_imx);
1559 if (spi_imx->count) {
1560 spi_imx_push(spi_imx);
1564 if (spi_imx->txfifo &&
1565 time_after(jiffies, timeout)) {
1567 dev_err_ratelimited(&spi->dev,
1568 "timeout period reached: jiffies: %lu- falling back to interrupt mode\n",
1571 /* fall back to interrupt mode */
1572 return spi_imx_pio_transfer(spi, transfer);
1579 static int spi_imx_pio_transfer_target(struct spi_device *spi,
1580 struct spi_transfer *transfer)
1582 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1585 if (is_imx53_ecspi(spi_imx) &&
1586 transfer->len > MX53_MAX_TRANSFER_BYTES) {
1587 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n",
1588 MX53_MAX_TRANSFER_BYTES);
1592 spi_imx->tx_buf = transfer->tx_buf;
1593 spi_imx->rx_buf = transfer->rx_buf;
1594 spi_imx->count = transfer->len;
1595 spi_imx->txfifo = 0;
1596 spi_imx->remainder = 0;
1598 reinit_completion(&spi_imx->xfer_done);
1599 spi_imx->target_aborted = false;
1601 spi_imx_push(spi_imx);
1603 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR);
1605 if (wait_for_completion_interruptible(&spi_imx->xfer_done) ||
1606 spi_imx->target_aborted) {
1607 dev_dbg(&spi->dev, "interrupted\n");
1611 /* ecspi has a HW issue when works in Target mode,
1612 * after 64 words writtern to TXFIFO, even TXFIFO becomes empty,
1613 * ECSPI_TXDATA keeps shift out the last word data,
1614 * so we have to disable ECSPI when in target mode after the
1615 * transfer completes
1617 if (spi_imx->devtype_data->disable)
1618 spi_imx->devtype_data->disable(spi_imx);
1623 static int spi_imx_transfer_one(struct spi_controller *controller,
1624 struct spi_device *spi,
1625 struct spi_transfer *transfer)
1627 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1628 unsigned long hz_per_byte, byte_limit;
1630 spi_imx_setupxfer(spi, transfer);
1631 transfer->effective_speed_hz = spi_imx->spi_bus_clk;
1633 /* flush rxfifo before transfer */
1634 while (spi_imx->devtype_data->rx_available(spi_imx))
1635 readl(spi_imx->base + MXC_CSPIRXDATA);
1637 if (spi_imx->target_mode)
1638 return spi_imx_pio_transfer_target(spi, transfer);
1641 * If we decided in spi_imx_can_dma() that we want to do a DMA
1642 * transfer, the SPI transfer has already been mapped, so we
1643 * have to do the DMA transfer here.
1645 if (spi_imx->usedma)
1646 return spi_imx_dma_transfer(spi_imx, transfer);
1648 * Calculate the estimated time in us the transfer runs. Find
1649 * the number of Hz per byte per polling limit.
1651 hz_per_byte = polling_limit_us ? ((8 + 4) * USEC_PER_SEC) / polling_limit_us : 0;
1652 byte_limit = hz_per_byte ? transfer->effective_speed_hz / hz_per_byte : 1;
1654 /* run in polling mode for short transfers */
1655 if (transfer->len < byte_limit)
1656 return spi_imx_poll_transfer(spi, transfer);
1658 return spi_imx_pio_transfer(spi, transfer);
1661 static int spi_imx_setup(struct spi_device *spi)
1663 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1664 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1669 static void spi_imx_cleanup(struct spi_device *spi)
1674 spi_imx_prepare_message(struct spi_controller *controller, struct spi_message *msg)
1676 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1679 ret = pm_runtime_resume_and_get(spi_imx->dev);
1681 dev_err(spi_imx->dev, "failed to enable clock\n");
1685 ret = spi_imx->devtype_data->prepare_message(spi_imx, msg);
1687 pm_runtime_mark_last_busy(spi_imx->dev);
1688 pm_runtime_put_autosuspend(spi_imx->dev);
1695 spi_imx_unprepare_message(struct spi_controller *controller, struct spi_message *msg)
1697 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1699 pm_runtime_mark_last_busy(spi_imx->dev);
1700 pm_runtime_put_autosuspend(spi_imx->dev);
1704 static int spi_imx_target_abort(struct spi_controller *controller)
1706 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1708 spi_imx->target_aborted = true;
1709 complete(&spi_imx->xfer_done);
1714 static int spi_imx_probe(struct platform_device *pdev)
1716 struct device_node *np = pdev->dev.of_node;
1717 struct spi_controller *controller;
1718 struct spi_imx_data *spi_imx;
1719 struct resource *res;
1720 int ret, irq, spi_drctl;
1721 const struct spi_imx_devtype_data *devtype_data =
1722 of_device_get_match_data(&pdev->dev);
1726 target_mode = devtype_data->has_targetmode &&
1727 of_property_read_bool(np, "spi-slave");
1729 controller = spi_alloc_target(&pdev->dev,
1730 sizeof(struct spi_imx_data));
1732 controller = spi_alloc_host(&pdev->dev,
1733 sizeof(struct spi_imx_data));
1737 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
1738 if ((ret < 0) || (spi_drctl >= 0x3)) {
1739 /* '11' is reserved */
1743 platform_set_drvdata(pdev, controller);
1745 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1746 controller->bus_num = np ? -1 : pdev->id;
1747 controller->use_gpio_descriptors = true;
1749 spi_imx = spi_controller_get_devdata(controller);
1750 spi_imx->controller = controller;
1751 spi_imx->dev = &pdev->dev;
1752 spi_imx->target_mode = target_mode;
1754 spi_imx->devtype_data = devtype_data;
1757 * Get number of chip selects from device properties. This can be
1758 * coming from device tree or boardfiles, if it is not defined,
1759 * a default value of 3 chip selects will be used, as all the legacy
1760 * board files have <= 3 chip selects.
1762 if (!device_property_read_u32(&pdev->dev, "num-cs", &val))
1763 controller->num_chipselect = val;
1765 controller->num_chipselect = 3;
1767 controller->transfer_one = spi_imx_transfer_one;
1768 controller->setup = spi_imx_setup;
1769 controller->cleanup = spi_imx_cleanup;
1770 controller->prepare_message = spi_imx_prepare_message;
1771 controller->unprepare_message = spi_imx_unprepare_message;
1772 controller->target_abort = spi_imx_target_abort;
1773 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS |
1776 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
1777 is_imx53_ecspi(spi_imx))
1778 controller->mode_bits |= SPI_LOOP | SPI_READY;
1780 if (is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx))
1781 controller->mode_bits |= SPI_RX_CPHA_FLIP;
1783 if (is_imx51_ecspi(spi_imx) &&
1784 device_property_read_u32(&pdev->dev, "cs-gpios", NULL))
1786 * When using HW-CS implementing SPI_CS_WORD can be done by just
1787 * setting the burst length to the word size. This is
1788 * considerably faster than manually controlling the CS.
1790 controller->mode_bits |= SPI_CS_WORD;
1792 if (is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx)) {
1793 controller->max_native_cs = 4;
1794 controller->flags |= SPI_CONTROLLER_GPIO_SS;
1797 spi_imx->spi_drctl = spi_drctl;
1799 init_completion(&spi_imx->xfer_done);
1801 spi_imx->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1802 if (IS_ERR(spi_imx->base)) {
1803 ret = PTR_ERR(spi_imx->base);
1804 goto out_controller_put;
1806 spi_imx->base_phys = res->start;
1808 irq = platform_get_irq(pdev, 0);
1811 goto out_controller_put;
1814 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1815 dev_name(&pdev->dev), spi_imx);
1817 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1818 goto out_controller_put;
1821 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1822 if (IS_ERR(spi_imx->clk_ipg)) {
1823 ret = PTR_ERR(spi_imx->clk_ipg);
1824 goto out_controller_put;
1827 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1828 if (IS_ERR(spi_imx->clk_per)) {
1829 ret = PTR_ERR(spi_imx->clk_per);
1830 goto out_controller_put;
1833 ret = clk_prepare_enable(spi_imx->clk_per);
1835 goto out_controller_put;
1837 ret = clk_prepare_enable(spi_imx->clk_ipg);
1841 pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT);
1842 pm_runtime_use_autosuspend(spi_imx->dev);
1843 pm_runtime_get_noresume(spi_imx->dev);
1844 pm_runtime_set_active(spi_imx->dev);
1845 pm_runtime_enable(spi_imx->dev);
1847 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1849 * Only validated on i.mx35 and i.mx6 now, can remove the constraint
1850 * if validated on other chips.
1852 if (spi_imx->devtype_data->has_dmamode) {
1853 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, controller);
1854 if (ret == -EPROBE_DEFER)
1855 goto out_runtime_pm_put;
1858 dev_dbg(&pdev->dev, "dma setup error %d, use pio\n",
1862 spi_imx->devtype_data->reset(spi_imx);
1864 spi_imx->devtype_data->intctrl(spi_imx, 0);
1866 controller->dev.of_node = pdev->dev.of_node;
1867 ret = spi_register_controller(controller);
1869 dev_err_probe(&pdev->dev, ret, "register controller failed\n");
1870 goto out_register_controller;
1873 pm_runtime_mark_last_busy(spi_imx->dev);
1874 pm_runtime_put_autosuspend(spi_imx->dev);
1878 out_register_controller:
1879 if (spi_imx->devtype_data->has_dmamode)
1880 spi_imx_sdma_exit(spi_imx);
1882 pm_runtime_dont_use_autosuspend(spi_imx->dev);
1883 pm_runtime_set_suspended(&pdev->dev);
1884 pm_runtime_disable(spi_imx->dev);
1886 clk_disable_unprepare(spi_imx->clk_ipg);
1888 clk_disable_unprepare(spi_imx->clk_per);
1890 spi_controller_put(controller);
1895 static void spi_imx_remove(struct platform_device *pdev)
1897 struct spi_controller *controller = platform_get_drvdata(pdev);
1898 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1901 spi_unregister_controller(controller);
1903 ret = pm_runtime_get_sync(spi_imx->dev);
1905 writel(0, spi_imx->base + MXC_CSPICTRL);
1907 dev_warn(spi_imx->dev, "failed to enable clock, skip hw disable\n");
1909 pm_runtime_dont_use_autosuspend(spi_imx->dev);
1910 pm_runtime_put_sync(spi_imx->dev);
1911 pm_runtime_disable(spi_imx->dev);
1913 spi_imx_sdma_exit(spi_imx);
1916 static int __maybe_unused spi_imx_runtime_resume(struct device *dev)
1918 struct spi_controller *controller = dev_get_drvdata(dev);
1919 struct spi_imx_data *spi_imx;
1922 spi_imx = spi_controller_get_devdata(controller);
1924 ret = clk_prepare_enable(spi_imx->clk_per);
1928 ret = clk_prepare_enable(spi_imx->clk_ipg);
1930 clk_disable_unprepare(spi_imx->clk_per);
1937 static int __maybe_unused spi_imx_runtime_suspend(struct device *dev)
1939 struct spi_controller *controller = dev_get_drvdata(dev);
1940 struct spi_imx_data *spi_imx;
1942 spi_imx = spi_controller_get_devdata(controller);
1944 clk_disable_unprepare(spi_imx->clk_per);
1945 clk_disable_unprepare(spi_imx->clk_ipg);
1950 static int __maybe_unused spi_imx_suspend(struct device *dev)
1952 pinctrl_pm_select_sleep_state(dev);
1956 static int __maybe_unused spi_imx_resume(struct device *dev)
1958 pinctrl_pm_select_default_state(dev);
1962 static const struct dev_pm_ops imx_spi_pm = {
1963 SET_RUNTIME_PM_OPS(spi_imx_runtime_suspend,
1964 spi_imx_runtime_resume, NULL)
1965 SET_SYSTEM_SLEEP_PM_OPS(spi_imx_suspend, spi_imx_resume)
1968 static struct platform_driver spi_imx_driver = {
1970 .name = DRIVER_NAME,
1971 .of_match_table = spi_imx_dt_ids,
1974 .probe = spi_imx_probe,
1975 .remove_new = spi_imx_remove,
1977 module_platform_driver(spi_imx_driver);
1979 MODULE_DESCRIPTION("i.MX SPI Controller driver");
1980 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1981 MODULE_LICENSE("GPL");
1982 MODULE_ALIAS("platform:" DRIVER_NAME);